projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Add cherryview_update_wm()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f9dcb0df 33#include <linux/vgaarb.h>
f4db9321 34#include <drm/i915_powerwell.h>
8a187455 35#include <linux/pm_runtime.h>
85208be0 36
dc39fff7
BW		 37/**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
f6750b3c
ED		 58/* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 61 *
f6750b3c
ED		 62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
85208be0 64 *
f6750b3c
ED		 65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
85208be0
ED		 67 */
68
1fa61106 69static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89}
90
993495ae 91static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 92{
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 95 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 96 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0
ED		 97 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
98 int cfb_pitch;
7f2cf220 99 int i;
159f9875 100 u32 fbc_ctl;
85208be0 101
5c3fe8b0 102 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 103 if (fb->pitches[0] < cfb_pitch)
104 cfb_pitch = fb->pitches[0];
105
42a430f5
VS		 106 /* FBC_CTL wants 32B or 64B units */
107 if (IS_GEN2(dev))
108 cfb_pitch = (cfb_pitch / 32) - 1;
109 else
110 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 111
112 /* Clear old tags */
113 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
114 I915_WRITE(FBC_TAG + (i * 4), 0);
115
159f9875
VS		 116 if (IS_GEN4(dev)) {
117 u32 fbc_ctl2;
118
119 /* Set it up... */
120 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
7f2cf220 121 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
159f9875
VS		 122 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
123 I915_WRITE(FBC_FENCE_OFF, crtc->y);
124 }
85208be0
ED		 125
126 /* enable it... */
993495ae
VS		 127 fbc_ctl = I915_READ(FBC_CONTROL);
128 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
129 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 130 if (IS_I945GM(dev))
131 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
132 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 133 fbc_ctl |= obj->fence_reg;
134 I915_WRITE(FBC_CONTROL, fbc_ctl);
135
5cd5410e 136 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
84f44ce7 137 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 138}
139
1fa61106 140static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
145}
146
993495ae 147static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 148{
149 struct drm_device *dev = crtc->dev;
150 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 151 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 152 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0 153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 154 u32 dpfc_ctl;
155
3fa2e0ee
VS		 156 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
157 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
158 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
159 else
160 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
85208be0 161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
85208be0 162
85208be0
ED		 163 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
164
165 /* enable it... */
fe74c1a5 166 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
85208be0 167
84f44ce7 168 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 169}
170
1fa61106 171static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 172{
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 u32 dpfc_ctl;
175
176 /* Disable compression */
177 dpfc_ctl = I915_READ(DPFC_CONTROL);
178 if (dpfc_ctl & DPFC_CTL_EN) {
179 dpfc_ctl &= ~DPFC_CTL_EN;
180 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
181
182 DRM_DEBUG_KMS("disabled FBC\n");
183 }
184}
185
1fa61106 186static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 187{
188 struct drm_i915_private *dev_priv = dev->dev_private;
189
190 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
191}
192
193static void sandybridge_blit_fbc_update(struct drm_device *dev)
194{
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 u32 blt_ecoskpd;
197
198 /* Make sure blitter notifies FBC of writes */
940aece4
D		 199
200 /* Blitter is part of Media powerwell on VLV. No impact of
201 * his param in other platforms for now */
202 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 203
85208be0
ED		 204 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
205 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
206 GEN6_BLITTER_LOCK_SHIFT;
207 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
208 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
211 GEN6_BLITTER_LOCK_SHIFT);
212 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
213 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 214
940aece4 215 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 216}
217
993495ae 218static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 219{
220 struct drm_device *dev = crtc->dev;
221 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 222 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 223 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0 224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 225 u32 dpfc_ctl;
226
46f3dab9 227 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
3fa2e0ee 228 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
5e59f717
BW		 229 dev_priv->fbc.threshold++;
230
231 switch (dev_priv->fbc.threshold) {
232 case 4:
233 case 3:
234 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
235 break;
236 case 2:
3fa2e0ee 237 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
5e59f717
BW		 238 break;
239 case 1:
3fa2e0ee 240 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
5e59f717
BW		 241 break;
242 }
d629336b
VS		 243 dpfc_ctl |= DPFC_CTL_FENCE_EN;
244 if (IS_GEN5(dev))
245 dpfc_ctl |= obj->fence_reg;
85208be0 246
85208be0 247 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 248 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 249 /* enable it... */
250 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
251
252 if (IS_GEN6(dev)) {
253 I915_WRITE(SNB_DPFC_CTL_SA,
254 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
255 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
256 sandybridge_blit_fbc_update(dev);
257 }
258
84f44ce7 259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 260}
261
1fa61106 262static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 263{
264 struct drm_i915_private *dev_priv = dev->dev_private;
265 u32 dpfc_ctl;
266
267 /* Disable compression */
268 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
269 if (dpfc_ctl & DPFC_CTL_EN) {
270 dpfc_ctl &= ~DPFC_CTL_EN;
271 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
272
273 DRM_DEBUG_KMS("disabled FBC\n");
274 }
275}
276
1fa61106 277static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 278{
279 struct drm_i915_private *dev_priv = dev->dev_private;
280
281 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
282}
283
993495ae 284static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 285{
286 struct drm_device *dev = crtc->dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 288 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 289 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
abe959c7 290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3fa2e0ee 291 u32 dpfc_ctl;
abe959c7 292
3fa2e0ee
VS		 293 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
294 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
5e59f717
BW		 295 dev_priv->fbc.threshold++;
296
297 switch (dev_priv->fbc.threshold) {
298 case 4:
299 case 3:
300 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
301 break;
302 case 2:
3fa2e0ee 303 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
5e59f717
BW		 304 break;
305 case 1:
3fa2e0ee 306 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
5e59f717
BW		 307 break;
308 }
309
3fa2e0ee
VS		 310 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
311
da46f936
RV		 312 if (dev_priv->fbc.false_color)
313 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
314
3fa2e0ee 315 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
abe959c7 316
891348b2 317 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 318 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
2adb6db8
VS		 319 I915_WRITE(ILK_DISPLAY_CHICKEN1,
320 I915_READ(ILK_DISPLAY_CHICKEN1) |
321 ILK_FBCQ_DIS);
28554164 322 } else {
2adb6db8 323 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
8f670bb1
VS		 324 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
325 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
326 HSW_FBCQ_DIS);
891348b2 327 }
b74ea102 328
abe959c7
RV		 329 I915_WRITE(SNB_DPFC_CTL_SA,
330 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
331 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
332
333 sandybridge_blit_fbc_update(dev);
334
b19870ee 335 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 336}
337
85208be0
ED		 338bool intel_fbc_enabled(struct drm_device *dev)
339{
340 struct drm_i915_private *dev_priv = dev->dev_private;
341
342 if (!dev_priv->display.fbc_enabled)
343 return false;
344
345 return dev_priv->display.fbc_enabled(dev);
346}
347
348static void intel_fbc_work_fn(struct work_struct *__work)
349{
350 struct intel_fbc_work *work =
351 container_of(to_delayed_work(__work),
352 struct intel_fbc_work, work);
353 struct drm_device *dev = work->crtc->dev;
354 struct drm_i915_private *dev_priv = dev->dev_private;
355
356 mutex_lock(&dev->struct_mutex);
5c3fe8b0 357 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 358 /* Double check that we haven't switched fb without cancelling
359 * the prior work.
360 */
f4510a27 361 if (work->crtc->primary->fb == work->fb) {
993495ae 362 dev_priv->display.enable_fbc(work->crtc);
85208be0 363
5c3fe8b0 364 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
f4510a27 365 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
5c3fe8b0 366 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 367 }
368
5c3fe8b0 369 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 370 }
371 mutex_unlock(&dev->struct_mutex);
372
373 kfree(work);
374}
375
376static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
377{
5c3fe8b0 378 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 379 return;
380
381 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
382
383 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 384 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 385 * entirely asynchronously.
386 */
5c3fe8b0 387 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 388 /* tasklet was killed before being run, clean up */
5c3fe8b0 389 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 390
391 /* Mark the work as no longer wanted so that if it does
392 * wake-up (because the work was already running and waiting
393 * for our mutex), it will discover that is no longer
394 * necessary to run.
395 */
5c3fe8b0 396 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 397}
398
993495ae 399static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 400{
401 struct intel_fbc_work *work;
402 struct drm_device *dev = crtc->dev;
403 struct drm_i915_private *dev_priv = dev->dev_private;
404
405 if (!dev_priv->display.enable_fbc)
406 return;
407
408 intel_cancel_fbc_work(dev_priv);
409
b14c5679 410 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 411 if (work == NULL) {
6cdcb5e7 412 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 413 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 414 return;
415 }
416
417 work->crtc = crtc;
f4510a27 418 work->fb = crtc->primary->fb;
85208be0
ED		 419 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
420
5c3fe8b0 421 dev_priv->fbc.fbc_work = work;
85208be0 422
85208be0
ED		 423 /* Delay the actual enabling to let pageflipping cease and the
424 * display to settle before starting the compression. Note that
425 * this delay also serves a second purpose: it allows for a
426 * vblank to pass after disabling the FBC before we attempt
427 * to modify the control registers.
428 *
429 * A more complicated solution would involve tracking vblanks
430 * following the termination of the page-flipping sequence
431 * and indeed performing the enable as a co-routine and not
432 * waiting synchronously upon the vblank.
7457d617
DL		 433 *
434 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 435 */
436 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
437}
438
439void intel_disable_fbc(struct drm_device *dev)
440{
441 struct drm_i915_private *dev_priv = dev->dev_private;
442
443 intel_cancel_fbc_work(dev_priv);
444
445 if (!dev_priv->display.disable_fbc)
446 return;
447
448 dev_priv->display.disable_fbc(dev);
5c3fe8b0 449 dev_priv->fbc.plane = -1;
85208be0
ED		 450}
451
29ebf90f
CW		 452static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
453 enum no_fbc_reason reason)
454{
455 if (dev_priv->fbc.no_fbc_reason == reason)
456 return false;
457
458 dev_priv->fbc.no_fbc_reason = reason;
459 return true;
460}
461
85208be0
ED		 462/**
463 * intel_update_fbc - enable/disable FBC as needed
464 * @dev: the drm_device
465 *
466 * Set up the framebuffer compression hardware at mode set time. We
467 * enable it if possible:
468 * - plane A only (on pre-965)
469 * - no pixel mulitply/line duplication
470 * - no alpha buffer discard
471 * - no dual wide
f85da868 472 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 473 *
474 * We can't assume that any compression will take place (worst case),
475 * so the compressed buffer has to be the same size as the uncompressed
476 * one. It also must reside (along with the line length buffer) in
477 * stolen memory.
478 *
479 * We need to enable/disable FBC on a global basis.
480 */
481void intel_update_fbc(struct drm_device *dev)
482{
483 struct drm_i915_private *dev_priv = dev->dev_private;
484 struct drm_crtc *crtc = NULL, *tmp_crtc;
485 struct intel_crtc *intel_crtc;
486 struct drm_framebuffer *fb;
85208be0 487 struct drm_i915_gem_object *obj;
ef644fda 488 const struct drm_display_mode *adjusted_mode;
37327abd 489 unsigned int max_width, max_height;
85208be0 490
3a77c4c4 491 if (!HAS_FBC(dev)) {
29ebf90f 492 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 493 return;
29ebf90f 494 }
85208be0 495
d330a953 496 if (!i915.powersave) {
29ebf90f
CW		 497 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
498 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 499 return;
29ebf90f 500 }
85208be0
ED		 501
502 /*
503 * If FBC is already on, we just have to verify that we can
504 * keep it that way...
505 * Need to disable if:
506 * - more than one pipe is active
507 * - changing FBC params (stride, fence, mode)
508 * - new fb is too large to fit in compressed buffer
509 * - going to an unsupported config (interlace, pixel multiply, etc.)
510 */
70e1e0ec 511 for_each_crtc(dev, tmp_crtc) {
3490ea5d 512 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 513 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 514 if (crtc) {
29ebf90f
CW		 515 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
516 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 517 goto out_disable;
518 }
519 crtc = tmp_crtc;
520 }
521 }
522
f4510a27 523 if (!crtc || crtc->primary->fb == NULL) {
29ebf90f
CW		 524 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
525 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 526 goto out_disable;
527 }
528
529 intel_crtc = to_intel_crtc(crtc);
f4510a27 530 fb = crtc->primary->fb;
2ff8fde1 531 obj = intel_fb_obj(fb);
ef644fda 532 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 533
0368920e 534 if (i915.enable_fbc < 0) {
29ebf90f
CW		 535 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
536 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 537 goto out_disable;
85208be0 538 }
d330a953 539 if (!i915.enable_fbc) {
29ebf90f
CW		 540 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
541 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 542 goto out_disable;
543 }
ef644fda
VS		 544 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
545 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 546 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
547 DRM_DEBUG_KMS("mode incompatible with compression, "
548 "disabling\n");
85208be0
ED		 549 goto out_disable;
550 }
f85da868 551
032843a5
DS		 552 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
553 max_width = 4096;
554 max_height = 4096;
555 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 556 max_width = 4096;
557 max_height = 2048;
f85da868 558 } else {
37327abd
VS		 559 max_width = 2048;
560 max_height = 1536;
f85da868 561 }
37327abd
VS		 562 if (intel_crtc->config.pipe_src_w > max_width ||
563 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 564 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
565 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 566 goto out_disable;
567 }
8f94d24b 568 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
c5a44aa0 569 intel_crtc->plane != PLANE_A) {
29ebf90f 570 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 571 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 572 goto out_disable;
573 }
574
575 /* The use of a CPU fence is mandatory in order to detect writes
576 * by the CPU to the scanout and trigger updates to the FBC.
577 */
578 if (obj->tiling_mode != I915_TILING_X ||
579 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 580 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
581 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 582 goto out_disable;
583 }
584
585 /* If the kernel debugger is active, always disable compression */
586 if (in_dbg_master())
587 goto out_disable;
588
2ff8fde1 589 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
5e59f717 590 drm_format_plane_cpp(fb->pixel_format, 0))) {
29ebf90f
CW		 591 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
592 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 593 goto out_disable;
594 }
595
85208be0
ED		 596 /* If the scanout has not changed, don't modify the FBC settings.
597 * Note that we make the fundamental assumption that the fb->obj
598 * cannot be unpinned (and have its GTT offset and fence revoked)
599 * without first being decoupled from the scanout and FBC disabled.
600 */
5c3fe8b0
BW		 601 if (dev_priv->fbc.plane == intel_crtc->plane &&
602 dev_priv->fbc.fb_id == fb->base.id &&
603 dev_priv->fbc.y == crtc->y)
85208be0
ED		 604 return;
605
606 if (intel_fbc_enabled(dev)) {
607 /* We update FBC along two paths, after changing fb/crtc
608 * configuration (modeswitching) and after page-flipping
609 * finishes. For the latter, we know that not only did
610 * we disable the FBC at the start of the page-flip
611 * sequence, but also more than one vblank has passed.
612 *
613 * For the former case of modeswitching, it is possible
614 * to switch between two FBC valid configurations
615 * instantaneously so we do need to disable the FBC
616 * before we can modify its control registers. We also
617 * have to wait for the next vblank for that to take
618 * effect. However, since we delay enabling FBC we can
619 * assume that a vblank has passed since disabling and
620 * that we can safely alter the registers in the deferred
621 * callback.
622 *
623 * In the scenario that we go from a valid to invalid
624 * and then back to valid FBC configuration we have
625 * no strict enforcement that a vblank occurred since
626 * disabling the FBC. However, along all current pipe
627 * disabling paths we do need to wait for a vblank at
628 * some point. And we wait before enabling FBC anyway.
629 */
630 DRM_DEBUG_KMS("disabling active FBC for update\n");
631 intel_disable_fbc(dev);
632 }
633
993495ae 634 intel_enable_fbc(crtc);
29ebf90f 635 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 636 return;
637
638out_disable:
639 /* Multiple disables should be harmless */
640 if (intel_fbc_enabled(dev)) {
641 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
642 intel_disable_fbc(dev);
643 }
11be49eb 644 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 645}
646
c921aba8
DV		 647static void i915_pineview_get_mem_freq(struct drm_device *dev)
648{
50227e1c 649 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 650 u32 tmp;
651
652 tmp = I915_READ(CLKCFG);
653
654 switch (tmp & CLKCFG_FSB_MASK) {
655 case CLKCFG_FSB_533:
656 dev_priv->fsb_freq = 533; /* 133*4 */
657 break;
658 case CLKCFG_FSB_800:
659 dev_priv->fsb_freq = 800; /* 200*4 */
660 break;
661 case CLKCFG_FSB_667:
662 dev_priv->fsb_freq = 667; /* 167*4 */
663 break;
664 case CLKCFG_FSB_400:
665 dev_priv->fsb_freq = 400; /* 100*4 */
666 break;
667 }
668
669 switch (tmp & CLKCFG_MEM_MASK) {
670 case CLKCFG_MEM_533:
671 dev_priv->mem_freq = 533;
672 break;
673 case CLKCFG_MEM_667:
674 dev_priv->mem_freq = 667;
675 break;
676 case CLKCFG_MEM_800:
677 dev_priv->mem_freq = 800;
678 break;
679 }
680
681 /* detect pineview DDR3 setting */
682 tmp = I915_READ(CSHRDDR3CTL);
683 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
684}
685
686static void i915_ironlake_get_mem_freq(struct drm_device *dev)
687{
50227e1c 688 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 689 u16 ddrpll, csipll;
690
691 ddrpll = I915_READ16(DDRMPLL1);
692 csipll = I915_READ16(CSIPLL0);
693
694 switch (ddrpll & 0xff) {
695 case 0xc:
696 dev_priv->mem_freq = 800;
697 break;
698 case 0x10:
699 dev_priv->mem_freq = 1066;
700 break;
701 case 0x14:
702 dev_priv->mem_freq = 1333;
703 break;
704 case 0x18:
705 dev_priv->mem_freq = 1600;
706 break;
707 default:
708 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
709 ddrpll & 0xff);
710 dev_priv->mem_freq = 0;
711 break;
712 }
713
20e4d407 714 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 715
716 switch (csipll & 0x3ff) {
717 case 0x00c:
718 dev_priv->fsb_freq = 3200;
719 break;
720 case 0x00e:
721 dev_priv->fsb_freq = 3733;
722 break;
723 case 0x010:
724 dev_priv->fsb_freq = 4266;
725 break;
726 case 0x012:
727 dev_priv->fsb_freq = 4800;
728 break;
729 case 0x014:
730 dev_priv->fsb_freq = 5333;
731 break;
732 case 0x016:
733 dev_priv->fsb_freq = 5866;
734 break;
735 case 0x018:
736 dev_priv->fsb_freq = 6400;
737 break;
738 default:
739 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
740 csipll & 0x3ff);
741 dev_priv->fsb_freq = 0;
742 break;
743 }
744
745 if (dev_priv->fsb_freq == 3200) {
20e4d407 746 dev_priv->ips.c_m = 0;
c921aba8 747 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 748 dev_priv->ips.c_m = 1;
c921aba8 749 } else {
20e4d407 750 dev_priv->ips.c_m = 2;
c921aba8
DV		 751 }
752}
753
b445e3b0
ED		 754static const struct cxsr_latency cxsr_latency_table[] = {
755 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
756 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
757 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
758 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
759 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
760
761 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
762 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
763 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
764 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
765 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
766
767 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
768 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
769 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
770 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
771 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
772
773 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
774 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
775 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
776 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
777 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
778
779 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
780 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
781 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
782 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
783 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
784
785 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
786 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
787 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
788 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
789 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
790};
791
63c62275 792static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 793 int is_ddr3,
794 int fsb,
795 int mem)
796{
797 const struct cxsr_latency *latency;
798 int i;
799
800 if (fsb == 0 || mem == 0)
801 return NULL;
802
803 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
804 latency = &cxsr_latency_table[i];
805 if (is_desktop == latency->is_desktop &&
806 is_ddr3 == latency->is_ddr3 &&
807 fsb == latency->fsb_freq && mem == latency->mem_freq)
808 return latency;
809 }
810
811 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
812
813 return NULL;
814}
815
5209b1f4 816void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 817{
5209b1f4
ID		 818 struct drm_device *dev = dev_priv->dev;
819 u32 val;
b445e3b0 820
5209b1f4
ID		 821 if (IS_VALLEYVIEW(dev)) {
822 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
823 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
824 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
825 } else if (IS_PINEVIEW(dev)) {
826 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
827 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
828 I915_WRITE(DSPFW3, val);
829 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
830 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
831 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
832 I915_WRITE(FW_BLC_SELF, val);
833 } else if (IS_I915GM(dev)) {
834 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
835 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
836 I915_WRITE(INSTPM, val);
837 } else {
838 return;
839 }
840
841 DRM_DEBUG_KMS("memory self-refresh is %s\n",
842 enable ? "enabled" : "disabled");
b445e3b0
ED		 843}
844
845/*
846 * Latency for FIFO fetches is dependent on several factors:
847 * - memory configuration (speed, channels)
848 * - chipset
849 * - current MCH state
850 * It can be fairly high in some situations, so here we assume a fairly
851 * pessimal value. It's a tradeoff between extra memory fetches (if we
852 * set this value too high, the FIFO will fetch frequently to stay full)
853 * and power consumption (set it too low to save power and we might see
854 * FIFO underruns and display "flicker").
855 *
856 * A value of 5us seems to be a good balance; safe for very low end
857 * platforms but not overly aggressive on lower latency configs.
858 */
859static const int latency_ns = 5000;
860
1fa61106 861static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 862{
863 struct drm_i915_private *dev_priv = dev->dev_private;
864 uint32_t dsparb = I915_READ(DSPARB);
865 int size;
866
867 size = dsparb & 0x7f;
868 if (plane)
869 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
870
871 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
872 plane ? "B" : "A", size);
873
874 return size;
875}
876
feb56b93 877static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 878{
879 struct drm_i915_private *dev_priv = dev->dev_private;
880 uint32_t dsparb = I915_READ(DSPARB);
881 int size;
882
883 size = dsparb & 0x1ff;
884 if (plane)
885 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
886 size >>= 1; /* Convert to cachelines */
887
888 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
889 plane ? "B" : "A", size);
890
891 return size;
892}
893
1fa61106 894static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 895{
896 struct drm_i915_private *dev_priv = dev->dev_private;
897 uint32_t dsparb = I915_READ(DSPARB);
898 int size;
899
900 size = dsparb & 0x7f;
901 size >>= 2; /* Convert to cachelines */
902
903 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
904 plane ? "B" : "A",
905 size);
906
907 return size;
908}
909
b445e3b0
ED		 910/* Pineview has different values for various configs */
911static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 912 .fifo_size = PINEVIEW_DISPLAY_FIFO,
913 .max_wm = PINEVIEW_MAX_WM,
914 .default_wm = PINEVIEW_DFT_WM,
915 .guard_size = PINEVIEW_GUARD_WM,
916 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 917};
918static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 919 .fifo_size = PINEVIEW_DISPLAY_FIFO,
920 .max_wm = PINEVIEW_MAX_WM,
921 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
922 .guard_size = PINEVIEW_GUARD_WM,
923 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 924};
925static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 926 .fifo_size = PINEVIEW_CURSOR_FIFO,
927 .max_wm = PINEVIEW_CURSOR_MAX_WM,
928 .default_wm = PINEVIEW_CURSOR_DFT_WM,
929 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
930 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 931};
932static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 933 .fifo_size = PINEVIEW_CURSOR_FIFO,
934 .max_wm = PINEVIEW_CURSOR_MAX_WM,
935 .default_wm = PINEVIEW_CURSOR_DFT_WM,
936 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
937 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 938};
939static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 940 .fifo_size = G4X_FIFO_SIZE,
941 .max_wm = G4X_MAX_WM,
942 .default_wm = G4X_MAX_WM,
943 .guard_size = 2,
944 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 945};
946static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 947 .fifo_size = I965_CURSOR_FIFO,
948 .max_wm = I965_CURSOR_MAX_WM,
949 .default_wm = I965_CURSOR_DFT_WM,
950 .guard_size = 2,
951 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 952};
953static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 954 .fifo_size = VALLEYVIEW_FIFO_SIZE,
955 .max_wm = VALLEYVIEW_MAX_WM,
956 .default_wm = VALLEYVIEW_MAX_WM,
957 .guard_size = 2,
958 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 959};
960static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 961 .fifo_size = I965_CURSOR_FIFO,
962 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
963 .default_wm = I965_CURSOR_DFT_WM,
964 .guard_size = 2,
965 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 966};
967static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 968 .fifo_size = I965_CURSOR_FIFO,
969 .max_wm = I965_CURSOR_MAX_WM,
970 .default_wm = I965_CURSOR_DFT_WM,
971 .guard_size = 2,
972 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 973};
974static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 975 .fifo_size = I945_FIFO_SIZE,
976 .max_wm = I915_MAX_WM,
977 .default_wm = 1,
978 .guard_size = 2,
979 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 980};
981static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 982 .fifo_size = I915_FIFO_SIZE,
983 .max_wm = I915_MAX_WM,
984 .default_wm = 1,
985 .guard_size = 2,
986 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 987};
feb56b93 988static const struct intel_watermark_params i830_wm_info = {
e0f0273e
VS		 989 .fifo_size = I855GM_FIFO_SIZE,
990 .max_wm = I915_MAX_WM,
991 .default_wm = 1,
992 .guard_size = 2,
993 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 994};
feb56b93 995static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 996 .fifo_size = I830_FIFO_SIZE,
997 .max_wm = I915_MAX_WM,
998 .default_wm = 1,
999 .guard_size = 2,
1000 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 1001};
1002
b445e3b0
ED		 1003/**
1004 * intel_calculate_wm - calculate watermark level
1005 * @clock_in_khz: pixel clock
1006 * @wm: chip FIFO params
1007 * @pixel_size: display pixel size
1008 * @latency_ns: memory latency for the platform
1009 *
1010 * Calculate the watermark level (the level at which the display plane will
1011 * start fetching from memory again). Each chip has a different display
1012 * FIFO size and allocation, so the caller needs to figure that out and pass
1013 * in the correct intel_watermark_params structure.
1014 *
1015 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1016 * on the pixel size. When it reaches the watermark level, it'll start
1017 * fetching FIFO line sized based chunks from memory until the FIFO fills
1018 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1019 * will occur, and a display engine hang could result.
1020 */
1021static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1022 const struct intel_watermark_params *wm,
1023 int fifo_size,
1024 int pixel_size,
1025 unsigned long latency_ns)
1026{
1027 long entries_required, wm_size;
1028
1029 /*
1030 * Note: we need to make sure we don't overflow for various clock &
1031 * latency values.
1032 * clocks go from a few thousand to several hundred thousand.
1033 * latency is usually a few thousand
1034 */
1035 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1036 1000;
1037 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1038
1039 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1040
1041 wm_size = fifo_size - (entries_required + wm->guard_size);
1042
1043 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1044
1045 /* Don't promote wm_size to unsigned... */
1046 if (wm_size > (long)wm->max_wm)
1047 wm_size = wm->max_wm;
1048 if (wm_size <= 0)
1049 wm_size = wm->default_wm;
1050 return wm_size;
1051}
1052
1053static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1054{
1055 struct drm_crtc *crtc, *enabled = NULL;
1056
70e1e0ec 1057 for_each_crtc(dev, crtc) {
3490ea5d 1058 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1059 if (enabled)
1060 return NULL;
1061 enabled = crtc;
1062 }
1063 }
1064
1065 return enabled;
1066}
1067
46ba614c 1068static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1069{
46ba614c 1070 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1071 struct drm_i915_private *dev_priv = dev->dev_private;
1072 struct drm_crtc *crtc;
1073 const struct cxsr_latency *latency;
1074 u32 reg;
1075 unsigned long wm;
1076
1077 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1078 dev_priv->fsb_freq, dev_priv->mem_freq);
1079 if (!latency) {
1080 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 1081 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1082 return;
1083 }
1084
1085 crtc = single_enabled_crtc(dev);
1086 if (crtc) {
241bfc38 1087 const struct drm_display_mode *adjusted_mode;
f4510a27 1088 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
241bfc38
DL		 1089 int clock;
1090
1091 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1092 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1093
1094 /* Display SR */
1095 wm = intel_calculate_wm(clock, &pineview_display_wm,
1096 pineview_display_wm.fifo_size,
1097 pixel_size, latency->display_sr);
1098 reg = I915_READ(DSPFW1);
1099 reg &= ~DSPFW_SR_MASK;
1100 reg |= wm << DSPFW_SR_SHIFT;
1101 I915_WRITE(DSPFW1, reg);
1102 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1103
1104 /* cursor SR */
1105 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1106 pineview_display_wm.fifo_size,
1107 pixel_size, latency->cursor_sr);
1108 reg = I915_READ(DSPFW3);
1109 reg &= ~DSPFW_CURSOR_SR_MASK;
1110 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1111 I915_WRITE(DSPFW3, reg);
1112
1113 /* Display HPLL off SR */
1114 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1115 pineview_display_hplloff_wm.fifo_size,
1116 pixel_size, latency->display_hpll_disable);
1117 reg = I915_READ(DSPFW3);
1118 reg &= ~DSPFW_HPLL_SR_MASK;
1119 reg |= wm & DSPFW_HPLL_SR_MASK;
1120 I915_WRITE(DSPFW3, reg);
1121
1122 /* cursor HPLL off SR */
1123 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1124 pineview_display_hplloff_wm.fifo_size,
1125 pixel_size, latency->cursor_hpll_disable);
1126 reg = I915_READ(DSPFW3);
1127 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1128 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1129 I915_WRITE(DSPFW3, reg);
1130 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1131
5209b1f4 1132 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 1133 } else {
5209b1f4 1134 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1135 }
1136}
1137
1138static bool g4x_compute_wm0(struct drm_device *dev,
1139 int plane,
1140 const struct intel_watermark_params *display,
1141 int display_latency_ns,
1142 const struct intel_watermark_params *cursor,
1143 int cursor_latency_ns,
1144 int *plane_wm,
1145 int *cursor_wm)
1146{
1147 struct drm_crtc *crtc;
4fe8590a 1148 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1149 int htotal, hdisplay, clock, pixel_size;
1150 int line_time_us, line_count;
1151 int entries, tlb_miss;
1152
1153 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1154 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1155 *cursor_wm = cursor->guard_size;
1156 *plane_wm = display->guard_size;
1157 return false;
1158 }
1159
4fe8590a 1160 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1161 clock = adjusted_mode->crtc_clock;
fec8cba3 1162 htotal = adjusted_mode->crtc_htotal;
37327abd 1163 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1164 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1165
1166 /* Use the small buffer method to calculate plane watermark */
1167 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1168 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1169 if (tlb_miss > 0)
1170 entries += tlb_miss;
1171 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1172 *plane_wm = entries + display->guard_size;
1173 if (*plane_wm > (int)display->max_wm)
1174 *plane_wm = display->max_wm;
1175
1176 /* Use the large buffer method to calculate cursor watermark */
922044c9 1177 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 1178 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
7bb836dd 1179 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
b445e3b0
ED		 1180 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1181 if (tlb_miss > 0)
1182 entries += tlb_miss;
1183 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1184 *cursor_wm = entries + cursor->guard_size;
1185 if (*cursor_wm > (int)cursor->max_wm)
1186 *cursor_wm = (int)cursor->max_wm;
1187
1188 return true;
1189}
1190
1191/*
1192 * Check the wm result.
1193 *
1194 * If any calculated watermark values is larger than the maximum value that
1195 * can be programmed into the associated watermark register, that watermark
1196 * must be disabled.
1197 */
1198static bool g4x_check_srwm(struct drm_device *dev,
1199 int display_wm, int cursor_wm,
1200 const struct intel_watermark_params *display,
1201 const struct intel_watermark_params *cursor)
1202{
1203 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1204 display_wm, cursor_wm);
1205
1206 if (display_wm > display->max_wm) {
1207 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1208 display_wm, display->max_wm);
1209 return false;
1210 }
1211
1212 if (cursor_wm > cursor->max_wm) {
1213 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1214 cursor_wm, cursor->max_wm);
1215 return false;
1216 }
1217
1218 if (!(display_wm || cursor_wm)) {
1219 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1220 return false;
1221 }
1222
1223 return true;
1224}
1225
1226static bool g4x_compute_srwm(struct drm_device *dev,
1227 int plane,
1228 int latency_ns,
1229 const struct intel_watermark_params *display,
1230 const struct intel_watermark_params *cursor,
1231 int *display_wm, int *cursor_wm)
1232{
1233 struct drm_crtc *crtc;
4fe8590a 1234 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1235 int hdisplay, htotal, pixel_size, clock;
1236 unsigned long line_time_us;
1237 int line_count, line_size;
1238 int small, large;
1239 int entries;
1240
1241 if (!latency_ns) {
1242 *display_wm = *cursor_wm = 0;
1243 return false;
1244 }
1245
1246 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1247 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1248 clock = adjusted_mode->crtc_clock;
fec8cba3 1249 htotal = adjusted_mode->crtc_htotal;
37327abd 1250 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1251 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0 1252
922044c9 1253 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1254 line_count = (latency_ns / line_time_us + 1000) / 1000;
1255 line_size = hdisplay * pixel_size;
1256
1257 /* Use the minimum of the small and large buffer method for primary */
1258 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1259 large = line_count * line_size;
1260
1261 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1262 *display_wm = entries + display->guard_size;
1263
1264 /* calculate the self-refresh watermark for display cursor */
7bb836dd 1265 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1266 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1267 *cursor_wm = entries + cursor->guard_size;
1268
1269 return g4x_check_srwm(dev,
1270 *display_wm, *cursor_wm,
1271 display, cursor);
1272}
1273
1274static bool vlv_compute_drain_latency(struct drm_device *dev,
1275 int plane,
1276 int *plane_prec_mult,
1277 int *plane_dl,
1278 int *cursor_prec_mult,
1279 int *cursor_dl)
1280{
1281 struct drm_crtc *crtc;
1282 int clock, pixel_size;
1283 int entries;
1284
1285 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1286 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1287 return false;
1288
241bfc38 1289 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
f4510a27 1290 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
b445e3b0
ED		 1291
1292 entries = (clock / 1000) * pixel_size;
69bbeb4a 1293 *plane_prec_mult = (entries > 128) ?
22c5aee3 1294 DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
69bbeb4a 1295 *plane_dl = (64 * (*plane_prec_mult) * 4) / entries;
b445e3b0
ED		 1296
1297 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
69bbeb4a 1298 *cursor_prec_mult = (entries > 128) ?
22c5aee3 1299 DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
69bbeb4a 1300 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / entries;
b445e3b0
ED		 1301
1302 return true;
1303}
1304
1305/*
1306 * Update drain latency registers of memory arbiter
1307 *
1308 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1309 * to be programmed. Each plane has a drain latency multiplier and a drain
1310 * latency value.
1311 */
1312
41aad816 1313static void vlv_update_drain_latency(struct drm_crtc *crtc)
b445e3b0 1314{
41aad816 1315 struct drm_device *dev = crtc->dev;
b445e3b0 1316 struct drm_i915_private *dev_priv = dev->dev_private;
41aad816
GB		 1317 enum pipe pipe = to_intel_crtc(crtc)->pipe;
1318 int plane_prec, plane_dl;
1319 int cursor_prec, cursor_dl;
1320 int plane_prec_mult, cursor_prec_mult;
b445e3b0 1321
41aad816
GB		 1322 if (vlv_compute_drain_latency(dev, pipe, &plane_prec_mult, &plane_dl,
1323 &cursor_prec_mult, &cursor_dl)) {
1abc4dc7
VS		 1324 cursor_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1325 DDL_CURSOR_PRECISION_64 : DDL_CURSOR_PRECISION_32;
1326 plane_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1327 DDL_PLANE_PRECISION_64 : DDL_PLANE_PRECISION_32;
1328
1329 I915_WRITE(VLV_DDL(pipe), cursor_prec |
1330 (cursor_dl << DDL_CURSOR_SHIFT) |
1331 plane_prec | (plane_dl << DDL_PLANE_SHIFT));
b445e3b0
ED		 1332 }
1333}
1334
1335#define single_plane_enabled(mask) is_power_of_2(mask)
1336
46ba614c 1337static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1338{
46ba614c 1339 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1340 static const int sr_latency_ns = 12000;
1341 struct drm_i915_private *dev_priv = dev->dev_private;
1342 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1343 int plane_sr, cursor_sr;
af6c4575 1344 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0 1345 unsigned int enabled = 0;
9858425c 1346 bool cxsr_enabled;
b445e3b0 1347
41aad816 1348 vlv_update_drain_latency(crtc);
b445e3b0 1349
51cea1f4 1350 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1351 &valleyview_wm_info, latency_ns,
1352 &valleyview_cursor_wm_info, latency_ns,
1353 &planea_wm, &cursora_wm))
51cea1f4 1354 enabled |= 1 << PIPE_A;
b445e3b0 1355
51cea1f4 1356 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1357 &valleyview_wm_info, latency_ns,
1358 &valleyview_cursor_wm_info, latency_ns,
1359 &planeb_wm, &cursorb_wm))
51cea1f4 1360 enabled |= 1 << PIPE_B;
b445e3b0 1361
b445e3b0
ED		 1362 if (single_plane_enabled(enabled) &&
1363 g4x_compute_srwm(dev, ffs(enabled) - 1,
1364 sr_latency_ns,
1365 &valleyview_wm_info,
1366 &valleyview_cursor_wm_info,
af6c4575
CW		 1367 &plane_sr, &ignore_cursor_sr) &&
1368 g4x_compute_srwm(dev, ffs(enabled) - 1,
1369 2*sr_latency_ns,
1370 &valleyview_wm_info,
1371 &valleyview_cursor_wm_info,
52bd02d8 1372 &ignore_plane_sr, &cursor_sr)) {
9858425c 1373 cxsr_enabled = true;
52bd02d8 1374 } else {
9858425c 1375 cxsr_enabled = false;
5209b1f4 1376 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1377 plane_sr = cursor_sr = 0;
1378 }
b445e3b0 1379
a5043453
VS		 1380 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1381 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1382 planea_wm, cursora_wm,
1383 planeb_wm, cursorb_wm,
1384 plane_sr, cursor_sr);
1385
1386 I915_WRITE(DSPFW1,
1387 (plane_sr << DSPFW_SR_SHIFT) |
1388 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1389 (planeb_wm << DSPFW_PLANEB_SHIFT) |
0a560674 1390 (planea_wm << DSPFW_PLANEA_SHIFT));
b445e3b0 1391 I915_WRITE(DSPFW2,
8c919b28 1392 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1393 (cursora_wm << DSPFW_CURSORA_SHIFT));
1394 I915_WRITE(DSPFW3,
8c919b28
CW		 1395 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1396 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1397
1398 if (cxsr_enabled)
1399 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1400}
1401
3c2777fd
VS		 1402static void cherryview_update_wm(struct drm_crtc *crtc)
1403{
1404 struct drm_device *dev = crtc->dev;
1405 static const int sr_latency_ns = 12000;
1406 struct drm_i915_private *dev_priv = dev->dev_private;
1407 int planea_wm, planeb_wm, planec_wm;
1408 int cursora_wm, cursorb_wm, cursorc_wm;
1409 int plane_sr, cursor_sr;
1410 int ignore_plane_sr, ignore_cursor_sr;
1411 unsigned int enabled = 0;
1412 bool cxsr_enabled;
1413
1414 vlv_update_drain_latency(crtc);
1415
1416 if (g4x_compute_wm0(dev, PIPE_A,
1417 &valleyview_wm_info, latency_ns,
1418 &valleyview_cursor_wm_info, latency_ns,
1419 &planea_wm, &cursora_wm))
1420 enabled |= 1 << PIPE_A;
1421
1422 if (g4x_compute_wm0(dev, PIPE_B,
1423 &valleyview_wm_info, latency_ns,
1424 &valleyview_cursor_wm_info, latency_ns,
1425 &planeb_wm, &cursorb_wm))
1426 enabled |= 1 << PIPE_B;
1427
1428 if (g4x_compute_wm0(dev, PIPE_C,
1429 &valleyview_wm_info, latency_ns,
1430 &valleyview_cursor_wm_info, latency_ns,
1431 &planec_wm, &cursorc_wm))
1432 enabled |= 1 << PIPE_C;
1433
1434 if (single_plane_enabled(enabled) &&
1435 g4x_compute_srwm(dev, ffs(enabled) - 1,
1436 sr_latency_ns,
1437 &valleyview_wm_info,
1438 &valleyview_cursor_wm_info,
1439 &plane_sr, &ignore_cursor_sr) &&
1440 g4x_compute_srwm(dev, ffs(enabled) - 1,
1441 2*sr_latency_ns,
1442 &valleyview_wm_info,
1443 &valleyview_cursor_wm_info,
1444 &ignore_plane_sr, &cursor_sr)) {
1445 cxsr_enabled = true;
1446 } else {
1447 cxsr_enabled = false;
1448 intel_set_memory_cxsr(dev_priv, false);
1449 plane_sr = cursor_sr = 0;
1450 }
1451
1452 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1453 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1454 "SR: plane=%d, cursor=%d\n",
1455 planea_wm, cursora_wm,
1456 planeb_wm, cursorb_wm,
1457 planec_wm, cursorc_wm,
1458 plane_sr, cursor_sr);
1459
1460 I915_WRITE(DSPFW1,
1461 (plane_sr << DSPFW_SR_SHIFT) |
1462 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1463 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1464 (planea_wm << DSPFW_PLANEA_SHIFT));
1465 I915_WRITE(DSPFW2,
1466 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1467 (cursora_wm << DSPFW_CURSORA_SHIFT));
1468 I915_WRITE(DSPFW3,
1469 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1470 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1471 I915_WRITE(DSPFW9_CHV,
1472 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
1473 DSPFW_CURSORC_MASK)) |
1474 (planec_wm << DSPFW_PLANEC_SHIFT) |
1475 (cursorc_wm << DSPFW_CURSORC_SHIFT));
1476
1477 if (cxsr_enabled)
1478 intel_set_memory_cxsr(dev_priv, true);
1479}
1480
46ba614c 1481static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1482{
46ba614c 1483 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1484 static const int sr_latency_ns = 12000;
1485 struct drm_i915_private *dev_priv = dev->dev_private;
1486 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1487 int plane_sr, cursor_sr;
1488 unsigned int enabled = 0;
9858425c 1489 bool cxsr_enabled;
b445e3b0 1490
51cea1f4 1491 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1492 &g4x_wm_info, latency_ns,
1493 &g4x_cursor_wm_info, latency_ns,
1494 &planea_wm, &cursora_wm))
51cea1f4 1495 enabled |= 1 << PIPE_A;
b445e3b0 1496
51cea1f4 1497 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1498 &g4x_wm_info, latency_ns,
1499 &g4x_cursor_wm_info, latency_ns,
1500 &planeb_wm, &cursorb_wm))
51cea1f4 1501 enabled |= 1 << PIPE_B;
b445e3b0 1502
b445e3b0
ED		 1503 if (single_plane_enabled(enabled) &&
1504 g4x_compute_srwm(dev, ffs(enabled) - 1,
1505 sr_latency_ns,
1506 &g4x_wm_info,
1507 &g4x_cursor_wm_info,
52bd02d8 1508 &plane_sr, &cursor_sr)) {
9858425c 1509 cxsr_enabled = true;
52bd02d8 1510 } else {
9858425c 1511 cxsr_enabled = false;
5209b1f4 1512 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1513 plane_sr = cursor_sr = 0;
1514 }
b445e3b0 1515
a5043453
VS		 1516 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1517 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1518 planea_wm, cursora_wm,
1519 planeb_wm, cursorb_wm,
1520 plane_sr, cursor_sr);
1521
1522 I915_WRITE(DSPFW1,
1523 (plane_sr << DSPFW_SR_SHIFT) |
1524 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1525 (planeb_wm << DSPFW_PLANEB_SHIFT) |
0a560674 1526 (planea_wm << DSPFW_PLANEA_SHIFT));
b445e3b0 1527 I915_WRITE(DSPFW2,
8c919b28 1528 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1529 (cursora_wm << DSPFW_CURSORA_SHIFT));
1530 /* HPLL off in SR has some issues on G4x... disable it */
1531 I915_WRITE(DSPFW3,
8c919b28 1532 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0 1533 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1534
1535 if (cxsr_enabled)
1536 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1537}
1538
46ba614c 1539static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1540{
46ba614c 1541 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1542 struct drm_i915_private *dev_priv = dev->dev_private;
1543 struct drm_crtc *crtc;
1544 int srwm = 1;
1545 int cursor_sr = 16;
9858425c 1546 bool cxsr_enabled;
b445e3b0
ED		 1547
1548 /* Calc sr entries for one plane configs */
1549 crtc = single_enabled_crtc(dev);
1550 if (crtc) {
1551 /* self-refresh has much higher latency */
1552 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1553 const struct drm_display_mode *adjusted_mode =
1554 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1555 int clock = adjusted_mode->crtc_clock;
fec8cba3 1556 int htotal = adjusted_mode->crtc_htotal;
37327abd 1557 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1558 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1559 unsigned long line_time_us;
1560 int entries;
1561
922044c9 1562 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1563
1564 /* Use ns/us then divide to preserve precision */
1565 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1566 pixel_size * hdisplay;
1567 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1568 srwm = I965_FIFO_SIZE - entries;
1569 if (srwm < 0)
1570 srwm = 1;
1571 srwm &= 0x1ff;
1572 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1573 entries, srwm);
1574
1575 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
7bb836dd 1576 pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1577 entries = DIV_ROUND_UP(entries,
1578 i965_cursor_wm_info.cacheline_size);
1579 cursor_sr = i965_cursor_wm_info.fifo_size -
1580 (entries + i965_cursor_wm_info.guard_size);
1581
1582 if (cursor_sr > i965_cursor_wm_info.max_wm)
1583 cursor_sr = i965_cursor_wm_info.max_wm;
1584
1585 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1586 "cursor %d\n", srwm, cursor_sr);
1587
9858425c 1588 cxsr_enabled = true;
b445e3b0 1589 } else {
9858425c 1590 cxsr_enabled = false;
b445e3b0 1591 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1592 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1593 }
1594
1595 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1596 srwm);
1597
1598 /* 965 has limitations... */
1599 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
0a560674
VS		 1600 (8 << DSPFW_CURSORB_SHIFT) |
1601 (8 << DSPFW_PLANEB_SHIFT) |
1602 (8 << DSPFW_PLANEA_SHIFT));
1603 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1604 (8 << DSPFW_PLANEC_SHIFT_OLD));
b445e3b0
ED		 1605 /* update cursor SR watermark */
1606 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1607
1608 if (cxsr_enabled)
1609 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1610}
1611
46ba614c 1612static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1613{
46ba614c 1614 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1615 struct drm_i915_private *dev_priv = dev->dev_private;
1616 const struct intel_watermark_params *wm_info;
1617 uint32_t fwater_lo;
1618 uint32_t fwater_hi;
1619 int cwm, srwm = 1;
1620 int fifo_size;
1621 int planea_wm, planeb_wm;
1622 struct drm_crtc *crtc, *enabled = NULL;
1623
1624 if (IS_I945GM(dev))
1625 wm_info = &i945_wm_info;
1626 else if (!IS_GEN2(dev))
1627 wm_info = &i915_wm_info;
1628 else
feb56b93 1629 wm_info = &i830_wm_info;
b445e3b0
ED		 1630
1631 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1632 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1633 if (intel_crtc_active(crtc)) {
241bfc38 1634 const struct drm_display_mode *adjusted_mode;
f4510a27 1635 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1636 if (IS_GEN2(dev))
1637 cpp = 4;
1638
241bfc38
DL		 1639 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1640 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1641 wm_info, fifo_size, cpp,
b445e3b0
ED		 1642 latency_ns);
1643 enabled = crtc;
1644 } else
1645 planea_wm = fifo_size - wm_info->guard_size;
1646
1647 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1648 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1649 if (intel_crtc_active(crtc)) {
241bfc38 1650 const struct drm_display_mode *adjusted_mode;
f4510a27 1651 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1652 if (IS_GEN2(dev))
1653 cpp = 4;
1654
241bfc38
DL		 1655 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1656 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1657 wm_info, fifo_size, cpp,
b445e3b0
ED		 1658 latency_ns);
1659 if (enabled == NULL)
1660 enabled = crtc;
1661 else
1662 enabled = NULL;
1663 } else
1664 planeb_wm = fifo_size - wm_info->guard_size;
1665
1666 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1667
2ab1bc9d 1668 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1669 struct drm_i915_gem_object *obj;
2ab1bc9d 1670
2ff8fde1 1671 obj = intel_fb_obj(enabled->primary->fb);
2ab1bc9d
DV		 1672
1673 /* self-refresh seems busted with untiled */
2ff8fde1 1674 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1675 enabled = NULL;
1676 }
1677
b445e3b0
ED		 1678 /*
1679 * Overlay gets an aggressive default since video jitter is bad.
1680 */
1681 cwm = 2;
1682
1683 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1684 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1685
1686 /* Calc sr entries for one plane configs */
1687 if (HAS_FW_BLC(dev) && enabled) {
1688 /* self-refresh has much higher latency */
1689 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1690 const struct drm_display_mode *adjusted_mode =
1691 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1692 int clock = adjusted_mode->crtc_clock;
fec8cba3 1693 int htotal = adjusted_mode->crtc_htotal;
f727b490 1694 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
f4510a27 1695 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1696 unsigned long line_time_us;
1697 int entries;
1698
922044c9 1699 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1700
1701 /* Use ns/us then divide to preserve precision */
1702 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1703 pixel_size * hdisplay;
1704 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1705 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1706 srwm = wm_info->fifo_size - entries;
1707 if (srwm < 0)
1708 srwm = 1;
1709
1710 if (IS_I945G(dev) || IS_I945GM(dev))
1711 I915_WRITE(FW_BLC_SELF,
1712 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1713 else if (IS_I915GM(dev))
1714 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1715 }
1716
1717 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1718 planea_wm, planeb_wm, cwm, srwm);
1719
1720 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1721 fwater_hi = (cwm & 0x1f);
1722
1723 /* Set request length to 8 cachelines per fetch */
1724 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1725 fwater_hi = fwater_hi | (1 << 8);
1726
1727 I915_WRITE(FW_BLC, fwater_lo);
1728 I915_WRITE(FW_BLC2, fwater_hi);
1729
5209b1f4
ID		 1730 if (enabled)
1731 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1732}
1733
feb56b93 1734static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1735{
46ba614c 1736 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1737 struct drm_i915_private *dev_priv = dev->dev_private;
1738 struct drm_crtc *crtc;
241bfc38 1739 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1740 uint32_t fwater_lo;
1741 int planea_wm;
1742
1743 crtc = single_enabled_crtc(dev);
1744 if (crtc == NULL)
1745 return;
1746
241bfc38
DL		 1747 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1748 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1749 &i845_wm_info,
b445e3b0 1750 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1751 4, latency_ns);
b445e3b0
ED		 1752 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1753 fwater_lo |= (3<<8) | planea_wm;
1754
1755 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1756
1757 I915_WRITE(FW_BLC, fwater_lo);
1758}
1759
3658729a
VS		 1760static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1761 struct drm_crtc *crtc)
801bcfff
PZ		 1762{
1763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1764 uint32_t pixel_rate;
801bcfff 1765
241bfc38 1766 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 1767
1768 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1769 * adjust the pixel_rate here. */
1770
fd4daa9c 1771 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1772 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1773 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1774
37327abd
VS		 1775 pipe_w = intel_crtc->config.pipe_src_w;
1776 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 1777 pfit_w = (pfit_size >> 16) & 0xFFFF;
1778 pfit_h = pfit_size & 0xFFFF;
1779 if (pipe_w < pfit_w)
1780 pipe_w = pfit_w;
1781 if (pipe_h < pfit_h)
1782 pipe_h = pfit_h;
1783
1784 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1785 pfit_w * pfit_h);
1786 }
1787
1788 return pixel_rate;
1789}
1790
37126462 1791/* latency must be in 0.1us units. */
23297044 1792static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1793 uint32_t latency)
1794{
1795 uint64_t ret;
1796
3312ba65
VS		 1797 if (WARN(latency == 0, "Latency value missing\n"))
1798 return UINT_MAX;
1799
801bcfff
PZ		 1800 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1801 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1802
1803 return ret;
1804}
1805
37126462 1806/* latency must be in 0.1us units. */
23297044 1807static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1808 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1809 uint32_t latency)
1810{
1811 uint32_t ret;
1812
3312ba65
VS		 1813 if (WARN(latency == 0, "Latency value missing\n"))
1814 return UINT_MAX;
1815
801bcfff
PZ		 1816 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1817 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1818 ret = DIV_ROUND_UP(ret, 64) + 2;
1819 return ret;
1820}
1821
23297044 1822static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1823 uint8_t bytes_per_pixel)
1824{
1825 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1826}
1827
820c1980 1828struct ilk_pipe_wm_parameters {
801bcfff 1829 bool active;
801bcfff
PZ		 1830 uint32_t pipe_htotal;
1831 uint32_t pixel_rate;
c35426d2
VS		 1832 struct intel_plane_wm_parameters pri;
1833 struct intel_plane_wm_parameters spr;
1834 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1835};
1836
820c1980 1837struct ilk_wm_maximums {
cca32e9a
PZ		 1838 uint16_t pri;
1839 uint16_t spr;
1840 uint16_t cur;
1841 uint16_t fbc;
1842};
1843
240264f4
VS		 1844/* used in computing the new watermarks state */
1845struct intel_wm_config {
1846 unsigned int num_pipes_active;
1847 bool sprites_enabled;
1848 bool sprites_scaled;
240264f4
VS		 1849};
1850
37126462
VS		 1851/*
1852 * For both WM_PIPE and WM_LP.
1853 * mem_value must be in 0.1us units.
1854 */
820c1980 1855static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1856 uint32_t mem_value,
1857 bool is_lp)
801bcfff 1858{
cca32e9a
PZ		 1859 uint32_t method1, method2;
1860
c35426d2 1861 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1862 return 0;
1863
23297044 1864 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1865 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1866 mem_value);
1867
1868 if (!is_lp)
1869 return method1;
1870
23297044 1871 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1872 params->pipe_htotal,
c35426d2
VS		 1873 params->pri.horiz_pixels,
1874 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1875 mem_value);
1876
1877 return min(method1, method2);
801bcfff
PZ		 1878}
1879
37126462
VS		 1880/*
1881 * For both WM_PIPE and WM_LP.
1882 * mem_value must be in 0.1us units.
1883 */
820c1980 1884static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1885 uint32_t mem_value)
1886{
1887 uint32_t method1, method2;
1888
c35426d2 1889 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1890 return 0;
1891
23297044 1892 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1893 params->spr.bytes_per_pixel,
801bcfff 1894 mem_value);
23297044 1895 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1896 params->pipe_htotal,
c35426d2
VS		 1897 params->spr.horiz_pixels,
1898 params->spr.bytes_per_pixel,
801bcfff
PZ		 1899 mem_value);
1900 return min(method1, method2);
1901}
1902
37126462
VS		 1903/*
1904 * For both WM_PIPE and WM_LP.
1905 * mem_value must be in 0.1us units.
1906 */
820c1980 1907static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1908 uint32_t mem_value)
1909{
c35426d2 1910 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1911 return 0;
1912
23297044 1913 return ilk_wm_method2(params->pixel_rate,
801bcfff 1914 params->pipe_htotal,
c35426d2
VS		 1915 params->cur.horiz_pixels,
1916 params->cur.bytes_per_pixel,
801bcfff
PZ		 1917 mem_value);
1918}
1919
cca32e9a 1920/* Only for WM_LP. */
820c1980 1921static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1922 uint32_t pri_val)
cca32e9a 1923{
c35426d2 1924 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1925 return 0;
1926
23297044 1927 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1928 params->pri.horiz_pixels,
1929 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1930}
1931
158ae64f
VS		 1932static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1933{
416f4727
VS		 1934 if (INTEL_INFO(dev)->gen >= 8)
1935 return 3072;
1936 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1937 return 768;
1938 else
1939 return 512;
1940}
1941
4e975081
VS		 1942static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1943 int level, bool is_sprite)
1944{
1945 if (INTEL_INFO(dev)->gen >= 8)
1946 /* BDW primary/sprite plane watermarks */
1947 return level == 0 ? 255 : 2047;
1948 else if (INTEL_INFO(dev)->gen >= 7)
1949 /* IVB/HSW primary/sprite plane watermarks */
1950 return level == 0 ? 127 : 1023;
1951 else if (!is_sprite)
1952 /* ILK/SNB primary plane watermarks */
1953 return level == 0 ? 127 : 511;
1954 else
1955 /* ILK/SNB sprite plane watermarks */
1956 return level == 0 ? 63 : 255;
1957}
1958
1959static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1960 int level)
1961{
1962 if (INTEL_INFO(dev)->gen >= 7)
1963 return level == 0 ? 63 : 255;
1964 else
1965 return level == 0 ? 31 : 63;
1966}
1967
1968static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1969{
1970 if (INTEL_INFO(dev)->gen >= 8)
1971 return 31;
1972 else
1973 return 15;
1974}
1975
158ae64f
VS		 1976/* Calculate the maximum primary/sprite plane watermark */
1977static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1978 int level,
240264f4 1979 const struct intel_wm_config *config,
158ae64f
VS		 1980 enum intel_ddb_partitioning ddb_partitioning,
1981 bool is_sprite)
1982{
1983 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1984
1985 /* if sprites aren't enabled, sprites get nothing */
240264f4 1986 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1987 return 0;
1988
1989 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1990 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1991 fifo_size /= INTEL_INFO(dev)->num_pipes;
1992
1993 /*
1994 * For some reason the non self refresh
1995 * FIFO size is only half of the self
1996 * refresh FIFO size on ILK/SNB.
1997 */
1998 if (INTEL_INFO(dev)->gen <= 6)
1999 fifo_size /= 2;
2000 }
2001
240264f4 2002 if (config->sprites_enabled) {
158ae64f
VS		 2003 /* level 0 is always calculated with 1:1 split */
2004 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2005 if (is_sprite)
2006 fifo_size *= 5;
2007 fifo_size /= 6;
2008 } else {
2009 fifo_size /= 2;
2010 }
2011 }
2012
2013 /* clamp to max that the registers can hold */
4e975081 2014 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 2015}
2016
2017/* Calculate the maximum cursor plane watermark */
2018static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 2019 int level,
2020 const struct intel_wm_config *config)
158ae64f
VS		 2021{
2022 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 2023 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 2024 return 64;
2025
2026 /* otherwise just report max that registers can hold */
4e975081 2027 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 2028}
2029
d34ff9c6 2030static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 2031 int level,
2032 const struct intel_wm_config *config,
2033 enum intel_ddb_partitioning ddb_partitioning,
820c1980 2034 struct ilk_wm_maximums *max)
158ae64f 2035{
240264f4
VS		 2036 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2037 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2038 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 2039 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 2040}
2041
a3cb4048
VS		 2042static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2043 int level,
2044 struct ilk_wm_maximums *max)
2045{
2046 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2047 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2048 max->cur = ilk_cursor_wm_reg_max(dev, level);
2049 max->fbc = ilk_fbc_wm_reg_max(dev);
2050}
2051
d9395655 2052static bool ilk_validate_wm_level(int level,
820c1980 2053 const struct ilk_wm_maximums *max,
d9395655 2054 struct intel_wm_level *result)
a9786a11
VS		 2055{
2056 bool ret;
2057
2058 /* already determined to be invalid? */
2059 if (!result->enable)
2060 return false;
2061
2062 result->enable = result->pri_val <= max->pri &&
2063 result->spr_val <= max->spr &&
2064 result->cur_val <= max->cur;
2065
2066 ret = result->enable;
2067
2068 /*
2069 * HACK until we can pre-compute everything,
2070 * and thus fail gracefully if LP0 watermarks
2071 * are exceeded...
2072 */
2073 if (level == 0 && !result->enable) {
2074 if (result->pri_val > max->pri)
2075 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2076 level, result->pri_val, max->pri);
2077 if (result->spr_val > max->spr)
2078 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2079 level, result->spr_val, max->spr);
2080 if (result->cur_val > max->cur)
2081 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2082 level, result->cur_val, max->cur);
2083
2084 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2085 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2086 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2087 result->enable = true;
2088 }
2089
a9786a11
VS		 2090 return ret;
2091}
2092
d34ff9c6 2093static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 2094 int level,
820c1980 2095 const struct ilk_pipe_wm_parameters *p,
1fd527cc 2096 struct intel_wm_level *result)
6f5ddd17
VS		 2097{
2098 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2099 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2100 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2101
2102 /* WM1+ latency values stored in 0.5us units */
2103 if (level > 0) {
2104 pri_latency *= 5;
2105 spr_latency *= 5;
2106 cur_latency *= 5;
2107 }
2108
2109 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2110 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2111 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2112 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2113 result->enable = true;
2114}
2115
801bcfff
PZ		 2116static uint32_t
2117hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2118{
2119 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2121 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2122 u32 linetime, ips_linetime;
1f8eeabf 2123
801bcfff
PZ		 2124 if (!intel_crtc_active(crtc))
2125 return 0;
1011d8c4 2126
1f8eeabf
ED		 2127 /* The WM are computed with base on how long it takes to fill a single
2128 * row at the given clock rate, multiplied by 8.
2129 * */
fec8cba3
JB		 2130 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2131 mode->crtc_clock);
2132 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 2133 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2134
801bcfff
PZ		 2135 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2136 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2137}
2138
12b134df
VS		 2139static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2140{
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2142
a42a5719 2143 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2144 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2145
2146 wm[0] = (sskpd >> 56) & 0xFF;
2147 if (wm[0] == 0)
2148 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2149 wm[1] = (sskpd >> 4) & 0xFF;
2150 wm[2] = (sskpd >> 12) & 0xFF;
2151 wm[3] = (sskpd >> 20) & 0x1FF;
2152 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2153 } else if (INTEL_INFO(dev)->gen >= 6) {
2154 uint32_t sskpd = I915_READ(MCH_SSKPD);
2155
2156 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2157 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2158 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2159 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2160 } else if (INTEL_INFO(dev)->gen >= 5) {
2161 uint32_t mltr = I915_READ(MLTR_ILK);
2162
2163 /* ILK primary LP0 latency is 700 ns */
2164 wm[0] = 7;
2165 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2166 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2167 }
2168}
2169
53615a5e
VS		 2170static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2171{
2172 /* ILK sprite LP0 latency is 1300 ns */
2173 if (INTEL_INFO(dev)->gen == 5)
2174 wm[0] = 13;
2175}
2176
2177static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2178{
2179 /* ILK cursor LP0 latency is 1300 ns */
2180 if (INTEL_INFO(dev)->gen == 5)
2181 wm[0] = 13;
2182
2183 /* WaDoubleCursorLP3Latency:ivb */
2184 if (IS_IVYBRIDGE(dev))
2185 wm[3] *= 2;
2186}
2187
546c81fd 2188int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2189{
26ec971e 2190 /* how many WM levels are we expecting */
a42a5719 2191 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2192 return 4;
26ec971e 2193 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2194 return 3;
26ec971e 2195 else
ad0d6dc4
VS		 2196 return 2;
2197}
2198
2199static void intel_print_wm_latency(struct drm_device *dev,
2200 const char *name,
2201 const uint16_t wm[5])
2202{
2203 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2204
2205 for (level = 0; level <= max_level; level++) {
2206 unsigned int latency = wm[level];
2207
2208 if (latency == 0) {
2209 DRM_ERROR("%s WM%d latency not provided\n",
2210 name, level);
2211 continue;
2212 }
2213
2214 /* WM1+ latency values in 0.5us units */
2215 if (level > 0)
2216 latency *= 5;
2217
2218 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2219 name, level, wm[level],
2220 latency / 10, latency % 10);
2221 }
2222}
2223
e95a2f75
VS		 2224static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2225 uint16_t wm[5], uint16_t min)
2226{
2227 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2228
2229 if (wm[0] >= min)
2230 return false;
2231
2232 wm[0] = max(wm[0], min);
2233 for (level = 1; level <= max_level; level++)
2234 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2235
2236 return true;
2237}
2238
2239static void snb_wm_latency_quirk(struct drm_device *dev)
2240{
2241 struct drm_i915_private *dev_priv = dev->dev_private;
2242 bool changed;
2243
2244 /*
2245 * The BIOS provided WM memory latency values are often
2246 * inadequate for high resolution displays. Adjust them.
2247 */
2248 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2249 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2250 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2251
2252 if (!changed)
2253 return;
2254
2255 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2256 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2257 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2258 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2259}
2260
fa50ad61 2261static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2262{
2263 struct drm_i915_private *dev_priv = dev->dev_private;
2264
2265 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2266
2267 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2268 sizeof(dev_priv->wm.pri_latency));
2269 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2270 sizeof(dev_priv->wm.pri_latency));
2271
2272 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2273 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2274
2275 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2276 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2277 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2278
2279 if (IS_GEN6(dev))
2280 snb_wm_latency_quirk(dev);
53615a5e
VS		 2281}
2282
820c1980 2283static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2284 struct ilk_pipe_wm_parameters *p)
1011d8c4 2285{
7c4a395f
VS		 2286 struct drm_device *dev = crtc->dev;
2287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2288 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2289 struct drm_plane *plane;
1011d8c4 2290
2a44b76b
VS		 2291 if (!intel_crtc_active(crtc))
2292 return;
801bcfff 2293
2a44b76b
VS		 2294 p->active = true;
2295 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2296 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2297 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2298 p->cur.bytes_per_pixel = 4;
2299 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2300 p->cur.horiz_pixels = intel_crtc->cursor_width;
2301 /* TODO: for now, assume primary and cursor planes are always enabled. */
2302 p->pri.enabled = true;
2303 p->cur.enabled = true;
7c4a395f 2304
af2b653b 2305 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2306 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2307
2a44b76b 2308 if (intel_plane->pipe == pipe) {
7c4a395f 2309 p->spr = intel_plane->wm;
2a44b76b
VS		 2310 break;
2311 }
2312 }
2313}
2314
2315static void ilk_compute_wm_config(struct drm_device *dev,
2316 struct intel_wm_config *config)
2317{
2318 struct intel_crtc *intel_crtc;
2319
2320 /* Compute the currently _active_ config */
d3fcc808 2321 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2322 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2323
2a44b76b
VS		 2324 if (!wm->pipe_enabled)
2325 continue;
cca32e9a 2326
2a44b76b
VS		 2327 config->sprites_enabled |= wm->sprites_enabled;
2328 config->sprites_scaled |= wm->sprites_scaled;
2329 config->num_pipes_active++;
cca32e9a 2330 }
801bcfff
PZ		 2331}
2332
0b2ae6d7
VS		 2333/* Compute new watermarks for the pipe */
2334static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2335 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2336 struct intel_pipe_wm *pipe_wm)
2337{
2338 struct drm_device *dev = crtc->dev;
d34ff9c6 2339 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2340 int level, max_level = ilk_wm_max_level(dev);
2341 /* LP0 watermark maximums depend on this pipe alone */
2342 struct intel_wm_config config = {
2343 .num_pipes_active = 1,
2344 .sprites_enabled = params->spr.enabled,
2345 .sprites_scaled = params->spr.scaled,
2346 };
820c1980 2347 struct ilk_wm_maximums max;
0b2ae6d7 2348
2a44b76b
VS		 2349 pipe_wm->pipe_enabled = params->active;
2350 pipe_wm->sprites_enabled = params->spr.enabled;
2351 pipe_wm->sprites_scaled = params->spr.scaled;
2352
7b39a0b7
VS		 2353 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2354 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2355 max_level = 1;
2356
2357 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2358 if (params->spr.scaled)
2359 max_level = 0;
2360
a3cb4048 2361 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2362
a42a5719 2363 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2364 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2365
a3cb4048
VS		 2366 /* LP0 watermarks always use 1/2 DDB partitioning */
2367 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2368
0b2ae6d7 2369 /* At least LP0 must be valid */
a3cb4048
VS		 2370 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2371 return false;
2372
2373 ilk_compute_wm_reg_maximums(dev, 1, &max);
2374
2375 for (level = 1; level <= max_level; level++) {
2376 struct intel_wm_level wm = {};
2377
2378 ilk_compute_wm_level(dev_priv, level, params, &wm);
2379
2380 /*
2381 * Disable any watermark level that exceeds the
2382 * register maximums since such watermarks are
2383 * always invalid.
2384 */
2385 if (!ilk_validate_wm_level(level, &max, &wm))
2386 break;
2387
2388 pipe_wm->wm[level] = wm;
2389 }
2390
2391 return true;
0b2ae6d7
VS		 2392}
2393
2394/*
2395 * Merge the watermarks from all active pipes for a specific level.
2396 */
2397static void ilk_merge_wm_level(struct drm_device *dev,
2398 int level,
2399 struct intel_wm_level *ret_wm)
2400{
2401 const struct intel_crtc *intel_crtc;
2402
d52fea5b
VS		 2403 ret_wm->enable = true;
2404
d3fcc808 2405 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2406 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2407 const struct intel_wm_level *wm = &active->wm[level];
2408
2409 if (!active->pipe_enabled)
2410 continue;
0b2ae6d7 2411
d52fea5b
VS		 2412 /*
2413 * The watermark values may have been used in the past,
2414 * so we must maintain them in the registers for some
2415 * time even if the level is now disabled.
2416 */
0b2ae6d7 2417 if (!wm->enable)
d52fea5b 2418 ret_wm->enable = false;
0b2ae6d7
VS		 2419
2420 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2421 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2422 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2423 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2424 }
0b2ae6d7
VS		 2425}
2426
2427/*
2428 * Merge all low power watermarks for all active pipes.
2429 */
2430static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2431 const struct intel_wm_config *config,
820c1980 2432 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2433 struct intel_pipe_wm *merged)
2434{
2435 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2436 int last_enabled_level = max_level;
0b2ae6d7 2437
0ba22e26
VS		 2438 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2439 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2440 config->num_pipes_active > 1)
2441 return;
2442
6c8b6c28
VS		 2443 /* ILK: FBC WM must be disabled always */
2444 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2445
2446 /* merge each WM1+ level */
2447 for (level = 1; level <= max_level; level++) {
2448 struct intel_wm_level *wm = &merged->wm[level];
2449
2450 ilk_merge_wm_level(dev, level, wm);
2451
d52fea5b
VS		 2452 if (level > last_enabled_level)
2453 wm->enable = false;
2454 else if (!ilk_validate_wm_level(level, max, wm))
2455 /* make sure all following levels get disabled */
2456 last_enabled_level = level - 1;
0b2ae6d7
VS		 2457
2458 /*
2459 * The spec says it is preferred to disable
2460 * FBC WMs instead of disabling a WM level.
2461 */
2462 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2463 if (wm->enable)
2464 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2465 wm->fbc_val = 0;
2466 }
2467 }
6c8b6c28
VS		 2468
2469 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2470 /*
2471 * FIXME this is racy. FBC might get enabled later.
2472 * What we should check here is whether FBC can be
2473 * enabled sometime later.
2474 */
2475 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2476 for (level = 2; level <= max_level; level++) {
2477 struct intel_wm_level *wm = &merged->wm[level];
2478
2479 wm->enable = false;
2480 }
2481 }
0b2ae6d7
VS		 2482}
2483
b380ca3c
VS		 2484static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2485{
2486 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2487 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2488}
2489
a68d68ee
VS		 2490/* The value we need to program into the WM_LPx latency field */
2491static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2492{
2493 struct drm_i915_private *dev_priv = dev->dev_private;
2494
a42a5719 2495 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2496 return 2 * level;
2497 else
2498 return dev_priv->wm.pri_latency[level];
2499}
2500
820c1980 2501static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2502 const struct intel_pipe_wm *merged,
609cedef 2503 enum intel_ddb_partitioning partitioning,
820c1980 2504 struct ilk_wm_values *results)
801bcfff 2505{
0b2ae6d7
VS		 2506 struct intel_crtc *intel_crtc;
2507 int level, wm_lp;
cca32e9a 2508
0362c781 2509 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2510 results->partitioning = partitioning;
cca32e9a 2511
0b2ae6d7 2512 /* LP1+ register values */
cca32e9a 2513 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2514 const struct intel_wm_level *r;
801bcfff 2515
b380ca3c 2516 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2517
0362c781 2518 r = &merged->wm[level];
cca32e9a 2519
d52fea5b
VS		 2520 /*
2521 * Maintain the watermark values even if the level is
2522 * disabled. Doing otherwise could cause underruns.
2523 */
2524 results->wm_lp[wm_lp - 1] =
a68d68ee 2525 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2526 (r->pri_val << WM1_LP_SR_SHIFT) |
2527 r->cur_val;
2528
d52fea5b
VS		 2529 if (r->enable)
2530 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2531
416f4727
VS		 2532 if (INTEL_INFO(dev)->gen >= 8)
2533 results->wm_lp[wm_lp - 1] |=
2534 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2535 else
2536 results->wm_lp[wm_lp - 1] |=
2537 r->fbc_val << WM1_LP_FBC_SHIFT;
2538
d52fea5b
VS		 2539 /*
2540 * Always set WM1S_LP_EN when spr_val != 0, even if the
2541 * level is disabled. Doing otherwise could cause underruns.
2542 */
6cef2b8a
VS		 2543 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2544 WARN_ON(wm_lp != 1);
2545 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2546 } else
2547 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2548 }
801bcfff 2549
0b2ae6d7 2550 /* LP0 register values */
d3fcc808 2551 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2552 enum pipe pipe = intel_crtc->pipe;
2553 const struct intel_wm_level *r =
2554 &intel_crtc->wm.active.wm[0];
2555
2556 if (WARN_ON(!r->enable))
2557 continue;
2558
2559 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2560
0b2ae6d7
VS		 2561 results->wm_pipe[pipe] =
2562 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2563 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2564 r->cur_val;
801bcfff
PZ		 2565 }
2566}
2567
861f3389
PZ		 2568/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2569 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2570static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2571 struct intel_pipe_wm *r1,
2572 struct intel_pipe_wm *r2)
861f3389 2573{
198a1e9b
VS		 2574 int level, max_level = ilk_wm_max_level(dev);
2575 int level1 = 0, level2 = 0;
861f3389 2576
198a1e9b
VS		 2577 for (level = 1; level <= max_level; level++) {
2578 if (r1->wm[level].enable)
2579 level1 = level;
2580 if (r2->wm[level].enable)
2581 level2 = level;
861f3389
PZ		 2582 }
2583
198a1e9b
VS		 2584 if (level1 == level2) {
2585 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2586 return r2;
2587 else
2588 return r1;
198a1e9b 2589 } else if (level1 > level2) {
861f3389
PZ		 2590 return r1;
2591 } else {
2592 return r2;
2593 }
2594}
2595
49a687c4
VS		 2596/* dirty bits used to track which watermarks need changes */
2597#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2598#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2599#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2600#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2601#define WM_DIRTY_FBC (1 << 24)
2602#define WM_DIRTY_DDB (1 << 25)
2603
2604static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
820c1980
ID		 2605 const struct ilk_wm_values *old,
2606 const struct ilk_wm_values *new)
49a687c4
VS		 2607{
2608 unsigned int dirty = 0;
2609 enum pipe pipe;
2610 int wm_lp;
2611
2612 for_each_pipe(pipe) {
2613 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2614 dirty |= WM_DIRTY_LINETIME(pipe);
2615 /* Must disable LP1+ watermarks too */
2616 dirty |= WM_DIRTY_LP_ALL;
2617 }
2618
2619 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2620 dirty |= WM_DIRTY_PIPE(pipe);
2621 /* Must disable LP1+ watermarks too */
2622 dirty |= WM_DIRTY_LP_ALL;
2623 }
2624 }
2625
2626 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2627 dirty |= WM_DIRTY_FBC;
2628 /* Must disable LP1+ watermarks too */
2629 dirty |= WM_DIRTY_LP_ALL;
2630 }
2631
2632 if (old->partitioning != new->partitioning) {
2633 dirty |= WM_DIRTY_DDB;
2634 /* Must disable LP1+ watermarks too */
2635 dirty |= WM_DIRTY_LP_ALL;
2636 }
2637
2638 /* LP1+ watermarks already deemed dirty, no need to continue */
2639 if (dirty & WM_DIRTY_LP_ALL)
2640 return dirty;
2641
2642 /* Find the lowest numbered LP1+ watermark in need of an update... */
2643 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2644 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2645 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2646 break;
2647 }
2648
2649 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2650 for (; wm_lp <= 3; wm_lp++)
2651 dirty |= WM_DIRTY_LP(wm_lp);
2652
2653 return dirty;
2654}
2655
8553c18e
VS		 2656static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2657 unsigned int dirty)
801bcfff 2658{
820c1980 2659 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2660 bool changed = false;
801bcfff 2661
facd619b
VS		 2662 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2663 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2664 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2665 changed = true;
facd619b
VS		 2666 }
2667 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2668 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2669 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2670 changed = true;
facd619b
VS		 2671 }
2672 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2673 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2674 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2675 changed = true;
facd619b 2676 }
801bcfff 2677
facd619b
VS		 2678 /*
2679 * Don't touch WM1S_LP_EN here.
2680 * Doing so could cause underruns.
2681 */
6cef2b8a 2682
8553c18e
VS		 2683 return changed;
2684}
2685
2686/*
2687 * The spec says we shouldn't write when we don't need, because every write
2688 * causes WMs to be re-evaluated, expending some power.
2689 */
820c1980
ID		 2690static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2691 struct ilk_wm_values *results)
8553c18e
VS		 2692{
2693 struct drm_device *dev = dev_priv->dev;
820c1980 2694 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2695 unsigned int dirty;
2696 uint32_t val;
2697
2698 dirty = ilk_compute_wm_dirty(dev, previous, results);
2699 if (!dirty)
2700 return;
2701
2702 _ilk_disable_lp_wm(dev_priv, dirty);
2703
49a687c4 2704 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2705 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2706 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2707 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2708 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2709 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2710
49a687c4 2711 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2712 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2713 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2714 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2715 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2716 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2717
49a687c4 2718 if (dirty & WM_DIRTY_DDB) {
a42a5719 2719 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2720 val = I915_READ(WM_MISC);
2721 if (results->partitioning == INTEL_DDB_PART_1_2)
2722 val &= ~WM_MISC_DATA_PARTITION_5_6;
2723 else
2724 val |= WM_MISC_DATA_PARTITION_5_6;
2725 I915_WRITE(WM_MISC, val);
2726 } else {
2727 val = I915_READ(DISP_ARB_CTL2);
2728 if (results->partitioning == INTEL_DDB_PART_1_2)
2729 val &= ~DISP_DATA_PARTITION_5_6;
2730 else
2731 val |= DISP_DATA_PARTITION_5_6;
2732 I915_WRITE(DISP_ARB_CTL2, val);
2733 }
1011d8c4
PZ		 2734 }
2735
49a687c4 2736 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2737 val = I915_READ(DISP_ARB_CTL);
2738 if (results->enable_fbc_wm)
2739 val &= ~DISP_FBC_WM_DIS;
2740 else
2741 val |= DISP_FBC_WM_DIS;
2742 I915_WRITE(DISP_ARB_CTL, val);
2743 }
2744
954911eb
ID		 2745 if (dirty & WM_DIRTY_LP(1) &&
2746 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2747 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2748
2749 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2750 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2751 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2752 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2753 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2754 }
801bcfff 2755
facd619b 2756 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2757 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2758 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2759 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2760 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2761 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2762
2763 dev_priv->wm.hw = *results;
801bcfff
PZ		 2764}
2765
8553c18e
VS		 2766static bool ilk_disable_lp_wm(struct drm_device *dev)
2767{
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769
2770 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2771}
2772
820c1980 2773static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 2774{
7c4a395f 2775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2776 struct drm_device *dev = crtc->dev;
801bcfff 2777 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 2778 struct ilk_wm_maximums max;
2779 struct ilk_pipe_wm_parameters params = {};
2780 struct ilk_wm_values results = {};
77c122bc 2781 enum intel_ddb_partitioning partitioning;
7c4a395f 2782 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2783 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2784 struct intel_wm_config config = {};
7c4a395f 2785
2a44b76b 2786 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 2787
2788 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2789
2790 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2791 return;
861f3389 2792
7c4a395f 2793 intel_crtc->wm.active = pipe_wm;
861f3389 2794
2a44b76b
VS		 2795 ilk_compute_wm_config(dev, &config);
2796
34982fe1 2797 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 2798 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 2799
2800 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2801 if (INTEL_INFO(dev)->gen >= 7 &&
2802 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2803 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 2804 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 2805
820c1980 2806 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2807 } else {
198a1e9b 2808 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2809 }
2810
198a1e9b 2811 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2812 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2813
820c1980 2814 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 2815
820c1980 2816 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2817}
2818
ed57cb8a
DL		 2819static void
2820ilk_update_sprite_wm(struct drm_plane *plane,
2821 struct drm_crtc *crtc,
2822 uint32_t sprite_width, uint32_t sprite_height,
2823 int pixel_size, bool enabled, bool scaled)
526682e9 2824{
8553c18e 2825 struct drm_device *dev = plane->dev;
adf3d35e 2826 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2827
adf3d35e
VS		 2828 intel_plane->wm.enabled = enabled;
2829 intel_plane->wm.scaled = scaled;
2830 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 2831 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 2832 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2833
8553c18e
VS		 2834 /*
2835 * IVB workaround: must disable low power watermarks for at least
2836 * one frame before enabling scaling. LP watermarks can be re-enabled
2837 * when scaling is disabled.
2838 *
2839 * WaCxSRDisabledForSpriteScaling:ivb
2840 */
2841 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2842 intel_wait_for_vblank(dev, intel_plane->pipe);
2843
820c1980 2844 ilk_update_wm(crtc);
526682e9
PZ		 2845}
2846
243e6a44
VS		 2847static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2848{
2849 struct drm_device *dev = crtc->dev;
2850 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2851 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2853 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2854 enum pipe pipe = intel_crtc->pipe;
2855 static const unsigned int wm0_pipe_reg[] = {
2856 [PIPE_A] = WM0_PIPEA_ILK,
2857 [PIPE_B] = WM0_PIPEB_ILK,
2858 [PIPE_C] = WM0_PIPEC_IVB,
2859 };
2860
2861 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 2862 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2863 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 2864
2a44b76b
VS		 2865 active->pipe_enabled = intel_crtc_active(crtc);
2866
2867 if (active->pipe_enabled) {
243e6a44
VS		 2868 u32 tmp = hw->wm_pipe[pipe];
2869
2870 /*
2871 * For active pipes LP0 watermark is marked as
2872 * enabled, and LP1+ watermaks as disabled since
2873 * we can't really reverse compute them in case
2874 * multiple pipes are active.
2875 */
2876 active->wm[0].enable = true;
2877 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2878 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2879 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2880 active->linetime = hw->wm_linetime[pipe];
2881 } else {
2882 int level, max_level = ilk_wm_max_level(dev);
2883
2884 /*
2885 * For inactive pipes, all watermark levels
2886 * should be marked as enabled but zeroed,
2887 * which is what we'd compute them to.
2888 */
2889 for (level = 0; level <= max_level; level++)
2890 active->wm[level].enable = true;
2891 }
2892}
2893
2894void ilk_wm_get_hw_state(struct drm_device *dev)
2895{
2896 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2897 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2898 struct drm_crtc *crtc;
2899
70e1e0ec 2900 for_each_crtc(dev, crtc)
243e6a44
VS		 2901 ilk_pipe_wm_get_hw_state(crtc);
2902
2903 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2904 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2905 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2906
2907 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 2908 if (INTEL_INFO(dev)->gen >= 7) {
2909 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2910 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2911 }
243e6a44 2912
a42a5719 2913 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 2914 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2915 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2916 else if (IS_IVYBRIDGE(dev))
2917 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2918 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 2919
2920 hw->enable_fbc_wm =
2921 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2922}
2923
b445e3b0
ED		 2924/**
2925 * intel_update_watermarks - update FIFO watermark values based on current modes
2926 *
2927 * Calculate watermark values for the various WM regs based on current mode
2928 * and plane configuration.
2929 *
2930 * There are several cases to deal with here:
2931 * - normal (i.e. non-self-refresh)
2932 * - self-refresh (SR) mode
2933 * - lines are large relative to FIFO size (buffer can hold up to 2)
2934 * - lines are small relative to FIFO size (buffer can hold more than 2
2935 * lines), so need to account for TLB latency
2936 *
2937 * The normal calculation is:
2938 * watermark = dotclock * bytes per pixel * latency
2939 * where latency is platform & configuration dependent (we assume pessimal
2940 * values here).
2941 *
2942 * The SR calculation is:
2943 * watermark = (trunc(latency/line time)+1) * surface width *
2944 * bytes per pixel
2945 * where
2946 * line time = htotal / dotclock
2947 * surface width = hdisplay for normal plane and 64 for cursor
2948 * and latency is assumed to be high, as above.
2949 *
2950 * The final value programmed to the register should always be rounded up,
2951 * and include an extra 2 entries to account for clock crossings.
2952 *
2953 * We don't use the sprite, so we can ignore that. And on Crestline we have
2954 * to set the non-SR watermarks to 8.
2955 */
46ba614c 2956void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 2957{
46ba614c 2958 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 2959
2960 if (dev_priv->display.update_wm)
46ba614c 2961 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 2962}
2963
adf3d35e
VS		 2964void intel_update_sprite_watermarks(struct drm_plane *plane,
2965 struct drm_crtc *crtc,
ed57cb8a
DL		 2966 uint32_t sprite_width,
2967 uint32_t sprite_height,
2968 int pixel_size,
39db4a4d 2969 bool enabled, bool scaled)
b445e3b0 2970{
adf3d35e 2971 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 2972
2973 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 2974 dev_priv->display.update_sprite_wm(plane, crtc,
2975 sprite_width, sprite_height,
39db4a4d 2976 pixel_size, enabled, scaled);
b445e3b0
ED		 2977}
2978
2b4e57bd
ED		 2979static struct drm_i915_gem_object *
2980intel_alloc_context_page(struct drm_device *dev)
2981{
2982 struct drm_i915_gem_object *ctx;
2983 int ret;
2984
2985 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2986
2987 ctx = i915_gem_alloc_object(dev, 4096);
2988 if (!ctx) {
2989 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2990 return NULL;
2991 }
2992
c69766f2 2993 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2b4e57bd
ED		 2994 if (ret) {
2995 DRM_ERROR("failed to pin power context: %d\n", ret);
2996 goto err_unref;
2997 }
2998
2999 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3000 if (ret) {
3001 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3002 goto err_unpin;
3003 }
3004
3005 return ctx;
3006
3007err_unpin:
d7f46fc4 3008 i915_gem_object_ggtt_unpin(ctx);
2b4e57bd
ED		 3009err_unref:
3010 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 3011 return NULL;
3012}
3013
9270388e
DV		 3014/**
3015 * Lock protecting IPS related data structures
9270388e
DV		 3016 */
3017DEFINE_SPINLOCK(mchdev_lock);
3018
3019/* Global for IPS driver to get at the current i915 device. Protected by
3020 * mchdev_lock. */
3021static struct drm_i915_private *i915_mch_dev;
3022
2b4e57bd
ED		 3023bool ironlake_set_drps(struct drm_device *dev, u8 val)
3024{
3025 struct drm_i915_private *dev_priv = dev->dev_private;
3026 u16 rgvswctl;
3027
9270388e
DV		 3028 assert_spin_locked(&mchdev_lock);
3029
2b4e57bd
ED		 3030 rgvswctl = I915_READ16(MEMSWCTL);
3031 if (rgvswctl & MEMCTL_CMD_STS) {
3032 DRM_DEBUG("gpu busy, RCS change rejected\n");
3033 return false; /* still busy with another command */
3034 }
3035
3036 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3037 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3038 I915_WRITE16(MEMSWCTL, rgvswctl);
3039 POSTING_READ16(MEMSWCTL);
3040
3041 rgvswctl |= MEMCTL_CMD_STS;
3042 I915_WRITE16(MEMSWCTL, rgvswctl);
3043
3044 return true;
3045}
3046
8090c6b9 3047static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3048{
3049 struct drm_i915_private *dev_priv = dev->dev_private;
3050 u32 rgvmodectl = I915_READ(MEMMODECTL);
3051 u8 fmax, fmin, fstart, vstart;
3052
9270388e
DV		 3053 spin_lock_irq(&mchdev_lock);
3054
2b4e57bd
ED		 3055 /* Enable temp reporting */
3056 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3057 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3058
3059 /* 100ms RC evaluation intervals */
3060 I915_WRITE(RCUPEI, 100000);
3061 I915_WRITE(RCDNEI, 100000);
3062
3063 /* Set max/min thresholds to 90ms and 80ms respectively */
3064 I915_WRITE(RCBMAXAVG, 90000);
3065 I915_WRITE(RCBMINAVG, 80000);
3066
3067 I915_WRITE(MEMIHYST, 1);
3068
3069 /* Set up min, max, and cur for interrupt handling */
3070 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3071 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3072 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3073 MEMMODE_FSTART_SHIFT;
3074
3075 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3076 PXVFREQ_PX_SHIFT;
3077
20e4d407
DV		 3078 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3079 dev_priv->ips.fstart = fstart;
2b4e57bd 3080
20e4d407
DV		 3081 dev_priv->ips.max_delay = fstart;
3082 dev_priv->ips.min_delay = fmin;
3083 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3084
3085 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3086 fmax, fmin, fstart);
3087
3088 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3089
3090 /*
3091 * Interrupts will be enabled in ironlake_irq_postinstall
3092 */
3093
3094 I915_WRITE(VIDSTART, vstart);
3095 POSTING_READ(VIDSTART);
3096
3097 rgvmodectl |= MEMMODE_SWMODE_EN;
3098 I915_WRITE(MEMMODECTL, rgvmodectl);
3099
9270388e 3100 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3101 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3102 mdelay(1);
2b4e57bd
ED		 3103
3104 ironlake_set_drps(dev, fstart);
3105
20e4d407 3106 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3107 I915_READ(0x112e0);
20e4d407
DV		 3108 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3109 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3110 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 3111
3112 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3113}
3114
8090c6b9 3115static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3116{
3117 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3118 u16 rgvswctl;
3119
3120 spin_lock_irq(&mchdev_lock);
3121
3122 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3123
3124 /* Ack interrupts, disable EFC interrupt */
3125 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3126 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3127 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3128 I915_WRITE(DEIIR, DE_PCU_EVENT);
3129 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3130
3131 /* Go back to the starting frequency */
20e4d407 3132 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3133 mdelay(1);
2b4e57bd
ED		 3134 rgvswctl |= MEMCTL_CMD_STS;
3135 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3136 mdelay(1);
2b4e57bd 3137
9270388e 3138 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3139}
3140
acbe9475
DV		 3141/* There's a funny hw issue where the hw returns all 0 when reading from
3142 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3143 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3144 * all limits and the gpu stuck at whatever frequency it is at atm).
3145 */
6917c7b9 3146static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3147{
7b9e0ae6 3148 u32 limits;
2b4e57bd 3149
20b46e59
DV		 3150 /* Only set the down limit when we've reached the lowest level to avoid
3151 * getting more interrupts, otherwise leave this clear. This prevents a
3152 * race in the hw when coming out of rc6: There's a tiny window where
3153 * the hw runs at the minimal clock before selecting the desired
3154 * frequency, if the down threshold expires in that window we will not
3155 * receive a down interrupt. */
b39fb297
BW		 3156 limits = dev_priv->rps.max_freq_softlimit << 24;
3157 if (val <= dev_priv->rps.min_freq_softlimit)
3158 limits |= dev_priv->rps.min_freq_softlimit << 16;
20b46e59
DV		 3159
3160 return limits;
3161}
3162
dd75fdc8
CW		 3163static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3164{
3165 int new_power;
3166
3167 new_power = dev_priv->rps.power;
3168 switch (dev_priv->rps.power) {
3169 case LOW_POWER:
b39fb297 3170 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3171 new_power = BETWEEN;
3172 break;
3173
3174 case BETWEEN:
b39fb297 3175 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3176 new_power = LOW_POWER;
b39fb297 3177 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3178 new_power = HIGH_POWER;
3179 break;
3180
3181 case HIGH_POWER:
b39fb297 3182 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3183 new_power = BETWEEN;
3184 break;
3185 }
3186 /* Max/min bins are special */
b39fb297 3187 if (val == dev_priv->rps.min_freq_softlimit)
dd75fdc8 3188 new_power = LOW_POWER;
b39fb297 3189 if (val == dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3190 new_power = HIGH_POWER;
3191 if (new_power == dev_priv->rps.power)
3192 return;
3193
3194 /* Note the units here are not exactly 1us, but 1280ns. */
3195 switch (new_power) {
3196 case LOW_POWER:
3197 /* Upclock if more than 95% busy over 16ms */
3198 I915_WRITE(GEN6_RP_UP_EI, 12500);
3199 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3200
3201 /* Downclock if less than 85% busy over 32ms */
3202 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3203 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3204
3205 I915_WRITE(GEN6_RP_CONTROL,
3206 GEN6_RP_MEDIA_TURBO |
3207 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3208 GEN6_RP_MEDIA_IS_GFX |
3209 GEN6_RP_ENABLE |
3210 GEN6_RP_UP_BUSY_AVG |
3211 GEN6_RP_DOWN_IDLE_AVG);
3212 break;
3213
3214 case BETWEEN:
3215 /* Upclock if more than 90% busy over 13ms */
3216 I915_WRITE(GEN6_RP_UP_EI, 10250);
3217 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3218
3219 /* Downclock if less than 75% busy over 32ms */
3220 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3221 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3222
3223 I915_WRITE(GEN6_RP_CONTROL,
3224 GEN6_RP_MEDIA_TURBO |
3225 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3226 GEN6_RP_MEDIA_IS_GFX |
3227 GEN6_RP_ENABLE |
3228 GEN6_RP_UP_BUSY_AVG |
3229 GEN6_RP_DOWN_IDLE_AVG);
3230 break;
3231
3232 case HIGH_POWER:
3233 /* Upclock if more than 85% busy over 10ms */
3234 I915_WRITE(GEN6_RP_UP_EI, 8000);
3235 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3236
3237 /* Downclock if less than 60% busy over 32ms */
3238 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3239 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3240
3241 I915_WRITE(GEN6_RP_CONTROL,
3242 GEN6_RP_MEDIA_TURBO |
3243 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3244 GEN6_RP_MEDIA_IS_GFX |
3245 GEN6_RP_ENABLE |
3246 GEN6_RP_UP_BUSY_AVG |
3247 GEN6_RP_DOWN_IDLE_AVG);
3248 break;
3249 }
3250
3251 dev_priv->rps.power = new_power;
3252 dev_priv->rps.last_adj = 0;
3253}
3254
2876ce73
CW		 3255static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3256{
3257 u32 mask = 0;
3258
3259 if (val > dev_priv->rps.min_freq_softlimit)
3260 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3261 if (val < dev_priv->rps.max_freq_softlimit)
3262 mask |= GEN6_PM_RP_UP_THRESHOLD;
3263
7b3c29f6
CW		 3264 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3265 mask &= dev_priv->pm_rps_events;
3266
2876ce73
CW		 3267 /* IVB and SNB hard hangs on looping batchbuffer
3268 * if GEN6_PM_UP_EI_EXPIRED is masked.
3269 */
3270 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3271 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3272
baccd458
D		 3273 if (IS_GEN8(dev_priv->dev))
3274 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3275
2876ce73
CW		 3276 return ~mask;
3277}
3278
b8a5ff8d
JM		 3279/* gen6_set_rps is called to update the frequency request, but should also be
3280 * called when the range (min_delay and max_delay) is modified so that we can
3281 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
20b46e59
DV		 3282void gen6_set_rps(struct drm_device *dev, u8 val)
3283{
3284 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3285
4fc688ce 3286 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3287 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3288 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
004777cb 3289
eb64cad1
CW		 3290 /* min/max delay may still have been modified so be sure to
3291 * write the limits value.
3292 */
3293 if (val != dev_priv->rps.cur_freq) {
3294 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3295
50e6a2a7 3296 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3297 I915_WRITE(GEN6_RPNSWREQ,
3298 HSW_FREQUENCY(val));
3299 else
3300 I915_WRITE(GEN6_RPNSWREQ,
3301 GEN6_FREQUENCY(val) |
3302 GEN6_OFFSET(0) |
3303 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3304 }
7b9e0ae6 3305
7b9e0ae6
CW		 3306 /* Make sure we continue to get interrupts
3307 * until we hit the minimum or maximum frequencies.
3308 */
eb64cad1 3309 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
2876ce73 3310 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3311
d5570a72
BW		 3312 POSTING_READ(GEN6_RPNSWREQ);
3313
b39fb297 3314 dev_priv->rps.cur_freq = val;
be2cde9a 3315 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3316}
3317
76c3552f
D		 3318/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3319 *
3320 * * If Gfx is Idle, then
3321 * 1. Mask Turbo interrupts
3322 * 2. Bring up Gfx clock
3323 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3324 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3325 * 5. Unmask Turbo interrupts
3326*/
3327static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3328{
5549d25f
D		 3329 struct drm_device *dev = dev_priv->dev;
3330
3331 /* Latest VLV doesn't need to force the gfx clock */
3332 if (dev->pdev->revision >= 0xd) {
3333 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3334 return;
3335 }
3336
76c3552f
D		 3337 /*
3338 * When we are idle. Drop to min voltage state.
3339 */
3340
b39fb297 3341 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
76c3552f
D		 3342 return;
3343
3344 /* Mask turbo interrupt so that they will not come in between */
3345 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3346
650ad970 3347 vlv_force_gfx_clock(dev_priv, true);
76c3552f 3348
b39fb297 3349 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
76c3552f
D		 3350
3351 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
b39fb297 3352 dev_priv->rps.min_freq_softlimit);
76c3552f
D		 3353
3354 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3355 & GENFREQSTATUS) == 0, 5))
3356 DRM_ERROR("timed out waiting for Punit\n");
3357
650ad970 3358 vlv_force_gfx_clock(dev_priv, false);
76c3552f 3359
7b3c29f6
CW		 3360 I915_WRITE(GEN6_PMINTRMSK,
3361 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
76c3552f
D		 3362}
3363
b29c19b6
CW		 3364void gen6_rps_idle(struct drm_i915_private *dev_priv)
3365{
691bb717
DL		 3366 struct drm_device *dev = dev_priv->dev;
3367
b29c19b6 3368 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3369 if (dev_priv->rps.enabled) {
34638118
D		 3370 if (IS_CHERRYVIEW(dev))
3371 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3372 else if (IS_VALLEYVIEW(dev))
76c3552f 3373 vlv_set_rps_idle(dev_priv);
c0951f0c 3374 else
b39fb297 3375 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
c0951f0c
CW		 3376 dev_priv->rps.last_adj = 0;
3377 }
b29c19b6
CW		 3378 mutex_unlock(&dev_priv->rps.hw_lock);
3379}
3380
3381void gen6_rps_boost(struct drm_i915_private *dev_priv)
3382{
691bb717
DL		 3383 struct drm_device *dev = dev_priv->dev;
3384
b29c19b6 3385 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3386 if (dev_priv->rps.enabled) {
691bb717 3387 if (IS_VALLEYVIEW(dev))
b39fb297 3388 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c 3389 else
b39fb297 3390 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c
CW		 3391 dev_priv->rps.last_adj = 0;
3392 }
b29c19b6
CW		 3393 mutex_unlock(&dev_priv->rps.hw_lock);
3394}
3395
0a073b84
JB		 3396void valleyview_set_rps(struct drm_device *dev, u8 val)
3397{
3398 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3399
0a073b84 3400 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3401 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3402 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
0a073b84 3403
73008b98 3404 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
b39fb297
BW		 3405 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3406 dev_priv->rps.cur_freq,
2ec3815f 3407 vlv_gpu_freq(dev_priv, val), val);
0a073b84 3408
2876ce73
CW		 3409 if (val != dev_priv->rps.cur_freq)
3410 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3411
09c87db8 3412 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
0a073b84 3413
b39fb297 3414 dev_priv->rps.cur_freq = val;
2ec3815f 3415 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3416}
3417
0961021a
BW		 3418static void gen8_disable_rps_interrupts(struct drm_device *dev)
3419{
3420 struct drm_i915_private *dev_priv = dev->dev_private;
3421
992f191f 3422 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
0961021a
BW		 3423 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3424 ~dev_priv->pm_rps_events);
3425 /* Complete PM interrupt masking here doesn't race with the rps work
3426 * item again unmasking PM interrupts because that is using a different
3427 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3428 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3429 * gen8_enable_rps will clean up. */
3430
3431 spin_lock_irq(&dev_priv->irq_lock);
3432 dev_priv->rps.pm_iir = 0;
3433 spin_unlock_irq(&dev_priv->irq_lock);
3434
3435 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3436}
3437
44fc7d5c 3438static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3439{
3440 struct drm_i915_private *dev_priv = dev->dev_private;
3441
2b4e57bd 3442 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
a6706b45
D		 3443 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3444 ~dev_priv->pm_rps_events);
2b4e57bd
ED		 3445 /* Complete PM interrupt masking here doesn't race with the rps work
3446 * item again unmasking PM interrupts because that is using a different
3447 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3448 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3449
59cdb63d 3450 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3451 dev_priv->rps.pm_iir = 0;
59cdb63d 3452 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3453
a6706b45 3454 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
2b4e57bd
ED		 3455}
3456
44fc7d5c 3457static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3458{
3459 struct drm_i915_private *dev_priv = dev->dev_private;
3460
3461 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3462 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3463
0961021a
BW		 3464 if (IS_BROADWELL(dev))
3465 gen8_disable_rps_interrupts(dev);
3466 else
3467 gen6_disable_rps_interrupts(dev);
44fc7d5c
DV		 3468}
3469
38807746
D		 3470static void cherryview_disable_rps(struct drm_device *dev)
3471{
3472 struct drm_i915_private *dev_priv = dev->dev_private;
3473
3474 I915_WRITE(GEN6_RC_CONTROL, 0);
3497a562
D		 3475
3476 gen8_disable_rps_interrupts(dev);
38807746
D		 3477}
3478
44fc7d5c
DV		 3479static void valleyview_disable_rps(struct drm_device *dev)
3480{
3481 struct drm_i915_private *dev_priv = dev->dev_private;
3482
3483 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3484
44fc7d5c 3485 gen6_disable_rps_interrupts(dev);
d20d4f0c
JB		 3486}
3487
dc39fff7
BW		 3488static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3489{
91ca689a
ID		 3490 if (IS_VALLEYVIEW(dev)) {
3491 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3492 mode = GEN6_RC_CTL_RC6_ENABLE;
3493 else
3494 mode = 0;
3495 }
8dfd1f04
DV		 3496 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3497 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3498 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3499 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
dc39fff7
BW		 3500}
3501
e6069ca8 3502static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 3503{
eb4926e4
DL		 3504 /* No RC6 before Ironlake */
3505 if (INTEL_INFO(dev)->gen < 5)
3506 return 0;
3507
e6069ca8
ID		 3508 /* RC6 is only on Ironlake mobile not on desktop */
3509 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3510 return 0;
3511
456470eb 3512 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 3513 if (enable_rc6 >= 0) {
3514 int mask;
3515
3516 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3517 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3518 INTEL_RC6pp_ENABLE;
3519 else
3520 mask = INTEL_RC6_ENABLE;
3521
3522 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 3523 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3524 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 3525
3526 return enable_rc6 & mask;
3527 }
2b4e57bd 3528
6567d748
CW		 3529 /* Disable RC6 on Ironlake */
3530 if (INTEL_INFO(dev)->gen == 5)
3531 return 0;
2b4e57bd 3532
8bade1ad 3533 if (IS_IVYBRIDGE(dev))
cca84a1f 3534 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 3535
3536 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 3537}
3538
e6069ca8
ID		 3539int intel_enable_rc6(const struct drm_device *dev)
3540{
3541 return i915.enable_rc6;
3542}
3543
0961021a
BW		 3544static void gen8_enable_rps_interrupts(struct drm_device *dev)
3545{
3546 struct drm_i915_private *dev_priv = dev->dev_private;
3547
3548 spin_lock_irq(&dev_priv->irq_lock);
3549 WARN_ON(dev_priv->rps.pm_iir);
480c8033 3550 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
0961021a
BW		 3551 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3552 spin_unlock_irq(&dev_priv->irq_lock);
3553}
3554
44fc7d5c
DV		 3555static void gen6_enable_rps_interrupts(struct drm_device *dev)
3556{
3557 struct drm_i915_private *dev_priv = dev->dev_private;
3558
3559 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3560 WARN_ON(dev_priv->rps.pm_iir);
480c8033 3561 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
a6706b45 3562 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
44fc7d5c 3563 spin_unlock_irq(&dev_priv->irq_lock);
44fc7d5c
DV		 3564}
3565
3280e8b0
BW		 3566static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3567{
3568 /* All of these values are in units of 50MHz */
3569 dev_priv->rps.cur_freq = 0;
3570 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3571 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3572 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3573 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3574 /* XXX: only BYT has a special efficient freq */
3575 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3576 /* hw_max = RP0 until we check for overclocking */
3577 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3578
3579 /* Preserve min/max settings in case of re-init */
3580 if (dev_priv->rps.max_freq_softlimit == 0)
3581 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3582
3583 if (dev_priv->rps.min_freq_softlimit == 0)
3584 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3585}
3586
6edee7f3
BW		 3587static void gen8_enable_rps(struct drm_device *dev)
3588{
3589 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3590 struct intel_engine_cs *ring;
6edee7f3
BW		 3591 uint32_t rc6_mask = 0, rp_state_cap;
3592 int unused;
3593
3594 /* 1a: Software RC state - RC0 */
3595 I915_WRITE(GEN6_RC_STATE, 0);
3596
3597 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3598 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3599 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3600
3601 /* 2a: Disable RC states. */
3602 I915_WRITE(GEN6_RC_CONTROL, 0);
3603
3604 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0 3605 parse_rp_state_cap(dev_priv, rp_state_cap);
6edee7f3
BW		 3606
3607 /* 2b: Program RC6 thresholds.*/
3608 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3609 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3610 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3611 for_each_ring(ring, dev_priv, unused)
3612 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3613 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 3614 if (IS_BROADWELL(dev))
3615 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3616 else
3617 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 3618
3619 /* 3: Enable RC6 */
3620 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3621 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 3622 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 3623 if (IS_BROADWELL(dev))
3624 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3625 GEN7_RC_CTL_TO_MODE |
3626 rc6_mask);
3627 else
3628 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3629 GEN6_RC_CTL_EI_MODE(1) |
3630 rc6_mask);
6edee7f3
BW		 3631
3632 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 3633 I915_WRITE(GEN6_RPNSWREQ,
3634 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3635 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3636 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
6edee7f3
BW		 3637 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3638 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3639
3640 /* Docs recommend 900MHz, and 300 MHz respectively */
3641 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
b39fb297
BW		 3642 dev_priv->rps.max_freq_softlimit << 24 |
3643 dev_priv->rps.min_freq_softlimit << 16);
6edee7f3
BW		 3644
3645 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3646 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3647 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3648 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3649
3650 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3651
3652 /* 5: Enable RPS */
3653 I915_WRITE(GEN6_RP_CONTROL,
3654 GEN6_RP_MEDIA_TURBO |
3655 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7405f42c 3656 GEN6_RP_MEDIA_IS_GFX |
6edee7f3
BW		 3657 GEN6_RP_ENABLE |
3658 GEN6_RP_UP_BUSY_AVG |
3659 GEN6_RP_DOWN_IDLE_AVG);
3660
3661 /* 6: Ring frequency + overclocking (our driver does this later */
3662
3663 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3664
0961021a 3665 gen8_enable_rps_interrupts(dev);
6edee7f3 3666
c8d9a590 3667 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3668}
3669
79f5b2c7 3670static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3671{
79f5b2c7 3672 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3673 struct intel_engine_cs *ring;
2a5913a8 3674 u32 rp_state_cap;
7b9e0ae6 3675 u32 gt_perf_status;
d060c169 3676 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 3677 u32 gtfifodbg;
2b4e57bd 3678 int rc6_mode;
42c0526c 3679 int i, ret;
2b4e57bd 3680
4fc688ce 3681 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3682
2b4e57bd
ED		 3683 /* Here begins a magic sequence of register writes to enable
3684 * auto-downclocking.
3685 *
3686 * Perhaps there might be some value in exposing these to
3687 * userspace...
3688 */
3689 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3690
3691 /* Clear the DBG now so we don't confuse earlier errors */
3692 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3693 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3694 I915_WRITE(GTFIFODBG, gtfifodbg);
3695 }
3696
c8d9a590 3697 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3698
7b9e0ae6
CW		 3699 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3700 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3701
3280e8b0 3702 parse_rp_state_cap(dev_priv, rp_state_cap);
dd0a1aa1 3703
2b4e57bd
ED		 3704 /* disable the counters and set deterministic thresholds */
3705 I915_WRITE(GEN6_RC_CONTROL, 0);
3706
3707 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3708 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3709 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3710 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3711 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3712
b4519513
CW		 3713 for_each_ring(ring, dev_priv, i)
3714 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3715
3716 I915_WRITE(GEN6_RC_SLEEP, 0);
3717 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3718 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3719 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3720 else
3721 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3722 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3723 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3724
5a7dc92a 3725 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3726 rc6_mode = intel_enable_rc6(dev_priv->dev);
3727 if (rc6_mode & INTEL_RC6_ENABLE)
3728 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3729
5a7dc92a
ED		 3730 /* We don't use those on Haswell */
3731 if (!IS_HASWELL(dev)) {
3732 if (rc6_mode & INTEL_RC6p_ENABLE)
3733 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3734
5a7dc92a
ED		 3735 if (rc6_mode & INTEL_RC6pp_ENABLE)
3736 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3737 }
2b4e57bd 3738
dc39fff7 3739 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3740
3741 I915_WRITE(GEN6_RC_CONTROL,
3742 rc6_mask |
3743 GEN6_RC_CTL_EI_MODE(1) |
3744 GEN6_RC_CTL_HW_ENABLE);
3745
dd75fdc8
CW		 3746 /* Power down if completely idle for over 50ms */
3747 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3748 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3749
42c0526c 3750 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 3751 if (ret)
42c0526c 3752 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 3753
3754 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3755 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3756 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 3757 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 3758 (pcu_mbox & 0xff) * 50);
b39fb297 3759 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 3760 }
3761
dd75fdc8 3762 dev_priv->rps.power = HIGH_POWER; /* force a reset */
b39fb297 3763 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
2b4e57bd 3764
44fc7d5c 3765 gen6_enable_rps_interrupts(dev);
2b4e57bd 3766
31643d54
BW		 3767 rc6vids = 0;
3768 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3769 if (IS_GEN6(dev) && ret) {
3770 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3771 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3772 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3773 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3774 rc6vids &= 0xffff00;
3775 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3776 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3777 if (ret)
3778 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3779 }
3780
c8d9a590 3781 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 3782}
3783
c2bc2fc5 3784static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3785{
79f5b2c7 3786 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3787 int min_freq = 15;
3ebecd07
CW		 3788 unsigned int gpu_freq;
3789 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3790 int scaling_factor = 180;
eda79642 3791 struct cpufreq_policy *policy;
2b4e57bd 3792
4fc688ce 3793 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3794
eda79642
BW		 3795 policy = cpufreq_cpu_get(0);
3796 if (policy) {
3797 max_ia_freq = policy->cpuinfo.max_freq;
3798 cpufreq_cpu_put(policy);
3799 } else {
3800 /*
3801 * Default to measured freq if none found, PCU will ensure we
3802 * don't go over
3803 */
2b4e57bd 3804 max_ia_freq = tsc_khz;
eda79642 3805 }
2b4e57bd
ED		 3806
3807 /* Convert from kHz to MHz */
3808 max_ia_freq /= 1000;
3809
153b4b95 3810 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3811 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3812 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3813
2b4e57bd
ED		 3814 /*
3815 * For each potential GPU frequency, load a ring frequency we'd like
3816 * to use for memory access. We do this by specifying the IA frequency
3817 * the PCU should use as a reference to determine the ring frequency.
3818 */
b39fb297 3819 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
2b4e57bd 3820 gpu_freq--) {
b39fb297 3821 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3ebecd07
CW		 3822 unsigned int ia_freq = 0, ring_freq = 0;
3823
46c764d4
BW		 3824 if (INTEL_INFO(dev)->gen >= 8) {
3825 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3826 ring_freq = max(min_ring_freq, gpu_freq);
3827 } else if (IS_HASWELL(dev)) {
f6aca45c 3828 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3829 ring_freq = max(min_ring_freq, ring_freq);
3830 /* leave ia_freq as the default, chosen by cpufreq */
3831 } else {
3832 /* On older processors, there is no separate ring
3833 * clock domain, so in order to boost the bandwidth
3834 * of the ring, we need to upclock the CPU (ia_freq).
3835 *
3836 * For GPU frequencies less than 750MHz,
3837 * just use the lowest ring freq.
3838 */
3839 if (gpu_freq < min_freq)
3840 ia_freq = 800;
3841 else
3842 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3843 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3844 }
2b4e57bd 3845
42c0526c
BW		 3846 sandybridge_pcode_write(dev_priv,
3847 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3848 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3849 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3850 gpu_freq);
2b4e57bd 3851 }
2b4e57bd
ED		 3852}
3853
c2bc2fc5
ID		 3854void gen6_update_ring_freq(struct drm_device *dev)
3855{
3856 struct drm_i915_private *dev_priv = dev->dev_private;
3857
3858 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3859 return;
3860
3861 mutex_lock(&dev_priv->rps.hw_lock);
3862 __gen6_update_ring_freq(dev);
3863 mutex_unlock(&dev_priv->rps.hw_lock);
3864}
3865
03af2045 3866static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 3867{
3868 u32 val, rp0;
3869
3870 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3871 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3872
3873 return rp0;
3874}
3875
3876static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3877{
3878 u32 val, rpe;
3879
3880 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
3881 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
3882
3883 return rpe;
3884}
3885
7707df4a
D		 3886static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
3887{
3888 u32 val, rp1;
3889
3890 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3891 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3892
3893 return rp1;
3894}
3895
03af2045 3896static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 3897{
3898 u32 val, rpn;
3899
3900 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3901 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
3902 return rpn;
3903}
3904
f8f2b001
D		 3905static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
3906{
3907 u32 val, rp1;
3908
3909 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3910
3911 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
3912
3913 return rp1;
3914}
3915
03af2045 3916static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 3917{
3918 u32 val, rp0;
3919
64936258 3920 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3921
3922 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3923 /* Clamp to max */
3924 rp0 = min_t(u32, rp0, 0xea);
3925
3926 return rp0;
3927}
3928
3929static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3930{
3931 u32 val, rpe;
3932
64936258 3933 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3934 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3935 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3936 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3937
3938 return rpe;
3939}
3940
03af2045 3941static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 3942{
64936258 3943 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3944}
3945
ae48434c
ID		 3946/* Check that the pctx buffer wasn't move under us. */
3947static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3948{
3949 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3950
3951 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3952 dev_priv->vlv_pctx->stolen->start);
3953}
3954
38807746
D		 3955
3956/* Check that the pcbr address is not empty. */
3957static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
3958{
3959 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3960
3961 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
3962}
3963
3964static void cherryview_setup_pctx(struct drm_device *dev)
3965{
3966 struct drm_i915_private *dev_priv = dev->dev_private;
3967 unsigned long pctx_paddr, paddr;
3968 struct i915_gtt *gtt = &dev_priv->gtt;
3969 u32 pcbr;
3970 int pctx_size = 32*1024;
3971
3972 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3973
3974 pcbr = I915_READ(VLV_PCBR);
3975 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
3976 paddr = (dev_priv->mm.stolen_base +
3977 (gtt->stolen_size - pctx_size));
3978
3979 pctx_paddr = (paddr & (~4095));
3980 I915_WRITE(VLV_PCBR, pctx_paddr);
3981 }
3982}
3983
c9cddffc
JB		 3984static void valleyview_setup_pctx(struct drm_device *dev)
3985{
3986 struct drm_i915_private *dev_priv = dev->dev_private;
3987 struct drm_i915_gem_object *pctx;
3988 unsigned long pctx_paddr;
3989 u32 pcbr;
3990 int pctx_size = 24*1024;
3991
17b0c1f7
ID		 3992 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3993
c9cddffc
JB		 3994 pcbr = I915_READ(VLV_PCBR);
3995 if (pcbr) {
3996 /* BIOS set it up already, grab the pre-alloc'd space */
3997 int pcbr_offset;
3998
3999 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4000 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4001 pcbr_offset,
190d6cd5 4002 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 4003 pctx_size);
4004 goto out;
4005 }
4006
4007 /*
4008 * From the Gunit register HAS:
4009 * The Gfx driver is expected to program this register and ensure
4010 * proper allocation within Gfx stolen memory. For example, this
4011 * register should be programmed such than the PCBR range does not
4012 * overlap with other ranges, such as the frame buffer, protected
4013 * memory, or any other relevant ranges.
4014 */
4015 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4016 if (!pctx) {
4017 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4018 return;
4019 }
4020
4021 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4022 I915_WRITE(VLV_PCBR, pctx_paddr);
4023
4024out:
4025 dev_priv->vlv_pctx = pctx;
4026}
4027
ae48434c
ID		 4028static void valleyview_cleanup_pctx(struct drm_device *dev)
4029{
4030 struct drm_i915_private *dev_priv = dev->dev_private;
4031
4032 if (WARN_ON(!dev_priv->vlv_pctx))
4033 return;
4034
4035 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4036 dev_priv->vlv_pctx = NULL;
4037}
4038
4e80519e
ID		 4039static void valleyview_init_gt_powersave(struct drm_device *dev)
4040{
4041 struct drm_i915_private *dev_priv = dev->dev_private;
4042
4043 valleyview_setup_pctx(dev);
4044
4045 mutex_lock(&dev_priv->rps.hw_lock);
4046
4047 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4048 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4049 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4050 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4051 dev_priv->rps.max_freq);
4052
4053 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4054 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4055 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4056 dev_priv->rps.efficient_freq);
4057
f8f2b001
D		 4058 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4059 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4060 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4061 dev_priv->rps.rp1_freq);
4062
4e80519e
ID		 4063 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4064 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4065 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4066 dev_priv->rps.min_freq);
4067
4068 /* Preserve min/max settings in case of re-init */
4069 if (dev_priv->rps.max_freq_softlimit == 0)
4070 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4071
4072 if (dev_priv->rps.min_freq_softlimit == 0)
4073 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4074
4075 mutex_unlock(&dev_priv->rps.hw_lock);
4076}
4077
38807746
D		 4078static void cherryview_init_gt_powersave(struct drm_device *dev)
4079{
2b6b3a09
D		 4080 struct drm_i915_private *dev_priv = dev->dev_private;
4081
38807746 4082 cherryview_setup_pctx(dev);
2b6b3a09
D		 4083
4084 mutex_lock(&dev_priv->rps.hw_lock);
4085
4086 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4087 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4088 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4089 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4090 dev_priv->rps.max_freq);
4091
4092 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4093 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4094 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4095 dev_priv->rps.efficient_freq);
4096
7707df4a
D		 4097 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4098 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4099 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4100 dev_priv->rps.rp1_freq);
4101
2b6b3a09
D		 4102 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4103 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4104 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4105 dev_priv->rps.min_freq);
4106
4107 /* Preserve min/max settings in case of re-init */
4108 if (dev_priv->rps.max_freq_softlimit == 0)
4109 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4110
4111 if (dev_priv->rps.min_freq_softlimit == 0)
4112 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4113
4114 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 4115}
4116
4e80519e
ID		 4117static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4118{
4119 valleyview_cleanup_pctx(dev);
4120}
4121
38807746
D		 4122static void cherryview_enable_rps(struct drm_device *dev)
4123{
4124 struct drm_i915_private *dev_priv = dev->dev_private;
4125 struct intel_engine_cs *ring;
2b6b3a09 4126 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 4127 int i;
4128
4129 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4130
4131 gtfifodbg = I915_READ(GTFIFODBG);
4132 if (gtfifodbg) {
4133 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4134 gtfifodbg);
4135 I915_WRITE(GTFIFODBG, gtfifodbg);
4136 }
4137
4138 cherryview_check_pctx(dev_priv);
4139
4140 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4141 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4142 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4143
4144 /* 2a: Program RC6 thresholds.*/
4145 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4146 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4147 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4148
4149 for_each_ring(ring, dev_priv, i)
4150 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4151 I915_WRITE(GEN6_RC_SLEEP, 0);
4152
4153 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4154
4155 /* allows RC6 residency counter to work */
4156 I915_WRITE(VLV_COUNTER_CONTROL,
4157 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4158 VLV_MEDIA_RC6_COUNT_EN |
4159 VLV_RENDER_RC6_COUNT_EN));
4160
4161 /* For now we assume BIOS is allocating and populating the PCBR */
4162 pcbr = I915_READ(VLV_PCBR);
4163
4164 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4165
4166 /* 3: Enable RC6 */
4167 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4168 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4169 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4170
4171 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4172
2b6b3a09
D		 4173 /* 4 Program defaults and thresholds for RPS*/
4174 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4175 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4176 I915_WRITE(GEN6_RP_UP_EI, 66000);
4177 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4178
4179 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4180
7405f42c
TR		 4181 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4182 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4183 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4184
2b6b3a09
D		 4185 /* 5: Enable RPS */
4186 I915_WRITE(GEN6_RP_CONTROL,
4187 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7405f42c 4188 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
2b6b3a09
D		 4189 GEN6_RP_ENABLE |
4190 GEN6_RP_UP_BUSY_AVG |
4191 GEN6_RP_DOWN_IDLE_AVG);
4192
4193 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4194
4195 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4196 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4197
4198 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4199 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4200 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4201 dev_priv->rps.cur_freq);
4202
4203 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4204 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4205 dev_priv->rps.efficient_freq);
4206
4207 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4208
3497a562
D		 4209 gen8_enable_rps_interrupts(dev);
4210
38807746
D		 4211 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4212}
4213
0a073b84
JB		 4214static void valleyview_enable_rps(struct drm_device *dev)
4215{
4216 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4217 struct intel_engine_cs *ring;
2a5913a8 4218 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 4219 int i;
4220
4221 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4222
ae48434c
ID		 4223 valleyview_check_pctx(dev_priv);
4224
0a073b84 4225 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 4226 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4227 gtfifodbg);
0a073b84
JB		 4228 I915_WRITE(GTFIFODBG, gtfifodbg);
4229 }
4230
c8d9a590
D		 4231 /* If VLV, Forcewake all wells, else re-direct to regular path */
4232 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4233
4234 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4235 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4236 I915_WRITE(GEN6_RP_UP_EI, 66000);
4237 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4238
4239 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
31685c25 4240 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
0a073b84
JB		 4241
4242 I915_WRITE(GEN6_RP_CONTROL,
4243 GEN6_RP_MEDIA_TURBO |
4244 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4245 GEN6_RP_MEDIA_IS_GFX |
4246 GEN6_RP_ENABLE |
4247 GEN6_RP_UP_BUSY_AVG |
4248 GEN6_RP_DOWN_IDLE_CONT);
4249
4250 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4251 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4252 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4253
4254 for_each_ring(ring, dev_priv, i)
4255 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4256
2f0aa304 4257 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 4258
4259 /* allows RC6 residency counter to work */
49798eb2 4260 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 4261 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4262 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 4263 VLV_MEDIA_RC6_COUNT_EN |
4264 VLV_RENDER_RC6_COUNT_EN));
31685c25 4265
a2b23fe0 4266 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 4267 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 4268
4269 intel_print_rc6_info(dev, rc6_mode);
4270
a2b23fe0 4271 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 4272
64936258 4273 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 4274
4275 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4276 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4277
b39fb297 4278 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 4279 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
b39fb297
BW		 4280 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4281 dev_priv->rps.cur_freq);
0a073b84 4282
73008b98 4283 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
b39fb297
BW		 4284 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4285 dev_priv->rps.efficient_freq);
0a073b84 4286
b39fb297 4287 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 4288
44fc7d5c 4289 gen6_enable_rps_interrupts(dev);
0a073b84 4290
c8d9a590 4291 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4292}
4293
930ebb46 4294void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 4295{
4296 struct drm_i915_private *dev_priv = dev->dev_private;
4297
3e373948 4298 if (dev_priv->ips.renderctx) {
d7f46fc4 4299 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3e373948
DV		 4300 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4301 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 4302 }
4303
3e373948 4304 if (dev_priv->ips.pwrctx) {
d7f46fc4 4305 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3e373948
DV		 4306 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4307 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 4308 }
4309}
4310
930ebb46 4311static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4312{
4313 struct drm_i915_private *dev_priv = dev->dev_private;
4314
4315 if (I915_READ(PWRCTXA)) {
4316 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4317 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4318 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4319 50);
4320
4321 I915_WRITE(PWRCTXA, 0);
4322 POSTING_READ(PWRCTXA);
4323
4324 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4325 POSTING_READ(RSTDBYCTL);
4326 }
2b4e57bd
ED		 4327}
4328
4329static int ironlake_setup_rc6(struct drm_device *dev)
4330{
4331 struct drm_i915_private *dev_priv = dev->dev_private;
4332
3e373948
DV		 4333 if (dev_priv->ips.renderctx == NULL)
4334 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4335 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 4336 return -ENOMEM;
4337
3e373948
DV		 4338 if (dev_priv->ips.pwrctx == NULL)
4339 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4340 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 4341 ironlake_teardown_rc6(dev);
4342 return -ENOMEM;
4343 }
4344
4345 return 0;
4346}
4347
930ebb46 4348static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4349{
4350 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4351 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e960501 4352 bool was_interruptible;
2b4e57bd
ED		 4353 int ret;
4354
4355 /* rc6 disabled by default due to repeated reports of hanging during
4356 * boot and resume.
4357 */
4358 if (!intel_enable_rc6(dev))
4359 return;
4360
79f5b2c7
DV		 4361 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4362
2b4e57bd 4363 ret = ironlake_setup_rc6(dev);
79f5b2c7 4364 if (ret)
2b4e57bd 4365 return;
2b4e57bd 4366
3e960501
CW		 4367 was_interruptible = dev_priv->mm.interruptible;
4368 dev_priv->mm.interruptible = false;
4369
2b4e57bd
ED		 4370 /*
4371 * GPU can automatically power down the render unit if given a page
4372 * to save state.
4373 */
6d90c952 4374 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 4375 if (ret) {
4376 ironlake_teardown_rc6(dev);
3e960501 4377 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 4378 return;
4379 }
4380
6d90c952
DV		 4381 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4382 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 4383 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 4384 MI_MM_SPACE_GTT |
4385 MI_SAVE_EXT_STATE_EN |
4386 MI_RESTORE_EXT_STATE_EN |
4387 MI_RESTORE_INHIBIT);
4388 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4389 intel_ring_emit(ring, MI_NOOP);
4390 intel_ring_emit(ring, MI_FLUSH);
4391 intel_ring_advance(ring);
2b4e57bd
ED		 4392
4393 /*
4394 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4395 * does an implicit flush, combined with MI_FLUSH above, it should be
4396 * safe to assume that renderctx is valid
4397 */
3e960501
CW		 4398 ret = intel_ring_idle(ring);
4399 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 4400 if (ret) {
def27a58 4401 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4402 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4403 return;
4404 }
4405
f343c5f6 4406 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4407 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7 4408
91ca689a 4409 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
2b4e57bd
ED		 4410}
4411
dde18883
ED		 4412static unsigned long intel_pxfreq(u32 vidfreq)
4413{
4414 unsigned long freq;
4415 int div = (vidfreq & 0x3f0000) >> 16;
4416 int post = (vidfreq & 0x3000) >> 12;
4417 int pre = (vidfreq & 0x7);
4418
4419 if (!pre)
4420 return 0;
4421
4422 freq = ((div * 133333) / ((1<<post) * pre));
4423
4424 return freq;
4425}
4426
eb48eb00
DV		 4427static const struct cparams {
4428 u16 i;
4429 u16 t;
4430 u16 m;
4431 u16 c;
4432} cparams[] = {
4433 { 1, 1333, 301, 28664 },
4434 { 1, 1066, 294, 24460 },
4435 { 1, 800, 294, 25192 },
4436 { 0, 1333, 276, 27605 },
4437 { 0, 1066, 276, 27605 },
4438 { 0, 800, 231, 23784 },
4439};
4440
f531dcb2 4441static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4442{
4443 u64 total_count, diff, ret;
4444 u32 count1, count2, count3, m = 0, c = 0;
4445 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4446 int i;
4447
02d71956
DV		 4448 assert_spin_locked(&mchdev_lock);
4449
20e4d407 4450 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4451
4452 /* Prevent division-by-zero if we are asking too fast.
4453 * Also, we don't get interesting results if we are polling
4454 * faster than once in 10ms, so just return the saved value
4455 * in such cases.
4456 */
4457 if (diff1 <= 10)
20e4d407 4458 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4459
4460 count1 = I915_READ(DMIEC);
4461 count2 = I915_READ(DDREC);
4462 count3 = I915_READ(CSIEC);
4463
4464 total_count = count1 + count2 + count3;
4465
4466 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4467 if (total_count < dev_priv->ips.last_count1) {
4468 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4469 diff += total_count;
4470 } else {
20e4d407 4471 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4472 }
4473
4474 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4475 if (cparams[i].i == dev_priv->ips.c_m &&
4476 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4477 m = cparams[i].m;
4478 c = cparams[i].c;
4479 break;
4480 }
4481 }
4482
4483 diff = div_u64(diff, diff1);
4484 ret = ((m * diff) + c);
4485 ret = div_u64(ret, 10);
4486
20e4d407
DV		 4487 dev_priv->ips.last_count1 = total_count;
4488 dev_priv->ips.last_time1 = now;
eb48eb00 4489
20e4d407 4490 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4491
4492 return ret;
4493}
4494
f531dcb2
CW		 4495unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4496{
3d13ef2e 4497 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4498 unsigned long val;
4499
3d13ef2e 4500 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4501 return 0;
4502
4503 spin_lock_irq(&mchdev_lock);
4504
4505 val = __i915_chipset_val(dev_priv);
4506
4507 spin_unlock_irq(&mchdev_lock);
4508
4509 return val;
4510}
4511
eb48eb00
DV		 4512unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4513{
4514 unsigned long m, x, b;
4515 u32 tsfs;
4516
4517 tsfs = I915_READ(TSFS);
4518
4519 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4520 x = I915_READ8(TR1);
4521
4522 b = tsfs & TSFS_INTR_MASK;
4523
4524 return ((m * x) / 127) - b;
4525}
4526
4527static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4528{
3d13ef2e 4529 struct drm_device *dev = dev_priv->dev;
eb48eb00
DV		 4530 static const struct v_table {
4531 u16 vd; /* in .1 mil */
4532 u16 vm; /* in .1 mil */
4533 } v_table[] = {
4534 { 0, 0, },
4535 { 375, 0, },
4536 { 500, 0, },
4537 { 625, 0, },
4538 { 750, 0, },
4539 { 875, 0, },
4540 { 1000, 0, },
4541 { 1125, 0, },
4542 { 4125, 3000, },
4543 { 4125, 3000, },
4544 { 4125, 3000, },
4545 { 4125, 3000, },
4546 { 4125, 3000, },
4547 { 4125, 3000, },
4548 { 4125, 3000, },
4549 { 4125, 3000, },
4550 { 4125, 3000, },
4551 { 4125, 3000, },
4552 { 4125, 3000, },
4553 { 4125, 3000, },
4554 { 4125, 3000, },
4555 { 4125, 3000, },
4556 { 4125, 3000, },
4557 { 4125, 3000, },
4558 { 4125, 3000, },
4559 { 4125, 3000, },
4560 { 4125, 3000, },
4561 { 4125, 3000, },
4562 { 4125, 3000, },
4563 { 4125, 3000, },
4564 { 4125, 3000, },
4565 { 4125, 3000, },
4566 { 4250, 3125, },
4567 { 4375, 3250, },
4568 { 4500, 3375, },
4569 { 4625, 3500, },
4570 { 4750, 3625, },
4571 { 4875, 3750, },
4572 { 5000, 3875, },
4573 { 5125, 4000, },
4574 { 5250, 4125, },
4575 { 5375, 4250, },
4576 { 5500, 4375, },
4577 { 5625, 4500, },
4578 { 5750, 4625, },
4579 { 5875, 4750, },
4580 { 6000, 4875, },
4581 { 6125, 5000, },
4582 { 6250, 5125, },
4583 { 6375, 5250, },
4584 { 6500, 5375, },
4585 { 6625, 5500, },
4586 { 6750, 5625, },
4587 { 6875, 5750, },
4588 { 7000, 5875, },
4589 { 7125, 6000, },
4590 { 7250, 6125, },
4591 { 7375, 6250, },
4592 { 7500, 6375, },
4593 { 7625, 6500, },
4594 { 7750, 6625, },
4595 { 7875, 6750, },
4596 { 8000, 6875, },
4597 { 8125, 7000, },
4598 { 8250, 7125, },
4599 { 8375, 7250, },
4600 { 8500, 7375, },
4601 { 8625, 7500, },
4602 { 8750, 7625, },
4603 { 8875, 7750, },
4604 { 9000, 7875, },
4605 { 9125, 8000, },
4606 { 9250, 8125, },
4607 { 9375, 8250, },
4608 { 9500, 8375, },
4609 { 9625, 8500, },
4610 { 9750, 8625, },
4611 { 9875, 8750, },
4612 { 10000, 8875, },
4613 { 10125, 9000, },
4614 { 10250, 9125, },
4615 { 10375, 9250, },
4616 { 10500, 9375, },
4617 { 10625, 9500, },
4618 { 10750, 9625, },
4619 { 10875, 9750, },
4620 { 11000, 9875, },
4621 { 11125, 10000, },
4622 { 11250, 10125, },
4623 { 11375, 10250, },
4624 { 11500, 10375, },
4625 { 11625, 10500, },
4626 { 11750, 10625, },
4627 { 11875, 10750, },
4628 { 12000, 10875, },
4629 { 12125, 11000, },
4630 { 12250, 11125, },
4631 { 12375, 11250, },
4632 { 12500, 11375, },
4633 { 12625, 11500, },
4634 { 12750, 11625, },
4635 { 12875, 11750, },
4636 { 13000, 11875, },
4637 { 13125, 12000, },
4638 { 13250, 12125, },
4639 { 13375, 12250, },
4640 { 13500, 12375, },
4641 { 13625, 12500, },
4642 { 13750, 12625, },
4643 { 13875, 12750, },
4644 { 14000, 12875, },
4645 { 14125, 13000, },
4646 { 14250, 13125, },
4647 { 14375, 13250, },
4648 { 14500, 13375, },
4649 { 14625, 13500, },
4650 { 14750, 13625, },
4651 { 14875, 13750, },
4652 { 15000, 13875, },
4653 { 15125, 14000, },
4654 { 15250, 14125, },
4655 { 15375, 14250, },
4656 { 15500, 14375, },
4657 { 15625, 14500, },
4658 { 15750, 14625, },
4659 { 15875, 14750, },
4660 { 16000, 14875, },
4661 { 16125, 15000, },
4662 };
3d13ef2e 4663 if (INTEL_INFO(dev)->is_mobile)
eb48eb00
DV		 4664 return v_table[pxvid].vm;
4665 else
4666 return v_table[pxvid].vd;
4667}
4668
02d71956 4669static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4670{
4671 struct timespec now, diff1;
4672 u64 diff;
4673 unsigned long diffms;
4674 u32 count;
4675
02d71956 4676 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4677
4678 getrawmonotonic(&now);
20e4d407 4679 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4680
4681 /* Don't divide by 0 */
4682 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4683 if (!diffms)
4684 return;
4685
4686 count = I915_READ(GFXEC);
4687
20e4d407
DV		 4688 if (count < dev_priv->ips.last_count2) {
4689 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4690 diff += count;
4691 } else {
20e4d407 4692 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4693 }
4694
20e4d407
DV		 4695 dev_priv->ips.last_count2 = count;
4696 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4697
4698 /* More magic constants... */
4699 diff = diff * 1181;
4700 diff = div_u64(diff, diffms * 10);
20e4d407 4701 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4702}
4703
02d71956
DV		 4704void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4705{
3d13ef2e
DL		 4706 struct drm_device *dev = dev_priv->dev;
4707
4708 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 4709 return;
4710
9270388e 4711 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4712
4713 __i915_update_gfx_val(dev_priv);
4714
9270388e 4715 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4716}
4717
f531dcb2 4718static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4719{
4720 unsigned long t, corr, state1, corr2, state2;
4721 u32 pxvid, ext_v;
4722
02d71956
DV		 4723 assert_spin_locked(&mchdev_lock);
4724
b39fb297 4725 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 4726 pxvid = (pxvid >> 24) & 0x7f;
4727 ext_v = pvid_to_extvid(dev_priv, pxvid);
4728
4729 state1 = ext_v;
4730
4731 t = i915_mch_val(dev_priv);
4732
4733 /* Revel in the empirically derived constants */
4734
4735 /* Correction factor in 1/100000 units */
4736 if (t > 80)
4737 corr = ((t * 2349) + 135940);
4738 else if (t >= 50)
4739 corr = ((t * 964) + 29317);
4740 else /* < 50 */
4741 corr = ((t * 301) + 1004);
4742
4743 corr = corr * ((150142 * state1) / 10000 - 78642);
4744 corr /= 100000;
20e4d407 4745 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4746
4747 state2 = (corr2 * state1) / 10000;
4748 state2 /= 100; /* convert to mW */
4749
02d71956 4750 __i915_update_gfx_val(dev_priv);
eb48eb00 4751
20e4d407 4752 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4753}
4754
f531dcb2
CW		 4755unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4756{
3d13ef2e 4757 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4758 unsigned long val;
4759
3d13ef2e 4760 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4761 return 0;
4762
4763 spin_lock_irq(&mchdev_lock);
4764
4765 val = __i915_gfx_val(dev_priv);
4766
4767 spin_unlock_irq(&mchdev_lock);
4768
4769 return val;
4770}
4771
eb48eb00
DV		 4772/**
4773 * i915_read_mch_val - return value for IPS use
4774 *
4775 * Calculate and return a value for the IPS driver to use when deciding whether
4776 * we have thermal and power headroom to increase CPU or GPU power budget.
4777 */
4778unsigned long i915_read_mch_val(void)
4779{
4780 struct drm_i915_private *dev_priv;
4781 unsigned long chipset_val, graphics_val, ret = 0;
4782
9270388e 4783 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4784 if (!i915_mch_dev)
4785 goto out_unlock;
4786 dev_priv = i915_mch_dev;
4787
f531dcb2
CW		 4788 chipset_val = __i915_chipset_val(dev_priv);
4789 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4790
4791 ret = chipset_val + graphics_val;
4792
4793out_unlock:
9270388e 4794 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4795
4796 return ret;
4797}
4798EXPORT_SYMBOL_GPL(i915_read_mch_val);
4799
4800/**
4801 * i915_gpu_raise - raise GPU frequency limit
4802 *
4803 * Raise the limit; IPS indicates we have thermal headroom.
4804 */
4805bool i915_gpu_raise(void)
4806{
4807 struct drm_i915_private *dev_priv;
4808 bool ret = true;
4809
9270388e 4810 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4811 if (!i915_mch_dev) {
4812 ret = false;
4813 goto out_unlock;
4814 }
4815 dev_priv = i915_mch_dev;
4816
20e4d407
DV		 4817 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4818 dev_priv->ips.max_delay--;
eb48eb00
DV		 4819
4820out_unlock:
9270388e 4821 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4822
4823 return ret;
4824}
4825EXPORT_SYMBOL_GPL(i915_gpu_raise);
4826
4827/**
4828 * i915_gpu_lower - lower GPU frequency limit
4829 *
4830 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4831 * frequency maximum.
4832 */
4833bool i915_gpu_lower(void)
4834{
4835 struct drm_i915_private *dev_priv;
4836 bool ret = true;
4837
9270388e 4838 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4839 if (!i915_mch_dev) {
4840 ret = false;
4841 goto out_unlock;
4842 }
4843 dev_priv = i915_mch_dev;
4844
20e4d407
DV		 4845 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4846 dev_priv->ips.max_delay++;
eb48eb00
DV		 4847
4848out_unlock:
9270388e 4849 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4850
4851 return ret;
4852}
4853EXPORT_SYMBOL_GPL(i915_gpu_lower);
4854
4855/**
4856 * i915_gpu_busy - indicate GPU business to IPS
4857 *
4858 * Tell the IPS driver whether or not the GPU is busy.
4859 */
4860bool i915_gpu_busy(void)
4861{
4862 struct drm_i915_private *dev_priv;
a4872ba6 4863 struct intel_engine_cs *ring;
eb48eb00 4864 bool ret = false;
f047e395 4865 int i;
eb48eb00 4866
9270388e 4867 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4868 if (!i915_mch_dev)
4869 goto out_unlock;
4870 dev_priv = i915_mch_dev;
4871
f047e395
CW		 4872 for_each_ring(ring, dev_priv, i)
4873 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4874
4875out_unlock:
9270388e 4876 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4877
4878 return ret;
4879}
4880EXPORT_SYMBOL_GPL(i915_gpu_busy);
4881
4882/**
4883 * i915_gpu_turbo_disable - disable graphics turbo
4884 *
4885 * Disable graphics turbo by resetting the max frequency and setting the
4886 * current frequency to the default.
4887 */
4888bool i915_gpu_turbo_disable(void)
4889{
4890 struct drm_i915_private *dev_priv;
4891 bool ret = true;
4892
9270388e 4893 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4894 if (!i915_mch_dev) {
4895 ret = false;
4896 goto out_unlock;
4897 }
4898 dev_priv = i915_mch_dev;
4899
20e4d407 4900 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4901
20e4d407 4902 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4903 ret = false;
4904
4905out_unlock:
9270388e 4906 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4907
4908 return ret;
4909}
4910EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4911
4912/**
4913 * Tells the intel_ips driver that the i915 driver is now loaded, if
4914 * IPS got loaded first.
4915 *
4916 * This awkward dance is so that neither module has to depend on the
4917 * other in order for IPS to do the appropriate communication of
4918 * GPU turbo limits to i915.
4919 */
4920static void
4921ips_ping_for_i915_load(void)
4922{
4923 void (*link)(void);
4924
4925 link = symbol_get(ips_link_to_i915_driver);
4926 if (link) {
4927 link();
4928 symbol_put(ips_link_to_i915_driver);
4929 }
4930}
4931
4932void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4933{
02d71956
DV		 4934 /* We only register the i915 ips part with intel-ips once everything is
4935 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4936 spin_lock_irq(&mchdev_lock);
eb48eb00 4937 i915_mch_dev = dev_priv;
9270388e 4938 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4939
4940 ips_ping_for_i915_load();
4941}
4942
4943void intel_gpu_ips_teardown(void)
4944{
9270388e 4945 spin_lock_irq(&mchdev_lock);
eb48eb00 4946 i915_mch_dev = NULL;
9270388e 4947 spin_unlock_irq(&mchdev_lock);
eb48eb00 4948}
76c3552f 4949
8090c6b9 4950static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4951{
4952 struct drm_i915_private *dev_priv = dev->dev_private;
4953 u32 lcfuse;
4954 u8 pxw[16];
4955 int i;
4956
4957 /* Disable to program */
4958 I915_WRITE(ECR, 0);
4959 POSTING_READ(ECR);
4960
4961 /* Program energy weights for various events */
4962 I915_WRITE(SDEW, 0x15040d00);
4963 I915_WRITE(CSIEW0, 0x007f0000);
4964 I915_WRITE(CSIEW1, 0x1e220004);
4965 I915_WRITE(CSIEW2, 0x04000004);
4966
4967 for (i = 0; i < 5; i++)
4968 I915_WRITE(PEW + (i * 4), 0);
4969 for (i = 0; i < 3; i++)
4970 I915_WRITE(DEW + (i * 4), 0);
4971
4972 /* Program P-state weights to account for frequency power adjustment */
4973 for (i = 0; i < 16; i++) {
4974 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4975 unsigned long freq = intel_pxfreq(pxvidfreq);
4976 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4977 PXVFREQ_PX_SHIFT;
4978 unsigned long val;
4979
4980 val = vid * vid;
4981 val *= (freq / 1000);
4982 val *= 255;
4983 val /= (127*127*900);
4984 if (val > 0xff)
4985 DRM_ERROR("bad pxval: %ld\n", val);
4986 pxw[i] = val;
4987 }
4988 /* Render standby states get 0 weight */
4989 pxw[14] = 0;
4990 pxw[15] = 0;
4991
4992 for (i = 0; i < 4; i++) {
4993 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4994 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4995 I915_WRITE(PXW + (i * 4), val);
4996 }
4997
4998 /* Adjust magic regs to magic values (more experimental results) */
4999 I915_WRITE(OGW0, 0);
5000 I915_WRITE(OGW1, 0);
5001 I915_WRITE(EG0, 0x00007f00);
5002 I915_WRITE(EG1, 0x0000000e);
5003 I915_WRITE(EG2, 0x000e0000);
5004 I915_WRITE(EG3, 0x68000300);
5005 I915_WRITE(EG4, 0x42000000);
5006 I915_WRITE(EG5, 0x00140031);
5007 I915_WRITE(EG6, 0);
5008 I915_WRITE(EG7, 0);
5009
5010 for (i = 0; i < 8; i++)
5011 I915_WRITE(PXWL + (i * 4), 0);
5012
5013 /* Enable PMON + select events */
5014 I915_WRITE(ECR, 0x80000019);
5015
5016 lcfuse = I915_READ(LCFUSE02);
5017
20e4d407 5018 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 5019}
5020
ae48434c
ID		 5021void intel_init_gt_powersave(struct drm_device *dev)
5022{
e6069ca8
ID		 5023 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5024
38807746
D		 5025 if (IS_CHERRYVIEW(dev))
5026 cherryview_init_gt_powersave(dev);
5027 else if (IS_VALLEYVIEW(dev))
4e80519e 5028 valleyview_init_gt_powersave(dev);
ae48434c
ID		 5029}
5030
5031void intel_cleanup_gt_powersave(struct drm_device *dev)
5032{
38807746
D		 5033 if (IS_CHERRYVIEW(dev))
5034 return;
5035 else if (IS_VALLEYVIEW(dev))
4e80519e 5036 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 5037}
5038
156c7ca0
JB		 5039/**
5040 * intel_suspend_gt_powersave - suspend PM work and helper threads
5041 * @dev: drm device
5042 *
5043 * We don't want to disable RC6 or other features here, we just want
5044 * to make sure any work we've queued has finished and won't bother
5045 * us while we're suspended.
5046 */
5047void intel_suspend_gt_powersave(struct drm_device *dev)
5048{
5049 struct drm_i915_private *dev_priv = dev->dev_private;
5050
5051 /* Interrupts should be disabled already to avoid re-arming. */
9df7575f 5052 WARN_ON(intel_irqs_enabled(dev_priv));
156c7ca0
JB		 5053
5054 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5055
5056 cancel_work_sync(&dev_priv->rps.work);
b47adc17
D		 5057
5058 /* Force GPU to min freq during suspend */
5059 gen6_rps_idle(dev_priv);
156c7ca0
JB		 5060}
5061
8090c6b9
DV		 5062void intel_disable_gt_powersave(struct drm_device *dev)
5063{
1a01ab3b
JB		 5064 struct drm_i915_private *dev_priv = dev->dev_private;
5065
fd0c0642 5066 /* Interrupts should be disabled already to avoid re-arming. */
9df7575f 5067 WARN_ON(intel_irqs_enabled(dev_priv));
fd0c0642 5068
930ebb46 5069 if (IS_IRONLAKE_M(dev)) {
8090c6b9 5070 ironlake_disable_drps(dev);
930ebb46 5071 ironlake_disable_rc6(dev);
38807746 5072 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 5073 intel_suspend_gt_powersave(dev);
e494837a 5074
4fc688ce 5075 mutex_lock(&dev_priv->rps.hw_lock);
38807746
D		 5076 if (IS_CHERRYVIEW(dev))
5077 cherryview_disable_rps(dev);
5078 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 5079 valleyview_disable_rps(dev);
5080 else
5081 gen6_disable_rps(dev);
c0951f0c 5082 dev_priv->rps.enabled = false;
4fc688ce 5083 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 5084 }
8090c6b9
DV		 5085}
5086
1a01ab3b
JB		 5087static void intel_gen6_powersave_work(struct work_struct *work)
5088{
5089 struct drm_i915_private *dev_priv =
5090 container_of(work, struct drm_i915_private,
5091 rps.delayed_resume_work.work);
5092 struct drm_device *dev = dev_priv->dev;
5093
4fc688ce 5094 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 5095
38807746
D		 5096 if (IS_CHERRYVIEW(dev)) {
5097 cherryview_enable_rps(dev);
5098 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 5099 valleyview_enable_rps(dev);
6edee7f3
BW		 5100 } else if (IS_BROADWELL(dev)) {
5101 gen8_enable_rps(dev);
c2bc2fc5 5102 __gen6_update_ring_freq(dev);
0a073b84
JB		 5103 } else {
5104 gen6_enable_rps(dev);
c2bc2fc5 5105 __gen6_update_ring_freq(dev);
0a073b84 5106 }
c0951f0c 5107 dev_priv->rps.enabled = true;
4fc688ce 5108 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 5109
5110 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 5111}
5112
8090c6b9
DV		 5113void intel_enable_gt_powersave(struct drm_device *dev)
5114{
1a01ab3b
JB		 5115 struct drm_i915_private *dev_priv = dev->dev_private;
5116
8090c6b9 5117 if (IS_IRONLAKE_M(dev)) {
dc1d0136 5118 mutex_lock(&dev->struct_mutex);
8090c6b9
DV		 5119 ironlake_enable_drps(dev);
5120 ironlake_enable_rc6(dev);
5121 intel_init_emon(dev);
dc1d0136 5122 mutex_unlock(&dev->struct_mutex);
38807746 5123 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 5124 /*
5125 * PCU communication is slow and this doesn't need to be
5126 * done at any specific time, so do this out of our fast path
5127 * to make resume and init faster.
c6df39b5
ID		 5128 *
5129 * We depend on the HW RC6 power context save/restore
5130 * mechanism when entering D3 through runtime PM suspend. So
5131 * disable RPM until RPS/RC6 is properly setup. We can only
5132 * get here via the driver load/system resume/runtime resume
5133 * paths, so the _noresume version is enough (and in case of
5134 * runtime resume it's necessary).
1a01ab3b 5135 */
c6df39b5
ID		 5136 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5137 round_jiffies_up_relative(HZ)))
5138 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 5139 }
5140}
5141
c6df39b5
ID		 5142void intel_reset_gt_powersave(struct drm_device *dev)
5143{
5144 struct drm_i915_private *dev_priv = dev->dev_private;
5145
5146 dev_priv->rps.enabled = false;
5147 intel_enable_gt_powersave(dev);
5148}
5149
3107bd48
DV		 5150static void ibx_init_clock_gating(struct drm_device *dev)
5151{
5152 struct drm_i915_private *dev_priv = dev->dev_private;
5153
5154 /*
5155 * On Ibex Peak and Cougar Point, we need to disable clock
5156 * gating for the panel power sequencer or it will fail to
5157 * start up when no ports are active.
5158 */
5159 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5160}
5161
0e088b8f
VS		 5162static void g4x_disable_trickle_feed(struct drm_device *dev)
5163{
5164 struct drm_i915_private *dev_priv = dev->dev_private;
5165 int pipe;
5166
5167 for_each_pipe(pipe) {
5168 I915_WRITE(DSPCNTR(pipe),
5169 I915_READ(DSPCNTR(pipe)) |
5170 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 5171 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 5172 }
5173}
5174
017636cc
VS		 5175static void ilk_init_lp_watermarks(struct drm_device *dev)
5176{
5177 struct drm_i915_private *dev_priv = dev->dev_private;
5178
5179 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5180 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5181 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5182
5183 /*
5184 * Don't touch WM1S_LP_EN here.
5185 * Doing so could cause underruns.
5186 */
5187}
5188
1fa61106 5189static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5190{
5191 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5192 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5193
f1e8fa56
DL		 5194 /*
5195 * Required for FBC
5196 * WaFbcDisableDpfcClockGating:ilk
5197 */
4d47e4f5
DL		 5198 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5199 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5200 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5201
5202 I915_WRITE(PCH_3DCGDIS0,
5203 MARIUNIT_CLOCK_GATE_DISABLE |
5204 SVSMUNIT_CLOCK_GATE_DISABLE);
5205 I915_WRITE(PCH_3DCGDIS1,
5206 VFMUNIT_CLOCK_GATE_DISABLE);
5207
6f1d69b0
ED		 5208 /*
5209 * According to the spec the following bits should be set in
5210 * order to enable memory self-refresh
5211 * The bit 22/21 of 0x42004
5212 * The bit 5 of 0x42020
5213 * The bit 15 of 0x45000
5214 */
5215 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5216 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5217 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5218 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5219 I915_WRITE(DISP_ARB_CTL,
5220 (I915_READ(DISP_ARB_CTL) |
5221 DISP_FBC_WM_DIS));
017636cc
VS		 5222
5223 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 5224
5225 /*
5226 * Based on the document from hardware guys the following bits
5227 * should be set unconditionally in order to enable FBC.
5228 * The bit 22 of 0x42000
5229 * The bit 22 of 0x42004
5230 * The bit 7,8,9 of 0x42020.
5231 */
5232 if (IS_IRONLAKE_M(dev)) {
4bb35334 5233 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5234 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5235 I915_READ(ILK_DISPLAY_CHICKEN1) |
5236 ILK_FBCQ_DIS);
5237 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5238 I915_READ(ILK_DISPLAY_CHICKEN2) |
5239 ILK_DPARB_GATE);
6f1d69b0
ED		 5240 }
5241
4d47e4f5
DL		 5242 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5243
6f1d69b0
ED		 5244 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5245 I915_READ(ILK_DISPLAY_CHICKEN2) |
5246 ILK_ELPIN_409_SELECT);
5247 I915_WRITE(_3D_CHICKEN2,
5248 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5249 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5250
ecdb4eb7 5251 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5252 I915_WRITE(CACHE_MODE_0,
5253 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5254
4e04632e
AG		 5255 /* WaDisable_RenderCache_OperationalFlush:ilk */
5256 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5257
0e088b8f 5258 g4x_disable_trickle_feed(dev);
bdad2b2f 5259
3107bd48
DV		 5260 ibx_init_clock_gating(dev);
5261}
5262
5263static void cpt_init_clock_gating(struct drm_device *dev)
5264{
5265 struct drm_i915_private *dev_priv = dev->dev_private;
5266 int pipe;
3f704fa2 5267 uint32_t val;
3107bd48
DV		 5268
5269 /*
5270 * On Ibex Peak and Cougar Point, we need to disable clock
5271 * gating for the panel power sequencer or it will fail to
5272 * start up when no ports are active.
5273 */
cd664078
JB		 5274 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5275 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5276 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5277 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5278 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5279 /* The below fixes the weird display corruption, a few pixels shifted
5280 * downward, on (only) LVDS of some HP laptops with IVY.
5281 */
3f704fa2 5282 for_each_pipe(pipe) {
dc4bd2d1
PZ		 5283 val = I915_READ(TRANS_CHICKEN2(pipe));
5284 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5285 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5286 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5287 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5288 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5289 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5290 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5291 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5292 }
3107bd48
DV		 5293 /* WADP0ClockGatingDisable */
5294 for_each_pipe(pipe) {
5295 I915_WRITE(TRANS_CHICKEN1(pipe),
5296 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5297 }
6f1d69b0
ED		 5298}
5299
1d7aaa0c
DV		 5300static void gen6_check_mch_setup(struct drm_device *dev)
5301{
5302 struct drm_i915_private *dev_priv = dev->dev_private;
5303 uint32_t tmp;
5304
5305 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 5306 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5307 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5308 tmp);
1d7aaa0c
DV		 5309}
5310
1fa61106 5311static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5312{
5313 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5314 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5315
231e54f6 5316 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5317
5318 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5319 I915_READ(ILK_DISPLAY_CHICKEN2) |
5320 ILK_ELPIN_409_SELECT);
5321
ecdb4eb7 5322 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5323 I915_WRITE(_3D_CHICKEN,
5324 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5325
ecdb4eb7 5326 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 5327 if (IS_SNB_GT1(dev))
5328 I915_WRITE(GEN6_GT_MODE,
5329 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5330
4e04632e
AG		 5331 /* WaDisable_RenderCache_OperationalFlush:snb */
5332 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5333
8d85d272
VS		 5334 /*
5335 * BSpec recoomends 8x4 when MSAA is used,
5336 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5337 *
5338 * Note that PS/WM thread counts depend on the WIZ hashing
5339 * disable bit, which we don't touch here, but it's good
5340 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 5341 */
5342 I915_WRITE(GEN6_GT_MODE,
5343 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5344
017636cc 5345 ilk_init_lp_watermarks(dev);
6f1d69b0 5346
6f1d69b0 5347 I915_WRITE(CACHE_MODE_0,
50743298 5348 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5349
5350 I915_WRITE(GEN6_UCGCTL1,
5351 I915_READ(GEN6_UCGCTL1) |
5352 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5353 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5354
5355 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5356 * gating disable must be set. Failure to set it results in
5357 * flickering pixels due to Z write ordering failures after
5358 * some amount of runtime in the Mesa "fire" demo, and Unigine
5359 * Sanctuary and Tropics, and apparently anything else with
5360 * alpha test or pixel discard.
5361 *
5362 * According to the spec, bit 11 (RCCUNIT) must also be set,
5363 * but we didn't debug actual testcases to find it out.
0f846f81 5364 *
ef59318c
VS		 5365 * WaDisableRCCUnitClockGating:snb
5366 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 5367 */
5368 I915_WRITE(GEN6_UCGCTL2,
5369 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5370 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5371
5eb146dd 5372 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 5373 I915_WRITE(_3D_CHICKEN3,
5374 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 5375
e927ecde
VS		 5376 /*
5377 * Bspec says:
5378 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5379 * 3DSTATE_SF number of SF output attributes is more than 16."
5380 */
5381 I915_WRITE(_3D_CHICKEN3,
5382 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5383
6f1d69b0
ED		 5384 /*
5385 * According to the spec the following bits should be
5386 * set in order to enable memory self-refresh and fbc:
5387 * The bit21 and bit22 of 0x42000
5388 * The bit21 and bit22 of 0x42004
5389 * The bit5 and bit7 of 0x42020
5390 * The bit14 of 0x70180
5391 * The bit14 of 0x71180
4bb35334
DL		 5392 *
5393 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 5394 */
5395 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5396 I915_READ(ILK_DISPLAY_CHICKEN1) |
5397 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5398 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5399 I915_READ(ILK_DISPLAY_CHICKEN2) |
5400 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 5401 I915_WRITE(ILK_DSPCLK_GATE_D,
5402 I915_READ(ILK_DSPCLK_GATE_D) |
5403 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5404 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 5405
0e088b8f 5406 g4x_disable_trickle_feed(dev);
f8f2ac9a 5407
3107bd48 5408 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5409
5410 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5411}
5412
5413static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5414{
5415 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5416
3aad9059 5417 /*
46680e0a 5418 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 5419 *
5420 * This actually overrides the dispatch
5421 * mode for all thread types.
5422 */
6f1d69b0
ED		 5423 reg &= ~GEN7_FF_SCHED_MASK;
5424 reg |= GEN7_FF_TS_SCHED_HW;
5425 reg |= GEN7_FF_VS_SCHED_HW;
5426 reg |= GEN7_FF_DS_SCHED_HW;
5427
5428 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5429}
5430
17a303ec
PZ		 5431static void lpt_init_clock_gating(struct drm_device *dev)
5432{
5433 struct drm_i915_private *dev_priv = dev->dev_private;
5434
5435 /*
5436 * TODO: this bit should only be enabled when really needed, then
5437 * disabled when not needed anymore in order to save power.
5438 */
5439 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5440 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5441 I915_READ(SOUTH_DSPCLK_GATE_D) |
5442 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 5443
5444 /* WADPOClockGatingDisable:hsw */
5445 I915_WRITE(_TRANSA_CHICKEN1,
5446 I915_READ(_TRANSA_CHICKEN1) |
5447 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 5448}
5449
7d708ee4
ID		 5450static void lpt_suspend_hw(struct drm_device *dev)
5451{
5452 struct drm_i915_private *dev_priv = dev->dev_private;
5453
5454 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5455 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5456
5457 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5458 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5459 }
5460}
5461
1020a5c2
BW		 5462static void gen8_init_clock_gating(struct drm_device *dev)
5463{
5464 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 5465 enum pipe pipe;
1020a5c2
BW		 5466
5467 I915_WRITE(WM3_LP_ILK, 0);
5468 I915_WRITE(WM2_LP_ILK, 0);
5469 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 5470
5471 /* FIXME(BDW): Check all the w/a, some might only apply to
5472 * pre-production hw. */
5473
c8966e10
KG		 5474 /* WaDisablePartialInstShootdown:bdw */
5475 I915_WRITE(GEN8_ROW_CHICKEN,
5476 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5477
1411e6a5
KG		 5478 /* WaDisableThreadStallDopClockGating:bdw */
5479 /* FIXME: Unclear whether we really need this on production bdw. */
5480 I915_WRITE(GEN8_ROW_CHICKEN,
5481 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5482
4167e32c
DL		 5483 /*
5484 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5485 * pre-production hardware
5486 */
fd392b60
BW		 5487 I915_WRITE(HALF_SLICE_CHICKEN3,
5488 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 5489 I915_WRITE(HALF_SLICE_CHICKEN3,
5490 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 5491 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5492
7f88da0c 5493 I915_WRITE(_3D_CHICKEN3,
b3f9ad93 5494 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
7f88da0c 5495
a75f3628
BW		 5496 I915_WRITE(COMMON_SLICE_CHICKEN2,
5497 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5498
4c2e7a5f
BW		 5499 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5500 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5501
242a4018
BW		 5502 /* WaDisableDopClockGating:bdw May not be needed for production */
5503 I915_WRITE(GEN7_ROW_CHICKEN2,
5504 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5505
ab57fff1 5506 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 5507 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 5508
ab57fff1 5509 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 5510 I915_WRITE(CHICKEN_PAR1_1,
5511 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5512
ab57fff1 5513 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
07d27e20
DL		 5514 for_each_pipe(pipe) {
5515 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 5516 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 5517 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 5518 }
63801f21
BW		 5519
5520 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5521 * workaround for for a possible hang in the unlikely event a TLB
5522 * invalidation occurs during a PSD flush.
5523 */
5524 I915_WRITE(HDC_CHICKEN0,
5525 I915_READ(HDC_CHICKEN0) |
5526 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
ab57fff1
BW		 5527
5528 /* WaVSRefCountFullforceMissDisable:bdw */
5529 /* WaDSRefCountFullforceMissDisable:bdw */
5530 I915_WRITE(GEN7_FF_THREAD_MODE,
5531 I915_READ(GEN7_FF_THREAD_MODE) &
5532 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c
VS		 5533
5534 /*
5535 * BSpec recommends 8x4 when MSAA is used,
5536 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5537 *
5538 * Note that PS/WM thread counts depend on the WIZ hashing
5539 * disable bit, which we don't touch here, but it's good
5540 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
36075a4c
VS		 5541 */
5542 I915_WRITE(GEN7_GT_MODE,
5543 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
295e8bb7
VS		 5544
5545 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5546 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 5547
5548 /* WaDisableSDEUnitClockGating:bdw */
5549 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5550 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680
DL		 5551
5552 /* Wa4x4STCOptimizationDisable:bdw */
5553 I915_WRITE(CACHE_MODE_1,
5554 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
1020a5c2
BW		 5555}
5556
cad2a2d7
ED		 5557static void haswell_init_clock_gating(struct drm_device *dev)
5558{
5559 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 5560
017636cc 5561 ilk_init_lp_watermarks(dev);
cad2a2d7 5562
f3fc4884
FJ		 5563 /* L3 caching of data atomics doesn't work -- disable it. */
5564 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5565 I915_WRITE(HSW_ROW_CHICKEN3,
5566 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5567
ecdb4eb7 5568 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5569 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5570 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5571 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5572
e36ea7ff
VS		 5573 /* WaVSRefCountFullforceMissDisable:hsw */
5574 I915_WRITE(GEN7_FF_THREAD_MODE,
5575 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 5576
4e04632e
AG		 5577 /* WaDisable_RenderCache_OperationalFlush:hsw */
5578 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5579
fe27c606
CW		 5580 /* enable HiZ Raw Stall Optimization */
5581 I915_WRITE(CACHE_MODE_0_GEN7,
5582 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5583
ecdb4eb7 5584 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5585 I915_WRITE(CACHE_MODE_1,
5586 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5587
a12c4967
VS		 5588 /*
5589 * BSpec recommends 8x4 when MSAA is used,
5590 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5591 *
5592 * Note that PS/WM thread counts depend on the WIZ hashing
5593 * disable bit, which we don't touch here, but it's good
5594 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 5595 */
5596 I915_WRITE(GEN7_GT_MODE,
5597 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5598
ecdb4eb7 5599 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5600 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5601
90a88643
PZ		 5602 /* WaRsPkgCStateDisplayPMReq:hsw */
5603 I915_WRITE(CHICKEN_PAR1_1,
5604 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5605
17a303ec 5606 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5607}
5608
1fa61106 5609static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5610{
5611 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5612 uint32_t snpcr;
6f1d69b0 5613
017636cc 5614 ilk_init_lp_watermarks(dev);
6f1d69b0 5615
231e54f6 5616 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5617
ecdb4eb7 5618 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5619 I915_WRITE(_3D_CHICKEN3,
5620 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5621
ecdb4eb7 5622 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5623 I915_WRITE(IVB_CHICKEN3,
5624 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5625 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5626
ecdb4eb7 5627 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5628 if (IS_IVB_GT1(dev))
5629 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5630 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5631
4e04632e
AG		 5632 /* WaDisable_RenderCache_OperationalFlush:ivb */
5633 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5634
ecdb4eb7 5635 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5636 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5637 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5638
ecdb4eb7 5639 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5640 I915_WRITE(GEN7_L3CNTLREG1,
5641 GEN7_WA_FOR_GEN7_L3_CONTROL);
5642 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5643 GEN7_WA_L3_CHICKEN_MODE);
5644 if (IS_IVB_GT1(dev))
5645 I915_WRITE(GEN7_ROW_CHICKEN2,
5646 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 5647 else {
5648 /* must write both registers */
5649 I915_WRITE(GEN7_ROW_CHICKEN2,
5650 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 5651 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5652 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 5653 }
6f1d69b0 5654
ecdb4eb7 5655 /* WaForceL3Serialization:ivb */
61939d97
JB		 5656 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5657 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5658
1b80a19a 5659 /*
0f846f81 5660 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5661 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5662 */
5663 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 5664 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5665
ecdb4eb7 5666 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5667 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5668 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5669 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5670
0e088b8f 5671 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5672
5673 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5674
22721343
CW		 5675 if (0) { /* causes HiZ corruption on ivb:gt1 */
5676 /* enable HiZ Raw Stall Optimization */
5677 I915_WRITE(CACHE_MODE_0_GEN7,
5678 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5679 }
116f2b6d 5680
ecdb4eb7 5681 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5682 I915_WRITE(CACHE_MODE_1,
5683 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 5684
a607c1a4
VS		 5685 /*
5686 * BSpec recommends 8x4 when MSAA is used,
5687 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5688 *
5689 * Note that PS/WM thread counts depend on the WIZ hashing
5690 * disable bit, which we don't touch here, but it's good
5691 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 5692 */
5693 I915_WRITE(GEN7_GT_MODE,
5694 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5695
20848223
BW		 5696 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5697 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5698 snpcr |= GEN6_MBC_SNPCR_MED;
5699 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5700
ab5c608b
BW		 5701 if (!HAS_PCH_NOP(dev))
5702 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5703
5704 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5705}
5706
1fa61106 5707static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5708{
5709 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 5710 u32 val;
5711
5712 mutex_lock(&dev_priv->rps.hw_lock);
5713 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5714 mutex_unlock(&dev_priv->rps.hw_lock);
5715 switch ((val >> 6) & 3) {
5716 case 0:
f64a28a7 5717 case 1:
f6d51948 5718 dev_priv->mem_freq = 800;
85b1d7b3 5719 break;
f64a28a7 5720 case 2:
f6d51948 5721 dev_priv->mem_freq = 1066;
85b1d7b3 5722 break;
f64a28a7 5723 case 3:
2325991e 5724 dev_priv->mem_freq = 1333;
f64a28a7 5725 break;
85b1d7b3
JB		 5726 }
5727 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 5728
d7fe0cc0 5729 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5730
ecdb4eb7 5731 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5732 I915_WRITE(_3D_CHICKEN3,
5733 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5734
ecdb4eb7 5735 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5736 I915_WRITE(IVB_CHICKEN3,
5737 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5738 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5739
fad7d36e 5740 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 5741 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5742 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5743 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5744 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5745
4e04632e
AG		 5746 /* WaDisable_RenderCache_OperationalFlush:vlv */
5747 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5748
ecdb4eb7 5749 /* WaForceL3Serialization:vlv */
61939d97
JB		 5750 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5751 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5752
ecdb4eb7 5753 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5754 I915_WRITE(GEN7_ROW_CHICKEN2,
5755 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5756
ecdb4eb7 5757 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5758 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5759 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5760 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5761
46680e0a
VS		 5762 gen7_setup_fixed_func_scheduler(dev_priv);
5763
3c0edaeb 5764 /*
0f846f81 5765 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5766 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 5767 */
5768 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 5769 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5770
c98f5062
AG		 5771 /* WaDisableL3Bank2xClockGate:vlv
5772 * Disabling L3 clock gating- MMIO 940c[25] = 1
5773 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5774 I915_WRITE(GEN7_UCGCTL4,
5775 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 5776
e0d8d59b 5777 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5778
afd58e79
VS		 5779 /*
5780 * BSpec says this must be set, even though
5781 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5782 */
6b26c86d
DV		 5783 I915_WRITE(CACHE_MODE_1,
5784 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5785
031994ee
VS		 5786 /*
5787 * WaIncreaseL3CreditsForVLVB0:vlv
5788 * This is the hardware default actually.
5789 */
5790 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5791
2d809570 5792 /*
ecdb4eb7 5793 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5794 * Disable clock gating on th GCFG unit to prevent a delay
5795 * in the reporting of vblank events.
5796 */
7a0d1eed 5797 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 5798}
5799
a4565da8
VS		 5800static void cherryview_init_clock_gating(struct drm_device *dev)
5801{
5802 struct drm_i915_private *dev_priv = dev->dev_private;
67c3bf6f
D		 5803 u32 val;
5804
5805 mutex_lock(&dev_priv->rps.hw_lock);
5806 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
5807 mutex_unlock(&dev_priv->rps.hw_lock);
5808 switch ((val >> 2) & 0x7) {
5809 case 0:
5810 case 1:
5811 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;
5812 dev_priv->mem_freq = 1600;
5813 break;
5814 case 2:
5815 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;
5816 dev_priv->mem_freq = 1600;
5817 break;
5818 case 3:
5819 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;
5820 dev_priv->mem_freq = 2000;
5821 break;
5822 case 4:
5823 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;
5824 dev_priv->mem_freq = 1600;
5825 break;
5826 case 5:
5827 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;
5828 dev_priv->mem_freq = 1600;
5829 break;
5830 }
5831 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
a4565da8
VS		 5832
5833 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5834
5835 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
dd811e70
VS		 5836
5837 /* WaDisablePartialInstShootdown:chv */
5838 I915_WRITE(GEN8_ROW_CHICKEN,
5839 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
a7068025
VS		 5840
5841 /* WaDisableThreadStallDopClockGating:chv */
5842 I915_WRITE(GEN8_ROW_CHICKEN,
5843 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
232ce337
VS		 5844
5845 /* WaVSRefCountFullforceMissDisable:chv */
5846 /* WaDSRefCountFullforceMissDisable:chv */
5847 I915_WRITE(GEN7_FF_THREAD_MODE,
5848 I915_READ(GEN7_FF_THREAD_MODE) &
5849 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 5850
5851 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5852 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5853 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 5854
5855 /* WaDisableCSUnitClockGating:chv */
5856 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5857 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 5858
5859 /* WaDisableSDEUnitClockGating:chv */
5860 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5861 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
e0d34ce7
RB		 5862
5863 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5864 I915_WRITE(HALF_SLICE_CHICKEN3,
5865 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
e4443e45
VS		 5866
5867 /* WaDisableGunitClockGating:chv (pre-production hw) */
5868 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5869 GINT_DIS);
5870
5871 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5872 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5873 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5874
5875 /* WaDisableDopClockGating:chv (pre-production hw) */
5876 I915_WRITE(GEN7_ROW_CHICKEN2,
5877 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5878 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5879 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS		 5880}
5881
1fa61106 5882static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5883{
5884 struct drm_i915_private *dev_priv = dev->dev_private;
5885 uint32_t dspclk_gate;
5886
5887 I915_WRITE(RENCLK_GATE_D1, 0);
5888 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5889 GS_UNIT_CLOCK_GATE_DISABLE |
5890 CL_UNIT_CLOCK_GATE_DISABLE);
5891 I915_WRITE(RAMCLK_GATE_D, 0);
5892 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5893 OVRUNIT_CLOCK_GATE_DISABLE |
5894 OVCUNIT_CLOCK_GATE_DISABLE;
5895 if (IS_GM45(dev))
5896 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5897 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5898
5899 /* WaDisableRenderCachePipelinedFlush */
5900 I915_WRITE(CACHE_MODE_0,
5901 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5902
4e04632e
AG		 5903 /* WaDisable_RenderCache_OperationalFlush:g4x */
5904 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5905
0e088b8f 5906 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5907}
5908
1fa61106 5909static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5910{
5911 struct drm_i915_private *dev_priv = dev->dev_private;
5912
5913 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5914 I915_WRITE(RENCLK_GATE_D2, 0);
5915 I915_WRITE(DSPCLK_GATE_D, 0);
5916 I915_WRITE(RAMCLK_GATE_D, 0);
5917 I915_WRITE16(DEUC, 0);
20f94967
VS		 5918 I915_WRITE(MI_ARB_STATE,
5919 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5920
5921 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5922 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5923}
5924
1fa61106 5925static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5926{
5927 struct drm_i915_private *dev_priv = dev->dev_private;
5928
5929 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5930 I965_RCC_CLOCK_GATE_DISABLE |
5931 I965_RCPB_CLOCK_GATE_DISABLE |
5932 I965_ISC_CLOCK_GATE_DISABLE |
5933 I965_FBC_CLOCK_GATE_DISABLE);
5934 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5935 I915_WRITE(MI_ARB_STATE,
5936 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5937
5938 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5939 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5940}
5941
1fa61106 5942static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5943{
5944 struct drm_i915_private *dev_priv = dev->dev_private;
5945 u32 dstate = I915_READ(D_STATE);
5946
5947 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5948 DSTATE_DOT_CLOCK_GATING;
5949 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5950
5951 if (IS_PINEVIEW(dev))
5952 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5953
5954 /* IIR "flip pending" means done if this bit is set */
5955 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 5956
5957 /* interrupts should cause a wake up from C3 */
3299254f 5958 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 5959
5960 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5961 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6f1d69b0
ED		 5962}
5963
1fa61106 5964static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5965{
5966 struct drm_i915_private *dev_priv = dev->dev_private;
5967
5968 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 5969
5970 /* interrupts should cause a wake up from C3 */
5971 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
5972 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6f1d69b0
ED		 5973}
5974
1fa61106 5975static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5976{
5977 struct drm_i915_private *dev_priv = dev->dev_private;
5978
5979 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5980}
5981
6f1d69b0
ED		 5982void intel_init_clock_gating(struct drm_device *dev)
5983{
5984 struct drm_i915_private *dev_priv = dev->dev_private;
5985
5986 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5987}
5988
7d708ee4
ID		 5989void intel_suspend_hw(struct drm_device *dev)
5990{
5991 if (HAS_PCH_LPT(dev))
5992 lpt_suspend_hw(dev);
5993}
5994
c1ca727f
ID		 5995#define for_each_power_well(i, power_well, domain_mask, power_domains) \
5996 for (i = 0; \
5997 i < (power_domains)->power_well_count && \
5998 ((power_well) = &(power_domains)->power_wells[i]); \
5999 i++) \
6000 if ((power_well)->domains & (domain_mask))
6001
6002#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
6003 for (i = (power_domains)->power_well_count - 1; \
6004 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
6005 i--) \
6006 if ((power_well)->domains & (domain_mask))
6007
15d199ea
PZ		 6008/**
6009 * We should only use the power well if we explicitly asked the hardware to
6010 * enable it, so check if it's enabled and also check if we've requested it to
6011 * be enabled.
6012 */
da7e29bd 6013static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
c1ca727f
ID		 6014 struct i915_power_well *power_well)
6015{
c1ca727f
ID		 6016 return I915_READ(HSW_PWR_WELL_DRIVER) ==
6017 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
6018}
6019
bfafe93a
ID		 6020bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
6021 enum intel_display_power_domain domain)
ddf9c536 6022{
ddf9c536 6023 struct i915_power_domains *power_domains;
b8c000d9
ID		 6024 struct i915_power_well *power_well;
6025 bool is_enabled;
6026 int i;
6027
6028 if (dev_priv->pm.suspended)
6029 return false;
ddf9c536
ID		 6030
6031 power_domains = &dev_priv->power_domains;
bfafe93a 6032
b8c000d9 6033 is_enabled = true;
bfafe93a 6034
b8c000d9
ID		 6035 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6036 if (power_well->always_on)
6037 continue;
ddf9c536 6038
bfafe93a 6039 if (!power_well->hw_enabled) {
b8c000d9
ID		 6040 is_enabled = false;
6041 break;
6042 }
6043 }
bfafe93a 6044
b8c000d9 6045 return is_enabled;
ddf9c536
ID		 6046}
6047
da7e29bd 6048bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
b97186f0 6049 enum intel_display_power_domain domain)
15d199ea 6050{
c1ca727f 6051 struct i915_power_domains *power_domains;
bfafe93a 6052 bool ret;
882244a3 6053
c1ca727f
ID		 6054 power_domains = &dev_priv->power_domains;
6055
c1ca727f 6056 mutex_lock(&power_domains->lock);
bfafe93a 6057 ret = intel_display_power_enabled_unlocked(dev_priv, domain);
c1ca727f
ID		 6058 mutex_unlock(&power_domains->lock);
6059
bfafe93a 6060 return ret;
15d199ea
PZ		 6061}
6062
93c73e8c
ID		 6063/*
6064 * Starting with Haswell, we have a "Power Down Well" that can be turned off
6065 * when not needed anymore. We have 4 registers that can request the power well
6066 * to be enabled, and it will only be disabled if none of the registers is
6067 * requesting it to be enabled.
6068 */
d5e8fdc8
PZ		 6069static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
6070{
6071 struct drm_device *dev = dev_priv->dev;
d5e8fdc8 6072
f9dcb0df
PZ		 6073 /*
6074 * After we re-enable the power well, if we touch VGA register 0x3d5
6075 * we'll get unclaimed register interrupts. This stops after we write
6076 * anything to the VGA MSR register. The vgacon module uses this
6077 * register all the time, so if we unbind our driver and, as a
6078 * consequence, bind vgacon, we'll get stuck in an infinite loop at
6079 * console_unlock(). So make here we touch the VGA MSR register, making
6080 * sure vgacon can keep working normally without triggering interrupts
6081 * and error messages.
6082 */
6083 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6084 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
6085 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6086
d49bdb0e
PZ		 6087 if (IS_BROADWELL(dev))
6088 gen8_irq_power_well_post_enable(dev_priv);
d5e8fdc8
PZ		 6089}
6090
da7e29bd 6091static void hsw_set_power_well(struct drm_i915_private *dev_priv,
c1ca727f 6092 struct i915_power_well *power_well, bool enable)
d0d3e513 6093{
fa42e23c
PZ		 6094 bool is_enabled, enable_requested;
6095 uint32_t tmp;
d0d3e513 6096
fa42e23c 6097 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 6098 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
6099 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 6100
fa42e23c
PZ		 6101 if (enable) {
6102 if (!enable_requested)
6aedd1f5
PZ		 6103 I915_WRITE(HSW_PWR_WELL_DRIVER,
6104 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 6105
fa42e23c
PZ		 6106 if (!is_enabled) {
6107 DRM_DEBUG_KMS("Enabling power well\n");
6108 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 6109 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 6110 DRM_ERROR("Timeout enabling power well\n");
6111 }
596cc11e 6112
d5e8fdc8 6113 hsw_power_well_post_enable(dev_priv);
fa42e23c
PZ		 6114 } else {
6115 if (enable_requested) {
6116 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 6117 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 6118 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 6119 }
6120 }
fa42e23c 6121}
d0d3e513 6122
c6cb582e
ID		 6123static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
6124 struct i915_power_well *power_well)
6125{
6126 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
6127
6128 /*
6129 * We're taking over the BIOS, so clear any requests made by it since
6130 * the driver is in charge now.
6131 */
6132 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6133 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6134}
6135
6136static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
6137 struct i915_power_well *power_well)
6138{
c6cb582e
ID		 6139 hsw_set_power_well(dev_priv, power_well, true);
6140}
6141
6142static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
6143 struct i915_power_well *power_well)
6144{
6145 hsw_set_power_well(dev_priv, power_well, false);
c6cb582e
ID		 6146}
6147
a45f4466
ID		 6148static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
6149 struct i915_power_well *power_well)
6150{
6151}
6152
6153static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
6154 struct i915_power_well *power_well)
6155{
6156 return true;
6157}
6158
d2011dc8
VS		 6159static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6160 struct i915_power_well *power_well, bool enable)
77961eb9 6161{
d2011dc8 6162 enum punit_power_well power_well_id = power_well->data;
77961eb9
ID		 6163 u32 mask;
6164 u32 state;
6165 u32 ctrl;
6166
6167 mask = PUNIT_PWRGT_MASK(power_well_id);
6168 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6169 PUNIT_PWRGT_PWR_GATE(power_well_id);
6170
6171 mutex_lock(&dev_priv->rps.hw_lock);
6172
6173#define COND \
6174 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6175
6176 if (COND)
6177 goto out;
6178
6179 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6180 ctrl &= ~mask;
6181 ctrl |= state;
6182 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6183
6184 if (wait_for(COND, 100))
6185 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6186 state,
6187 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6188
6189#undef COND
6190
6191out:
6192 mutex_unlock(&dev_priv->rps.hw_lock);
6193}
6194
6195static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6196 struct i915_power_well *power_well)
6197{
6198 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6199}
6200
6201static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6202 struct i915_power_well *power_well)
6203{
6204 vlv_set_power_well(dev_priv, power_well, true);
6205}
6206
6207static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6208 struct i915_power_well *power_well)
6209{
6210 vlv_set_power_well(dev_priv, power_well, false);
6211}
6212
6213static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6214 struct i915_power_well *power_well)
6215{
6216 int power_well_id = power_well->data;
6217 bool enabled = false;
6218 u32 mask;
6219 u32 state;
6220 u32 ctrl;
6221
6222 mask = PUNIT_PWRGT_MASK(power_well_id);
6223 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6224
6225 mutex_lock(&dev_priv->rps.hw_lock);
6226
6227 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6228 /*
6229 * We only ever set the power-on and power-gate states, anything
6230 * else is unexpected.
6231 */
6232 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6233 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6234 if (state == ctrl)
6235 enabled = true;
6236
6237 /*
6238 * A transient state at this point would mean some unexpected party
6239 * is poking at the power controls too.
6240 */
6241 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6242 WARN_ON(ctrl != state);
6243
6244 mutex_unlock(&dev_priv->rps.hw_lock);
6245
6246 return enabled;
6247}
6248
6249static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6250 struct i915_power_well *power_well)
6251{
6252 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6253
6254 vlv_set_power_well(dev_priv, power_well, true);
6255
6256 spin_lock_irq(&dev_priv->irq_lock);
6257 valleyview_enable_display_irqs(dev_priv);
6258 spin_unlock_irq(&dev_priv->irq_lock);
6259
6260 /*
0d116a29
ID		 6261 * During driver initialization/resume we can avoid restoring the
6262 * part of the HW/SW state that will be inited anyway explicitly.
77961eb9 6263 */
0d116a29
ID		 6264 if (dev_priv->power_domains.initializing)
6265 return;
6266
6267 intel_hpd_init(dev_priv->dev);
77961eb9
ID		 6268
6269 i915_redisable_vga_power_on(dev_priv->dev);
6270}
6271
6272static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6273 struct i915_power_well *power_well)
6274{
77961eb9
ID		 6275 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6276
6277 spin_lock_irq(&dev_priv->irq_lock);
77961eb9
ID		 6278 valleyview_disable_display_irqs(dev_priv);
6279 spin_unlock_irq(&dev_priv->irq_lock);
6280
77961eb9
ID		 6281 vlv_set_power_well(dev_priv, power_well, false);
6282}
6283
aa519f23
VS		 6284static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6285 struct i915_power_well *power_well)
6286{
6287 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6288
6289 /*
6290 * Enable the CRI clock source so we can get at the
6291 * display and the reference clock for VGA
6292 * hotplug / manual detection.
6293 */
6294 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6295 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6296 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6297
6298 vlv_set_power_well(dev_priv, power_well, true);
6299
6300 /*
6301 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6302 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6303 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6304 * b. The other bits such as sfr settings / modesel may all
6305 * be set to 0.
6306 *
6307 * This should only be done on init and resume from S3 with
6308 * both PLLs disabled, or we risk losing DPIO and PLL
6309 * synchronization.
6310 */
6311 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
6312}
6313
6314static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6315 struct i915_power_well *power_well)
6316{
6317 struct drm_device *dev = dev_priv->dev;
6318 enum pipe pipe;
6319
6320 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6321
6322 for_each_pipe(pipe)
6323 assert_pll_disabled(dev_priv, pipe);
6324
6325 /* Assert common reset */
6326 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
6327
6328 vlv_set_power_well(dev_priv, power_well, false);
6329}
6330
5d6f7ea7
VS		 6331static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6332 struct i915_power_well *power_well)
6333{
6334 enum dpio_phy phy;
6335
6336 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6337 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6338
6339 /*
6340 * Enable the CRI clock source so we can get at the
6341 * display and the reference clock for VGA
6342 * hotplug / manual detection.
6343 */
6344 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6345 phy = DPIO_PHY0;
6346 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6347 DPLL_REFA_CLK_ENABLE_VLV);
6348 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6349 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6350 } else {
6351 phy = DPIO_PHY1;
6352 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
6353 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6354 }
6355 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6356 vlv_set_power_well(dev_priv, power_well, true);
6357
6358 /* Poll for phypwrgood signal */
6359 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
6360 DRM_ERROR("Display PHY %d is not power up\n", phy);
6361
6362 I915_WRITE(DISPLAY_PHY_CONTROL,
6363 PHY_COM_LANE_RESET_DEASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL)));
6364}
6365
6366static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6367 struct i915_power_well *power_well)
6368{
6369 enum dpio_phy phy;
6370
6371 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6372 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6373
6374 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6375 phy = DPIO_PHY0;
6376 assert_pll_disabled(dev_priv, PIPE_A);
6377 assert_pll_disabled(dev_priv, PIPE_B);
6378 } else {
6379 phy = DPIO_PHY1;
6380 assert_pll_disabled(dev_priv, PIPE_C);
6381 }
6382
6383 I915_WRITE(DISPLAY_PHY_CONTROL,
6384 PHY_COM_LANE_RESET_ASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL)));
6385
6386 vlv_set_power_well(dev_priv, power_well, false);
6387}
6388
26972b0a
VS		 6389static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
6390 struct i915_power_well *power_well)
6391{
6392 enum pipe pipe = power_well->data;
6393 bool enabled;
6394 u32 state, ctrl;
6395
6396 mutex_lock(&dev_priv->rps.hw_lock);
6397
6398 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
6399 /*
6400 * We only ever set the power-on and power-gate states, anything
6401 * else is unexpected.
6402 */
6403 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
6404 enabled = state == DP_SSS_PWR_ON(pipe);
6405
6406 /*
6407 * A transient state at this point would mean some unexpected party
6408 * is poking at the power controls too.
6409 */
6410 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
6411 WARN_ON(ctrl << 16 != state);
6412
6413 mutex_unlock(&dev_priv->rps.hw_lock);
6414
6415 return enabled;
6416}
6417
6418static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
6419 struct i915_power_well *power_well,
6420 bool enable)
6421{
6422 enum pipe pipe = power_well->data;
6423 u32 state;
6424 u32 ctrl;
6425
6426 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
6427
6428 mutex_lock(&dev_priv->rps.hw_lock);
6429
6430#define COND \
6431 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
6432
6433 if (COND)
6434 goto out;
6435
6436 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6437 ctrl &= ~DP_SSC_MASK(pipe);
6438 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
6439 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
6440
6441 if (wait_for(COND, 100))
6442 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6443 state,
6444 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
6445
6446#undef COND
6447
6448out:
6449 mutex_unlock(&dev_priv->rps.hw_lock);
6450}
6451
6452static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
6453 struct i915_power_well *power_well)
6454{
6455 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
6456}
6457
6458static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
6459 struct i915_power_well *power_well)
6460{
6461 WARN_ON_ONCE(power_well->data != PIPE_A &&
6462 power_well->data != PIPE_B &&
6463 power_well->data != PIPE_C);
6464
6465 chv_set_pipe_power_well(dev_priv, power_well, true);
6466}
6467
6468static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
6469 struct i915_power_well *power_well)
6470{
6471 WARN_ON_ONCE(power_well->data != PIPE_A &&
6472 power_well->data != PIPE_B &&
6473 power_well->data != PIPE_C);
6474
6475 chv_set_pipe_power_well(dev_priv, power_well, false);
6476}
6477
25eaa003
ID		 6478static void check_power_well_state(struct drm_i915_private *dev_priv,
6479 struct i915_power_well *power_well)
6480{
6481 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6482
6483 if (power_well->always_on || !i915.disable_power_well) {
6484 if (!enabled)
6485 goto mismatch;
6486
6487 return;
6488 }
6489
6490 if (enabled != (power_well->count > 0))
6491 goto mismatch;
6492
6493 return;
6494
6495mismatch:
6496 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6497 power_well->name, power_well->always_on, enabled,
6498 power_well->count, i915.disable_power_well);
6499}
6500
da7e29bd 6501void intel_display_power_get(struct drm_i915_private *dev_priv,
6765625e
VS		 6502 enum intel_display_power_domain domain)
6503{
83c00f55 6504 struct i915_power_domains *power_domains;
c1ca727f
ID		 6505 struct i915_power_well *power_well;
6506 int i;
6765625e 6507
9e6ea71a
PZ		 6508 intel_runtime_pm_get(dev_priv);
6509
83c00f55
ID		 6510 power_domains = &dev_priv->power_domains;
6511
6512 mutex_lock(&power_domains->lock);
1da51581 6513
25eaa003
ID		 6514 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6515 if (!power_well->count++) {
6516 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
c6cb582e 6517 power_well->ops->enable(dev_priv, power_well);
bfafe93a 6518 power_well->hw_enabled = true;
25eaa003
ID		 6519 }
6520
6521 check_power_well_state(dev_priv, power_well);
6522 }
1da51581 6523
ddf9c536
ID		 6524 power_domains->domain_use_count[domain]++;
6525
83c00f55 6526 mutex_unlock(&power_domains->lock);
6765625e
VS		 6527}
6528
da7e29bd 6529void intel_display_power_put(struct drm_i915_private *dev_priv,
6765625e
VS		 6530 enum intel_display_power_domain domain)
6531{
83c00f55 6532 struct i915_power_domains *power_domains;
c1ca727f
ID		 6533 struct i915_power_well *power_well;
6534 int i;
6765625e 6535
83c00f55
ID		 6536 power_domains = &dev_priv->power_domains;
6537
6538 mutex_lock(&power_domains->lock);
1da51581 6539
1da51581
ID		 6540 WARN_ON(!power_domains->domain_use_count[domain]);
6541 power_domains->domain_use_count[domain]--;
ddf9c536 6542
70bf407c
ID		 6543 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6544 WARN_ON(!power_well->count);
6545
25eaa003
ID		 6546 if (!--power_well->count && i915.disable_power_well) {
6547 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
bfafe93a 6548 power_well->hw_enabled = false;
c6cb582e 6549 power_well->ops->disable(dev_priv, power_well);
25eaa003
ID		 6550 }
6551
6552 check_power_well_state(dev_priv, power_well);
70bf407c 6553 }
1da51581 6554
83c00f55 6555 mutex_unlock(&power_domains->lock);
9e6ea71a
PZ		 6556
6557 intel_runtime_pm_put(dev_priv);
6765625e
VS		 6558}
6559
83c00f55 6560static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 6561
6562/* Display audio driver power well request */
74b0c2d7 6563int i915_request_power_well(void)
a38911a3 6564{
b4ed4484
ID		 6565 struct drm_i915_private *dev_priv;
6566
74b0c2d7
TI		 6567 if (!hsw_pwr)
6568 return -ENODEV;
a38911a3 6569
b4ed4484
ID		 6570 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6571 power_domains);
da7e29bd 6572 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
74b0c2d7 6573 return 0;
a38911a3
WX		 6574}
6575EXPORT_SYMBOL_GPL(i915_request_power_well);
6576
6577/* Display audio driver power well release */
74b0c2d7 6578int i915_release_power_well(void)
a38911a3 6579{
b4ed4484
ID		 6580 struct drm_i915_private *dev_priv;
6581
74b0c2d7
TI		 6582 if (!hsw_pwr)
6583 return -ENODEV;
a38911a3 6584
b4ed4484
ID		 6585 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6586 power_domains);
da7e29bd 6587 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
74b0c2d7 6588 return 0;
a38911a3
WX		 6589}
6590EXPORT_SYMBOL_GPL(i915_release_power_well);
6591
c149dcb5
JN		 6592/*
6593 * Private interface for the audio driver to get CDCLK in kHz.
6594 *
6595 * Caller must request power well using i915_request_power_well() prior to
6596 * making the call.
6597 */
6598int i915_get_cdclk_freq(void)
6599{
6600 struct drm_i915_private *dev_priv;
6601
6602 if (!hsw_pwr)
6603 return -ENODEV;
6604
6605 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6606 power_domains);
6607
6608 return intel_ddi_get_cdclk_freq(dev_priv);
6609}
6610EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6611
6612
efcad917
ID		 6613#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6614
6615#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6616 BIT(POWER_DOMAIN_PIPE_A) | \
f5938f36 6617 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
319be8ae
ID		 6618 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6619 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6620 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6621 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6622 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6623 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6624 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6625 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6626 BIT(POWER_DOMAIN_PORT_CRT) | \
bd2bb1b9 6627 BIT(POWER_DOMAIN_PLLS) | \
f5938f36 6628 BIT(POWER_DOMAIN_INIT))
efcad917
ID		 6629#define HSW_DISPLAY_POWER_DOMAINS ( \
6630 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6631 BIT(POWER_DOMAIN_INIT))
6632
6633#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6634 HSW_ALWAYS_ON_POWER_DOMAINS | \
6635 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6636#define BDW_DISPLAY_POWER_DOMAINS ( \
6637 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6638 BIT(POWER_DOMAIN_INIT))
6639
77961eb9
ID		 6640#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6641#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6642
6643#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6644 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6645 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6646 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6647 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6648 BIT(POWER_DOMAIN_PORT_CRT) | \
6649 BIT(POWER_DOMAIN_INIT))
6650
6651#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6652 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6653 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6654 BIT(POWER_DOMAIN_INIT))
6655
6656#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6657 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6658 BIT(POWER_DOMAIN_INIT))
6659
6660#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6661 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6662 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6663 BIT(POWER_DOMAIN_INIT))
6664
6665#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6666 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6667 BIT(POWER_DOMAIN_INIT))
6668
26972b0a
VS		 6669#define CHV_PIPE_A_POWER_DOMAINS ( \
6670 BIT(POWER_DOMAIN_PIPE_A) | \
6671 BIT(POWER_DOMAIN_INIT))
6672
6673#define CHV_PIPE_B_POWER_DOMAINS ( \
6674 BIT(POWER_DOMAIN_PIPE_B) | \
6675 BIT(POWER_DOMAIN_INIT))
6676
6677#define CHV_PIPE_C_POWER_DOMAINS ( \
6678 BIT(POWER_DOMAIN_PIPE_C) | \
6679 BIT(POWER_DOMAIN_INIT))
6680
5d6f7ea7
VS		 6681#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6682 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6683 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6684 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6685 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6686 BIT(POWER_DOMAIN_INIT))
6687
6688#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6689 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6690 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6691 BIT(POWER_DOMAIN_INIT))
6692
2ce147f3
VS		 6693#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
6694 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6695 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6696 BIT(POWER_DOMAIN_INIT))
6697
6698#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
6699 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6700 BIT(POWER_DOMAIN_INIT))
6701
a45f4466
ID		 6702static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6703 .sync_hw = i9xx_always_on_power_well_noop,
6704 .enable = i9xx_always_on_power_well_noop,
6705 .disable = i9xx_always_on_power_well_noop,
6706 .is_enabled = i9xx_always_on_power_well_enabled,
6707};
c6cb582e 6708
26972b0a
VS		 6709static const struct i915_power_well_ops chv_pipe_power_well_ops = {
6710 .sync_hw = chv_pipe_power_well_sync_hw,
6711 .enable = chv_pipe_power_well_enable,
6712 .disable = chv_pipe_power_well_disable,
6713 .is_enabled = chv_pipe_power_well_enabled,
6714};
6715
5d6f7ea7
VS		 6716static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
6717 .sync_hw = vlv_power_well_sync_hw,
6718 .enable = chv_dpio_cmn_power_well_enable,
6719 .disable = chv_dpio_cmn_power_well_disable,
6720 .is_enabled = vlv_power_well_enabled,
6721};
6722
1c2256df
ID		 6723static struct i915_power_well i9xx_always_on_power_well[] = {
6724 {
6725 .name = "always-on",
6726 .always_on = 1,
6727 .domains = POWER_DOMAIN_MASK,
c6cb582e 6728 .ops = &i9xx_always_on_power_well_ops,
1c2256df
ID		 6729 },
6730};
6731
c6cb582e
ID		 6732static const struct i915_power_well_ops hsw_power_well_ops = {
6733 .sync_hw = hsw_power_well_sync_hw,
6734 .enable = hsw_power_well_enable,
6735 .disable = hsw_power_well_disable,
6736 .is_enabled = hsw_power_well_enabled,
6737};
6738
c1ca727f 6739static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 6740 {
6741 .name = "always-on",
6742 .always_on = 1,
6743 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 6744 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 6745 },
c1ca727f
ID		 6746 {
6747 .name = "display",
efcad917 6748 .domains = HSW_DISPLAY_POWER_DOMAINS,
c6cb582e 6749 .ops = &hsw_power_well_ops,
c1ca727f
ID		 6750 },
6751};
6752
6753static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 6754 {
6755 .name = "always-on",
6756 .always_on = 1,
6757 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 6758 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 6759 },
c1ca727f
ID		 6760 {
6761 .name = "display",
efcad917 6762 .domains = BDW_DISPLAY_POWER_DOMAINS,
c6cb582e 6763 .ops = &hsw_power_well_ops,
c1ca727f
ID		 6764 },
6765};
6766
77961eb9
ID		 6767static const struct i915_power_well_ops vlv_display_power_well_ops = {
6768 .sync_hw = vlv_power_well_sync_hw,
6769 .enable = vlv_display_power_well_enable,
6770 .disable = vlv_display_power_well_disable,
6771 .is_enabled = vlv_power_well_enabled,
6772};
6773
aa519f23
VS		 6774static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
6775 .sync_hw = vlv_power_well_sync_hw,
6776 .enable = vlv_dpio_cmn_power_well_enable,
6777 .disable = vlv_dpio_cmn_power_well_disable,
6778 .is_enabled = vlv_power_well_enabled,
6779};
6780
77961eb9
ID		 6781static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6782 .sync_hw = vlv_power_well_sync_hw,
6783 .enable = vlv_power_well_enable,
6784 .disable = vlv_power_well_disable,
6785 .is_enabled = vlv_power_well_enabled,
6786};
6787
6788static struct i915_power_well vlv_power_wells[] = {
6789 {
6790 .name = "always-on",
6791 .always_on = 1,
6792 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6793 .ops = &i9xx_always_on_power_well_ops,
6794 },
6795 {
6796 .name = "display",
6797 .domains = VLV_DISPLAY_POWER_DOMAINS,
6798 .data = PUNIT_POWER_WELL_DISP2D,
6799 .ops = &vlv_display_power_well_ops,
6800 },
77961eb9
ID		 6801 {
6802 .name = "dpio-tx-b-01",
6803 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6804 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6805 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6806 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6807 .ops = &vlv_dpio_power_well_ops,
6808 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6809 },
6810 {
6811 .name = "dpio-tx-b-23",
6812 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6813 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6814 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6815 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6816 .ops = &vlv_dpio_power_well_ops,
6817 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6818 },
6819 {
6820 .name = "dpio-tx-c-01",
6821 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6822 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6823 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6824 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6825 .ops = &vlv_dpio_power_well_ops,
6826 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6827 },
6828 {
6829 .name = "dpio-tx-c-23",
6830 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6831 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6832 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6833 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6834 .ops = &vlv_dpio_power_well_ops,
6835 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6836 },
f099a3c6
JB		 6837 {
6838 .name = "dpio-common",
6839 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6840 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
aa519f23 6841 .ops = &vlv_dpio_cmn_power_well_ops,
f099a3c6 6842 },
77961eb9
ID		 6843};
6844
4811ff4f
VS		 6845static struct i915_power_well chv_power_wells[] = {
6846 {
6847 .name = "always-on",
6848 .always_on = 1,
6849 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6850 .ops = &i9xx_always_on_power_well_ops,
6851 },
f07057d1
VS		 6852#if 0
6853 {
6854 .name = "display",
6855 .domains = VLV_DISPLAY_POWER_DOMAINS,
6856 .data = PUNIT_POWER_WELL_DISP2D,
6857 .ops = &vlv_display_power_well_ops,
6858 },
26972b0a
VS		 6859 {
6860 .name = "pipe-a",
6861 .domains = CHV_PIPE_A_POWER_DOMAINS,
6862 .data = PIPE_A,
6863 .ops = &chv_pipe_power_well_ops,
6864 },
6865 {
6866 .name = "pipe-b",
6867 .domains = CHV_PIPE_B_POWER_DOMAINS,
6868 .data = PIPE_B,
6869 .ops = &chv_pipe_power_well_ops,
6870 },
6871 {
6872 .name = "pipe-c",
6873 .domains = CHV_PIPE_C_POWER_DOMAINS,
6874 .data = PIPE_C,
6875 .ops = &chv_pipe_power_well_ops,
6876 },
f07057d1 6877#endif
5d6f7ea7
VS		 6878 {
6879 .name = "dpio-common-bc",
6880 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
6881 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6882 .ops = &chv_dpio_cmn_power_well_ops,
6883 },
6884 {
6885 .name = "dpio-common-d",
6886 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
6887 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
6888 .ops = &chv_dpio_cmn_power_well_ops,
6889 },
82583565
VS		 6890#if 0
6891 {
6892 .name = "dpio-tx-b-01",
6893 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6894 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
6895 .ops = &vlv_dpio_power_well_ops,
6896 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6897 },
6898 {
6899 .name = "dpio-tx-b-23",
6900 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6901 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
6902 .ops = &vlv_dpio_power_well_ops,
6903 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6904 },
6905 {
6906 .name = "dpio-tx-c-01",
6907 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6908 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6909 .ops = &vlv_dpio_power_well_ops,
6910 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6911 },
6912 {
6913 .name = "dpio-tx-c-23",
6914 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6915 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6916 .ops = &vlv_dpio_power_well_ops,
6917 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6918 },
2ce147f3
VS		 6919 {
6920 .name = "dpio-tx-d-01",
6921 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
6922 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
6923 .ops = &vlv_dpio_power_well_ops,
6924 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
6925 },
6926 {
6927 .name = "dpio-tx-d-23",
6928 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
6929 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
6930 .ops = &vlv_dpio_power_well_ops,
6931 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
6932 },
82583565 6933#endif
4811ff4f
VS		 6934};
6935
d2011dc8
VS		 6936static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
6937 enum punit_power_well power_well_id)
6938{
6939 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6940 struct i915_power_well *power_well;
6941 int i;
6942
6943 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
6944 if (power_well->data == power_well_id)
6945 return power_well;
6946 }
6947
6948 return NULL;
6949}
6950
c1ca727f
ID		 6951#define set_power_wells(power_domains, __power_wells) ({ \
6952 (power_domains)->power_wells = (__power_wells); \
6953 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6954})
6955
da7e29bd 6956int intel_power_domains_init(struct drm_i915_private *dev_priv)
a38911a3 6957{
83c00f55 6958 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 6959
83c00f55 6960 mutex_init(&power_domains->lock);
a38911a3 6961
c1ca727f
ID		 6962 /*
6963 * The enabling order will be from lower to higher indexed wells,
6964 * the disabling order is reversed.
6965 */
da7e29bd 6966 if (IS_HASWELL(dev_priv->dev)) {
c1ca727f
ID		 6967 set_power_wells(power_domains, hsw_power_wells);
6968 hsw_pwr = power_domains;
da7e29bd 6969 } else if (IS_BROADWELL(dev_priv->dev)) {
c1ca727f
ID		 6970 set_power_wells(power_domains, bdw_power_wells);
6971 hsw_pwr = power_domains;
4811ff4f
VS		 6972 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
6973 set_power_wells(power_domains, chv_power_wells);
77961eb9
ID		 6974 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6975 set_power_wells(power_domains, vlv_power_wells);
c1ca727f 6976 } else {
1c2256df 6977 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 6978 }
a38911a3
WX		 6979
6980 return 0;
6981}
6982
da7e29bd 6983void intel_power_domains_remove(struct drm_i915_private *dev_priv)
a38911a3
WX		 6984{
6985 hsw_pwr = NULL;
6986}
6987
da7e29bd 6988static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
9cdb826c 6989{
83c00f55
ID		 6990 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6991 struct i915_power_well *power_well;
c1ca727f 6992 int i;
9cdb826c 6993
83c00f55 6994 mutex_lock(&power_domains->lock);
bfafe93a 6995 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
a45f4466 6996 power_well->ops->sync_hw(dev_priv, power_well);
bfafe93a
ID		 6997 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
6998 power_well);
6999 }
83c00f55 7000 mutex_unlock(&power_domains->lock);
a38911a3
WX		 7001}
7002
d2011dc8
VS		 7003static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
7004{
7005 struct i915_power_well *cmn =
7006 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
7007 struct i915_power_well *disp2d =
7008 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
7009
7010 /* nothing to do if common lane is already off */
7011 if (!cmn->ops->is_enabled(dev_priv, cmn))
7012 return;
7013
7014 /* If the display might be already active skip this */
7015 if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
7016 I915_READ(DPIO_CTL) & DPIO_CMNRST)
7017 return;
7018
7019 DRM_DEBUG_KMS("toggling display PHY side reset\n");
7020
7021 /* cmnlane needs DPLL registers */
7022 disp2d->ops->enable(dev_priv, disp2d);
7023
7024 /*
7025 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
7026 * Need to assert and de-assert PHY SB reset by gating the
7027 * common lane power, then un-gating it.
7028 * Simply ungating isn't enough to reset the PHY enough to get
7029 * ports and lanes running.
7030 */
7031 cmn->ops->disable(dev_priv, cmn);
7032}
7033
da7e29bd 7034void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
d0d3e513 7035{
d2011dc8 7036 struct drm_device *dev = dev_priv->dev;
0d116a29
ID		 7037 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7038
7039 power_domains->initializing = true;
d2011dc8
VS		 7040
7041 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
7042 mutex_lock(&power_domains->lock);
7043 vlv_cmnlane_wa(dev_priv);
7044 mutex_unlock(&power_domains->lock);
7045 }
7046
fa42e23c 7047 /* For now, we need the power well to be always enabled. */
da7e29bd
ID		 7048 intel_display_set_init_power(dev_priv, true);
7049 intel_power_domains_resume(dev_priv);
0d116a29 7050 power_domains->initializing = false;
d0d3e513
ED		 7051}
7052
c67a470b
PZ		 7053void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
7054{
d361ae26 7055 intel_runtime_pm_get(dev_priv);
c67a470b
PZ		 7056}
7057
7058void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
7059{
d361ae26 7060 intel_runtime_pm_put(dev_priv);
c67a470b
PZ		 7061}
7062
8a187455
PZ		 7063void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
7064{
7065 struct drm_device *dev = dev_priv->dev;
7066 struct device *device = &dev->pdev->dev;
7067
7068 if (!HAS_RUNTIME_PM(dev))
7069 return;
7070
7071 pm_runtime_get_sync(device);
7072 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
7073}
7074
c6df39b5
ID		 7075void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
7076{
7077 struct drm_device *dev = dev_priv->dev;
7078 struct device *device = &dev->pdev->dev;
7079
7080 if (!HAS_RUNTIME_PM(dev))
7081 return;
7082
7083 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
7084 pm_runtime_get_noresume(device);
7085}
7086
8a187455
PZ		 7087void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
7088{
7089 struct drm_device *dev = dev_priv->dev;
7090 struct device *device = &dev->pdev->dev;
7091
7092 if (!HAS_RUNTIME_PM(dev))
7093 return;
7094
7095 pm_runtime_mark_last_busy(device);
7096 pm_runtime_put_autosuspend(device);
7097}
7098
7099void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
7100{
7101 struct drm_device *dev = dev_priv->dev;
7102 struct device *device = &dev->pdev->dev;
7103
8a187455
PZ		 7104 if (!HAS_RUNTIME_PM(dev))
7105 return;
7106
7107 pm_runtime_set_active(device);
7108
aeab0b5a
ID		 7109 /*
7110 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7111 * requirement.
7112 */
7113 if (!intel_enable_rc6(dev)) {
7114 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7115 return;
7116 }
7117
8a187455
PZ		 7118 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
7119 pm_runtime_mark_last_busy(device);
7120 pm_runtime_use_autosuspend(device);
ba0239e0
PZ		 7121
7122 pm_runtime_put_autosuspend(device);
8a187455
PZ		 7123}
7124
7125void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
7126{
7127 struct drm_device *dev = dev_priv->dev;
7128 struct device *device = &dev->pdev->dev;
7129
7130 if (!HAS_RUNTIME_PM(dev))
7131 return;
7132
aeab0b5a
ID		 7133 if (!intel_enable_rc6(dev))
7134 return;
7135
8a187455
PZ		 7136 /* Make sure we're not suspended first. */
7137 pm_runtime_get_sync(device);
7138 pm_runtime_disable(device);
7139}
7140
1fa61106
ED		 7141/* Set up chip specific power management-related functions */
7142void intel_init_pm(struct drm_device *dev)
7143{
7144 struct drm_i915_private *dev_priv = dev->dev_private;
7145
3a77c4c4 7146 if (HAS_FBC(dev)) {
40045465 7147 if (INTEL_INFO(dev)->gen >= 7) {
1fa61106 7148 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
40045465
VS		 7149 dev_priv->display.enable_fbc = gen7_enable_fbc;
7150 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7151 } else if (INTEL_INFO(dev)->gen >= 5) {
7152 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7153 dev_priv->display.enable_fbc = ironlake_enable_fbc;
1fa61106
ED		 7154 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7155 } else if (IS_GM45(dev)) {
7156 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7157 dev_priv->display.enable_fbc = g4x_enable_fbc;
7158 dev_priv->display.disable_fbc = g4x_disable_fbc;
40045465 7159 } else {
1fa61106
ED		 7160 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7161 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7162 dev_priv->display.disable_fbc = i8xx_disable_fbc;
993495ae
VS		 7163
7164 /* This value was pulled out of someone's hat */
7165 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1fa61106 7166 }
1fa61106
ED		 7167 }
7168
c921aba8
DV		 7169 /* For cxsr */
7170 if (IS_PINEVIEW(dev))
7171 i915_pineview_get_mem_freq(dev);
7172 else if (IS_GEN5(dev))
7173 i915_ironlake_get_mem_freq(dev);
7174
1fa61106
ED		 7175 /* For FIFO watermark updates */
7176 if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7177 ilk_setup_wm_latency(dev);
53615a5e 7178
bd602544
VS		 7179 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7180 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7181 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7182 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7183 dev_priv->display.update_wm = ilk_update_wm;
7184 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7185 } else {
7186 DRM_DEBUG_KMS("Failed to read display plane latency. "
7187 "Disable CxSR\n");
7188 }
7189
7190 if (IS_GEN5(dev))
1fa61106 7191 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7192 else if (IS_GEN6(dev))
1fa61106 7193 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7194 else if (IS_IVYBRIDGE(dev))
1fa61106 7195 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7196 else if (IS_HASWELL(dev))
cad2a2d7 7197 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7198 else if (INTEL_INFO(dev)->gen == 8)
1020a5c2 7199 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
a4565da8 7200 } else if (IS_CHERRYVIEW(dev)) {
3c2777fd 7201 dev_priv->display.update_wm = cherryview_update_wm;
a4565da8
VS		 7202 dev_priv->display.init_clock_gating =
7203 cherryview_init_clock_gating;
1fa61106
ED		 7204 } else if (IS_VALLEYVIEW(dev)) {
7205 dev_priv->display.update_wm = valleyview_update_wm;
7206 dev_priv->display.init_clock_gating =
7207 valleyview_init_clock_gating;
1fa61106
ED		 7208 } else if (IS_PINEVIEW(dev)) {
7209 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7210 dev_priv->is_ddr3,
7211 dev_priv->fsb_freq,
7212 dev_priv->mem_freq)) {
7213 DRM_INFO("failed to find known CxSR latency "
7214 "(found ddr%s fsb freq %d, mem freq %d), "
7215 "disabling CxSR\n",
7216 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7217 dev_priv->fsb_freq, dev_priv->mem_freq);
7218 /* Disable CxSR and never update its watermark again */
5209b1f4 7219 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7220 dev_priv->display.update_wm = NULL;
7221 } else
7222 dev_priv->display.update_wm = pineview_update_wm;
7223 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7224 } else if (IS_G4X(dev)) {
7225 dev_priv->display.update_wm = g4x_update_wm;
7226 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7227 } else if (IS_GEN4(dev)) {
7228 dev_priv->display.update_wm = i965_update_wm;
7229 if (IS_CRESTLINE(dev))
7230 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7231 else if (IS_BROADWATER(dev))
7232 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7233 } else if (IS_GEN3(dev)) {
7234 dev_priv->display.update_wm = i9xx_update_wm;
7235 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7236 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7237 } else if (IS_GEN2(dev)) {
7238 if (INTEL_INFO(dev)->num_pipes == 1) {
7239 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7240 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7241 } else {
7242 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7243 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7244 }
7245
7246 if (IS_I85X(dev) || IS_I865G(dev))
7247 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7248 else
7249 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7250 } else {
7251 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7252 }
7253}
7254
42c0526c
BW		 7255int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
7256{
4fc688ce 7257 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7258
7259 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7260 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7261 return -EAGAIN;
7262 }
7263
7264 I915_WRITE(GEN6_PCODE_DATA, *val);
7265 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7266
7267 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7268 500)) {
7269 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7270 return -ETIMEDOUT;
7271 }
7272
7273 *val = I915_READ(GEN6_PCODE_DATA);
7274 I915_WRITE(GEN6_PCODE_DATA, 0);
7275
7276 return 0;
7277}
7278
7279int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
7280{
4fc688ce 7281 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7282
7283 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7284 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7285 return -EAGAIN;
7286 }
7287
7288 I915_WRITE(GEN6_PCODE_DATA, val);
7289 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7290
7291 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7292 500)) {
7293 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7294 return -ETIMEDOUT;
7295 }
7296
7297 I915_WRITE(GEN6_PCODE_DATA, 0);
7298
7299 return 0;
7300}
a0e4e199 7301
b55dd647 7302static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 7303{
07ab118b 7304 int div;
855ba3be 7305
07ab118b 7306 /* 4 x czclk */
2ec3815f 7307 switch (dev_priv->mem_freq) {
855ba3be 7308 case 800:
07ab118b 7309 div = 10;
855ba3be
JB		 7310 break;
7311 case 1066:
07ab118b 7312 div = 12;
855ba3be
JB		 7313 break;
7314 case 1333:
07ab118b 7315 div = 16;
855ba3be
JB		 7316 break;
7317 default:
7318 return -1;
7319 }
7320
2ec3815f 7321 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 7322}
7323
b55dd647 7324static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7325{
07ab118b 7326 int mul;
855ba3be 7327
07ab118b 7328 /* 4 x czclk */
2ec3815f 7329 switch (dev_priv->mem_freq) {
855ba3be 7330 case 800:
07ab118b 7331 mul = 10;
855ba3be
JB		 7332 break;
7333 case 1066:
07ab118b 7334 mul = 12;
855ba3be
JB		 7335 break;
7336 case 1333:
07ab118b 7337 mul = 16;
855ba3be
JB		 7338 break;
7339 default:
7340 return -1;
7341 }
7342
2ec3815f 7343 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 7344}
7345
b55dd647 7346static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8
D		 7347{
7348 int div, freq;
7349
7350 switch (dev_priv->rps.cz_freq) {
7351 case 200:
7352 div = 5;
7353 break;
7354 case 267:
7355 div = 6;
7356 break;
7357 case 320:
7358 case 333:
7359 case 400:
7360 div = 8;
7361 break;
7362 default:
7363 return -1;
7364 }
7365
7366 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
7367
7368 return freq;
7369}
7370
b55dd647 7371static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8
D		 7372{
7373 int mul, opcode;
7374
7375 switch (dev_priv->rps.cz_freq) {
7376 case 200:
7377 mul = 5;
7378 break;
7379 case 267:
7380 mul = 6;
7381 break;
7382 case 320:
7383 case 333:
7384 case 400:
7385 mul = 8;
7386 break;
7387 default:
7388 return -1;
7389 }
7390
7391 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7392
7393 return opcode;
7394}
7395
7396int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7397{
7398 int ret = -1;
7399
7400 if (IS_CHERRYVIEW(dev_priv->dev))
7401 ret = chv_gpu_freq(dev_priv, val);
7402 else if (IS_VALLEYVIEW(dev_priv->dev))
7403 ret = byt_gpu_freq(dev_priv, val);
7404
7405 return ret;
7406}
7407
7408int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7409{
7410 int ret = -1;
7411
7412 if (IS_CHERRYVIEW(dev_priv->dev))
7413 ret = chv_freq_opcode(dev_priv, val);
7414 else if (IS_VALLEYVIEW(dev_priv->dev))
7415 ret = byt_freq_opcode(dev_priv, val);
7416
7417 return ret;
7418}
7419
f742a552 7420void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7421{
7422 struct drm_i915_private *dev_priv = dev->dev_private;
7423
f742a552
DV		 7424 mutex_init(&dev_priv->rps.hw_lock);
7425
907b28c5
CW		 7426 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7427 intel_gen6_powersave_work);
5d584b2e 7428
33688d95 7429 dev_priv->pm.suspended = false;
9df7575f 7430 dev_priv->pm._irqs_disabled = false;
907b28c5 7431}
Linux kernel - Deliverables
This page took 0.927108 seconds and 5 git commands to generate.