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drm/i915/gen9: Implement WaDisableKillLogic for gen 9
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL		 55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
77719d28
DL		 59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
6381b550
NH		 62
63 /* WaDisableKillLogic:bxt,skl */
64 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
65 ECOCHK_DIS_TLB);
77719d28 66}
91e41d16 67
45db2194 68static void skl_init_clock_gating(struct drm_device *dev)
da2078cd 69{
acd5c346 70 struct drm_i915_private *dev_priv = dev->dev_private;
3ca5da43 71
77719d28
DL		 72 gen9_init_clock_gating(dev);
73
669506e7 74 if (INTEL_REVID(dev) <= SKL_REVID_B0) {
3dcd020a
HN		 75 /*
76 * WaDisableSDEUnitClockGating:skl
9253c2e5 77 * WaSetGAPSunitClckGateDisable:skl
3dcd020a
HN		 78 */
79 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9253c2e5 80 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
3dcd020a 81 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
f9fc42f4
DL		 82
83 /* WaDisableVFUnitClockGating:skl */
84 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
85 GEN6_VFUNIT_CLOCK_GATE_DISABLE);
3dcd020a 86 }
8bc0ccf6 87
2caa3b26 88 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
81e231af
DL		 89 /* WaDisableHDCInvalidation:skl */
90 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
91 BDW_DISABLE_HDC_INVALIDATION);
92
2caa3b26
DL		 93 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
94 I915_WRITE(FF_SLICE_CS_CHICKEN2,
f1d3d34d 95 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
2caa3b26 96 }
81e231af 97
8bc0ccf6
DL		 98 if (INTEL_REVID(dev) <= SKL_REVID_E0)
99 /* WaDisableLSQCROPERFforOCL:skl */
100 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
101 GEN8_LQSC_RO_PERF_DIS);
da2078cd
DL		 102}
103
a82abe43
ID		 104static void bxt_init_clock_gating(struct drm_device *dev)
105{
32608ca2
ID		 106 struct drm_i915_private *dev_priv = dev->dev_private;
107
a82abe43 108 gen9_init_clock_gating(dev);
32608ca2
ID		 109
110 /*
111 * FIXME:
112 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
868434c5 113 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2
ID		 114 */
115 /* WaDisableSDEUnitClockGating:bxt */
116 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5
BW		 117 GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
118 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
32608ca2 119
e3a29055
RB		 120 /* FIXME: apply on A0 only */
121 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
a82abe43
ID		 122}
123
c921aba8
DV		 124static void i915_pineview_get_mem_freq(struct drm_device *dev)
125{
50227e1c 126 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 127 u32 tmp;
128
129 tmp = I915_READ(CLKCFG);
130
131 switch (tmp & CLKCFG_FSB_MASK) {
132 case CLKCFG_FSB_533:
133 dev_priv->fsb_freq = 533; /* 133*4 */
134 break;
135 case CLKCFG_FSB_800:
136 dev_priv->fsb_freq = 800; /* 200*4 */
137 break;
138 case CLKCFG_FSB_667:
139 dev_priv->fsb_freq = 667; /* 167*4 */
140 break;
141 case CLKCFG_FSB_400:
142 dev_priv->fsb_freq = 400; /* 100*4 */
143 break;
144 }
145
146 switch (tmp & CLKCFG_MEM_MASK) {
147 case CLKCFG_MEM_533:
148 dev_priv->mem_freq = 533;
149 break;
150 case CLKCFG_MEM_667:
151 dev_priv->mem_freq = 667;
152 break;
153 case CLKCFG_MEM_800:
154 dev_priv->mem_freq = 800;
155 break;
156 }
157
158 /* detect pineview DDR3 setting */
159 tmp = I915_READ(CSHRDDR3CTL);
160 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
161}
162
163static void i915_ironlake_get_mem_freq(struct drm_device *dev)
164{
50227e1c 165 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 166 u16 ddrpll, csipll;
167
168 ddrpll = I915_READ16(DDRMPLL1);
169 csipll = I915_READ16(CSIPLL0);
170
171 switch (ddrpll & 0xff) {
172 case 0xc:
173 dev_priv->mem_freq = 800;
174 break;
175 case 0x10:
176 dev_priv->mem_freq = 1066;
177 break;
178 case 0x14:
179 dev_priv->mem_freq = 1333;
180 break;
181 case 0x18:
182 dev_priv->mem_freq = 1600;
183 break;
184 default:
185 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
186 ddrpll & 0xff);
187 dev_priv->mem_freq = 0;
188 break;
189 }
190
20e4d407 191 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 192
193 switch (csipll & 0x3ff) {
194 case 0x00c:
195 dev_priv->fsb_freq = 3200;
196 break;
197 case 0x00e:
198 dev_priv->fsb_freq = 3733;
199 break;
200 case 0x010:
201 dev_priv->fsb_freq = 4266;
202 break;
203 case 0x012:
204 dev_priv->fsb_freq = 4800;
205 break;
206 case 0x014:
207 dev_priv->fsb_freq = 5333;
208 break;
209 case 0x016:
210 dev_priv->fsb_freq = 5866;
211 break;
212 case 0x018:
213 dev_priv->fsb_freq = 6400;
214 break;
215 default:
216 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
217 csipll & 0x3ff);
218 dev_priv->fsb_freq = 0;
219 break;
220 }
221
222 if (dev_priv->fsb_freq == 3200) {
20e4d407 223 dev_priv->ips.c_m = 0;
c921aba8 224 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 225 dev_priv->ips.c_m = 1;
c921aba8 226 } else {
20e4d407 227 dev_priv->ips.c_m = 2;
c921aba8
DV		 228 }
229}
230
b445e3b0
ED		 231static const struct cxsr_latency cxsr_latency_table[] = {
232 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
233 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
234 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
235 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
236 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
237
238 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
239 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
240 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
241 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
242 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
243
244 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
245 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
246 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
247 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
248 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
249
250 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
251 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
252 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
253 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
254 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
255
256 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
257 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
258 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
259 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
260 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
261
262 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
263 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
264 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
265 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
266 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
267};
268
63c62275 269static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 270 int is_ddr3,
271 int fsb,
272 int mem)
273{
274 const struct cxsr_latency *latency;
275 int i;
276
277 if (fsb == 0 || mem == 0)
278 return NULL;
279
280 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
281 latency = &cxsr_latency_table[i];
282 if (is_desktop == latency->is_desktop &&
283 is_ddr3 == latency->is_ddr3 &&
284 fsb == latency->fsb_freq && mem == latency->mem_freq)
285 return latency;
286 }
287
288 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
289
290 return NULL;
291}
292
fc1ac8de
VS		 293static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
294{
295 u32 val;
296
297 mutex_lock(&dev_priv->rps.hw_lock);
298
299 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
300 if (enable)
301 val &= ~FORCE_DDR_HIGH_FREQ;
302 else
303 val |= FORCE_DDR_HIGH_FREQ;
304 val &= ~FORCE_DDR_LOW_FREQ;
305 val |= FORCE_DDR_FREQ_REQ_ACK;
306 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
307
308 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
309 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
310 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
311
312 mutex_unlock(&dev_priv->rps.hw_lock);
313}
314
cfb41411
VS		 315static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
316{
317 u32 val;
318
319 mutex_lock(&dev_priv->rps.hw_lock);
320
321 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
322 if (enable)
323 val |= DSP_MAXFIFO_PM5_ENABLE;
324 else
325 val &= ~DSP_MAXFIFO_PM5_ENABLE;
326 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
327
328 mutex_unlock(&dev_priv->rps.hw_lock);
329}
330
f4998963
VS		 331#define FW_WM(value, plane) \
332 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
333
5209b1f4 334void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 335{
5209b1f4
ID		 336 struct drm_device *dev = dev_priv->dev;
337 u32 val;
b445e3b0 338
5209b1f4
ID		 339 if (IS_VALLEYVIEW(dev)) {
340 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 341 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 342 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 343 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
344 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 345 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 346 } else if (IS_PINEVIEW(dev)) {
347 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
348 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
349 I915_WRITE(DSPFW3, val);
a7a6c498 350 POSTING_READ(DSPFW3);
5209b1f4
ID		 351 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
352 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
353 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
354 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 355 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 356 } else if (IS_I915GM(dev)) {
357 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
358 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
359 I915_WRITE(INSTPM, val);
a7a6c498 360 POSTING_READ(INSTPM);
5209b1f4
ID		 361 } else {
362 return;
363 }
b445e3b0 364
5209b1f4
ID		 365 DRM_DEBUG_KMS("memory self-refresh is %s\n",
366 enable ? "enabled" : "disabled");
b445e3b0
ED		 367}
368
fc1ac8de 369
b445e3b0
ED		 370/*
371 * Latency for FIFO fetches is dependent on several factors:
372 * - memory configuration (speed, channels)
373 * - chipset
374 * - current MCH state
375 * It can be fairly high in some situations, so here we assume a fairly
376 * pessimal value. It's a tradeoff between extra memory fetches (if we
377 * set this value too high, the FIFO will fetch frequently to stay full)
378 * and power consumption (set it too low to save power and we might see
379 * FIFO underruns and display "flicker").
380 *
381 * A value of 5us seems to be a good balance; safe for very low end
382 * platforms but not overly aggressive on lower latency configs.
383 */
5aef6003 384static const int pessimal_latency_ns = 5000;
b445e3b0 385
b5004720
VS		 386#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
387 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
388
389static int vlv_get_fifo_size(struct drm_device *dev,
390 enum pipe pipe, int plane)
391{
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 int sprite0_start, sprite1_start, size;
394
395 switch (pipe) {
396 uint32_t dsparb, dsparb2, dsparb3;
397 case PIPE_A:
398 dsparb = I915_READ(DSPARB);
399 dsparb2 = I915_READ(DSPARB2);
400 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
401 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
402 break;
403 case PIPE_B:
404 dsparb = I915_READ(DSPARB);
405 dsparb2 = I915_READ(DSPARB2);
406 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
407 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
408 break;
409 case PIPE_C:
410 dsparb2 = I915_READ(DSPARB2);
411 dsparb3 = I915_READ(DSPARB3);
412 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
413 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
414 break;
415 default:
416 return 0;
417 }
418
419 switch (plane) {
420 case 0:
421 size = sprite0_start;
422 break;
423 case 1:
424 size = sprite1_start - sprite0_start;
425 break;
426 case 2:
427 size = 512 - 1 - sprite1_start;
428 break;
429 default:
430 return 0;
431 }
432
433 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
434 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
435 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
436 size);
437
438 return size;
439}
440
1fa61106 441static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 442{
443 struct drm_i915_private *dev_priv = dev->dev_private;
444 uint32_t dsparb = I915_READ(DSPARB);
445 int size;
446
447 size = dsparb & 0x7f;
448 if (plane)
449 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
450
451 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
452 plane ? "B" : "A", size);
453
454 return size;
455}
456
feb56b93 457static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 458{
459 struct drm_i915_private *dev_priv = dev->dev_private;
460 uint32_t dsparb = I915_READ(DSPARB);
461 int size;
462
463 size = dsparb & 0x1ff;
464 if (plane)
465 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
466 size >>= 1; /* Convert to cachelines */
467
468 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
469 plane ? "B" : "A", size);
470
471 return size;
472}
473
1fa61106 474static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 475{
476 struct drm_i915_private *dev_priv = dev->dev_private;
477 uint32_t dsparb = I915_READ(DSPARB);
478 int size;
479
480 size = dsparb & 0x7f;
481 size >>= 2; /* Convert to cachelines */
482
483 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
484 plane ? "B" : "A",
485 size);
486
487 return size;
488}
489
b445e3b0
ED		 490/* Pineview has different values for various configs */
491static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 492 .fifo_size = PINEVIEW_DISPLAY_FIFO,
493 .max_wm = PINEVIEW_MAX_WM,
494 .default_wm = PINEVIEW_DFT_WM,
495 .guard_size = PINEVIEW_GUARD_WM,
496 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 497};
498static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 499 .fifo_size = PINEVIEW_DISPLAY_FIFO,
500 .max_wm = PINEVIEW_MAX_WM,
501 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
502 .guard_size = PINEVIEW_GUARD_WM,
503 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 504};
505static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 506 .fifo_size = PINEVIEW_CURSOR_FIFO,
507 .max_wm = PINEVIEW_CURSOR_MAX_WM,
508 .default_wm = PINEVIEW_CURSOR_DFT_WM,
509 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
510 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 511};
512static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 513 .fifo_size = PINEVIEW_CURSOR_FIFO,
514 .max_wm = PINEVIEW_CURSOR_MAX_WM,
515 .default_wm = PINEVIEW_CURSOR_DFT_WM,
516 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
517 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 518};
519static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 520 .fifo_size = G4X_FIFO_SIZE,
521 .max_wm = G4X_MAX_WM,
522 .default_wm = G4X_MAX_WM,
523 .guard_size = 2,
524 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 525};
526static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 527 .fifo_size = I965_CURSOR_FIFO,
528 .max_wm = I965_CURSOR_MAX_WM,
529 .default_wm = I965_CURSOR_DFT_WM,
530 .guard_size = 2,
531 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 532};
533static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 534 .fifo_size = VALLEYVIEW_FIFO_SIZE,
535 .max_wm = VALLEYVIEW_MAX_WM,
536 .default_wm = VALLEYVIEW_MAX_WM,
537 .guard_size = 2,
538 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 539};
540static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 541 .fifo_size = I965_CURSOR_FIFO,
542 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
543 .default_wm = I965_CURSOR_DFT_WM,
544 .guard_size = 2,
545 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 546};
547static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 548 .fifo_size = I965_CURSOR_FIFO,
549 .max_wm = I965_CURSOR_MAX_WM,
550 .default_wm = I965_CURSOR_DFT_WM,
551 .guard_size = 2,
552 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 553};
554static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 555 .fifo_size = I945_FIFO_SIZE,
556 .max_wm = I915_MAX_WM,
557 .default_wm = 1,
558 .guard_size = 2,
559 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 560};
561static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 562 .fifo_size = I915_FIFO_SIZE,
563 .max_wm = I915_MAX_WM,
564 .default_wm = 1,
565 .guard_size = 2,
566 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 567};
9d539105 568static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 569 .fifo_size = I855GM_FIFO_SIZE,
570 .max_wm = I915_MAX_WM,
571 .default_wm = 1,
572 .guard_size = 2,
573 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 574};
9d539105
VS		 575static const struct intel_watermark_params i830_bc_wm_info = {
576 .fifo_size = I855GM_FIFO_SIZE,
577 .max_wm = I915_MAX_WM/2,
578 .default_wm = 1,
579 .guard_size = 2,
580 .cacheline_size = I830_FIFO_LINE_SIZE,
581};
feb56b93 582static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 583 .fifo_size = I830_FIFO_SIZE,
584 .max_wm = I915_MAX_WM,
585 .default_wm = 1,
586 .guard_size = 2,
587 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 588};
589
b445e3b0
ED		 590/**
591 * intel_calculate_wm - calculate watermark level
592 * @clock_in_khz: pixel clock
593 * @wm: chip FIFO params
594 * @pixel_size: display pixel size
595 * @latency_ns: memory latency for the platform
596 *
597 * Calculate the watermark level (the level at which the display plane will
598 * start fetching from memory again). Each chip has a different display
599 * FIFO size and allocation, so the caller needs to figure that out and pass
600 * in the correct intel_watermark_params structure.
601 *
602 * As the pixel clock runs, the FIFO will be drained at a rate that depends
603 * on the pixel size. When it reaches the watermark level, it'll start
604 * fetching FIFO line sized based chunks from memory until the FIFO fills
605 * past the watermark point. If the FIFO drains completely, a FIFO underrun
606 * will occur, and a display engine hang could result.
607 */
608static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
609 const struct intel_watermark_params *wm,
610 int fifo_size,
611 int pixel_size,
612 unsigned long latency_ns)
613{
614 long entries_required, wm_size;
615
616 /*
617 * Note: we need to make sure we don't overflow for various clock &
618 * latency values.
619 * clocks go from a few thousand to several hundred thousand.
620 * latency is usually a few thousand
621 */
622 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
623 1000;
624 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
625
626 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
627
628 wm_size = fifo_size - (entries_required + wm->guard_size);
629
630 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
631
632 /* Don't promote wm_size to unsigned... */
633 if (wm_size > (long)wm->max_wm)
634 wm_size = wm->max_wm;
635 if (wm_size <= 0)
636 wm_size = wm->default_wm;
d6feb196
VS		 637
638 /*
639 * Bspec seems to indicate that the value shouldn't be lower than
640 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
641 * Lets go for 8 which is the burst size since certain platforms
642 * already use a hardcoded 8 (which is what the spec says should be
643 * done).
644 */
645 if (wm_size <= 8)
646 wm_size = 8;
647
b445e3b0
ED		 648 return wm_size;
649}
650
651static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
652{
653 struct drm_crtc *crtc, *enabled = NULL;
654
70e1e0ec 655 for_each_crtc(dev, crtc) {
3490ea5d 656 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 657 if (enabled)
658 return NULL;
659 enabled = crtc;
660 }
661 }
662
663 return enabled;
664}
665
46ba614c 666static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 667{
46ba614c 668 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 669 struct drm_i915_private *dev_priv = dev->dev_private;
670 struct drm_crtc *crtc;
671 const struct cxsr_latency *latency;
672 u32 reg;
673 unsigned long wm;
674
675 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
676 dev_priv->fsb_freq, dev_priv->mem_freq);
677 if (!latency) {
678 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 679 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 680 return;
681 }
682
683 crtc = single_enabled_crtc(dev);
684 if (crtc) {
241bfc38 685 const struct drm_display_mode *adjusted_mode;
59bea882 686 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
241bfc38
DL		 687 int clock;
688
6e3c9717 689 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 690 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 691
692 /* Display SR */
693 wm = intel_calculate_wm(clock, &pineview_display_wm,
694 pineview_display_wm.fifo_size,
695 pixel_size, latency->display_sr);
696 reg = I915_READ(DSPFW1);
697 reg &= ~DSPFW_SR_MASK;
f4998963 698 reg |= FW_WM(wm, SR);
b445e3b0
ED		 699 I915_WRITE(DSPFW1, reg);
700 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
701
702 /* cursor SR */
703 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
704 pineview_display_wm.fifo_size,
705 pixel_size, latency->cursor_sr);
706 reg = I915_READ(DSPFW3);
707 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 708 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 709 I915_WRITE(DSPFW3, reg);
710
711 /* Display HPLL off SR */
712 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
713 pineview_display_hplloff_wm.fifo_size,
714 pixel_size, latency->display_hpll_disable);
715 reg = I915_READ(DSPFW3);
716 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 717 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 718 I915_WRITE(DSPFW3, reg);
719
720 /* cursor HPLL off SR */
721 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
722 pineview_display_hplloff_wm.fifo_size,
723 pixel_size, latency->cursor_hpll_disable);
724 reg = I915_READ(DSPFW3);
725 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 726 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 727 I915_WRITE(DSPFW3, reg);
728 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
729
5209b1f4 730 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 731 } else {
5209b1f4 732 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 733 }
734}
735
736static bool g4x_compute_wm0(struct drm_device *dev,
737 int plane,
738 const struct intel_watermark_params *display,
739 int display_latency_ns,
740 const struct intel_watermark_params *cursor,
741 int cursor_latency_ns,
742 int *plane_wm,
743 int *cursor_wm)
744{
745 struct drm_crtc *crtc;
4fe8590a 746 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 747 int htotal, hdisplay, clock, pixel_size;
748 int line_time_us, line_count;
749 int entries, tlb_miss;
750
751 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 752 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 753 *cursor_wm = cursor->guard_size;
754 *plane_wm = display->guard_size;
755 return false;
756 }
757
6e3c9717 758 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 759 clock = adjusted_mode->crtc_clock;
fec8cba3 760 htotal = adjusted_mode->crtc_htotal;
6e3c9717 761 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 762 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 763
764 /* Use the small buffer method to calculate plane watermark */
765 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
766 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
767 if (tlb_miss > 0)
768 entries += tlb_miss;
769 entries = DIV_ROUND_UP(entries, display->cacheline_size);
770 *plane_wm = entries + display->guard_size;
771 if (*plane_wm > (int)display->max_wm)
772 *plane_wm = display->max_wm;
773
774 /* Use the large buffer method to calculate cursor watermark */
922044c9 775 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 776 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 777 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 778 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
779 if (tlb_miss > 0)
780 entries += tlb_miss;
781 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
782 *cursor_wm = entries + cursor->guard_size;
783 if (*cursor_wm > (int)cursor->max_wm)
784 *cursor_wm = (int)cursor->max_wm;
785
786 return true;
787}
788
789/*
790 * Check the wm result.
791 *
792 * If any calculated watermark values is larger than the maximum value that
793 * can be programmed into the associated watermark register, that watermark
794 * must be disabled.
795 */
796static bool g4x_check_srwm(struct drm_device *dev,
797 int display_wm, int cursor_wm,
798 const struct intel_watermark_params *display,
799 const struct intel_watermark_params *cursor)
800{
801 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
802 display_wm, cursor_wm);
803
804 if (display_wm > display->max_wm) {
805 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
806 display_wm, display->max_wm);
807 return false;
808 }
809
810 if (cursor_wm > cursor->max_wm) {
811 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
812 cursor_wm, cursor->max_wm);
813 return false;
814 }
815
816 if (!(display_wm || cursor_wm)) {
817 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
818 return false;
819 }
820
821 return true;
822}
823
824static bool g4x_compute_srwm(struct drm_device *dev,
825 int plane,
826 int latency_ns,
827 const struct intel_watermark_params *display,
828 const struct intel_watermark_params *cursor,
829 int *display_wm, int *cursor_wm)
830{
831 struct drm_crtc *crtc;
4fe8590a 832 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 833 int hdisplay, htotal, pixel_size, clock;
834 unsigned long line_time_us;
835 int line_count, line_size;
836 int small, large;
837 int entries;
838
839 if (!latency_ns) {
840 *display_wm = *cursor_wm = 0;
841 return false;
842 }
843
844 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 845 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 846 clock = adjusted_mode->crtc_clock;
fec8cba3 847 htotal = adjusted_mode->crtc_htotal;
6e3c9717 848 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 849 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 850
922044c9 851 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 852 line_count = (latency_ns / line_time_us + 1000) / 1000;
853 line_size = hdisplay * pixel_size;
854
855 /* Use the minimum of the small and large buffer method for primary */
856 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
857 large = line_count * line_size;
858
859 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
860 *display_wm = entries + display->guard_size;
861
862 /* calculate the self-refresh watermark for display cursor */
3dd512fb 863 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 864 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
865 *cursor_wm = entries + cursor->guard_size;
866
867 return g4x_check_srwm(dev,
868 *display_wm, *cursor_wm,
869 display, cursor);
870}
871
15665979
VS		 872#define FW_WM_VLV(value, plane) \
873 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
874
0018fda1
VS		 875static void vlv_write_wm_values(struct intel_crtc *crtc,
876 const struct vlv_wm_values *wm)
877{
878 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
879 enum pipe pipe = crtc->pipe;
880
881 I915_WRITE(VLV_DDL(pipe),
882 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
883 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
884 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
885 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
886
ae80152d 887 I915_WRITE(DSPFW1,
15665979
VS		 888 FW_WM(wm->sr.plane, SR) |
889 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
890 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
891 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 892 I915_WRITE(DSPFW2,
15665979
VS		 893 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
894 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
895 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 896 I915_WRITE(DSPFW3,
15665979 897 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 898
899 if (IS_CHERRYVIEW(dev_priv)) {
900 I915_WRITE(DSPFW7_CHV,
15665979
VS		 901 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
902 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 903 I915_WRITE(DSPFW8_CHV,
15665979
VS		 904 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
905 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 906 I915_WRITE(DSPFW9_CHV,
15665979
VS		 907 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
908 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 909 I915_WRITE(DSPHOWM,
15665979
VS		 910 FW_WM(wm->sr.plane >> 9, SR_HI) |
911 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
912 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
913 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
914 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
915 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
916 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
917 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
918 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
919 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 920 } else {
921 I915_WRITE(DSPFW7,
15665979
VS		 922 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
923 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 924 I915_WRITE(DSPHOWM,
15665979
VS		 925 FW_WM(wm->sr.plane >> 9, SR_HI) |
926 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
927 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
928 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
929 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
930 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
931 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 932 }
933
2cb389b7
VS		 934 /* zero (unused) WM1 watermarks */
935 I915_WRITE(DSPFW4, 0);
936 I915_WRITE(DSPFW5, 0);
937 I915_WRITE(DSPFW6, 0);
938 I915_WRITE(DSPHOWM1, 0);
939
ae80152d 940 POSTING_READ(DSPFW1);
0018fda1
VS		 941}
942
15665979
VS		 943#undef FW_WM_VLV
944
6eb1a681
VS		 945enum vlv_wm_level {
946 VLV_WM_LEVEL_PM2,
947 VLV_WM_LEVEL_PM5,
948 VLV_WM_LEVEL_DDR_DVFS,
949 CHV_WM_NUM_LEVELS,
950 VLV_WM_NUM_LEVELS = 1,
951};
952
262cd2e1
VS		 953/* latency must be in 0.1us units. */
954static unsigned int vlv_wm_method2(unsigned int pixel_rate,
955 unsigned int pipe_htotal,
956 unsigned int horiz_pixels,
957 unsigned int bytes_per_pixel,
958 unsigned int latency)
959{
960 unsigned int ret;
961
962 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
963 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
964 ret = DIV_ROUND_UP(ret, 64);
965
966 return ret;
967}
968
969static void vlv_setup_wm_latency(struct drm_device *dev)
970{
971 struct drm_i915_private *dev_priv = dev->dev_private;
972
973 /* all latencies in usec */
974 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
975
976 if (IS_CHERRYVIEW(dev_priv)) {
977 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
978 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
979 }
980}
981
982static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
983 struct intel_crtc *crtc,
984 const struct intel_plane_state *state,
985 int level)
986{
987 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
988 int clock, htotal, pixel_size, width, wm;
989
990 if (dev_priv->wm.pri_latency[level] == 0)
991 return USHRT_MAX;
992
993 if (!state->visible)
994 return 0;
995
996 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
997 clock = crtc->config->base.adjusted_mode.crtc_clock;
998 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
999 width = crtc->config->pipe_src_w;
1000 if (WARN_ON(htotal == 0))
1001 htotal = 1;
1002
1003 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1004 /*
1005 * FIXME the formula gives values that are
1006 * too big for the cursor FIFO, and hence we
1007 * would never be able to use cursors. For
1008 * now just hardcode the watermark.
1009 */
1010 wm = 63;
1011 } else {
1012 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1013 dev_priv->wm.pri_latency[level] * 10);
1014 }
1015
1016 return min_t(int, wm, USHRT_MAX);
1017}
1018
54f1b6e1
VS		 1019static void vlv_compute_fifo(struct intel_crtc *crtc)
1020{
1021 struct drm_device *dev = crtc->base.dev;
1022 struct vlv_wm_state *wm_state = &crtc->wm_state;
1023 struct intel_plane *plane;
1024 unsigned int total_rate = 0;
1025 const int fifo_size = 512 - 1;
1026 int fifo_extra, fifo_left = fifo_size;
1027
1028 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1029 struct intel_plane_state *state =
1030 to_intel_plane_state(plane->base.state);
1031
1032 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1033 continue;
1034
1035 if (state->visible) {
1036 wm_state->num_active_planes++;
1037 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1038 }
1039 }
1040
1041 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1042 struct intel_plane_state *state =
1043 to_intel_plane_state(plane->base.state);
1044 unsigned int rate;
1045
1046 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1047 plane->wm.fifo_size = 63;
1048 continue;
1049 }
1050
1051 if (!state->visible) {
1052 plane->wm.fifo_size = 0;
1053 continue;
1054 }
1055
1056 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1057 plane->wm.fifo_size = fifo_size * rate / total_rate;
1058 fifo_left -= plane->wm.fifo_size;
1059 }
1060
1061 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1062
1063 /* spread the remainder evenly */
1064 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1065 int plane_extra;
1066
1067 if (fifo_left == 0)
1068 break;
1069
1070 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1071 continue;
1072
1073 /* give it all to the first plane if none are active */
1074 if (plane->wm.fifo_size == 0 &&
1075 wm_state->num_active_planes)
1076 continue;
1077
1078 plane_extra = min(fifo_extra, fifo_left);
1079 plane->wm.fifo_size += plane_extra;
1080 fifo_left -= plane_extra;
1081 }
1082
1083 WARN_ON(fifo_left != 0);
1084}
1085
262cd2e1
VS		 1086static void vlv_invert_wms(struct intel_crtc *crtc)
1087{
1088 struct vlv_wm_state *wm_state = &crtc->wm_state;
1089 int level;
1090
1091 for (level = 0; level < wm_state->num_levels; level++) {
1092 struct drm_device *dev = crtc->base.dev;
1093 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1094 struct intel_plane *plane;
1095
1096 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1097 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1098
1099 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1100 switch (plane->base.type) {
1101 int sprite;
1102 case DRM_PLANE_TYPE_CURSOR:
1103 wm_state->wm[level].cursor = plane->wm.fifo_size -
1104 wm_state->wm[level].cursor;
1105 break;
1106 case DRM_PLANE_TYPE_PRIMARY:
1107 wm_state->wm[level].primary = plane->wm.fifo_size -
1108 wm_state->wm[level].primary;
1109 break;
1110 case DRM_PLANE_TYPE_OVERLAY:
1111 sprite = plane->plane;
1112 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1113 wm_state->wm[level].sprite[sprite];
1114 break;
1115 }
1116 }
1117 }
1118}
1119
26e1fe4f 1120static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1121{
1122 struct drm_device *dev = crtc->base.dev;
1123 struct vlv_wm_state *wm_state = &crtc->wm_state;
1124 struct intel_plane *plane;
1125 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1126 int level;
1127
1128 memset(wm_state, 0, sizeof(*wm_state));
1129
852eb00d 1130 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
262cd2e1
VS		 1131 if (IS_CHERRYVIEW(dev))
1132 wm_state->num_levels = CHV_WM_NUM_LEVELS;
1133 else
1134 wm_state->num_levels = VLV_WM_NUM_LEVELS;
1135
1136 wm_state->num_active_planes = 0;
262cd2e1 1137
54f1b6e1 1138 vlv_compute_fifo(crtc);
262cd2e1
VS		 1139
1140 if (wm_state->num_active_planes != 1)
1141 wm_state->cxsr = false;
1142
1143 if (wm_state->cxsr) {
1144 for (level = 0; level < wm_state->num_levels; level++) {
1145 wm_state->sr[level].plane = sr_fifo_size;
1146 wm_state->sr[level].cursor = 63;
1147 }
1148 }
1149
1150 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1151 struct intel_plane_state *state =
1152 to_intel_plane_state(plane->base.state);
1153
1154 if (!state->visible)
1155 continue;
1156
1157 /* normal watermarks */
1158 for (level = 0; level < wm_state->num_levels; level++) {
1159 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1160 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1161
1162 /* hack */
1163 if (WARN_ON(level == 0 && wm > max_wm))
1164 wm = max_wm;
1165
1166 if (wm > plane->wm.fifo_size)
1167 break;
1168
1169 switch (plane->base.type) {
1170 int sprite;
1171 case DRM_PLANE_TYPE_CURSOR:
1172 wm_state->wm[level].cursor = wm;
1173 break;
1174 case DRM_PLANE_TYPE_PRIMARY:
1175 wm_state->wm[level].primary = wm;
1176 break;
1177 case DRM_PLANE_TYPE_OVERLAY:
1178 sprite = plane->plane;
1179 wm_state->wm[level].sprite[sprite] = wm;
1180 break;
1181 }
1182 }
1183
1184 wm_state->num_levels = level;
1185
1186 if (!wm_state->cxsr)
1187 continue;
1188
1189 /* maxfifo watermarks */
1190 switch (plane->base.type) {
1191 int sprite, level;
1192 case DRM_PLANE_TYPE_CURSOR:
1193 for (level = 0; level < wm_state->num_levels; level++)
1194 wm_state->sr[level].cursor =
1195 wm_state->sr[level].cursor;
1196 break;
1197 case DRM_PLANE_TYPE_PRIMARY:
1198 for (level = 0; level < wm_state->num_levels; level++)
1199 wm_state->sr[level].plane =
1200 min(wm_state->sr[level].plane,
1201 wm_state->wm[level].primary);
1202 break;
1203 case DRM_PLANE_TYPE_OVERLAY:
1204 sprite = plane->plane;
1205 for (level = 0; level < wm_state->num_levels; level++)
1206 wm_state->sr[level].plane =
1207 min(wm_state->sr[level].plane,
1208 wm_state->wm[level].sprite[sprite]);
1209 break;
1210 }
1211 }
1212
1213 /* clear any (partially) filled invalid levels */
1214 for (level = wm_state->num_levels; level < CHV_WM_NUM_LEVELS; level++) {
1215 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1216 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1217 }
1218
1219 vlv_invert_wms(crtc);
1220}
1221
54f1b6e1
VS		 1222#define VLV_FIFO(plane, value) \
1223 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1224
1225static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1226{
1227 struct drm_device *dev = crtc->base.dev;
1228 struct drm_i915_private *dev_priv = to_i915(dev);
1229 struct intel_plane *plane;
1230 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1231
1232 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1233 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1234 WARN_ON(plane->wm.fifo_size != 63);
1235 continue;
1236 }
1237
1238 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1239 sprite0_start = plane->wm.fifo_size;
1240 else if (plane->plane == 0)
1241 sprite1_start = sprite0_start + plane->wm.fifo_size;
1242 else
1243 fifo_size = sprite1_start + plane->wm.fifo_size;
1244 }
1245
1246 WARN_ON(fifo_size != 512 - 1);
1247
1248 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1249 pipe_name(crtc->pipe), sprite0_start,
1250 sprite1_start, fifo_size);
1251
1252 switch (crtc->pipe) {
1253 uint32_t dsparb, dsparb2, dsparb3;
1254 case PIPE_A:
1255 dsparb = I915_READ(DSPARB);
1256 dsparb2 = I915_READ(DSPARB2);
1257
1258 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1259 VLV_FIFO(SPRITEB, 0xff));
1260 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1261 VLV_FIFO(SPRITEB, sprite1_start));
1262
1263 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1264 VLV_FIFO(SPRITEB_HI, 0x1));
1265 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1266 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1267
1268 I915_WRITE(DSPARB, dsparb);
1269 I915_WRITE(DSPARB2, dsparb2);
1270 break;
1271 case PIPE_B:
1272 dsparb = I915_READ(DSPARB);
1273 dsparb2 = I915_READ(DSPARB2);
1274
1275 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1276 VLV_FIFO(SPRITED, 0xff));
1277 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1278 VLV_FIFO(SPRITED, sprite1_start));
1279
1280 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1281 VLV_FIFO(SPRITED_HI, 0xff));
1282 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1283 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1284
1285 I915_WRITE(DSPARB, dsparb);
1286 I915_WRITE(DSPARB2, dsparb2);
1287 break;
1288 case PIPE_C:
1289 dsparb3 = I915_READ(DSPARB3);
1290 dsparb2 = I915_READ(DSPARB2);
1291
1292 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1293 VLV_FIFO(SPRITEF, 0xff));
1294 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1295 VLV_FIFO(SPRITEF, sprite1_start));
1296
1297 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1298 VLV_FIFO(SPRITEF_HI, 0xff));
1299 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1300 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1301
1302 I915_WRITE(DSPARB3, dsparb3);
1303 I915_WRITE(DSPARB2, dsparb2);
1304 break;
1305 default:
1306 break;
1307 }
1308}
1309
1310#undef VLV_FIFO
1311
262cd2e1
VS		 1312static void vlv_merge_wm(struct drm_device *dev,
1313 struct vlv_wm_values *wm)
1314{
1315 struct intel_crtc *crtc;
1316 int num_active_crtcs = 0;
1317
1318 if (IS_CHERRYVIEW(dev))
1319 wm->level = VLV_WM_LEVEL_DDR_DVFS;
1320 else
1321 wm->level = VLV_WM_LEVEL_PM2;
1322 wm->cxsr = true;
1323
1324 for_each_intel_crtc(dev, crtc) {
1325 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1326
1327 if (!crtc->active)
1328 continue;
1329
1330 if (!wm_state->cxsr)
1331 wm->cxsr = false;
1332
1333 num_active_crtcs++;
1334 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1335 }
1336
1337 if (num_active_crtcs != 1)
1338 wm->cxsr = false;
1339
6f9c784b
VS		 1340 if (num_active_crtcs > 1)
1341 wm->level = VLV_WM_LEVEL_PM2;
1342
262cd2e1
VS		 1343 for_each_intel_crtc(dev, crtc) {
1344 struct vlv_wm_state *wm_state = &crtc->wm_state;
1345 enum pipe pipe = crtc->pipe;
1346
1347 if (!crtc->active)
1348 continue;
1349
1350 wm->pipe[pipe] = wm_state->wm[wm->level];
1351 if (wm->cxsr)
1352 wm->sr = wm_state->sr[wm->level];
1353
1354 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1355 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1356 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1357 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1358 }
1359}
1360
1361static void vlv_update_wm(struct drm_crtc *crtc)
1362{
1363 struct drm_device *dev = crtc->dev;
1364 struct drm_i915_private *dev_priv = dev->dev_private;
1365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1366 enum pipe pipe = intel_crtc->pipe;
1367 struct vlv_wm_values wm = {};
1368
26e1fe4f 1369 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1370 vlv_merge_wm(dev, &wm);
1371
54f1b6e1
VS		 1372 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1373 /* FIXME should be part of crtc atomic commit */
1374 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1375 return;
54f1b6e1 1376 }
262cd2e1
VS		 1377
1378 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1379 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1380 chv_set_memory_dvfs(dev_priv, false);
1381
1382 if (wm.level < VLV_WM_LEVEL_PM5 &&
1383 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1384 chv_set_memory_pm5(dev_priv, false);
1385
852eb00d 1386 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1387 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1388
54f1b6e1
VS		 1389 /* FIXME should be part of crtc atomic commit */
1390 vlv_pipe_set_fifo_size(intel_crtc);
1391
262cd2e1
VS		 1392 vlv_write_wm_values(intel_crtc, &wm);
1393
1394 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1395 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1396 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1397 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1398 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1399
852eb00d 1400 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1401 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1402
1403 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1404 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1405 chv_set_memory_pm5(dev_priv, true);
1406
1407 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1408 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1409 chv_set_memory_dvfs(dev_priv, true);
1410
1411 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1412}
1413
ae80152d
VS		 1414#define single_plane_enabled(mask) is_power_of_2(mask)
1415
46ba614c 1416static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1417{
46ba614c 1418 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1419 static const int sr_latency_ns = 12000;
1420 struct drm_i915_private *dev_priv = dev->dev_private;
1421 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1422 int plane_sr, cursor_sr;
1423 unsigned int enabled = 0;
9858425c 1424 bool cxsr_enabled;
b445e3b0 1425
51cea1f4 1426 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1427 &g4x_wm_info, pessimal_latency_ns,
1428 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1429 &planea_wm, &cursora_wm))
51cea1f4 1430 enabled |= 1 << PIPE_A;
b445e3b0 1431
51cea1f4 1432 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1433 &g4x_wm_info, pessimal_latency_ns,
1434 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1435 &planeb_wm, &cursorb_wm))
51cea1f4 1436 enabled |= 1 << PIPE_B;
b445e3b0 1437
b445e3b0
ED		 1438 if (single_plane_enabled(enabled) &&
1439 g4x_compute_srwm(dev, ffs(enabled) - 1,
1440 sr_latency_ns,
1441 &g4x_wm_info,
1442 &g4x_cursor_wm_info,
52bd02d8 1443 &plane_sr, &cursor_sr)) {
9858425c 1444 cxsr_enabled = true;
52bd02d8 1445 } else {
9858425c 1446 cxsr_enabled = false;
5209b1f4 1447 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1448 plane_sr = cursor_sr = 0;
1449 }
b445e3b0 1450
a5043453
VS		 1451 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1452 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1453 planea_wm, cursora_wm,
1454 planeb_wm, cursorb_wm,
1455 plane_sr, cursor_sr);
1456
1457 I915_WRITE(DSPFW1,
f4998963
VS		 1458 FW_WM(plane_sr, SR) |
1459 FW_WM(cursorb_wm, CURSORB) |
1460 FW_WM(planeb_wm, PLANEB) |
1461 FW_WM(planea_wm, PLANEA));
b445e3b0 1462 I915_WRITE(DSPFW2,
8c919b28 1463 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1464 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1465 /* HPLL off in SR has some issues on G4x... disable it */
1466 I915_WRITE(DSPFW3,
8c919b28 1467 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1468 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1469
1470 if (cxsr_enabled)
1471 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1472}
1473
46ba614c 1474static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1475{
46ba614c 1476 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1477 struct drm_i915_private *dev_priv = dev->dev_private;
1478 struct drm_crtc *crtc;
1479 int srwm = 1;
1480 int cursor_sr = 16;
9858425c 1481 bool cxsr_enabled;
b445e3b0
ED		 1482
1483 /* Calc sr entries for one plane configs */
1484 crtc = single_enabled_crtc(dev);
1485 if (crtc) {
1486 /* self-refresh has much higher latency */
1487 static const int sr_latency_ns = 12000;
4fe8590a 1488 const struct drm_display_mode *adjusted_mode =
6e3c9717 1489 &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1490 int clock = adjusted_mode->crtc_clock;
fec8cba3 1491 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1492 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1493 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1494 unsigned long line_time_us;
1495 int entries;
1496
922044c9 1497 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1498
1499 /* Use ns/us then divide to preserve precision */
1500 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1501 pixel_size * hdisplay;
1502 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1503 srwm = I965_FIFO_SIZE - entries;
1504 if (srwm < 0)
1505 srwm = 1;
1506 srwm &= 0x1ff;
1507 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1508 entries, srwm);
1509
1510 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1511 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1512 entries = DIV_ROUND_UP(entries,
1513 i965_cursor_wm_info.cacheline_size);
1514 cursor_sr = i965_cursor_wm_info.fifo_size -
1515 (entries + i965_cursor_wm_info.guard_size);
1516
1517 if (cursor_sr > i965_cursor_wm_info.max_wm)
1518 cursor_sr = i965_cursor_wm_info.max_wm;
1519
1520 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1521 "cursor %d\n", srwm, cursor_sr);
1522
9858425c 1523 cxsr_enabled = true;
b445e3b0 1524 } else {
9858425c 1525 cxsr_enabled = false;
b445e3b0 1526 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1527 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1528 }
1529
1530 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1531 srwm);
1532
1533 /* 965 has limitations... */
f4998963
VS		 1534 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1535 FW_WM(8, CURSORB) |
1536 FW_WM(8, PLANEB) |
1537 FW_WM(8, PLANEA));
1538 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1539 FW_WM(8, PLANEC_OLD));
b445e3b0 1540 /* update cursor SR watermark */
f4998963 1541 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1542
1543 if (cxsr_enabled)
1544 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1545}
1546
f4998963
VS		 1547#undef FW_WM
1548
46ba614c 1549static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1550{
46ba614c 1551 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1552 struct drm_i915_private *dev_priv = dev->dev_private;
1553 const struct intel_watermark_params *wm_info;
1554 uint32_t fwater_lo;
1555 uint32_t fwater_hi;
1556 int cwm, srwm = 1;
1557 int fifo_size;
1558 int planea_wm, planeb_wm;
1559 struct drm_crtc *crtc, *enabled = NULL;
1560
1561 if (IS_I945GM(dev))
1562 wm_info = &i945_wm_info;
1563 else if (!IS_GEN2(dev))
1564 wm_info = &i915_wm_info;
1565 else
9d539105 1566 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1567
1568 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1569 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1570 if (intel_crtc_active(crtc)) {
241bfc38 1571 const struct drm_display_mode *adjusted_mode;
59bea882 1572 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1573 if (IS_GEN2(dev))
1574 cpp = 4;
1575
6e3c9717 1576 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1577 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1578 wm_info, fifo_size, cpp,
5aef6003 1579 pessimal_latency_ns);
b445e3b0 1580 enabled = crtc;
9d539105 1581 } else {
b445e3b0 1582 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1583 if (planea_wm > (long)wm_info->max_wm)
1584 planea_wm = wm_info->max_wm;
1585 }
1586
1587 if (IS_GEN2(dev))
1588 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1589
1590 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1591 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1592 if (intel_crtc_active(crtc)) {
241bfc38 1593 const struct drm_display_mode *adjusted_mode;
59bea882 1594 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1595 if (IS_GEN2(dev))
1596 cpp = 4;
1597
6e3c9717 1598 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1599 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1600 wm_info, fifo_size, cpp,
5aef6003 1601 pessimal_latency_ns);
b445e3b0
ED		 1602 if (enabled == NULL)
1603 enabled = crtc;
1604 else
1605 enabled = NULL;
9d539105 1606 } else {
b445e3b0 1607 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1608 if (planeb_wm > (long)wm_info->max_wm)
1609 planeb_wm = wm_info->max_wm;
1610 }
b445e3b0
ED		 1611
1612 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1613
2ab1bc9d 1614 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1615 struct drm_i915_gem_object *obj;
2ab1bc9d 1616
59bea882 1617 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1618
1619 /* self-refresh seems busted with untiled */
2ff8fde1 1620 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1621 enabled = NULL;
1622 }
1623
b445e3b0
ED		 1624 /*
1625 * Overlay gets an aggressive default since video jitter is bad.
1626 */
1627 cwm = 2;
1628
1629 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1630 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1631
1632 /* Calc sr entries for one plane configs */
1633 if (HAS_FW_BLC(dev) && enabled) {
1634 /* self-refresh has much higher latency */
1635 static const int sr_latency_ns = 6000;
4fe8590a 1636 const struct drm_display_mode *adjusted_mode =
6e3c9717 1637 &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1638 int clock = adjusted_mode->crtc_clock;
fec8cba3 1639 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1640 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1641 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1642 unsigned long line_time_us;
1643 int entries;
1644
922044c9 1645 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1646
1647 /* Use ns/us then divide to preserve precision */
1648 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1649 pixel_size * hdisplay;
1650 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1651 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1652 srwm = wm_info->fifo_size - entries;
1653 if (srwm < 0)
1654 srwm = 1;
1655
1656 if (IS_I945G(dev) || IS_I945GM(dev))
1657 I915_WRITE(FW_BLC_SELF,
1658 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1659 else if (IS_I915GM(dev))
1660 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1661 }
1662
1663 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1664 planea_wm, planeb_wm, cwm, srwm);
1665
1666 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1667 fwater_hi = (cwm & 0x1f);
1668
1669 /* Set request length to 8 cachelines per fetch */
1670 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1671 fwater_hi = fwater_hi | (1 << 8);
1672
1673 I915_WRITE(FW_BLC, fwater_lo);
1674 I915_WRITE(FW_BLC2, fwater_hi);
1675
5209b1f4
ID		 1676 if (enabled)
1677 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1678}
1679
feb56b93 1680static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1681{
46ba614c 1682 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1683 struct drm_i915_private *dev_priv = dev->dev_private;
1684 struct drm_crtc *crtc;
241bfc38 1685 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1686 uint32_t fwater_lo;
1687 int planea_wm;
1688
1689 crtc = single_enabled_crtc(dev);
1690 if (crtc == NULL)
1691 return;
1692
6e3c9717 1693 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1694 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1695 &i845_wm_info,
b445e3b0 1696 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1697 4, pessimal_latency_ns);
b445e3b0
ED		 1698 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1699 fwater_lo |= (3<<8) | planea_wm;
1700
1701 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1702
1703 I915_WRITE(FW_BLC, fwater_lo);
1704}
1705
8cfb3407 1706uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1707{
fd4daa9c 1708 uint32_t pixel_rate;
801bcfff 1709
8cfb3407 1710 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1711
1712 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1713 * adjust the pixel_rate here. */
1714
8cfb3407 1715 if (pipe_config->pch_pfit.enabled) {
801bcfff 1716 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1717 uint32_t pfit_size = pipe_config->pch_pfit.size;
1718
1719 pipe_w = pipe_config->pipe_src_w;
1720 pipe_h = pipe_config->pipe_src_h;
801bcfff 1721
801bcfff
PZ		 1722 pfit_w = (pfit_size >> 16) & 0xFFFF;
1723 pfit_h = pfit_size & 0xFFFF;
1724 if (pipe_w < pfit_w)
1725 pipe_w = pfit_w;
1726 if (pipe_h < pfit_h)
1727 pipe_h = pfit_h;
1728
1729 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1730 pfit_w * pfit_h);
1731 }
1732
1733 return pixel_rate;
1734}
1735
37126462 1736/* latency must be in 0.1us units. */
23297044 1737static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1738 uint32_t latency)
1739{
1740 uint64_t ret;
1741
3312ba65
VS		 1742 if (WARN(latency == 0, "Latency value missing\n"))
1743 return UINT_MAX;
1744
801bcfff
PZ		 1745 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1746 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1747
1748 return ret;
1749}
1750
37126462 1751/* latency must be in 0.1us units. */
23297044 1752static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1753 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1754 uint32_t latency)
1755{
1756 uint32_t ret;
1757
3312ba65
VS		 1758 if (WARN(latency == 0, "Latency value missing\n"))
1759 return UINT_MAX;
1760
801bcfff
PZ		 1761 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1762 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1763 ret = DIV_ROUND_UP(ret, 64) + 2;
1764 return ret;
1765}
1766
23297044 1767static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1768 uint8_t bytes_per_pixel)
1769{
1770 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1771}
1772
2ac96d2a
PB		 1773struct skl_pipe_wm_parameters {
1774 bool active;
1775 uint32_t pipe_htotal;
1776 uint32_t pixel_rate; /* in KHz */
1777 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1778 struct intel_plane_wm_parameters cursor;
1779};
1780
820c1980 1781struct ilk_pipe_wm_parameters {
801bcfff 1782 bool active;
801bcfff
PZ		 1783 uint32_t pipe_htotal;
1784 uint32_t pixel_rate;
c35426d2
VS		 1785 struct intel_plane_wm_parameters pri;
1786 struct intel_plane_wm_parameters spr;
1787 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1788};
1789
820c1980 1790struct ilk_wm_maximums {
cca32e9a
PZ		 1791 uint16_t pri;
1792 uint16_t spr;
1793 uint16_t cur;
1794 uint16_t fbc;
1795};
1796
240264f4
VS		 1797/* used in computing the new watermarks state */
1798struct intel_wm_config {
1799 unsigned int num_pipes_active;
1800 bool sprites_enabled;
1801 bool sprites_scaled;
240264f4
VS		 1802};
1803
37126462
VS		 1804/*
1805 * For both WM_PIPE and WM_LP.
1806 * mem_value must be in 0.1us units.
1807 */
820c1980 1808static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1809 uint32_t mem_value,
1810 bool is_lp)
801bcfff 1811{
cca32e9a
PZ		 1812 uint32_t method1, method2;
1813
c35426d2 1814 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1815 return 0;
1816
23297044 1817 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1818 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1819 mem_value);
1820
1821 if (!is_lp)
1822 return method1;
1823
23297044 1824 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1825 params->pipe_htotal,
c35426d2
VS		 1826 params->pri.horiz_pixels,
1827 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1828 mem_value);
1829
1830 return min(method1, method2);
801bcfff
PZ		 1831}
1832
37126462
VS		 1833/*
1834 * For both WM_PIPE and WM_LP.
1835 * mem_value must be in 0.1us units.
1836 */
820c1980 1837static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1838 uint32_t mem_value)
1839{
1840 uint32_t method1, method2;
1841
c35426d2 1842 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1843 return 0;
1844
23297044 1845 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1846 params->spr.bytes_per_pixel,
801bcfff 1847 mem_value);
23297044 1848 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1849 params->pipe_htotal,
c35426d2
VS		 1850 params->spr.horiz_pixels,
1851 params->spr.bytes_per_pixel,
801bcfff
PZ		 1852 mem_value);
1853 return min(method1, method2);
1854}
1855
37126462
VS		 1856/*
1857 * For both WM_PIPE and WM_LP.
1858 * mem_value must be in 0.1us units.
1859 */
820c1980 1860static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1861 uint32_t mem_value)
1862{
c35426d2 1863 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1864 return 0;
1865
23297044 1866 return ilk_wm_method2(params->pixel_rate,
801bcfff 1867 params->pipe_htotal,
c35426d2
VS		 1868 params->cur.horiz_pixels,
1869 params->cur.bytes_per_pixel,
801bcfff
PZ		 1870 mem_value);
1871}
1872
cca32e9a 1873/* Only for WM_LP. */
820c1980 1874static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1875 uint32_t pri_val)
cca32e9a 1876{
c35426d2 1877 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1878 return 0;
1879
23297044 1880 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1881 params->pri.horiz_pixels,
1882 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1883}
1884
158ae64f
VS		 1885static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1886{
416f4727
VS		 1887 if (INTEL_INFO(dev)->gen >= 8)
1888 return 3072;
1889 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1890 return 768;
1891 else
1892 return 512;
1893}
1894
4e975081
VS		 1895static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1896 int level, bool is_sprite)
1897{
1898 if (INTEL_INFO(dev)->gen >= 8)
1899 /* BDW primary/sprite plane watermarks */
1900 return level == 0 ? 255 : 2047;
1901 else if (INTEL_INFO(dev)->gen >= 7)
1902 /* IVB/HSW primary/sprite plane watermarks */
1903 return level == 0 ? 127 : 1023;
1904 else if (!is_sprite)
1905 /* ILK/SNB primary plane watermarks */
1906 return level == 0 ? 127 : 511;
1907 else
1908 /* ILK/SNB sprite plane watermarks */
1909 return level == 0 ? 63 : 255;
1910}
1911
1912static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1913 int level)
1914{
1915 if (INTEL_INFO(dev)->gen >= 7)
1916 return level == 0 ? 63 : 255;
1917 else
1918 return level == 0 ? 31 : 63;
1919}
1920
1921static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1922{
1923 if (INTEL_INFO(dev)->gen >= 8)
1924 return 31;
1925 else
1926 return 15;
1927}
1928
158ae64f
VS		 1929/* Calculate the maximum primary/sprite plane watermark */
1930static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1931 int level,
240264f4 1932 const struct intel_wm_config *config,
158ae64f
VS		 1933 enum intel_ddb_partitioning ddb_partitioning,
1934 bool is_sprite)
1935{
1936 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1937
1938 /* if sprites aren't enabled, sprites get nothing */
240264f4 1939 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1940 return 0;
1941
1942 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1943 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1944 fifo_size /= INTEL_INFO(dev)->num_pipes;
1945
1946 /*
1947 * For some reason the non self refresh
1948 * FIFO size is only half of the self
1949 * refresh FIFO size on ILK/SNB.
1950 */
1951 if (INTEL_INFO(dev)->gen <= 6)
1952 fifo_size /= 2;
1953 }
1954
240264f4 1955 if (config->sprites_enabled) {
158ae64f
VS		 1956 /* level 0 is always calculated with 1:1 split */
1957 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1958 if (is_sprite)
1959 fifo_size *= 5;
1960 fifo_size /= 6;
1961 } else {
1962 fifo_size /= 2;
1963 }
1964 }
1965
1966 /* clamp to max that the registers can hold */
4e975081 1967 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1968}
1969
1970/* Calculate the maximum cursor plane watermark */
1971static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1972 int level,
1973 const struct intel_wm_config *config)
158ae64f
VS		 1974{
1975 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1976 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1977 return 64;
1978
1979 /* otherwise just report max that registers can hold */
4e975081 1980 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1981}
1982
d34ff9c6 1983static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1984 int level,
1985 const struct intel_wm_config *config,
1986 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1987 struct ilk_wm_maximums *max)
158ae64f 1988{
240264f4
VS		 1989 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1990 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1991 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1992 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1993}
1994
a3cb4048
VS		 1995static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1996 int level,
1997 struct ilk_wm_maximums *max)
1998{
1999 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2000 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2001 max->cur = ilk_cursor_wm_reg_max(dev, level);
2002 max->fbc = ilk_fbc_wm_reg_max(dev);
2003}
2004
d9395655 2005static bool ilk_validate_wm_level(int level,
820c1980 2006 const struct ilk_wm_maximums *max,
d9395655 2007 struct intel_wm_level *result)
a9786a11
VS		 2008{
2009 bool ret;
2010
2011 /* already determined to be invalid? */
2012 if (!result->enable)
2013 return false;
2014
2015 result->enable = result->pri_val <= max->pri &&
2016 result->spr_val <= max->spr &&
2017 result->cur_val <= max->cur;
2018
2019 ret = result->enable;
2020
2021 /*
2022 * HACK until we can pre-compute everything,
2023 * and thus fail gracefully if LP0 watermarks
2024 * are exceeded...
2025 */
2026 if (level == 0 && !result->enable) {
2027 if (result->pri_val > max->pri)
2028 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2029 level, result->pri_val, max->pri);
2030 if (result->spr_val > max->spr)
2031 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2032 level, result->spr_val, max->spr);
2033 if (result->cur_val > max->cur)
2034 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2035 level, result->cur_val, max->cur);
2036
2037 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2038 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2039 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2040 result->enable = true;
2041 }
2042
a9786a11
VS		 2043 return ret;
2044}
2045
d34ff9c6 2046static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 2047 int level,
820c1980 2048 const struct ilk_pipe_wm_parameters *p,
1fd527cc 2049 struct intel_wm_level *result)
6f5ddd17
VS		 2050{
2051 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2052 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2053 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2054
2055 /* WM1+ latency values stored in 0.5us units */
2056 if (level > 0) {
2057 pri_latency *= 5;
2058 spr_latency *= 5;
2059 cur_latency *= 5;
2060 }
2061
2062 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2063 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2064 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2065 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2066 result->enable = true;
2067}
2068
801bcfff
PZ		 2069static uint32_t
2070hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2071{
2072 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 2074 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 2075 u32 linetime, ips_linetime;
1f8eeabf 2076
3ef00284 2077 if (!intel_crtc->active)
801bcfff 2078 return 0;
1011d8c4 2079
1f8eeabf
ED		 2080 /* The WM are computed with base on how long it takes to fill a single
2081 * row at the given clock rate, multiplied by 8.
2082 * */
fec8cba3
JB		 2083 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2084 mode->crtc_clock);
2085 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
05024da3 2086 dev_priv->cdclk_freq);
1f8eeabf 2087
801bcfff
PZ		 2088 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2089 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2090}
2091
2af30a5c 2092static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2093{
2094 struct drm_i915_private *dev_priv = dev->dev_private;
2095
2af30a5c
PB		 2096 if (IS_GEN9(dev)) {
2097 uint32_t val;
4f947386 2098 int ret, i;
367294be 2099 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2100
2101 /* read the first set of memory latencies[0:3] */
2102 val = 0; /* data0 to be programmed to 0 for first set */
2103 mutex_lock(&dev_priv->rps.hw_lock);
2104 ret = sandybridge_pcode_read(dev_priv,
2105 GEN9_PCODE_READ_MEM_LATENCY,
2106 &val);
2107 mutex_unlock(&dev_priv->rps.hw_lock);
2108
2109 if (ret) {
2110 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2111 return;
2112 }
2113
2114 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2115 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2116 GEN9_MEM_LATENCY_LEVEL_MASK;
2117 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2118 GEN9_MEM_LATENCY_LEVEL_MASK;
2119 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2120 GEN9_MEM_LATENCY_LEVEL_MASK;
2121
2122 /* read the second set of memory latencies[4:7] */
2123 val = 1; /* data0 to be programmed to 1 for second set */
2124 mutex_lock(&dev_priv->rps.hw_lock);
2125 ret = sandybridge_pcode_read(dev_priv,
2126 GEN9_PCODE_READ_MEM_LATENCY,
2127 &val);
2128 mutex_unlock(&dev_priv->rps.hw_lock);
2129 if (ret) {
2130 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2131 return;
2132 }
2133
2134 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2135 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2136 GEN9_MEM_LATENCY_LEVEL_MASK;
2137 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2138 GEN9_MEM_LATENCY_LEVEL_MASK;
2139 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2140 GEN9_MEM_LATENCY_LEVEL_MASK;
2141
367294be 2142 /*
6f97235b
DL		 2143 * WaWmMemoryReadLatency:skl
2144 *
367294be
VK		 2145 * punit doesn't take into account the read latency so we need
2146 * to add 2us to the various latency levels we retrieve from
2147 * the punit.
2148 * - W0 is a bit special in that it's the only level that
2149 * can't be disabled if we want to have display working, so
2150 * we always add 2us there.
2151 * - For levels >=1, punit returns 0us latency when they are
2152 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2153 *
2154 * Additionally, if a level n (n > 1) has a 0us latency, all
2155 * levels m (m >= n) need to be disabled. We make sure to
2156 * sanitize the values out of the punit to satisfy this
2157 * requirement.
367294be
VK		 2158 */
2159 wm[0] += 2;
2160 for (level = 1; level <= max_level; level++)
2161 if (wm[level] != 0)
2162 wm[level] += 2;
4f947386
VK		 2163 else {
2164 for (i = level + 1; i <= max_level; i++)
2165 wm[i] = 0;
367294be 2166
4f947386
VK		 2167 break;
2168 }
2af30a5c 2169 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2170 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2171
2172 wm[0] = (sskpd >> 56) & 0xFF;
2173 if (wm[0] == 0)
2174 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2175 wm[1] = (sskpd >> 4) & 0xFF;
2176 wm[2] = (sskpd >> 12) & 0xFF;
2177 wm[3] = (sskpd >> 20) & 0x1FF;
2178 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2179 } else if (INTEL_INFO(dev)->gen >= 6) {
2180 uint32_t sskpd = I915_READ(MCH_SSKPD);
2181
2182 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2183 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2184 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2185 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2186 } else if (INTEL_INFO(dev)->gen >= 5) {
2187 uint32_t mltr = I915_READ(MLTR_ILK);
2188
2189 /* ILK primary LP0 latency is 700 ns */
2190 wm[0] = 7;
2191 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2192 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2193 }
2194}
2195
53615a5e
VS		 2196static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2197{
2198 /* ILK sprite LP0 latency is 1300 ns */
2199 if (INTEL_INFO(dev)->gen == 5)
2200 wm[0] = 13;
2201}
2202
2203static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2204{
2205 /* ILK cursor LP0 latency is 1300 ns */
2206 if (INTEL_INFO(dev)->gen == 5)
2207 wm[0] = 13;
2208
2209 /* WaDoubleCursorLP3Latency:ivb */
2210 if (IS_IVYBRIDGE(dev))
2211 wm[3] *= 2;
2212}
2213
546c81fd 2214int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2215{
26ec971e 2216 /* how many WM levels are we expecting */
b6e742f6 2217 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2218 return 7;
2219 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2220 return 4;
26ec971e 2221 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2222 return 3;
26ec971e 2223 else
ad0d6dc4
VS		 2224 return 2;
2225}
7526ed79 2226
ad0d6dc4
VS		 2227static void intel_print_wm_latency(struct drm_device *dev,
2228 const char *name,
2af30a5c 2229 const uint16_t wm[8])
ad0d6dc4
VS		 2230{
2231 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2232
2233 for (level = 0; level <= max_level; level++) {
2234 unsigned int latency = wm[level];
2235
2236 if (latency == 0) {
2237 DRM_ERROR("%s WM%d latency not provided\n",
2238 name, level);
2239 continue;
2240 }
2241
2af30a5c
PB		 2242 /*
2243 * - latencies are in us on gen9.
2244 * - before then, WM1+ latency values are in 0.5us units
2245 */
2246 if (IS_GEN9(dev))
2247 latency *= 10;
2248 else if (level > 0)
26ec971e
VS		 2249 latency *= 5;
2250
2251 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2252 name, level, wm[level],
2253 latency / 10, latency % 10);
2254 }
2255}
2256
e95a2f75
VS		 2257static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2258 uint16_t wm[5], uint16_t min)
2259{
2260 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2261
2262 if (wm[0] >= min)
2263 return false;
2264
2265 wm[0] = max(wm[0], min);
2266 for (level = 1; level <= max_level; level++)
2267 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2268
2269 return true;
2270}
2271
2272static void snb_wm_latency_quirk(struct drm_device *dev)
2273{
2274 struct drm_i915_private *dev_priv = dev->dev_private;
2275 bool changed;
2276
2277 /*
2278 * The BIOS provided WM memory latency values are often
2279 * inadequate for high resolution displays. Adjust them.
2280 */
2281 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2282 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2283 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2284
2285 if (!changed)
2286 return;
2287
2288 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2289 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2290 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2291 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2292}
2293
fa50ad61 2294static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2295{
2296 struct drm_i915_private *dev_priv = dev->dev_private;
2297
2298 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2299
2300 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2301 sizeof(dev_priv->wm.pri_latency));
2302 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2303 sizeof(dev_priv->wm.pri_latency));
2304
2305 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2306 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2307
2308 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2309 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2310 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2311
2312 if (IS_GEN6(dev))
2313 snb_wm_latency_quirk(dev);
53615a5e
VS		 2314}
2315
2af30a5c
PB		 2316static void skl_setup_wm_latency(struct drm_device *dev)
2317{
2318 struct drm_i915_private *dev_priv = dev->dev_private;
2319
2320 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2321 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2322}
2323
820c1980 2324static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2325 struct ilk_pipe_wm_parameters *p)
1011d8c4 2326{
7c4a395f
VS		 2327 struct drm_device *dev = crtc->dev;
2328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2329 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2330 struct drm_plane *plane;
1011d8c4 2331
3ef00284 2332 if (!intel_crtc->active)
2a44b76b 2333 return;
801bcfff 2334
2a44b76b 2335 p->active = true;
6e3c9717 2336 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
8cfb3407 2337 p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
c9f038a1 2338
54da691d 2339 if (crtc->primary->state->fb)
c9f038a1
MR		 2340 p->pri.bytes_per_pixel =
2341 crtc->primary->state->fb->bits_per_pixel / 8;
54da691d
TG		 2342 else
2343 p->pri.bytes_per_pixel = 4;
2344
2345 p->cur.bytes_per_pixel = 4;
2346 /*
2347 * TODO: for now, assume primary and cursor planes are always enabled.
2348 * Setting them to false makes the screen flicker.
2349 */
2350 p->pri.enabled = true;
2351 p->cur.enabled = true;
c9f038a1 2352
6e3c9717 2353 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
3dd512fb 2354 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
7c4a395f 2355
af2b653b 2356 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2357 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2358
2a44b76b 2359 if (intel_plane->pipe == pipe) {
7c4a395f 2360 p->spr = intel_plane->wm;
2a44b76b
VS		 2361 break;
2362 }
2363 }
2364}
2365
2366static void ilk_compute_wm_config(struct drm_device *dev,
2367 struct intel_wm_config *config)
2368{
2369 struct intel_crtc *intel_crtc;
2370
2371 /* Compute the currently _active_ config */
d3fcc808 2372 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2373 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2374
2a44b76b
VS		 2375 if (!wm->pipe_enabled)
2376 continue;
cca32e9a 2377
2a44b76b
VS		 2378 config->sprites_enabled |= wm->sprites_enabled;
2379 config->sprites_scaled |= wm->sprites_scaled;
2380 config->num_pipes_active++;
cca32e9a 2381 }
801bcfff
PZ		 2382}
2383
0b2ae6d7
VS		 2384/* Compute new watermarks for the pipe */
2385static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2386 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2387 struct intel_pipe_wm *pipe_wm)
2388{
2389 struct drm_device *dev = crtc->dev;
d34ff9c6 2390 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2391 int level, max_level = ilk_wm_max_level(dev);
2392 /* LP0 watermark maximums depend on this pipe alone */
2393 struct intel_wm_config config = {
2394 .num_pipes_active = 1,
2395 .sprites_enabled = params->spr.enabled,
2396 .sprites_scaled = params->spr.scaled,
2397 };
820c1980 2398 struct ilk_wm_maximums max;
0b2ae6d7 2399
2a44b76b
VS		 2400 pipe_wm->pipe_enabled = params->active;
2401 pipe_wm->sprites_enabled = params->spr.enabled;
2402 pipe_wm->sprites_scaled = params->spr.scaled;
2403
7b39a0b7
VS		 2404 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2405 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2406 max_level = 1;
2407
2408 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2409 if (params->spr.scaled)
2410 max_level = 0;
2411
a3cb4048 2412 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2413
a42a5719 2414 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2415 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2416
a3cb4048
VS		 2417 /* LP0 watermarks always use 1/2 DDB partitioning */
2418 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2419
0b2ae6d7 2420 /* At least LP0 must be valid */
a3cb4048
VS		 2421 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2422 return false;
2423
2424 ilk_compute_wm_reg_maximums(dev, 1, &max);
2425
2426 for (level = 1; level <= max_level; level++) {
2427 struct intel_wm_level wm = {};
2428
2429 ilk_compute_wm_level(dev_priv, level, params, &wm);
2430
2431 /*
2432 * Disable any watermark level that exceeds the
2433 * register maximums since such watermarks are
2434 * always invalid.
2435 */
2436 if (!ilk_validate_wm_level(level, &max, &wm))
2437 break;
2438
2439 pipe_wm->wm[level] = wm;
2440 }
2441
2442 return true;
0b2ae6d7
VS		 2443}
2444
2445/*
2446 * Merge the watermarks from all active pipes for a specific level.
2447 */
2448static void ilk_merge_wm_level(struct drm_device *dev,
2449 int level,
2450 struct intel_wm_level *ret_wm)
2451{
2452 const struct intel_crtc *intel_crtc;
2453
d52fea5b
VS		 2454 ret_wm->enable = true;
2455
d3fcc808 2456 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2457 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2458 const struct intel_wm_level *wm = &active->wm[level];
2459
2460 if (!active->pipe_enabled)
2461 continue;
0b2ae6d7 2462
d52fea5b
VS		 2463 /*
2464 * The watermark values may have been used in the past,
2465 * so we must maintain them in the registers for some
2466 * time even if the level is now disabled.
2467 */
0b2ae6d7 2468 if (!wm->enable)
d52fea5b 2469 ret_wm->enable = false;
0b2ae6d7
VS		 2470
2471 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2472 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2473 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2474 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2475 }
0b2ae6d7
VS		 2476}
2477
2478/*
2479 * Merge all low power watermarks for all active pipes.
2480 */
2481static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2482 const struct intel_wm_config *config,
820c1980 2483 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2484 struct intel_pipe_wm *merged)
2485{
7733b49b 2486 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2487 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2488 int last_enabled_level = max_level;
0b2ae6d7 2489
0ba22e26
VS		 2490 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2491 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2492 config->num_pipes_active > 1)
2493 return;
2494
6c8b6c28
VS		 2495 /* ILK: FBC WM must be disabled always */
2496 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2497
2498 /* merge each WM1+ level */
2499 for (level = 1; level <= max_level; level++) {
2500 struct intel_wm_level *wm = &merged->wm[level];
2501
2502 ilk_merge_wm_level(dev, level, wm);
2503
d52fea5b
VS		 2504 if (level > last_enabled_level)
2505 wm->enable = false;
2506 else if (!ilk_validate_wm_level(level, max, wm))
2507 /* make sure all following levels get disabled */
2508 last_enabled_level = level - 1;
0b2ae6d7
VS		 2509
2510 /*
2511 * The spec says it is preferred to disable
2512 * FBC WMs instead of disabling a WM level.
2513 */
2514 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2515 if (wm->enable)
2516 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2517 wm->fbc_val = 0;
2518 }
2519 }
6c8b6c28
VS		 2520
2521 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2522 /*
2523 * FIXME this is racy. FBC might get enabled later.
2524 * What we should check here is whether FBC can be
2525 * enabled sometime later.
2526 */
7733b49b
PZ		 2527 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2528 intel_fbc_enabled(dev_priv)) {
6c8b6c28
VS		 2529 for (level = 2; level <= max_level; level++) {
2530 struct intel_wm_level *wm = &merged->wm[level];
2531
2532 wm->enable = false;
2533 }
2534 }
0b2ae6d7
VS		 2535}
2536
b380ca3c
VS		 2537static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2538{
2539 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2540 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2541}
2542
a68d68ee
VS		 2543/* The value we need to program into the WM_LPx latency field */
2544static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2545{
2546 struct drm_i915_private *dev_priv = dev->dev_private;
2547
a42a5719 2548 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2549 return 2 * level;
2550 else
2551 return dev_priv->wm.pri_latency[level];
2552}
2553
820c1980 2554static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2555 const struct intel_pipe_wm *merged,
609cedef 2556 enum intel_ddb_partitioning partitioning,
820c1980 2557 struct ilk_wm_values *results)
801bcfff 2558{
0b2ae6d7
VS		 2559 struct intel_crtc *intel_crtc;
2560 int level, wm_lp;
cca32e9a 2561
0362c781 2562 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2563 results->partitioning = partitioning;
cca32e9a 2564
0b2ae6d7 2565 /* LP1+ register values */
cca32e9a 2566 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2567 const struct intel_wm_level *r;
801bcfff 2568
b380ca3c 2569 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2570
0362c781 2571 r = &merged->wm[level];
cca32e9a 2572
d52fea5b
VS		 2573 /*
2574 * Maintain the watermark values even if the level is
2575 * disabled. Doing otherwise could cause underruns.
2576 */
2577 results->wm_lp[wm_lp - 1] =
a68d68ee 2578 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2579 (r->pri_val << WM1_LP_SR_SHIFT) |
2580 r->cur_val;
2581
d52fea5b
VS		 2582 if (r->enable)
2583 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2584
416f4727
VS		 2585 if (INTEL_INFO(dev)->gen >= 8)
2586 results->wm_lp[wm_lp - 1] |=
2587 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2588 else
2589 results->wm_lp[wm_lp - 1] |=
2590 r->fbc_val << WM1_LP_FBC_SHIFT;
2591
d52fea5b
VS		 2592 /*
2593 * Always set WM1S_LP_EN when spr_val != 0, even if the
2594 * level is disabled. Doing otherwise could cause underruns.
2595 */
6cef2b8a
VS		 2596 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2597 WARN_ON(wm_lp != 1);
2598 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2599 } else
2600 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2601 }
801bcfff 2602
0b2ae6d7 2603 /* LP0 register values */
d3fcc808 2604 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2605 enum pipe pipe = intel_crtc->pipe;
2606 const struct intel_wm_level *r =
2607 &intel_crtc->wm.active.wm[0];
2608
2609 if (WARN_ON(!r->enable))
2610 continue;
2611
2612 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2613
0b2ae6d7
VS		 2614 results->wm_pipe[pipe] =
2615 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2616 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2617 r->cur_val;
801bcfff
PZ		 2618 }
2619}
2620
861f3389
PZ		 2621/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2622 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2623static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2624 struct intel_pipe_wm *r1,
2625 struct intel_pipe_wm *r2)
861f3389 2626{
198a1e9b
VS		 2627 int level, max_level = ilk_wm_max_level(dev);
2628 int level1 = 0, level2 = 0;
861f3389 2629
198a1e9b
VS		 2630 for (level = 1; level <= max_level; level++) {
2631 if (r1->wm[level].enable)
2632 level1 = level;
2633 if (r2->wm[level].enable)
2634 level2 = level;
861f3389
PZ		 2635 }
2636
198a1e9b
VS		 2637 if (level1 == level2) {
2638 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2639 return r2;
2640 else
2641 return r1;
198a1e9b 2642 } else if (level1 > level2) {
861f3389
PZ		 2643 return r1;
2644 } else {
2645 return r2;
2646 }
2647}
2648
49a687c4
VS		 2649/* dirty bits used to track which watermarks need changes */
2650#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2651#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2652#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2653#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2654#define WM_DIRTY_FBC (1 << 24)
2655#define WM_DIRTY_DDB (1 << 25)
2656
055e393f 2657static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2658 const struct ilk_wm_values *old,
2659 const struct ilk_wm_values *new)
49a687c4
VS		 2660{
2661 unsigned int dirty = 0;
2662 enum pipe pipe;
2663 int wm_lp;
2664
055e393f 2665 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2666 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2667 dirty |= WM_DIRTY_LINETIME(pipe);
2668 /* Must disable LP1+ watermarks too */
2669 dirty |= WM_DIRTY_LP_ALL;
2670 }
2671
2672 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2673 dirty |= WM_DIRTY_PIPE(pipe);
2674 /* Must disable LP1+ watermarks too */
2675 dirty |= WM_DIRTY_LP_ALL;
2676 }
2677 }
2678
2679 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2680 dirty |= WM_DIRTY_FBC;
2681 /* Must disable LP1+ watermarks too */
2682 dirty |= WM_DIRTY_LP_ALL;
2683 }
2684
2685 if (old->partitioning != new->partitioning) {
2686 dirty |= WM_DIRTY_DDB;
2687 /* Must disable LP1+ watermarks too */
2688 dirty |= WM_DIRTY_LP_ALL;
2689 }
2690
2691 /* LP1+ watermarks already deemed dirty, no need to continue */
2692 if (dirty & WM_DIRTY_LP_ALL)
2693 return dirty;
2694
2695 /* Find the lowest numbered LP1+ watermark in need of an update... */
2696 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2697 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2698 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2699 break;
2700 }
2701
2702 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2703 for (; wm_lp <= 3; wm_lp++)
2704 dirty |= WM_DIRTY_LP(wm_lp);
2705
2706 return dirty;
2707}
2708
8553c18e
VS		 2709static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2710 unsigned int dirty)
801bcfff 2711{
820c1980 2712 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2713 bool changed = false;
801bcfff 2714
facd619b
VS		 2715 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2716 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2717 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2718 changed = true;
facd619b
VS		 2719 }
2720 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2721 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2722 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2723 changed = true;
facd619b
VS		 2724 }
2725 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2726 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2727 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2728 changed = true;
facd619b 2729 }
801bcfff 2730
facd619b
VS		 2731 /*
2732 * Don't touch WM1S_LP_EN here.
2733 * Doing so could cause underruns.
2734 */
6cef2b8a 2735
8553c18e
VS		 2736 return changed;
2737}
2738
2739/*
2740 * The spec says we shouldn't write when we don't need, because every write
2741 * causes WMs to be re-evaluated, expending some power.
2742 */
820c1980
ID		 2743static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2744 struct ilk_wm_values *results)
8553c18e
VS		 2745{
2746 struct drm_device *dev = dev_priv->dev;
820c1980 2747 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2748 unsigned int dirty;
2749 uint32_t val;
2750
055e393f 2751 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2752 if (!dirty)
2753 return;
2754
2755 _ilk_disable_lp_wm(dev_priv, dirty);
2756
49a687c4 2757 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2758 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2759 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2760 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2761 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2762 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2763
49a687c4 2764 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2765 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2766 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2767 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2768 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2769 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2770
49a687c4 2771 if (dirty & WM_DIRTY_DDB) {
a42a5719 2772 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2773 val = I915_READ(WM_MISC);
2774 if (results->partitioning == INTEL_DDB_PART_1_2)
2775 val &= ~WM_MISC_DATA_PARTITION_5_6;
2776 else
2777 val |= WM_MISC_DATA_PARTITION_5_6;
2778 I915_WRITE(WM_MISC, val);
2779 } else {
2780 val = I915_READ(DISP_ARB_CTL2);
2781 if (results->partitioning == INTEL_DDB_PART_1_2)
2782 val &= ~DISP_DATA_PARTITION_5_6;
2783 else
2784 val |= DISP_DATA_PARTITION_5_6;
2785 I915_WRITE(DISP_ARB_CTL2, val);
2786 }
1011d8c4
PZ		 2787 }
2788
49a687c4 2789 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2790 val = I915_READ(DISP_ARB_CTL);
2791 if (results->enable_fbc_wm)
2792 val &= ~DISP_FBC_WM_DIS;
2793 else
2794 val |= DISP_FBC_WM_DIS;
2795 I915_WRITE(DISP_ARB_CTL, val);
2796 }
2797
954911eb
ID		 2798 if (dirty & WM_DIRTY_LP(1) &&
2799 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2800 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2801
2802 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2803 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2804 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2805 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2806 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2807 }
801bcfff 2808
facd619b 2809 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2810 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2811 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2812 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2813 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2814 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2815
2816 dev_priv->wm.hw = *results;
801bcfff
PZ		 2817}
2818
8553c18e
VS		 2819static bool ilk_disable_lp_wm(struct drm_device *dev)
2820{
2821 struct drm_i915_private *dev_priv = dev->dev_private;
2822
2823 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2824}
2825
b9cec075
DL		 2826/*
2827 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2828 * different active planes.
2829 */
2830
2831#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2832#define BXT_DDB_SIZE 512
b9cec075
DL		 2833
2834static void
2835skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2836 struct drm_crtc *for_crtc,
2837 const struct intel_wm_config *config,
2838 const struct skl_pipe_wm_parameters *params,
2839 struct skl_ddb_entry *alloc /* out */)
2840{
2841 struct drm_crtc *crtc;
2842 unsigned int pipe_size, ddb_size;
2843 int nth_active_pipe;
2844
2845 if (!params->active) {
2846 alloc->start = 0;
2847 alloc->end = 0;
2848 return;
2849 }
2850
43d735a6
DL		 2851 if (IS_BROXTON(dev))
2852 ddb_size = BXT_DDB_SIZE;
2853 else
2854 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2855
2856 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2857
2858 nth_active_pipe = 0;
2859 for_each_crtc(dev, crtc) {
3ef00284 2860 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2861 continue;
2862
2863 if (crtc == for_crtc)
2864 break;
2865
2866 nth_active_pipe++;
2867 }
2868
2869 pipe_size = ddb_size / config->num_pipes_active;
2870 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2871 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2872}
2873
2874static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2875{
2876 if (config->num_pipes_active == 1)
2877 return 32;
2878
2879 return 8;
2880}
2881
a269c583
DL		 2882static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2883{
2884 entry->start = reg & 0x3ff;
2885 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2886 if (entry->end)
2887 entry->end += 1;
a269c583
DL		 2888}
2889
08db6652
DL		 2890void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2891 struct skl_ddb_allocation *ddb /* out */)
a269c583 2892{
a269c583
DL		 2893 enum pipe pipe;
2894 int plane;
2895 u32 val;
2896
2897 for_each_pipe(dev_priv, pipe) {
dd740780 2898 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2899 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2900 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2901 val);
2902 }
2903
2904 val = I915_READ(CUR_BUF_CFG(pipe));
2905 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2906 }
2907}
2908
b9cec075 2909static unsigned int
2cd601c6 2910skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
b9cec075 2911{
2cd601c6
CK		 2912
2913 /* for planar format */
2914 if (p->y_bytes_per_pixel) {
2915 if (y) /* y-plane data rate */
2916 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2917 else /* uv-plane data rate */
2918 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2919 }
2920
2921 /* for packed formats */
b9cec075
DL		 2922 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2923}
2924
2925/*
2926 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2927 * a 8192x4096@32bpp framebuffer:
2928 * 3 * 4096 * 8192 * 4 < 2^32
2929 */
2930static unsigned int
2931skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2932 const struct skl_pipe_wm_parameters *params)
2933{
2934 unsigned int total_data_rate = 0;
2935 int plane;
2936
2937 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2938 const struct intel_plane_wm_parameters *p;
2939
2940 p = &params->plane[plane];
2941 if (!p->enabled)
2942 continue;
2943
2cd601c6
CK		 2944 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2945 if (p->y_bytes_per_pixel) {
2946 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2947 }
b9cec075
DL		 2948 }
2949
2950 return total_data_rate;
2951}
2952
2953static void
2954skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2955 const struct intel_wm_config *config,
2956 const struct skl_pipe_wm_parameters *params,
2957 struct skl_ddb_allocation *ddb /* out */)
2958{
2959 struct drm_device *dev = crtc->dev;
dd740780 2960 struct drm_i915_private *dev_priv = dev->dev_private;
b9cec075
DL		 2961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2962 enum pipe pipe = intel_crtc->pipe;
34bb56af 2963 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2964 uint16_t alloc_size, start, cursor_blocks;
80958155 2965 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2966 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075
DL		 2967 unsigned int total_data_rate;
2968 int plane;
2969
34bb56af
DL		 2970 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2971 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2972 if (alloc_size == 0) {
2973 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2974 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2975 return;
2976 }
2977
2978 cursor_blocks = skl_cursor_allocation(config);
34bb56af
DL		 2979 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2980 ddb->cursor[pipe].end = alloc->end;
b9cec075
DL		 2981
2982 alloc_size -= cursor_blocks;
34bb56af 2983 alloc->end -= cursor_blocks;
b9cec075 2984
80958155 2985 /* 1. Allocate the mininum required blocks for each active plane */
dd740780 2986 for_each_plane(dev_priv, pipe, plane) {
80958155
DL		 2987 const struct intel_plane_wm_parameters *p;
2988
2989 p = &params->plane[plane];
2990 if (!p->enabled)
2991 continue;
2992
2993 minimum[plane] = 8;
2994 alloc_size -= minimum[plane];
2cd601c6
CK		 2995 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2996 alloc_size -= y_minimum[plane];
80958155
DL		 2997 }
2998
b9cec075 2999 /*
80958155
DL		 3000 * 2. Distribute the remaining space in proportion to the amount of
3001 * data each plane needs to fetch from memory.
b9cec075
DL		 3002 *
3003 * FIXME: we may not allocate every single block here.
3004 */
3005 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
3006
34bb56af 3007 start = alloc->start;
b9cec075
DL		 3008 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3009 const struct intel_plane_wm_parameters *p;
2cd601c6
CK		 3010 unsigned int data_rate, y_data_rate;
3011 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075
DL		 3012
3013 p = &params->plane[plane];
3014 if (!p->enabled)
3015 continue;
3016
2cd601c6 3017 data_rate = skl_plane_relative_data_rate(p, 0);
b9cec075
DL		 3018
3019 /*
2cd601c6 3020 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3021 * promote the expression to 64 bits to avoid overflowing, the
3022 * result is < available as data_rate / total_data_rate < 1
3023 */
80958155
DL		 3024 plane_blocks = minimum[plane];
3025 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3026 total_data_rate);
b9cec075
DL		 3027
3028 ddb->plane[pipe][plane].start = start;
16160e3d 3029 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL		 3030
3031 start += plane_blocks;
2cd601c6
CK		 3032
3033 /*
3034 * allocation for y_plane part of planar format:
3035 */
3036 if (p->y_bytes_per_pixel) {
3037 y_data_rate = skl_plane_relative_data_rate(p, 1);
3038 y_plane_blocks = y_minimum[plane];
3039 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3040 total_data_rate);
3041
3042 ddb->y_plane[pipe][plane].start = start;
3043 ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
3044
3045 start += y_plane_blocks;
3046 }
3047
b9cec075
DL		 3048 }
3049
3050}
3051
5cec258b 3052static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3053{
3054 /* TODO: Take into account the scalers once we support them */
2d112de7 3055 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3056}
3057
3058/*
3059 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3060 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3061 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3062 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3063*/
3064static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3065 uint32_t latency)
3066{
3067 uint32_t wm_intermediate_val, ret;
3068
3069 if (latency == 0)
3070 return UINT_MAX;
3071
d4c2aa60 3072 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 3073 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3074
3075 return ret;
3076}
3077
3078static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3079 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 3080 uint64_t tiling, uint32_t latency)
2d41c0b5 3081{
d4c2aa60
TU		 3082 uint32_t ret;
3083 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3084 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3085
3086 if (latency == 0)
3087 return UINT_MAX;
3088
3089 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 3090
3091 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3092 tiling == I915_FORMAT_MOD_Yf_TILED) {
3093 plane_bytes_per_line *= 4;
3094 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3095 plane_blocks_per_line /= 4;
3096 } else {
3097 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3098 }
3099
2d41c0b5
PB		 3100 wm_intermediate_val = latency * pixel_rate;
3101 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3102 plane_blocks_per_line;
2d41c0b5
PB		 3103
3104 return ret;
3105}
3106
2d41c0b5
PB		 3107static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3108 const struct intel_crtc *intel_crtc)
3109{
3110 struct drm_device *dev = intel_crtc->base.dev;
3111 struct drm_i915_private *dev_priv = dev->dev_private;
3112 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3113 enum pipe pipe = intel_crtc->pipe;
3114
3115 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3116 sizeof(new_ddb->plane[pipe])))
3117 return true;
3118
3119 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
3120 sizeof(new_ddb->cursor[pipe])))
3121 return true;
3122
3123 return false;
3124}
3125
3126static void skl_compute_wm_global_parameters(struct drm_device *dev,
3127 struct intel_wm_config *config)
3128{
3129 struct drm_crtc *crtc;
3130 struct drm_plane *plane;
3131
3132 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3ef00284 3133 config->num_pipes_active += to_intel_crtc(crtc)->active;
2d41c0b5
PB		 3134
3135 /* FIXME: I don't think we need those two global parameters on SKL */
3136 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3137 struct intel_plane *intel_plane = to_intel_plane(plane);
3138
3139 config->sprites_enabled |= intel_plane->wm.enabled;
3140 config->sprites_scaled |= intel_plane->wm.scaled;
3141 }
3142}
3143
3144static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3145 struct skl_pipe_wm_parameters *p)
3146{
3147 struct drm_device *dev = crtc->dev;
3148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3149 enum pipe pipe = intel_crtc->pipe;
3150 struct drm_plane *plane;
0fda6568 3151 struct drm_framebuffer *fb;
2d41c0b5
PB		 3152 int i = 1; /* Index for sprite planes start */
3153
3ef00284 3154 p->active = intel_crtc->active;
2d41c0b5 3155 if (p->active) {
6e3c9717
ACO		 3156 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3157 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2d41c0b5 3158
0fda6568 3159 fb = crtc->primary->state->fb;
2cd601c6 3160 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
c9f038a1
MR		 3161 if (fb) {
3162 p->plane[0].enabled = true;
2cd601c6
CK		 3163 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3164 drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 8;
3165 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3166 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
0fda6568 3167 p->plane[0].tiling = fb->modifier[0];
c9f038a1
MR		 3168 } else {
3169 p->plane[0].enabled = false;
3170 p->plane[0].bytes_per_pixel = 0;
2cd601c6 3171 p->plane[0].y_bytes_per_pixel = 0;
c9f038a1
MR		 3172 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3173 }
3174 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3175 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
1fc0a8f7 3176 p->plane[0].rotation = crtc->primary->state->rotation;
2d41c0b5 3177
c9f038a1 3178 fb = crtc->cursor->state->fb;
2cd601c6 3179 p->cursor.y_bytes_per_pixel = 0;
c9f038a1
MR		 3180 if (fb) {
3181 p->cursor.enabled = true;
3182 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
3183 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
3184 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
3185 } else {
3186 p->cursor.enabled = false;
3187 p->cursor.bytes_per_pixel = 0;
3188 p->cursor.horiz_pixels = 64;
3189 p->cursor.vert_pixels = 64;
3190 }
2d41c0b5
PB		 3191 }
3192
3193 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3194 struct intel_plane *intel_plane = to_intel_plane(plane);
3195
a712f8eb
SJ		 3196 if (intel_plane->pipe == pipe &&
3197 plane->type == DRM_PLANE_TYPE_OVERLAY)
2d41c0b5
PB		 3198 p->plane[i++] = intel_plane->wm;
3199 }
3200}
3201
d4c2aa60
TU		 3202static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3203 struct skl_pipe_wm_parameters *p,
afb024aa
DL		 3204 struct intel_plane_wm_parameters *p_params,
3205 uint16_t ddb_allocation,
d4c2aa60 3206 int level,
afb024aa
DL		 3207 uint16_t *out_blocks, /* out */
3208 uint8_t *out_lines /* out */)
2d41c0b5 3209{
d4c2aa60
TU		 3210 uint32_t latency = dev_priv->wm.skl_latency[level];
3211 uint32_t method1, method2;
3212 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3213 uint32_t res_blocks, res_lines;
3214 uint32_t selected_result;
2cd601c6 3215 uint8_t bytes_per_pixel;
2d41c0b5 3216
d4c2aa60 3217 if (latency == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB		 3218 return false;
3219
2cd601c6
CK		 3220 bytes_per_pixel = p_params->y_bytes_per_pixel ?
3221 p_params->y_bytes_per_pixel :
3222 p_params->bytes_per_pixel;
2d41c0b5 3223 method1 = skl_wm_method1(p->pixel_rate,
2cd601c6 3224 bytes_per_pixel,
d4c2aa60 3225 latency);
2d41c0b5
PB		 3226 method2 = skl_wm_method2(p->pixel_rate,
3227 p->pipe_htotal,
3228 p_params->horiz_pixels,
2cd601c6 3229 bytes_per_pixel,
0fda6568 3230 p_params->tiling,
d4c2aa60 3231 latency);
2d41c0b5 3232
2cd601c6 3233 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
d4c2aa60 3234 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3235
0fda6568
TU		 3236 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3237 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3238 uint32_t min_scanlines = 4;
3239 uint32_t y_tile_minimum;
3240 if (intel_rotation_90_or_270(p_params->rotation)) {
3241 switch (p_params->bytes_per_pixel) {
3242 case 1:
3243 min_scanlines = 16;
3244 break;
3245 case 2:
3246 min_scanlines = 8;
3247 break;
3248 case 8:
3249 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3250 }
1fc0a8f7
TU		 3251 }
3252 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3253 selected_result = max(method2, y_tile_minimum);
3254 } else {
3255 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3256 selected_result = min(method1, method2);
3257 else
3258 selected_result = method1;
3259 }
2d41c0b5 3260
d4c2aa60
TU		 3261 res_blocks = selected_result + 1;
3262 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3263
0fda6568
TU		 3264 if (level >= 1 && level <= 7) {
3265 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3266 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3267 res_lines += 4;
3268 else
3269 res_blocks++;
3270 }
e6d66171 3271
d4c2aa60 3272 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3273 return false;
3274
3275 *out_blocks = res_blocks;
3276 *out_lines = res_lines;
2d41c0b5
PB		 3277
3278 return true;
3279}
3280
3281static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3282 struct skl_ddb_allocation *ddb,
3283 struct skl_pipe_wm_parameters *p,
3284 enum pipe pipe,
3285 int level,
3286 int num_planes,
3287 struct skl_wm_level *result)
3288{
2d41c0b5
PB		 3289 uint16_t ddb_blocks;
3290 int i;
3291
3292 for (i = 0; i < num_planes; i++) {
3293 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3294
d4c2aa60
TU		 3295 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3296 p, &p->plane[i],
2d41c0b5 3297 ddb_blocks,
d4c2aa60 3298 level,
2d41c0b5
PB		 3299 &result->plane_res_b[i],
3300 &result->plane_res_l[i]);
3301 }
3302
3303 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
d4c2aa60
TU		 3304 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3305 ddb_blocks, level,
3306 &result->cursor_res_b,
2d41c0b5
PB		 3307 &result->cursor_res_l);
3308}
3309
407b50f3
DL		 3310static uint32_t
3311skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3312{
3ef00284 3313 if (!to_intel_crtc(crtc)->active)
407b50f3
DL		 3314 return 0;
3315
3316 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3317
3318}
3319
3320static void skl_compute_transition_wm(struct drm_crtc *crtc,
3321 struct skl_pipe_wm_parameters *params,
9414f563 3322 struct skl_wm_level *trans_wm /* out */)
407b50f3 3323{
9414f563
DL		 3324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3325 int i;
3326
407b50f3
DL		 3327 if (!params->active)
3328 return;
9414f563
DL		 3329
3330 /* Until we know more, just disable transition WMs */
3331 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3332 trans_wm->plane_en[i] = false;
3333 trans_wm->cursor_en = false;
407b50f3
DL		 3334}
3335
2d41c0b5
PB		 3336static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3337 struct skl_ddb_allocation *ddb,
3338 struct skl_pipe_wm_parameters *params,
3339 struct skl_pipe_wm *pipe_wm)
3340{
3341 struct drm_device *dev = crtc->dev;
3342 const struct drm_i915_private *dev_priv = dev->dev_private;
3343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3344 int level, max_level = ilk_wm_max_level(dev);
3345
3346 for (level = 0; level <= max_level; level++) {
3347 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3348 level, intel_num_planes(intel_crtc),
3349 &pipe_wm->wm[level]);
3350 }
3351 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3352
9414f563 3353 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2d41c0b5
PB		 3354}
3355
3356static void skl_compute_wm_results(struct drm_device *dev,
3357 struct skl_pipe_wm_parameters *p,
3358 struct skl_pipe_wm *p_wm,
3359 struct skl_wm_values *r,
3360 struct intel_crtc *intel_crtc)
3361{
3362 int level, max_level = ilk_wm_max_level(dev);
3363 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3364 uint32_t temp;
3365 int i;
2d41c0b5
PB		 3366
3367 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3368 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3369 temp = 0;
2d41c0b5
PB		 3370
3371 temp |= p_wm->wm[level].plane_res_l[i] <<
3372 PLANE_WM_LINES_SHIFT;
3373 temp |= p_wm->wm[level].plane_res_b[i];
3374 if (p_wm->wm[level].plane_en[i])
3375 temp |= PLANE_WM_EN;
3376
3377 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3378 }
3379
3380 temp = 0;
2d41c0b5
PB		 3381
3382 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3383 temp |= p_wm->wm[level].cursor_res_b;
3384
3385 if (p_wm->wm[level].cursor_en)
3386 temp |= PLANE_WM_EN;
3387
3388 r->cursor[pipe][level] = temp;
2d41c0b5
PB		 3389
3390 }
3391
9414f563
DL		 3392 /* transition WMs */
3393 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3394 temp = 0;
3395 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3396 temp |= p_wm->trans_wm.plane_res_b[i];
3397 if (p_wm->trans_wm.plane_en[i])
3398 temp |= PLANE_WM_EN;
3399
3400 r->plane_trans[pipe][i] = temp;
3401 }
3402
3403 temp = 0;
3404 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3405 temp |= p_wm->trans_wm.cursor_res_b;
3406 if (p_wm->trans_wm.cursor_en)
3407 temp |= PLANE_WM_EN;
3408
3409 r->cursor_trans[pipe] = temp;
3410
2d41c0b5
PB		 3411 r->wm_linetime[pipe] = p_wm->linetime;
3412}
3413
16160e3d
DL		 3414static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3415 const struct skl_ddb_entry *entry)
3416{
3417 if (entry->end)
3418 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3419 else
3420 I915_WRITE(reg, 0);
3421}
3422
2d41c0b5
PB		 3423static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3424 const struct skl_wm_values *new)
3425{
3426 struct drm_device *dev = dev_priv->dev;
3427 struct intel_crtc *crtc;
3428
3429 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3430 int i, level, max_level = ilk_wm_max_level(dev);
3431 enum pipe pipe = crtc->pipe;
3432
5d374d96
DL		 3433 if (!new->dirty[pipe])
3434 continue;
8211bd5b 3435
5d374d96 3436 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3437
5d374d96
DL		 3438 for (level = 0; level <= max_level; level++) {
3439 for (i = 0; i < intel_num_planes(crtc); i++)
3440 I915_WRITE(PLANE_WM(pipe, i, level),
3441 new->plane[pipe][i][level]);
3442 I915_WRITE(CUR_WM(pipe, level),
3443 new->cursor[pipe][level]);
2d41c0b5 3444 }
5d374d96
DL		 3445 for (i = 0; i < intel_num_planes(crtc); i++)
3446 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3447 new->plane_trans[pipe][i]);
3448 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3449
2cd601c6 3450 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3451 skl_ddb_entry_write(dev_priv,
3452 PLANE_BUF_CFG(pipe, i),
3453 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3454 skl_ddb_entry_write(dev_priv,
3455 PLANE_NV12_BUF_CFG(pipe, i),
3456 &new->ddb.y_plane[pipe][i]);
3457 }
5d374d96
DL		 3458
3459 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3460 &new->ddb.cursor[pipe]);
2d41c0b5 3461 }
2d41c0b5
PB		 3462}
3463
0e8fb7ba
DL		 3464/*
3465 * When setting up a new DDB allocation arrangement, we need to correctly
3466 * sequence the times at which the new allocations for the pipes are taken into
3467 * account or we'll have pipes fetching from space previously allocated to
3468 * another pipe.
3469 *
3470 * Roughly the sequence looks like:
3471 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3472 * overlapping with a previous light-up pipe (another way to put it is:
3473 * pipes with their new allocation strickly included into their old ones).
3474 * 2. re-allocate the other pipes that get their allocation reduced
3475 * 3. allocate the pipes having their allocation increased
3476 *
3477 * Steps 1. and 2. are here to take care of the following case:
3478 * - Initially DDB looks like this:
3479 * | B | C |
3480 * - enable pipe A.
3481 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3482 * allocation
3483 * | A | B | C |
3484 *
3485 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3486 */
3487
d21b795c
DL		 3488static void
3489skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3490{
0e8fb7ba
DL		 3491 int plane;
3492
d21b795c
DL		 3493 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3494
dd740780 3495 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3496 I915_WRITE(PLANE_SURF(pipe, plane),
3497 I915_READ(PLANE_SURF(pipe, plane)));
3498 }
3499 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3500}
3501
3502static bool
3503skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3504 const struct skl_ddb_allocation *new,
3505 enum pipe pipe)
3506{
3507 uint16_t old_size, new_size;
3508
3509 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3510 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3511
3512 return old_size != new_size &&
3513 new->pipe[pipe].start >= old->pipe[pipe].start &&
3514 new->pipe[pipe].end <= old->pipe[pipe].end;
3515}
3516
3517static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3518 struct skl_wm_values *new_values)
3519{
3520 struct drm_device *dev = dev_priv->dev;
3521 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3522 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3523 struct intel_crtc *crtc;
3524 enum pipe pipe;
3525
3526 new_ddb = &new_values->ddb;
3527 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3528
3529 /*
3530 * First pass: flush the pipes with the new allocation contained into
3531 * the old space.
3532 *
3533 * We'll wait for the vblank on those pipes to ensure we can safely
3534 * re-allocate the freed space without this pipe fetching from it.
3535 */
3536 for_each_intel_crtc(dev, crtc) {
3537 if (!crtc->active)
3538 continue;
3539
3540 pipe = crtc->pipe;
3541
3542 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3543 continue;
3544
d21b795c 3545 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3546 intel_wait_for_vblank(dev, pipe);
3547
3548 reallocated[pipe] = true;
3549 }
3550
3551
3552 /*
3553 * Second pass: flush the pipes that are having their allocation
3554 * reduced, but overlapping with a previous allocation.
3555 *
3556 * Here as well we need to wait for the vblank to make sure the freed
3557 * space is not used anymore.
3558 */
3559 for_each_intel_crtc(dev, crtc) {
3560 if (!crtc->active)
3561 continue;
3562
3563 pipe = crtc->pipe;
3564
3565 if (reallocated[pipe])
3566 continue;
3567
3568 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3569 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3570 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3571 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3572 reallocated[pipe] = true;
0e8fb7ba 3573 }
0e8fb7ba
DL		 3574 }
3575
3576 /*
3577 * Third pass: flush the pipes that got more space allocated.
3578 *
3579 * We don't need to actively wait for the update here, next vblank
3580 * will just get more DDB space with the correct WM values.
3581 */
3582 for_each_intel_crtc(dev, crtc) {
3583 if (!crtc->active)
3584 continue;
3585
3586 pipe = crtc->pipe;
3587
3588 /*
3589 * At this point, only the pipes more space than before are
3590 * left to re-allocate.
3591 */
3592 if (reallocated[pipe])
3593 continue;
3594
d21b795c 3595 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3596 }
3597}
3598
2d41c0b5
PB		 3599static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3600 struct skl_pipe_wm_parameters *params,
3601 struct intel_wm_config *config,
3602 struct skl_ddb_allocation *ddb, /* out */
3603 struct skl_pipe_wm *pipe_wm /* out */)
3604{
3605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3606
3607 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3608 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB		 3609 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3610
3611 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3612 return false;
3613
3614 intel_crtc->wm.skl_active = *pipe_wm;
2cd601c6 3615
2d41c0b5
PB		 3616 return true;
3617}
3618
3619static void skl_update_other_pipe_wm(struct drm_device *dev,
3620 struct drm_crtc *crtc,
3621 struct intel_wm_config *config,
3622 struct skl_wm_values *r)
3623{
3624 struct intel_crtc *intel_crtc;
3625 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3626
3627 /*
3628 * If the WM update hasn't changed the allocation for this_crtc (the
3629 * crtc we are currently computing the new WM values for), other
3630 * enabled crtcs will keep the same allocation and we don't need to
3631 * recompute anything for them.
3632 */
3633 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3634 return;
3635
3636 /*
3637 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3638 * other active pipes need new DDB allocation and WM values.
3639 */
3640 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3641 base.head) {
3642 struct skl_pipe_wm_parameters params = {};
3643 struct skl_pipe_wm pipe_wm = {};
3644 bool wm_changed;
3645
3646 if (this_crtc->pipe == intel_crtc->pipe)
3647 continue;
3648
3649 if (!intel_crtc->active)
3650 continue;
3651
3652 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3653 &params, config,
3654 &r->ddb, &pipe_wm);
3655
3656 /*
3657 * If we end up re-computing the other pipe WM values, it's
3658 * because it was really needed, so we expect the WM values to
3659 * be different.
3660 */
3661 WARN_ON(!wm_changed);
3662
3663 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3664 r->dirty[intel_crtc->pipe] = true;
3665 }
3666}
3667
3668static void skl_update_wm(struct drm_crtc *crtc)
3669{
3670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3671 struct drm_device *dev = crtc->dev;
3672 struct drm_i915_private *dev_priv = dev->dev_private;
3673 struct skl_pipe_wm_parameters params = {};
3674 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3675 struct skl_pipe_wm pipe_wm = {};
3676 struct intel_wm_config config = {};
3677
3678 memset(results, 0, sizeof(*results));
3679
3680 skl_compute_wm_global_parameters(dev, &config);
3681
3682 if (!skl_update_pipe_wm(crtc, &params, &config,
3683 &results->ddb, &pipe_wm))
3684 return;
3685
3686 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3687 results->dirty[intel_crtc->pipe] = true;
3688
3689 skl_update_other_pipe_wm(dev, crtc, &config, results);
3690 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3691 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3692
3693 /* store the new configuration */
3694 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3695}
3696
3697static void
3698skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3699 uint32_t sprite_width, uint32_t sprite_height,
3700 int pixel_size, bool enabled, bool scaled)
3701{
3702 struct intel_plane *intel_plane = to_intel_plane(plane);
0fda6568 3703 struct drm_framebuffer *fb = plane->state->fb;
2d41c0b5
PB		 3704
3705 intel_plane->wm.enabled = enabled;
3706 intel_plane->wm.scaled = scaled;
3707 intel_plane->wm.horiz_pixels = sprite_width;
3708 intel_plane->wm.vert_pixels = sprite_height;
0fda6568 3709 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
2cd601c6
CK		 3710
3711 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3712 intel_plane->wm.bytes_per_pixel =
3713 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3714 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3715 intel_plane->wm.y_bytes_per_pixel =
3716 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3717 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3718
0fda6568
TU		 3719 /*
3720 * Framebuffer can be NULL on plane disable, but it does not
3721 * matter for watermarks if we assume no tiling in that case.
3722 */
3723 if (fb)
3724 intel_plane->wm.tiling = fb->modifier[0];
1fc0a8f7 3725 intel_plane->wm.rotation = plane->state->rotation;
2d41c0b5
PB		 3726
3727 skl_update_wm(crtc);
3728}
3729
820c1980 3730static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3731{
7c4a395f 3732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3733 struct drm_device *dev = crtc->dev;
801bcfff 3734 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 3735 struct ilk_wm_maximums max;
3736 struct ilk_pipe_wm_parameters params = {};
3737 struct ilk_wm_values results = {};
77c122bc 3738 enum intel_ddb_partitioning partitioning;
7c4a395f 3739 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3740 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3741 struct intel_wm_config config = {};
7c4a395f 3742
2a44b76b 3743 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 3744
3745 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3746
3747 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3748 return;
861f3389 3749
7c4a395f 3750 intel_crtc->wm.active = pipe_wm;
861f3389 3751
2a44b76b
VS		 3752 ilk_compute_wm_config(dev, &config);
3753
34982fe1 3754 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3755 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3756
3757 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 3758 if (INTEL_INFO(dev)->gen >= 7 &&
3759 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3760 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3761 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3762
820c1980 3763 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3764 } else {
198a1e9b 3765 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3766 }
3767
198a1e9b 3768 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3769 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3770
820c1980 3771 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3772
820c1980 3773 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3774}
3775
ed57cb8a
DL		 3776static void
3777ilk_update_sprite_wm(struct drm_plane *plane,
3778 struct drm_crtc *crtc,
3779 uint32_t sprite_width, uint32_t sprite_height,
3780 int pixel_size, bool enabled, bool scaled)
526682e9 3781{
8553c18e 3782 struct drm_device *dev = plane->dev;
adf3d35e 3783 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3784
adf3d35e
VS		 3785 intel_plane->wm.enabled = enabled;
3786 intel_plane->wm.scaled = scaled;
3787 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3788 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3789 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3790
8553c18e
VS		 3791 /*
3792 * IVB workaround: must disable low power watermarks for at least
3793 * one frame before enabling scaling. LP watermarks can be re-enabled
3794 * when scaling is disabled.
3795 *
3796 * WaCxSRDisabledForSpriteScaling:ivb
3797 */
3798 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3799 intel_wait_for_vblank(dev, intel_plane->pipe);
3800
820c1980 3801 ilk_update_wm(crtc);
526682e9
PZ		 3802}
3803
3078999f
PB		 3804static void skl_pipe_wm_active_state(uint32_t val,
3805 struct skl_pipe_wm *active,
3806 bool is_transwm,
3807 bool is_cursor,
3808 int i,
3809 int level)
3810{
3811 bool is_enabled = (val & PLANE_WM_EN) != 0;
3812
3813 if (!is_transwm) {
3814 if (!is_cursor) {
3815 active->wm[level].plane_en[i] = is_enabled;
3816 active->wm[level].plane_res_b[i] =
3817 val & PLANE_WM_BLOCKS_MASK;
3818 active->wm[level].plane_res_l[i] =
3819 (val >> PLANE_WM_LINES_SHIFT) &
3820 PLANE_WM_LINES_MASK;
3821 } else {
3822 active->wm[level].cursor_en = is_enabled;
3823 active->wm[level].cursor_res_b =
3824 val & PLANE_WM_BLOCKS_MASK;
3825 active->wm[level].cursor_res_l =
3826 (val >> PLANE_WM_LINES_SHIFT) &
3827 PLANE_WM_LINES_MASK;
3828 }
3829 } else {
3830 if (!is_cursor) {
3831 active->trans_wm.plane_en[i] = is_enabled;
3832 active->trans_wm.plane_res_b[i] =
3833 val & PLANE_WM_BLOCKS_MASK;
3834 active->trans_wm.plane_res_l[i] =
3835 (val >> PLANE_WM_LINES_SHIFT) &
3836 PLANE_WM_LINES_MASK;
3837 } else {
3838 active->trans_wm.cursor_en = is_enabled;
3839 active->trans_wm.cursor_res_b =
3840 val & PLANE_WM_BLOCKS_MASK;
3841 active->trans_wm.cursor_res_l =
3842 (val >> PLANE_WM_LINES_SHIFT) &
3843 PLANE_WM_LINES_MASK;
3844 }
3845 }
3846}
3847
3848static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3849{
3850 struct drm_device *dev = crtc->dev;
3851 struct drm_i915_private *dev_priv = dev->dev_private;
3852 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3854 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3855 enum pipe pipe = intel_crtc->pipe;
3856 int level, i, max_level;
3857 uint32_t temp;
3858
3859 max_level = ilk_wm_max_level(dev);
3860
3861 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3862
3863 for (level = 0; level <= max_level; level++) {
3864 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3865 hw->plane[pipe][i][level] =
3866 I915_READ(PLANE_WM(pipe, i, level));
3867 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3868 }
3869
3870 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3871 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3872 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3873
3ef00284 3874 if (!intel_crtc->active)
3078999f
PB		 3875 return;
3876
3877 hw->dirty[pipe] = true;
3878
3879 active->linetime = hw->wm_linetime[pipe];
3880
3881 for (level = 0; level <= max_level; level++) {
3882 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3883 temp = hw->plane[pipe][i][level];
3884 skl_pipe_wm_active_state(temp, active, false,
3885 false, i, level);
3886 }
3887 temp = hw->cursor[pipe][level];
3888 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3889 }
3890
3891 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3892 temp = hw->plane_trans[pipe][i];
3893 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3894 }
3895
3896 temp = hw->cursor_trans[pipe];
3897 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3898}
3899
3900void skl_wm_get_hw_state(struct drm_device *dev)
3901{
a269c583
DL		 3902 struct drm_i915_private *dev_priv = dev->dev_private;
3903 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3904 struct drm_crtc *crtc;
3905
a269c583 3906 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3907 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3908 skl_pipe_wm_get_hw_state(crtc);
3909}
3910
243e6a44
VS		 3911static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3912{
3913 struct drm_device *dev = crtc->dev;
3914 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3915 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3917 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3918 enum pipe pipe = intel_crtc->pipe;
3919 static const unsigned int wm0_pipe_reg[] = {
3920 [PIPE_A] = WM0_PIPEA_ILK,
3921 [PIPE_B] = WM0_PIPEB_ILK,
3922 [PIPE_C] = WM0_PIPEC_IVB,
3923 };
3924
3925 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3926 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3927 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3928
3ef00284 3929 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3930
3931 if (active->pipe_enabled) {
243e6a44
VS		 3932 u32 tmp = hw->wm_pipe[pipe];
3933
3934 /*
3935 * For active pipes LP0 watermark is marked as
3936 * enabled, and LP1+ watermaks as disabled since
3937 * we can't really reverse compute them in case
3938 * multiple pipes are active.
3939 */
3940 active->wm[0].enable = true;
3941 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3942 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3943 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3944 active->linetime = hw->wm_linetime[pipe];
3945 } else {
3946 int level, max_level = ilk_wm_max_level(dev);
3947
3948 /*
3949 * For inactive pipes, all watermark levels
3950 * should be marked as enabled but zeroed,
3951 * which is what we'd compute them to.
3952 */
3953 for (level = 0; level <= max_level; level++)
3954 active->wm[level].enable = true;
3955 }
3956}
3957
6eb1a681
VS		 3958#define _FW_WM(value, plane) \
3959 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3960#define _FW_WM_VLV(value, plane) \
3961 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3962
3963static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3964 struct vlv_wm_values *wm)
3965{
3966 enum pipe pipe;
3967 uint32_t tmp;
3968
3969 for_each_pipe(dev_priv, pipe) {
3970 tmp = I915_READ(VLV_DDL(pipe));
3971
3972 wm->ddl[pipe].primary =
3973 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3974 wm->ddl[pipe].cursor =
3975 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3976 wm->ddl[pipe].sprite[0] =
3977 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3978 wm->ddl[pipe].sprite[1] =
3979 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3980 }
3981
3982 tmp = I915_READ(DSPFW1);
3983 wm->sr.plane = _FW_WM(tmp, SR);
3984 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3985 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3986 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3987
3988 tmp = I915_READ(DSPFW2);
3989 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3990 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3991 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3992
3993 tmp = I915_READ(DSPFW3);
3994 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3995
3996 if (IS_CHERRYVIEW(dev_priv)) {
3997 tmp = I915_READ(DSPFW7_CHV);
3998 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3999 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4000
4001 tmp = I915_READ(DSPFW8_CHV);
4002 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4003 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4004
4005 tmp = I915_READ(DSPFW9_CHV);
4006 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4007 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4008
4009 tmp = I915_READ(DSPHOWM);
4010 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4011 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4012 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4013 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4014 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4015 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4016 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4017 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4018 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4019 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4020 } else {
4021 tmp = I915_READ(DSPFW7);
4022 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4023 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4024
4025 tmp = I915_READ(DSPHOWM);
4026 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4027 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4028 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4029 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4030 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4031 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4032 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4033 }
4034}
4035
4036#undef _FW_WM
4037#undef _FW_WM_VLV
4038
4039void vlv_wm_get_hw_state(struct drm_device *dev)
4040{
4041 struct drm_i915_private *dev_priv = to_i915(dev);
4042 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4043 struct intel_plane *plane;
4044 enum pipe pipe;
4045 u32 val;
4046
4047 vlv_read_wm_values(dev_priv, wm);
4048
4049 for_each_intel_plane(dev, plane) {
4050 switch (plane->base.type) {
4051 int sprite;
4052 case DRM_PLANE_TYPE_CURSOR:
4053 plane->wm.fifo_size = 63;
4054 break;
4055 case DRM_PLANE_TYPE_PRIMARY:
4056 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4057 break;
4058 case DRM_PLANE_TYPE_OVERLAY:
4059 sprite = plane->plane;
4060 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4061 break;
4062 }
4063 }
4064
4065 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4066 wm->level = VLV_WM_LEVEL_PM2;
4067
4068 if (IS_CHERRYVIEW(dev_priv)) {
4069 mutex_lock(&dev_priv->rps.hw_lock);
4070
4071 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4072 if (val & DSP_MAXFIFO_PM5_ENABLE)
4073 wm->level = VLV_WM_LEVEL_PM5;
4074
4075 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4076 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4077 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4078
4079 mutex_unlock(&dev_priv->rps.hw_lock);
4080 }
4081
4082 for_each_pipe(dev_priv, pipe)
4083 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4084 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4085 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4086
4087 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4088 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4089}
4090
243e6a44
VS		 4091void ilk_wm_get_hw_state(struct drm_device *dev)
4092{
4093 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4094 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4095 struct drm_crtc *crtc;
4096
70e1e0ec 4097 for_each_crtc(dev, crtc)
243e6a44
VS		 4098 ilk_pipe_wm_get_hw_state(crtc);
4099
4100 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4101 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4102 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4103
4104 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4105 if (INTEL_INFO(dev)->gen >= 7) {
4106 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4107 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4108 }
243e6a44 4109
a42a5719 4110 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4111 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4112 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4113 else if (IS_IVYBRIDGE(dev))
4114 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4115 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4116
4117 hw->enable_fbc_wm =
4118 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4119}
4120
b445e3b0
ED		 4121/**
4122 * intel_update_watermarks - update FIFO watermark values based on current modes
4123 *
4124 * Calculate watermark values for the various WM regs based on current mode
4125 * and plane configuration.
4126 *
4127 * There are several cases to deal with here:
4128 * - normal (i.e. non-self-refresh)
4129 * - self-refresh (SR) mode
4130 * - lines are large relative to FIFO size (buffer can hold up to 2)
4131 * - lines are small relative to FIFO size (buffer can hold more than 2
4132 * lines), so need to account for TLB latency
4133 *
4134 * The normal calculation is:
4135 * watermark = dotclock * bytes per pixel * latency
4136 * where latency is platform & configuration dependent (we assume pessimal
4137 * values here).
4138 *
4139 * The SR calculation is:
4140 * watermark = (trunc(latency/line time)+1) * surface width *
4141 * bytes per pixel
4142 * where
4143 * line time = htotal / dotclock
4144 * surface width = hdisplay for normal plane and 64 for cursor
4145 * and latency is assumed to be high, as above.
4146 *
4147 * The final value programmed to the register should always be rounded up,
4148 * and include an extra 2 entries to account for clock crossings.
4149 *
4150 * We don't use the sprite, so we can ignore that. And on Crestline we have
4151 * to set the non-SR watermarks to 8.
4152 */
46ba614c 4153void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4154{
46ba614c 4155 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4156
4157 if (dev_priv->display.update_wm)
46ba614c 4158 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4159}
4160
adf3d35e
VS		 4161void intel_update_sprite_watermarks(struct drm_plane *plane,
4162 struct drm_crtc *crtc,
ed57cb8a
DL		 4163 uint32_t sprite_width,
4164 uint32_t sprite_height,
4165 int pixel_size,
39db4a4d 4166 bool enabled, bool scaled)
b445e3b0 4167{
adf3d35e 4168 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 4169
4170 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 4171 dev_priv->display.update_sprite_wm(plane, crtc,
4172 sprite_width, sprite_height,
39db4a4d 4173 pixel_size, enabled, scaled);
b445e3b0
ED		 4174}
4175
9270388e
DV		 4176/**
4177 * Lock protecting IPS related data structures
9270388e
DV		 4178 */
4179DEFINE_SPINLOCK(mchdev_lock);
4180
4181/* Global for IPS driver to get at the current i915 device. Protected by
4182 * mchdev_lock. */
4183static struct drm_i915_private *i915_mch_dev;
4184
2b4e57bd
ED		 4185bool ironlake_set_drps(struct drm_device *dev, u8 val)
4186{
4187 struct drm_i915_private *dev_priv = dev->dev_private;
4188 u16 rgvswctl;
4189
9270388e
DV		 4190 assert_spin_locked(&mchdev_lock);
4191
2b4e57bd
ED		 4192 rgvswctl = I915_READ16(MEMSWCTL);
4193 if (rgvswctl & MEMCTL_CMD_STS) {
4194 DRM_DEBUG("gpu busy, RCS change rejected\n");
4195 return false; /* still busy with another command */
4196 }
4197
4198 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4199 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4200 I915_WRITE16(MEMSWCTL, rgvswctl);
4201 POSTING_READ16(MEMSWCTL);
4202
4203 rgvswctl |= MEMCTL_CMD_STS;
4204 I915_WRITE16(MEMSWCTL, rgvswctl);
4205
4206 return true;
4207}
4208
8090c6b9 4209static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4210{
4211 struct drm_i915_private *dev_priv = dev->dev_private;
4212 u32 rgvmodectl = I915_READ(MEMMODECTL);
4213 u8 fmax, fmin, fstart, vstart;
4214
9270388e
DV		 4215 spin_lock_irq(&mchdev_lock);
4216
2b4e57bd
ED		 4217 /* Enable temp reporting */
4218 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4219 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4220
4221 /* 100ms RC evaluation intervals */
4222 I915_WRITE(RCUPEI, 100000);
4223 I915_WRITE(RCDNEI, 100000);
4224
4225 /* Set max/min thresholds to 90ms and 80ms respectively */
4226 I915_WRITE(RCBMAXAVG, 90000);
4227 I915_WRITE(RCBMINAVG, 80000);
4228
4229 I915_WRITE(MEMIHYST, 1);
4230
4231 /* Set up min, max, and cur for interrupt handling */
4232 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4233 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4234 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4235 MEMMODE_FSTART_SHIFT;
4236
4237 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4238 PXVFREQ_PX_SHIFT;
4239
20e4d407
DV		 4240 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4241 dev_priv->ips.fstart = fstart;
2b4e57bd 4242
20e4d407
DV		 4243 dev_priv->ips.max_delay = fstart;
4244 dev_priv->ips.min_delay = fmin;
4245 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4246
4247 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4248 fmax, fmin, fstart);
4249
4250 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4251
4252 /*
4253 * Interrupts will be enabled in ironlake_irq_postinstall
4254 */
4255
4256 I915_WRITE(VIDSTART, vstart);
4257 POSTING_READ(VIDSTART);
4258
4259 rgvmodectl |= MEMMODE_SWMODE_EN;
4260 I915_WRITE(MEMMODECTL, rgvmodectl);
4261
9270388e 4262 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4263 DRM_ERROR("stuck trying to change perf mode\n");
6adfb1ef 4264 msleep(1);
2b4e57bd
ED		 4265
4266 ironlake_set_drps(dev, fstart);
4267
20e4d407 4268 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 4269 I915_READ(0x112e0);
20e4d407
DV		 4270 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4271 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 4272 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4273
4274 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4275}
4276
8090c6b9 4277static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4278{
4279 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4280 u16 rgvswctl;
4281
4282 spin_lock_irq(&mchdev_lock);
4283
4284 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4285
4286 /* Ack interrupts, disable EFC interrupt */
4287 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4288 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4289 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4290 I915_WRITE(DEIIR, DE_PCU_EVENT);
4291 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4292
4293 /* Go back to the starting frequency */
20e4d407 4294 ironlake_set_drps(dev, dev_priv->ips.fstart);
6adfb1ef 4295 msleep(1);
2b4e57bd
ED		 4296 rgvswctl |= MEMCTL_CMD_STS;
4297 I915_WRITE(MEMSWCTL, rgvswctl);
6adfb1ef 4298 msleep(1);
2b4e57bd 4299
9270388e 4300 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4301}
4302
acbe9475
DV		 4303/* There's a funny hw issue where the hw returns all 0 when reading from
4304 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4305 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4306 * all limits and the gpu stuck at whatever frequency it is at atm).
4307 */
74ef1173 4308static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4309{
7b9e0ae6 4310 u32 limits;
2b4e57bd 4311
20b46e59
DV		 4312 /* Only set the down limit when we've reached the lowest level to avoid
4313 * getting more interrupts, otherwise leave this clear. This prevents a
4314 * race in the hw when coming out of rc6: There's a tiny window where
4315 * the hw runs at the minimal clock before selecting the desired
4316 * frequency, if the down threshold expires in that window we will not
4317 * receive a down interrupt. */
74ef1173
AG		 4318 if (IS_GEN9(dev_priv->dev)) {
4319 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4320 if (val <= dev_priv->rps.min_freq_softlimit)
4321 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4322 } else {
4323 limits = dev_priv->rps.max_freq_softlimit << 24;
4324 if (val <= dev_priv->rps.min_freq_softlimit)
4325 limits |= dev_priv->rps.min_freq_softlimit << 16;
4326 }
20b46e59
DV		 4327
4328 return limits;
4329}
4330
dd75fdc8
CW		 4331static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4332{
4333 int new_power;
8a586437
AG		 4334 u32 threshold_up = 0, threshold_down = 0; /* in % */
4335 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4336
4337 new_power = dev_priv->rps.power;
4338 switch (dev_priv->rps.power) {
4339 case LOW_POWER:
b39fb297 4340 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4341 new_power = BETWEEN;
4342 break;
4343
4344 case BETWEEN:
b39fb297 4345 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4346 new_power = LOW_POWER;
b39fb297 4347 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4348 new_power = HIGH_POWER;
4349 break;
4350
4351 case HIGH_POWER:
b39fb297 4352 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4353 new_power = BETWEEN;
4354 break;
4355 }
4356 /* Max/min bins are special */
aed242ff 4357 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4358 new_power = LOW_POWER;
aed242ff 4359 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4360 new_power = HIGH_POWER;
4361 if (new_power == dev_priv->rps.power)
4362 return;
4363
4364 /* Note the units here are not exactly 1us, but 1280ns. */
4365 switch (new_power) {
4366 case LOW_POWER:
4367 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4368 ei_up = 16000;
4369 threshold_up = 95;
dd75fdc8
CW		 4370
4371 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4372 ei_down = 32000;
4373 threshold_down = 85;
dd75fdc8
CW		 4374 break;
4375
4376 case BETWEEN:
4377 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4378 ei_up = 13000;
4379 threshold_up = 90;
dd75fdc8
CW		 4380
4381 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4382 ei_down = 32000;
4383 threshold_down = 75;
dd75fdc8
CW		 4384 break;
4385
4386 case HIGH_POWER:
4387 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4388 ei_up = 10000;
4389 threshold_up = 85;
dd75fdc8
CW		 4390
4391 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4392 ei_down = 32000;
4393 threshold_down = 60;
dd75fdc8
CW		 4394 break;
4395 }
4396
8a586437
AG		 4397 I915_WRITE(GEN6_RP_UP_EI,
4398 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4399 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4400 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4401
4402 I915_WRITE(GEN6_RP_DOWN_EI,
4403 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4404 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4405 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4406
4407 I915_WRITE(GEN6_RP_CONTROL,
4408 GEN6_RP_MEDIA_TURBO |
4409 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4410 GEN6_RP_MEDIA_IS_GFX |
4411 GEN6_RP_ENABLE |
4412 GEN6_RP_UP_BUSY_AVG |
4413 GEN6_RP_DOWN_IDLE_AVG);
4414
dd75fdc8 4415 dev_priv->rps.power = new_power;
8fb55197
CW		 4416 dev_priv->rps.up_threshold = threshold_up;
4417 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4418 dev_priv->rps.last_adj = 0;
4419}
4420
2876ce73
CW		 4421static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4422{
4423 u32 mask = 0;
4424
4425 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4426 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4427 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4428 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4429
7b3c29f6
CW		 4430 mask &= dev_priv->pm_rps_events;
4431
59d02a1f 4432 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4433}
4434
b8a5ff8d
JM		 4435/* gen6_set_rps is called to update the frequency request, but should also be
4436 * called when the range (min_delay and max_delay) is modified so that we can
4437 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4438static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4439{
4440 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4441
4fc688ce 4442 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4443 WARN_ON(val > dev_priv->rps.max_freq);
4444 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4445
eb64cad1
CW		 4446 /* min/max delay may still have been modified so be sure to
4447 * write the limits value.
4448 */
4449 if (val != dev_priv->rps.cur_freq) {
4450 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4451
5704195c
AG		 4452 if (IS_GEN9(dev))
4453 I915_WRITE(GEN6_RPNSWREQ,
4454 GEN9_FREQUENCY(val));
4455 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4456 I915_WRITE(GEN6_RPNSWREQ,
4457 HSW_FREQUENCY(val));
4458 else
4459 I915_WRITE(GEN6_RPNSWREQ,
4460 GEN6_FREQUENCY(val) |
4461 GEN6_OFFSET(0) |
4462 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4463 }
7b9e0ae6 4464
7b9e0ae6
CW		 4465 /* Make sure we continue to get interrupts
4466 * until we hit the minimum or maximum frequencies.
4467 */
74ef1173 4468 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4469 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4470
d5570a72
BW		 4471 POSTING_READ(GEN6_RPNSWREQ);
4472
b39fb297 4473 dev_priv->rps.cur_freq = val;
be2cde9a 4474 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 4475}
4476
ffe02b40
VS		 4477static void valleyview_set_rps(struct drm_device *dev, u8 val)
4478{
4479 struct drm_i915_private *dev_priv = dev->dev_private;
4480
4481 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4482 WARN_ON(val > dev_priv->rps.max_freq);
4483 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4484
4485 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4486 "Odd GPU freq value\n"))
4487 val &= ~1;
4488
cd25dd5b
D		 4489 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4490
8fb55197 4491 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4492 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4493 if (!IS_CHERRYVIEW(dev_priv))
4494 gen6_set_rps_thresholds(dev_priv, val);
4495 }
ffe02b40 4496
ffe02b40
VS		 4497 dev_priv->rps.cur_freq = val;
4498 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4499}
4500
a7f6e231 4501/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4502 *
4503 * * If Gfx is Idle, then
a7f6e231
D		 4504 * 1. Forcewake Media well.
4505 * 2. Request idle freq.
4506 * 3. Release Forcewake of Media well.
76c3552f
D		 4507*/
4508static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4509{
aed242ff 4510 u32 val = dev_priv->rps.idle_freq;
5549d25f 4511
aed242ff 4512 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4513 return;
4514
a7f6e231
D		 4515 /* Wake up the media well, as that takes a lot less
4516 * power than the Render well. */
4517 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4518 valleyview_set_rps(dev_priv->dev, val);
4519 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4520}
4521
43cf3bf0
CW		 4522void gen6_rps_busy(struct drm_i915_private *dev_priv)
4523{
4524 mutex_lock(&dev_priv->rps.hw_lock);
4525 if (dev_priv->rps.enabled) {
4526 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4527 gen6_rps_reset_ei(dev_priv);
4528 I915_WRITE(GEN6_PMINTRMSK,
4529 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4530 }
4531 mutex_unlock(&dev_priv->rps.hw_lock);
4532}
4533
b29c19b6
CW		 4534void gen6_rps_idle(struct drm_i915_private *dev_priv)
4535{
691bb717
DL		 4536 struct drm_device *dev = dev_priv->dev;
4537
b29c19b6 4538 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4539 if (dev_priv->rps.enabled) {
21a11fff 4540 if (IS_VALLEYVIEW(dev))
76c3552f 4541 vlv_set_rps_idle(dev_priv);
7526ed79 4542 else
aed242ff 4543 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4544 dev_priv->rps.last_adj = 0;
43cf3bf0 4545 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4546 }
8d3afd7d 4547 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4548
8d3afd7d 4549 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4550 while (!list_empty(&dev_priv->rps.clients))
4551 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4552 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4553}
4554
1854d5ca 4555void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4556 struct intel_rps_client *rps,
4557 unsigned long submitted)
b29c19b6 4558{
8d3afd7d
CW		 4559 /* This is intentionally racy! We peek at the state here, then
4560 * validate inside the RPS worker.
4561 */
4562 if (!(dev_priv->mm.busy &&
4563 dev_priv->rps.enabled &&
4564 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4565 return;
43cf3bf0 4566
e61b9958
CW		 4567 /* Force a RPS boost (and don't count it against the client) if
4568 * the GPU is severely congested.
4569 */
d0bc54f2 4570 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4571 rps = NULL;
4572
8d3afd7d
CW		 4573 spin_lock(&dev_priv->rps.client_lock);
4574 if (rps == NULL || list_empty(&rps->link)) {
4575 spin_lock_irq(&dev_priv->irq_lock);
4576 if (dev_priv->rps.interrupts_enabled) {
4577 dev_priv->rps.client_boost = true;
4578 queue_work(dev_priv->wq, &dev_priv->rps.work);
4579 }
4580 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4581
2e1b8730
CW		 4582 if (rps != NULL) {
4583 list_add(&rps->link, &dev_priv->rps.clients);
4584 rps->boosts++;
1854d5ca
CW		 4585 } else
4586 dev_priv->rps.boosts++;
c0951f0c 4587 }
8d3afd7d 4588 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4589}
4590
ffe02b40 4591void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4592{
ffe02b40
VS		 4593 if (IS_VALLEYVIEW(dev))
4594 valleyview_set_rps(dev, val);
4595 else
4596 gen6_set_rps(dev, val);
0a073b84
JB		 4597}
4598
20e49366
ZW		 4599static void gen9_disable_rps(struct drm_device *dev)
4600{
4601 struct drm_i915_private *dev_priv = dev->dev_private;
4602
4603 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4604 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4605}
4606
44fc7d5c 4607static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4608{
4609 struct drm_i915_private *dev_priv = dev->dev_private;
4610
4611 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4612 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4613}
4614
38807746
D		 4615static void cherryview_disable_rps(struct drm_device *dev)
4616{
4617 struct drm_i915_private *dev_priv = dev->dev_private;
4618
4619 I915_WRITE(GEN6_RC_CONTROL, 0);
4620}
4621
44fc7d5c
DV		 4622static void valleyview_disable_rps(struct drm_device *dev)
4623{
4624 struct drm_i915_private *dev_priv = dev->dev_private;
4625
98a2e5f9
D		 4626 /* we're doing forcewake before Disabling RC6,
4627 * This what the BIOS expects when going into suspend */
59bad947 4628 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4629
44fc7d5c 4630 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4631
59bad947 4632 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4633}
4634
dc39fff7
BW		 4635static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4636{
91ca689a
ID		 4637 if (IS_VALLEYVIEW(dev)) {
4638 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4639 mode = GEN6_RC_CTL_RC6_ENABLE;
4640 else
4641 mode = 0;
4642 }
58abf1da
RV		 4643 if (HAS_RC6p(dev))
4644 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4645 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4646 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4647 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4648
4649 else
4650 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4651 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4652}
4653
e6069ca8 4654static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4655{
e7d66d89
DV		 4656 /* No RC6 before Ironlake and code is gone for ilk. */
4657 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4658 return 0;
4659
456470eb 4660 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4661 if (enable_rc6 >= 0) {
4662 int mask;
4663
58abf1da 4664 if (HAS_RC6p(dev))
e6069ca8
ID		 4665 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4666 INTEL_RC6pp_ENABLE;
4667 else
4668 mask = INTEL_RC6_ENABLE;
4669
4670 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4671 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4672 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4673
4674 return enable_rc6 & mask;
4675 }
2b4e57bd 4676
8bade1ad 4677 if (IS_IVYBRIDGE(dev))
cca84a1f 4678 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4679
4680 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4681}
4682
e6069ca8
ID		 4683int intel_enable_rc6(const struct drm_device *dev)
4684{
4685 return i915.enable_rc6;
4686}
4687
93ee2920 4688static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4689{
93ee2920
TR		 4690 struct drm_i915_private *dev_priv = dev->dev_private;
4691 uint32_t rp_state_cap;
4692 u32 ddcc_status = 0;
4693 int ret;
4694
3280e8b0
BW		 4695 /* All of these values are in units of 50MHz */
4696 dev_priv->rps.cur_freq = 0;
93ee2920 4697 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4698 if (IS_BROXTON(dev)) {
4699 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4700 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4701 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4702 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4703 } else {
4704 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4705 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4706 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4707 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4708 }
4709
3280e8b0
BW		 4710 /* hw_max = RP0 until we check for overclocking */
4711 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4712
93ee2920 4713 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
c5e0688c 4714 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
93ee2920
TR		 4715 ret = sandybridge_pcode_read(dev_priv,
4716 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4717 &ddcc_status);
4718 if (0 == ret)
4719 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4720 clamp_t(u8,
4721 ((ddcc_status >> 8) & 0xff),
4722 dev_priv->rps.min_freq,
4723 dev_priv->rps.max_freq);
93ee2920
TR		 4724 }
4725
c5e0688c
AG		 4726 if (IS_SKYLAKE(dev)) {
4727 /* Store the frequency values in 16.66 MHZ units, which is
4728 the natural hardware unit for SKL */
4729 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4730 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4731 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4732 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4733 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4734 }
4735
aed242ff
CW		 4736 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4737
3280e8b0
BW		 4738 /* Preserve min/max settings in case of re-init */
4739 if (dev_priv->rps.max_freq_softlimit == 0)
4740 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4741
93ee2920
TR		 4742 if (dev_priv->rps.min_freq_softlimit == 0) {
4743 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4744 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4745 max_t(int, dev_priv->rps.efficient_freq,
4746 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4747 else
4748 dev_priv->rps.min_freq_softlimit =
4749 dev_priv->rps.min_freq;
4750 }
3280e8b0
BW		 4751}
4752
b6fef0ef 4753/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4754static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4755{
4756 struct drm_i915_private *dev_priv = dev->dev_private;
4757
4758 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4759
ba1c554c
DL		 4760 gen6_init_rps_frequencies(dev);
4761
0beb059a
AG		 4762 /* Program defaults and thresholds for RPS*/
4763 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4764 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4765
4766 /* 1 second timeout*/
4767 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4768 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4769
b6fef0ef 4770 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4771
0beb059a
AG		 4772 /* Leaning on the below call to gen6_set_rps to program/setup the
4773 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4774 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4775 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4776 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4777
4778 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4779}
4780
4781static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4782{
4783 struct drm_i915_private *dev_priv = dev->dev_private;
4784 struct intel_engine_cs *ring;
4785 uint32_t rc6_mask = 0;
4786 int unused;
4787
4788 /* 1a: Software RC state - RC0 */
4789 I915_WRITE(GEN6_RC_STATE, 0);
4790
4791 /* 1b: Get forcewake during program sequence. Although the driver
4792 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4793 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4794
4795 /* 2a: Disable RC states. */
4796 I915_WRITE(GEN6_RC_CONTROL, 0);
4797
4798 /* 2b: Program RC6 thresholds.*/
4799 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4800 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4801 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4802 for_each_ring(ring, dev_priv, unused)
4803 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4804 I915_WRITE(GEN6_RC_SLEEP, 0);
4805 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4806
38c23527
ZW		 4807 /* 2c: Program Coarse Power Gating Policies. */
4808 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4809 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4810
20e49366
ZW		 4811 /* 3a: Enable RC6 */
4812 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4813 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4814 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4815 "on" : "off");
4816 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4817 GEN6_RC_CTL_EI_MODE(1) |
4818 rc6_mask);
4819
cb07bae0
SK		 4820 /*
4821 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4822 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
4823 */
a4104c55 4824 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
cb07bae0 4825 GEN9_MEDIA_PG_ENABLE : 0);
a4104c55 4826
38c23527 4827
59bad947 4828 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4829
4830}
4831
6edee7f3
BW		 4832static void gen8_enable_rps(struct drm_device *dev)
4833{
4834 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4835 struct intel_engine_cs *ring;
93ee2920 4836 uint32_t rc6_mask = 0;
6edee7f3
BW		 4837 int unused;
4838
4839 /* 1a: Software RC state - RC0 */
4840 I915_WRITE(GEN6_RC_STATE, 0);
4841
4842 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4843 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4844 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4845
4846 /* 2a: Disable RC states. */
4847 I915_WRITE(GEN6_RC_CONTROL, 0);
4848
93ee2920
TR		 4849 /* Initialize rps frequencies */
4850 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4851
4852 /* 2b: Program RC6 thresholds.*/
4853 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4854 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4855 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4856 for_each_ring(ring, dev_priv, unused)
4857 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4858 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4859 if (IS_BROADWELL(dev))
4860 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4861 else
4862 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4863
4864 /* 3: Enable RC6 */
4865 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4866 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4867 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4868 if (IS_BROADWELL(dev))
4869 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4870 GEN7_RC_CTL_TO_MODE |
4871 rc6_mask);
4872 else
4873 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4874 GEN6_RC_CTL_EI_MODE(1) |
4875 rc6_mask);
6edee7f3
BW		 4876
4877 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4878 I915_WRITE(GEN6_RPNSWREQ,
4879 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4880 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4881 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4882 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4883 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4884
4885 /* Docs recommend 900MHz, and 300 MHz respectively */
4886 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4887 dev_priv->rps.max_freq_softlimit << 24 |
4888 dev_priv->rps.min_freq_softlimit << 16);
4889
4890 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4891 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4892 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4893 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4894
4895 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4896
4897 /* 5: Enable RPS */
7526ed79
DV		 4898 I915_WRITE(GEN6_RP_CONTROL,
4899 GEN6_RP_MEDIA_TURBO |
4900 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4901 GEN6_RP_MEDIA_IS_GFX |
4902 GEN6_RP_ENABLE |
4903 GEN6_RP_UP_BUSY_AVG |
4904 GEN6_RP_DOWN_IDLE_AVG);
4905
4906 /* 6: Ring frequency + overclocking (our driver does this later */
4907
c7f3153a 4908 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4909 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4910
59bad947 4911 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4912}
4913
79f5b2c7 4914static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4915{
79f5b2c7 4916 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4917 struct intel_engine_cs *ring;
d060c169 4918 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4919 u32 gtfifodbg;
2b4e57bd 4920 int rc6_mode;
42c0526c 4921 int i, ret;
2b4e57bd 4922
4fc688ce 4923 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4924
2b4e57bd
ED		 4925 /* Here begins a magic sequence of register writes to enable
4926 * auto-downclocking.
4927 *
4928 * Perhaps there might be some value in exposing these to
4929 * userspace...
4930 */
4931 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4932
4933 /* Clear the DBG now so we don't confuse earlier errors */
4934 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4935 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4936 I915_WRITE(GTFIFODBG, gtfifodbg);
4937 }
4938
59bad947 4939 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4940
93ee2920
TR		 4941 /* Initialize rps frequencies */
4942 gen6_init_rps_frequencies(dev);
dd0a1aa1 4943
2b4e57bd
ED		 4944 /* disable the counters and set deterministic thresholds */
4945 I915_WRITE(GEN6_RC_CONTROL, 0);
4946
4947 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4948 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4949 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4950 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4951 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4952
b4519513
CW		 4953 for_each_ring(ring, dev_priv, i)
4954 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4955
4956 I915_WRITE(GEN6_RC_SLEEP, 0);
4957 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4958 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4959 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4960 else
4961 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4962 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4963 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4964
5a7dc92a 4965 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4966 rc6_mode = intel_enable_rc6(dev_priv->dev);
4967 if (rc6_mode & INTEL_RC6_ENABLE)
4968 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4969
5a7dc92a
ED		 4970 /* We don't use those on Haswell */
4971 if (!IS_HASWELL(dev)) {
4972 if (rc6_mode & INTEL_RC6p_ENABLE)
4973 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4974
5a7dc92a
ED		 4975 if (rc6_mode & INTEL_RC6pp_ENABLE)
4976 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4977 }
2b4e57bd 4978
dc39fff7 4979 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4980
4981 I915_WRITE(GEN6_RC_CONTROL,
4982 rc6_mask |
4983 GEN6_RC_CTL_EI_MODE(1) |
4984 GEN6_RC_CTL_HW_ENABLE);
4985
dd75fdc8
CW		 4986 /* Power down if completely idle for over 50ms */
4987 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4988 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4989
42c0526c 4990 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4991 if (ret)
42c0526c 4992 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4993
4994 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4995 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4996 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4997 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4998 (pcu_mbox & 0xff) * 50);
b39fb297 4999 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 5000 }
5001
dd75fdc8 5002 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 5003 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 5004
31643d54
BW		 5005 rc6vids = 0;
5006 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5007 if (IS_GEN6(dev) && ret) {
5008 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5009 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5010 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5011 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5012 rc6vids &= 0xffff00;
5013 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5014 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5015 if (ret)
5016 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5017 }
5018
59bad947 5019 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5020}
5021
c2bc2fc5 5022static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 5023{
79f5b2c7 5024 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 5025 int min_freq = 15;
3ebecd07
CW		 5026 unsigned int gpu_freq;
5027 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5028 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5029 int scaling_factor = 180;
eda79642 5030 struct cpufreq_policy *policy;
2b4e57bd 5031
4fc688ce 5032 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5033
eda79642
BW		 5034 policy = cpufreq_cpu_get(0);
5035 if (policy) {
5036 max_ia_freq = policy->cpuinfo.max_freq;
5037 cpufreq_cpu_put(policy);
5038 } else {
5039 /*
5040 * Default to measured freq if none found, PCU will ensure we
5041 * don't go over
5042 */
2b4e57bd 5043 max_ia_freq = tsc_khz;
eda79642 5044 }
2b4e57bd
ED		 5045
5046 /* Convert from kHz to MHz */
5047 max_ia_freq /= 1000;
5048
153b4b95 5049 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5050 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5051 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5052
4c8c7743
AG		 5053 if (IS_SKYLAKE(dev)) {
5054 /* Convert GT frequency to 50 HZ units */
5055 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5056 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5057 } else {
5058 min_gpu_freq = dev_priv->rps.min_freq;
5059 max_gpu_freq = dev_priv->rps.max_freq;
5060 }
5061
2b4e57bd
ED		 5062 /*
5063 * For each potential GPU frequency, load a ring frequency we'd like
5064 * to use for memory access. We do this by specifying the IA frequency
5065 * the PCU should use as a reference to determine the ring frequency.
5066 */
4c8c7743
AG		 5067 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5068 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5069 unsigned int ia_freq = 0, ring_freq = 0;
5070
4c8c7743
AG		 5071 if (IS_SKYLAKE(dev)) {
5072 /*
5073 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5074 * No floor required for ring frequency on SKL.
5075 */
5076 ring_freq = gpu_freq;
5077 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 5078 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5079 ring_freq = max(min_ring_freq, gpu_freq);
5080 } else if (IS_HASWELL(dev)) {
f6aca45c 5081 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5082 ring_freq = max(min_ring_freq, ring_freq);
5083 /* leave ia_freq as the default, chosen by cpufreq */
5084 } else {
5085 /* On older processors, there is no separate ring
5086 * clock domain, so in order to boost the bandwidth
5087 * of the ring, we need to upclock the CPU (ia_freq).
5088 *
5089 * For GPU frequencies less than 750MHz,
5090 * just use the lowest ring freq.
5091 */
5092 if (gpu_freq < min_freq)
5093 ia_freq = 800;
5094 else
5095 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5096 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5097 }
2b4e57bd 5098
42c0526c
BW		 5099 sandybridge_pcode_write(dev_priv,
5100 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5101 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5102 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5103 gpu_freq);
2b4e57bd 5104 }
2b4e57bd
ED		 5105}
5106
c2bc2fc5
ID		 5107void gen6_update_ring_freq(struct drm_device *dev)
5108{
5109 struct drm_i915_private *dev_priv = dev->dev_private;
5110
97d3308a 5111 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5112 return;
5113
5114 mutex_lock(&dev_priv->rps.hw_lock);
5115 __gen6_update_ring_freq(dev);
5116 mutex_unlock(&dev_priv->rps.hw_lock);
5117}
5118
03af2045 5119static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5120{
095acd5f 5121 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5122 u32 val, rp0;
5123
095acd5f
D		 5124 if (dev->pdev->revision >= 0x20) {
5125 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5126
095acd5f
D		 5127 switch (INTEL_INFO(dev)->eu_total) {
5128 case 8:
5129 /* (2 * 4) config */
5130 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5131 break;
5132 case 12:
5133 /* (2 * 6) config */
5134 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5135 break;
5136 case 16:
5137 /* (2 * 8) config */
5138 default:
5139 /* Setting (2 * 8) Min RP0 for any other combination */
5140 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5141 break;
5142 }
5143 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5144 } else {
5145 /* For pre-production hardware */
5146 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5147 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5148 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5149 }
2b6b3a09
D		 5150 return rp0;
5151}
5152
5153static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5154{
5155 u32 val, rpe;
5156
5157 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5158 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5159
5160 return rpe;
5161}
5162
7707df4a
D		 5163static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5164{
095acd5f 5165 struct drm_device *dev = dev_priv->dev;
7707df4a
D		 5166 u32 val, rp1;
5167
095acd5f
D		 5168 if (dev->pdev->revision >= 0x20) {
5169 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5170 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5171 } else {
5172 /* For pre-production hardware */
5173 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5174 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5175 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5176 }
7707df4a
D		 5177 return rp1;
5178}
5179
f8f2b001
D		 5180static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5181{
5182 u32 val, rp1;
5183
5184 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5185
5186 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5187
5188 return rp1;
5189}
5190
03af2045 5191static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5192{
5193 u32 val, rp0;
5194
64936258 5195 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5196
5197 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5198 /* Clamp to max */
5199 rp0 = min_t(u32, rp0, 0xea);
5200
5201 return rp0;
5202}
5203
5204static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5205{
5206 u32 val, rpe;
5207
64936258 5208 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5209 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5210 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5211 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5212
5213 return rpe;
5214}
5215
03af2045 5216static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5217{
64936258 5218 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 5219}
5220
ae48434c
ID		 5221/* Check that the pctx buffer wasn't move under us. */
5222static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5223{
5224 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5225
5226 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5227 dev_priv->vlv_pctx->stolen->start);
5228}
5229
38807746
D		 5230
5231/* Check that the pcbr address is not empty. */
5232static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5233{
5234 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5235
5236 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5237}
5238
5239static void cherryview_setup_pctx(struct drm_device *dev)
5240{
5241 struct drm_i915_private *dev_priv = dev->dev_private;
5242 unsigned long pctx_paddr, paddr;
5243 struct i915_gtt *gtt = &dev_priv->gtt;
5244 u32 pcbr;
5245 int pctx_size = 32*1024;
5246
5247 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5248
5249 pcbr = I915_READ(VLV_PCBR);
5250 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5251 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5252 paddr = (dev_priv->mm.stolen_base +
5253 (gtt->stolen_size - pctx_size));
5254
5255 pctx_paddr = (paddr & (~4095));
5256 I915_WRITE(VLV_PCBR, pctx_paddr);
5257 }
ce611ef8
VS		 5258
5259 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5260}
5261
c9cddffc
JB		 5262static void valleyview_setup_pctx(struct drm_device *dev)
5263{
5264 struct drm_i915_private *dev_priv = dev->dev_private;
5265 struct drm_i915_gem_object *pctx;
5266 unsigned long pctx_paddr;
5267 u32 pcbr;
5268 int pctx_size = 24*1024;
5269
17b0c1f7
ID		 5270 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5271
c9cddffc
JB		 5272 pcbr = I915_READ(VLV_PCBR);
5273 if (pcbr) {
5274 /* BIOS set it up already, grab the pre-alloc'd space */
5275 int pcbr_offset;
5276
5277 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5278 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5279 pcbr_offset,
190d6cd5 5280 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5281 pctx_size);
5282 goto out;
5283 }
5284
ce611ef8
VS		 5285 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5286
c9cddffc
JB		 5287 /*
5288 * From the Gunit register HAS:
5289 * The Gfx driver is expected to program this register and ensure
5290 * proper allocation within Gfx stolen memory. For example, this
5291 * register should be programmed such than the PCBR range does not
5292 * overlap with other ranges, such as the frame buffer, protected
5293 * memory, or any other relevant ranges.
5294 */
5295 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5296 if (!pctx) {
5297 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5298 return;
5299 }
5300
5301 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5302 I915_WRITE(VLV_PCBR, pctx_paddr);
5303
5304out:
ce611ef8 5305 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5306 dev_priv->vlv_pctx = pctx;
5307}
5308
ae48434c
ID		 5309static void valleyview_cleanup_pctx(struct drm_device *dev)
5310{
5311 struct drm_i915_private *dev_priv = dev->dev_private;
5312
5313 if (WARN_ON(!dev_priv->vlv_pctx))
5314 return;
5315
5316 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5317 dev_priv->vlv_pctx = NULL;
5318}
5319
4e80519e
ID		 5320static void valleyview_init_gt_powersave(struct drm_device *dev)
5321{
5322 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5323 u32 val;
4e80519e
ID		 5324
5325 valleyview_setup_pctx(dev);
5326
5327 mutex_lock(&dev_priv->rps.hw_lock);
5328
2bb25c17
VS		 5329 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5330 switch ((val >> 6) & 3) {
5331 case 0:
5332 case 1:
5333 dev_priv->mem_freq = 800;
5334 break;
5335 case 2:
5336 dev_priv->mem_freq = 1066;
5337 break;
5338 case 3:
5339 dev_priv->mem_freq = 1333;
5340 break;
5341 }
80b83b62 5342 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5343
4e80519e
ID		 5344 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5345 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5346 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5347 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5348 dev_priv->rps.max_freq);
5349
5350 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5351 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5352 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5353 dev_priv->rps.efficient_freq);
5354
f8f2b001
D		 5355 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5356 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5357 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5358 dev_priv->rps.rp1_freq);
5359
4e80519e
ID		 5360 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5361 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5362 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5363 dev_priv->rps.min_freq);
5364
aed242ff
CW		 5365 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5366
4e80519e
ID		 5367 /* Preserve min/max settings in case of re-init */
5368 if (dev_priv->rps.max_freq_softlimit == 0)
5369 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5370
5371 if (dev_priv->rps.min_freq_softlimit == 0)
5372 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5373
5374 mutex_unlock(&dev_priv->rps.hw_lock);
5375}
5376
38807746
D		 5377static void cherryview_init_gt_powersave(struct drm_device *dev)
5378{
2b6b3a09 5379 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5380 u32 val;
2b6b3a09 5381
38807746 5382 cherryview_setup_pctx(dev);
2b6b3a09
D		 5383
5384 mutex_lock(&dev_priv->rps.hw_lock);
5385
a580516d 5386 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5387 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5388 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5389
2bb25c17
VS		 5390 switch ((val >> 2) & 0x7) {
5391 case 0:
5392 case 1:
5393 dev_priv->rps.cz_freq = 200;
5394 dev_priv->mem_freq = 1600;
5395 break;
5396 case 2:
5397 dev_priv->rps.cz_freq = 267;
5398 dev_priv->mem_freq = 1600;
5399 break;
5400 case 3:
5401 dev_priv->rps.cz_freq = 333;
5402 dev_priv->mem_freq = 2000;
5403 break;
5404 case 4:
5405 dev_priv->rps.cz_freq = 320;
5406 dev_priv->mem_freq = 1600;
5407 break;
5408 case 5:
5409 dev_priv->rps.cz_freq = 400;
5410 dev_priv->mem_freq = 1600;
5411 break;
5412 }
80b83b62 5413 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5414
2b6b3a09
D		 5415 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5416 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5417 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5418 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5419 dev_priv->rps.max_freq);
5420
5421 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5422 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5423 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5424 dev_priv->rps.efficient_freq);
5425
7707df4a
D		 5426 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5427 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5428 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5429 dev_priv->rps.rp1_freq);
5430
5b7c91b7
D		 5431 /* PUnit validated range is only [RPe, RP0] */
5432 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5433 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5434 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5435 dev_priv->rps.min_freq);
5436
1c14762d
VS		 5437 WARN_ONCE((dev_priv->rps.max_freq |
5438 dev_priv->rps.efficient_freq |
5439 dev_priv->rps.rp1_freq |
5440 dev_priv->rps.min_freq) & 1,
5441 "Odd GPU freq values\n");
5442
aed242ff
CW		 5443 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5444
2b6b3a09
D		 5445 /* Preserve min/max settings in case of re-init */
5446 if (dev_priv->rps.max_freq_softlimit == 0)
5447 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5448
5449 if (dev_priv->rps.min_freq_softlimit == 0)
5450 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5451
5452 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5453}
5454
4e80519e
ID		 5455static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5456{
5457 valleyview_cleanup_pctx(dev);
5458}
5459
38807746
D		 5460static void cherryview_enable_rps(struct drm_device *dev)
5461{
5462 struct drm_i915_private *dev_priv = dev->dev_private;
5463 struct intel_engine_cs *ring;
2b6b3a09 5464 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5465 int i;
5466
5467 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5468
5469 gtfifodbg = I915_READ(GTFIFODBG);
5470 if (gtfifodbg) {
5471 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5472 gtfifodbg);
5473 I915_WRITE(GTFIFODBG, gtfifodbg);
5474 }
5475
5476 cherryview_check_pctx(dev_priv);
5477
5478 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5479 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5480 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5481
160614a2
VS		 5482 /* Disable RC states. */
5483 I915_WRITE(GEN6_RC_CONTROL, 0);
5484
38807746
D		 5485 /* 2a: Program RC6 thresholds.*/
5486 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5487 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5488 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5489
5490 for_each_ring(ring, dev_priv, i)
5491 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5492 I915_WRITE(GEN6_RC_SLEEP, 0);
5493
f4f71c7d
D		 5494 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5495 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5496
5497 /* allows RC6 residency counter to work */
5498 I915_WRITE(VLV_COUNTER_CONTROL,
5499 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5500 VLV_MEDIA_RC6_COUNT_EN |
5501 VLV_RENDER_RC6_COUNT_EN));
5502
5503 /* For now we assume BIOS is allocating and populating the PCBR */
5504 pcbr = I915_READ(VLV_PCBR);
5505
38807746
D		 5506 /* 3: Enable RC6 */
5507 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5508 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5509 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5510
5511 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5512
2b6b3a09 5513 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5514 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5515 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5516 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5517 I915_WRITE(GEN6_RP_UP_EI, 66000);
5518 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5519
5520 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5521
5522 /* 5: Enable RPS */
5523 I915_WRITE(GEN6_RP_CONTROL,
5524 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5525 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5526 GEN6_RP_ENABLE |
5527 GEN6_RP_UP_BUSY_AVG |
5528 GEN6_RP_DOWN_IDLE_AVG);
5529
3ef62342
D		 5530 /* Setting Fixed Bias */
5531 val = VLV_OVERRIDE_EN |
5532 VLV_SOC_TDP_EN |
5533 CHV_BIAS_CPU_50_SOC_50;
5534 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5535
2b6b3a09
D		 5536 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5537
8d40c3ae
VS		 5538 /* RPS code assumes GPLL is used */
5539 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5540
c8e9627d 5541 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
2b6b3a09
D		 5542 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5543
5544 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5545 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5546 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5547 dev_priv->rps.cur_freq);
5548
5549 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5550 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5551 dev_priv->rps.efficient_freq);
5552
5553 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5554
59bad947 5555 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5556}
5557
0a073b84
JB		 5558static void valleyview_enable_rps(struct drm_device *dev)
5559{
5560 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5561 struct intel_engine_cs *ring;
2a5913a8 5562 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5563 int i;
5564
5565 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5566
ae48434c
ID		 5567 valleyview_check_pctx(dev_priv);
5568
0a073b84 5569 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5570 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5571 gtfifodbg);
0a073b84
JB		 5572 I915_WRITE(GTFIFODBG, gtfifodbg);
5573 }
5574
c8d9a590 5575 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5576 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5577
160614a2
VS		 5578 /* Disable RC states. */
5579 I915_WRITE(GEN6_RC_CONTROL, 0);
5580
cad725fe 5581 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5582 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5583 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5584 I915_WRITE(GEN6_RP_UP_EI, 66000);
5585 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5586
5587 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5588
5589 I915_WRITE(GEN6_RP_CONTROL,
5590 GEN6_RP_MEDIA_TURBO |
5591 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5592 GEN6_RP_MEDIA_IS_GFX |
5593 GEN6_RP_ENABLE |
5594 GEN6_RP_UP_BUSY_AVG |
5595 GEN6_RP_DOWN_IDLE_CONT);
5596
5597 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5598 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5599 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5600
5601 for_each_ring(ring, dev_priv, i)
5602 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5603
2f0aa304 5604 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5605
5606 /* allows RC6 residency counter to work */
49798eb2 5607 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5608 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5609 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5610 VLV_MEDIA_RC6_COUNT_EN |
5611 VLV_RENDER_RC6_COUNT_EN));
31685c25 5612
a2b23fe0 5613 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5614 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5615
5616 intel_print_rc6_info(dev, rc6_mode);
5617
a2b23fe0 5618 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5619
3ef62342
D		 5620 /* Setting Fixed Bias */
5621 val = VLV_OVERRIDE_EN |
5622 VLV_SOC_TDP_EN |
5623 VLV_BIAS_CPU_125_SOC_875;
5624 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5625
64936258 5626 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5627
8d40c3ae
VS		 5628 /* RPS code assumes GPLL is used */
5629 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5630
c8e9627d 5631 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
0a073b84
JB		 5632 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5633
b39fb297 5634 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5635 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5636 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5637 dev_priv->rps.cur_freq);
0a073b84 5638
73008b98 5639 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5640 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5641 dev_priv->rps.efficient_freq);
0a073b84 5642
b39fb297 5643 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5644
59bad947 5645 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5646}
5647
dde18883
ED		 5648static unsigned long intel_pxfreq(u32 vidfreq)
5649{
5650 unsigned long freq;
5651 int div = (vidfreq & 0x3f0000) >> 16;
5652 int post = (vidfreq & 0x3000) >> 12;
5653 int pre = (vidfreq & 0x7);
5654
5655 if (!pre)
5656 return 0;
5657
5658 freq = ((div * 133333) / ((1<<post) * pre));
5659
5660 return freq;
5661}
5662
eb48eb00
DV		 5663static const struct cparams {
5664 u16 i;
5665 u16 t;
5666 u16 m;
5667 u16 c;
5668} cparams[] = {
5669 { 1, 1333, 301, 28664 },
5670 { 1, 1066, 294, 24460 },
5671 { 1, 800, 294, 25192 },
5672 { 0, 1333, 276, 27605 },
5673 { 0, 1066, 276, 27605 },
5674 { 0, 800, 231, 23784 },
5675};
5676
f531dcb2 5677static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5678{
5679 u64 total_count, diff, ret;
5680 u32 count1, count2, count3, m = 0, c = 0;
5681 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5682 int i;
5683
02d71956
DV		 5684 assert_spin_locked(&mchdev_lock);
5685
20e4d407 5686 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5687
5688 /* Prevent division-by-zero if we are asking too fast.
5689 * Also, we don't get interesting results if we are polling
5690 * faster than once in 10ms, so just return the saved value
5691 * in such cases.
5692 */
5693 if (diff1 <= 10)
20e4d407 5694 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5695
5696 count1 = I915_READ(DMIEC);
5697 count2 = I915_READ(DDREC);
5698 count3 = I915_READ(CSIEC);
5699
5700 total_count = count1 + count2 + count3;
5701
5702 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5703 if (total_count < dev_priv->ips.last_count1) {
5704 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5705 diff += total_count;
5706 } else {
20e4d407 5707 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5708 }
5709
5710 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5711 if (cparams[i].i == dev_priv->ips.c_m &&
5712 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5713 m = cparams[i].m;
5714 c = cparams[i].c;
5715 break;
5716 }
5717 }
5718
5719 diff = div_u64(diff, diff1);
5720 ret = ((m * diff) + c);
5721 ret = div_u64(ret, 10);
5722
20e4d407
DV		 5723 dev_priv->ips.last_count1 = total_count;
5724 dev_priv->ips.last_time1 = now;
eb48eb00 5725
20e4d407 5726 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5727
5728 return ret;
5729}
5730
f531dcb2
CW		 5731unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5732{
3d13ef2e 5733 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5734 unsigned long val;
5735
3d13ef2e 5736 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5737 return 0;
5738
5739 spin_lock_irq(&mchdev_lock);
5740
5741 val = __i915_chipset_val(dev_priv);
5742
5743 spin_unlock_irq(&mchdev_lock);
5744
5745 return val;
5746}
5747
eb48eb00
DV		 5748unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5749{
5750 unsigned long m, x, b;
5751 u32 tsfs;
5752
5753 tsfs = I915_READ(TSFS);
5754
5755 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5756 x = I915_READ8(TR1);
5757
5758 b = tsfs & TSFS_INTR_MASK;
5759
5760 return ((m * x) / 127) - b;
5761}
5762
d972d6ee
MK		 5763static int _pxvid_to_vd(u8 pxvid)
5764{
5765 if (pxvid == 0)
5766 return 0;
5767
5768 if (pxvid >= 8 && pxvid < 31)
5769 pxvid = 31;
5770
5771 return (pxvid + 2) * 125;
5772}
5773
5774static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5775{
3d13ef2e 5776 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5777 const int vd = _pxvid_to_vd(pxvid);
5778 const int vm = vd - 1125;
5779
3d13ef2e 5780 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5781 return vm > 0 ? vm : 0;
5782
5783 return vd;
eb48eb00
DV		 5784}
5785
02d71956 5786static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5787{
5ed0bdf2 5788 u64 now, diff, diffms;
eb48eb00
DV		 5789 u32 count;
5790
02d71956 5791 assert_spin_locked(&mchdev_lock);
eb48eb00 5792
5ed0bdf2
TG		 5793 now = ktime_get_raw_ns();
5794 diffms = now - dev_priv->ips.last_time2;
5795 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5796
5797 /* Don't divide by 0 */
eb48eb00
DV		 5798 if (!diffms)
5799 return;
5800
5801 count = I915_READ(GFXEC);
5802
20e4d407
DV		 5803 if (count < dev_priv->ips.last_count2) {
5804 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5805 diff += count;
5806 } else {
20e4d407 5807 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5808 }
5809
20e4d407
DV		 5810 dev_priv->ips.last_count2 = count;
5811 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5812
5813 /* More magic constants... */
5814 diff = diff * 1181;
5815 diff = div_u64(diff, diffms * 10);
20e4d407 5816 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5817}
5818
02d71956
DV		 5819void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5820{
3d13ef2e
DL		 5821 struct drm_device *dev = dev_priv->dev;
5822
5823 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5824 return;
5825
9270388e 5826 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5827
5828 __i915_update_gfx_val(dev_priv);
5829
9270388e 5830 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5831}
5832
f531dcb2 5833static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5834{
5835 unsigned long t, corr, state1, corr2, state2;
5836 u32 pxvid, ext_v;
5837
02d71956
DV		 5838 assert_spin_locked(&mchdev_lock);
5839
b39fb297 5840 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 5841 pxvid = (pxvid >> 24) & 0x7f;
5842 ext_v = pvid_to_extvid(dev_priv, pxvid);
5843
5844 state1 = ext_v;
5845
5846 t = i915_mch_val(dev_priv);
5847
5848 /* Revel in the empirically derived constants */
5849
5850 /* Correction factor in 1/100000 units */
5851 if (t > 80)
5852 corr = ((t * 2349) + 135940);
5853 else if (t >= 50)
5854 corr = ((t * 964) + 29317);
5855 else /* < 50 */
5856 corr = ((t * 301) + 1004);
5857
5858 corr = corr * ((150142 * state1) / 10000 - 78642);
5859 corr /= 100000;
20e4d407 5860 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5861
5862 state2 = (corr2 * state1) / 10000;
5863 state2 /= 100; /* convert to mW */
5864
02d71956 5865 __i915_update_gfx_val(dev_priv);
eb48eb00 5866
20e4d407 5867 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5868}
5869
f531dcb2
CW		 5870unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5871{
3d13ef2e 5872 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5873 unsigned long val;
5874
3d13ef2e 5875 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5876 return 0;
5877
5878 spin_lock_irq(&mchdev_lock);
5879
5880 val = __i915_gfx_val(dev_priv);
5881
5882 spin_unlock_irq(&mchdev_lock);
5883
5884 return val;
5885}
5886
eb48eb00
DV		 5887/**
5888 * i915_read_mch_val - return value for IPS use
5889 *
5890 * Calculate and return a value for the IPS driver to use when deciding whether
5891 * we have thermal and power headroom to increase CPU or GPU power budget.
5892 */
5893unsigned long i915_read_mch_val(void)
5894{
5895 struct drm_i915_private *dev_priv;
5896 unsigned long chipset_val, graphics_val, ret = 0;
5897
9270388e 5898 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5899 if (!i915_mch_dev)
5900 goto out_unlock;
5901 dev_priv = i915_mch_dev;
5902
f531dcb2
CW		 5903 chipset_val = __i915_chipset_val(dev_priv);
5904 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5905
5906 ret = chipset_val + graphics_val;
5907
5908out_unlock:
9270388e 5909 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5910
5911 return ret;
5912}
5913EXPORT_SYMBOL_GPL(i915_read_mch_val);
5914
5915/**
5916 * i915_gpu_raise - raise GPU frequency limit
5917 *
5918 * Raise the limit; IPS indicates we have thermal headroom.
5919 */
5920bool i915_gpu_raise(void)
5921{
5922 struct drm_i915_private *dev_priv;
5923 bool ret = true;
5924
9270388e 5925 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5926 if (!i915_mch_dev) {
5927 ret = false;
5928 goto out_unlock;
5929 }
5930 dev_priv = i915_mch_dev;
5931
20e4d407
DV		 5932 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5933 dev_priv->ips.max_delay--;
eb48eb00
DV		 5934
5935out_unlock:
9270388e 5936 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5937
5938 return ret;
5939}
5940EXPORT_SYMBOL_GPL(i915_gpu_raise);
5941
5942/**
5943 * i915_gpu_lower - lower GPU frequency limit
5944 *
5945 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5946 * frequency maximum.
5947 */
5948bool i915_gpu_lower(void)
5949{
5950 struct drm_i915_private *dev_priv;
5951 bool ret = true;
5952
9270388e 5953 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5954 if (!i915_mch_dev) {
5955 ret = false;
5956 goto out_unlock;
5957 }
5958 dev_priv = i915_mch_dev;
5959
20e4d407
DV		 5960 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5961 dev_priv->ips.max_delay++;
eb48eb00
DV		 5962
5963out_unlock:
9270388e 5964 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5965
5966 return ret;
5967}
5968EXPORT_SYMBOL_GPL(i915_gpu_lower);
5969
5970/**
5971 * i915_gpu_busy - indicate GPU business to IPS
5972 *
5973 * Tell the IPS driver whether or not the GPU is busy.
5974 */
5975bool i915_gpu_busy(void)
5976{
5977 struct drm_i915_private *dev_priv;
a4872ba6 5978 struct intel_engine_cs *ring;
eb48eb00 5979 bool ret = false;
f047e395 5980 int i;
eb48eb00 5981
9270388e 5982 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5983 if (!i915_mch_dev)
5984 goto out_unlock;
5985 dev_priv = i915_mch_dev;
5986
f047e395
CW		 5987 for_each_ring(ring, dev_priv, i)
5988 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5989
5990out_unlock:
9270388e 5991 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5992
5993 return ret;
5994}
5995EXPORT_SYMBOL_GPL(i915_gpu_busy);
5996
5997/**
5998 * i915_gpu_turbo_disable - disable graphics turbo
5999 *
6000 * Disable graphics turbo by resetting the max frequency and setting the
6001 * current frequency to the default.
6002 */
6003bool i915_gpu_turbo_disable(void)
6004{
6005 struct drm_i915_private *dev_priv;
6006 bool ret = true;
6007
9270388e 6008 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6009 if (!i915_mch_dev) {
6010 ret = false;
6011 goto out_unlock;
6012 }
6013 dev_priv = i915_mch_dev;
6014
20e4d407 6015 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6016
20e4d407 6017 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 6018 ret = false;
6019
6020out_unlock:
9270388e 6021 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6022
6023 return ret;
6024}
6025EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6026
6027/**
6028 * Tells the intel_ips driver that the i915 driver is now loaded, if
6029 * IPS got loaded first.
6030 *
6031 * This awkward dance is so that neither module has to depend on the
6032 * other in order for IPS to do the appropriate communication of
6033 * GPU turbo limits to i915.
6034 */
6035static void
6036ips_ping_for_i915_load(void)
6037{
6038 void (*link)(void);
6039
6040 link = symbol_get(ips_link_to_i915_driver);
6041 if (link) {
6042 link();
6043 symbol_put(ips_link_to_i915_driver);
6044 }
6045}
6046
6047void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6048{
02d71956
DV		 6049 /* We only register the i915 ips part with intel-ips once everything is
6050 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6051 spin_lock_irq(&mchdev_lock);
eb48eb00 6052 i915_mch_dev = dev_priv;
9270388e 6053 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6054
6055 ips_ping_for_i915_load();
6056}
6057
6058void intel_gpu_ips_teardown(void)
6059{
9270388e 6060 spin_lock_irq(&mchdev_lock);
eb48eb00 6061 i915_mch_dev = NULL;
9270388e 6062 spin_unlock_irq(&mchdev_lock);
eb48eb00 6063}
76c3552f 6064
8090c6b9 6065static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 6066{
6067 struct drm_i915_private *dev_priv = dev->dev_private;
6068 u32 lcfuse;
6069 u8 pxw[16];
6070 int i;
6071
6072 /* Disable to program */
6073 I915_WRITE(ECR, 0);
6074 POSTING_READ(ECR);
6075
6076 /* Program energy weights for various events */
6077 I915_WRITE(SDEW, 0x15040d00);
6078 I915_WRITE(CSIEW0, 0x007f0000);
6079 I915_WRITE(CSIEW1, 0x1e220004);
6080 I915_WRITE(CSIEW2, 0x04000004);
6081
6082 for (i = 0; i < 5; i++)
6083 I915_WRITE(PEW + (i * 4), 0);
6084 for (i = 0; i < 3; i++)
6085 I915_WRITE(DEW + (i * 4), 0);
6086
6087 /* Program P-state weights to account for frequency power adjustment */
6088 for (i = 0; i < 16; i++) {
6089 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6090 unsigned long freq = intel_pxfreq(pxvidfreq);
6091 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6092 PXVFREQ_PX_SHIFT;
6093 unsigned long val;
6094
6095 val = vid * vid;
6096 val *= (freq / 1000);
6097 val *= 255;
6098 val /= (127*127*900);
6099 if (val > 0xff)
6100 DRM_ERROR("bad pxval: %ld\n", val);
6101 pxw[i] = val;
6102 }
6103 /* Render standby states get 0 weight */
6104 pxw[14] = 0;
6105 pxw[15] = 0;
6106
6107 for (i = 0; i < 4; i++) {
6108 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6109 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6110 I915_WRITE(PXW + (i * 4), val);
6111 }
6112
6113 /* Adjust magic regs to magic values (more experimental results) */
6114 I915_WRITE(OGW0, 0);
6115 I915_WRITE(OGW1, 0);
6116 I915_WRITE(EG0, 0x00007f00);
6117 I915_WRITE(EG1, 0x0000000e);
6118 I915_WRITE(EG2, 0x000e0000);
6119 I915_WRITE(EG3, 0x68000300);
6120 I915_WRITE(EG4, 0x42000000);
6121 I915_WRITE(EG5, 0x00140031);
6122 I915_WRITE(EG6, 0);
6123 I915_WRITE(EG7, 0);
6124
6125 for (i = 0; i < 8; i++)
6126 I915_WRITE(PXWL + (i * 4), 0);
6127
6128 /* Enable PMON + select events */
6129 I915_WRITE(ECR, 0x80000019);
6130
6131 lcfuse = I915_READ(LCFUSE02);
6132
20e4d407 6133 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6134}
6135
ae48434c
ID		 6136void intel_init_gt_powersave(struct drm_device *dev)
6137{
e6069ca8
ID		 6138 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6139
38807746
D		 6140 if (IS_CHERRYVIEW(dev))
6141 cherryview_init_gt_powersave(dev);
6142 else if (IS_VALLEYVIEW(dev))
4e80519e 6143 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6144}
6145
6146void intel_cleanup_gt_powersave(struct drm_device *dev)
6147{
38807746
D		 6148 if (IS_CHERRYVIEW(dev))
6149 return;
6150 else if (IS_VALLEYVIEW(dev))
4e80519e 6151 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 6152}
6153
dbea3cea
ID		 6154static void gen6_suspend_rps(struct drm_device *dev)
6155{
6156 struct drm_i915_private *dev_priv = dev->dev_private;
6157
6158 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6159
4c2a8897 6160 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6161}
6162
156c7ca0
JB		 6163/**
6164 * intel_suspend_gt_powersave - suspend PM work and helper threads
6165 * @dev: drm device
6166 *
6167 * We don't want to disable RC6 or other features here, we just want
6168 * to make sure any work we've queued has finished and won't bother
6169 * us while we're suspended.
6170 */
6171void intel_suspend_gt_powersave(struct drm_device *dev)
6172{
6173 struct drm_i915_private *dev_priv = dev->dev_private;
6174
d4d70aa5
ID		 6175 if (INTEL_INFO(dev)->gen < 6)
6176 return;
6177
dbea3cea 6178 gen6_suspend_rps(dev);
b47adc17
D		 6179
6180 /* Force GPU to min freq during suspend */
6181 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6182}
6183
8090c6b9
DV		 6184void intel_disable_gt_powersave(struct drm_device *dev)
6185{
1a01ab3b
JB		 6186 struct drm_i915_private *dev_priv = dev->dev_private;
6187
930ebb46 6188 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6189 ironlake_disable_drps(dev);
38807746 6190 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6191 intel_suspend_gt_powersave(dev);
e494837a 6192
4fc688ce 6193 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6194 if (INTEL_INFO(dev)->gen >= 9)
6195 gen9_disable_rps(dev);
6196 else if (IS_CHERRYVIEW(dev))
38807746
D		 6197 cherryview_disable_rps(dev);
6198 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6199 valleyview_disable_rps(dev);
6200 else
6201 gen6_disable_rps(dev);
e534770a 6202
c0951f0c 6203 dev_priv->rps.enabled = false;
4fc688ce 6204 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6205 }
8090c6b9
DV		 6206}
6207
1a01ab3b
JB		 6208static void intel_gen6_powersave_work(struct work_struct *work)
6209{
6210 struct drm_i915_private *dev_priv =
6211 container_of(work, struct drm_i915_private,
6212 rps.delayed_resume_work.work);
6213 struct drm_device *dev = dev_priv->dev;
6214
4fc688ce 6215 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6216
4c2a8897 6217 gen6_reset_rps_interrupts(dev);
3cc134e3 6218
38807746
D		 6219 if (IS_CHERRYVIEW(dev)) {
6220 cherryview_enable_rps(dev);
6221 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6222 valleyview_enable_rps(dev);
20e49366 6223 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6224 gen9_enable_rc6(dev);
20e49366 6225 gen9_enable_rps(dev);
cc017fb4
AG		 6226 if (IS_SKYLAKE(dev))
6227 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6228 } else if (IS_BROADWELL(dev)) {
6229 gen8_enable_rps(dev);
c2bc2fc5 6230 __gen6_update_ring_freq(dev);
0a073b84
JB		 6231 } else {
6232 gen6_enable_rps(dev);
c2bc2fc5 6233 __gen6_update_ring_freq(dev);
0a073b84 6234 }
aed242ff
CW		 6235
6236 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6237 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6238
6239 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6240 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6241
c0951f0c 6242 dev_priv->rps.enabled = true;
3cc134e3 6243
4c2a8897 6244 gen6_enable_rps_interrupts(dev);
3cc134e3 6245
4fc688ce 6246 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6247
6248 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6249}
6250
8090c6b9
DV		 6251void intel_enable_gt_powersave(struct drm_device *dev)
6252{
1a01ab3b
JB		 6253 struct drm_i915_private *dev_priv = dev->dev_private;
6254
f61018b1
YZ		 6255 /* Powersaving is controlled by the host when inside a VM */
6256 if (intel_vgpu_active(dev))
6257 return;
6258
8090c6b9 6259 if (IS_IRONLAKE_M(dev)) {
dc1d0136 6260 mutex_lock(&dev->struct_mutex);
8090c6b9 6261 ironlake_enable_drps(dev);
8090c6b9 6262 intel_init_emon(dev);
dc1d0136 6263 mutex_unlock(&dev->struct_mutex);
38807746 6264 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6265 /*
6266 * PCU communication is slow and this doesn't need to be
6267 * done at any specific time, so do this out of our fast path
6268 * to make resume and init faster.
c6df39b5
ID		 6269 *
6270 * We depend on the HW RC6 power context save/restore
6271 * mechanism when entering D3 through runtime PM suspend. So
6272 * disable RPM until RPS/RC6 is properly setup. We can only
6273 * get here via the driver load/system resume/runtime resume
6274 * paths, so the _noresume version is enough (and in case of
6275 * runtime resume it's necessary).
1a01ab3b 6276 */
c6df39b5
ID		 6277 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6278 round_jiffies_up_relative(HZ)))
6279 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6280 }
6281}
6282
c6df39b5
ID		 6283void intel_reset_gt_powersave(struct drm_device *dev)
6284{
6285 struct drm_i915_private *dev_priv = dev->dev_private;
6286
dbea3cea
ID		 6287 if (INTEL_INFO(dev)->gen < 6)
6288 return;
6289
6290 gen6_suspend_rps(dev);
c6df39b5 6291 dev_priv->rps.enabled = false;
c6df39b5
ID		 6292}
6293
3107bd48
DV		 6294static void ibx_init_clock_gating(struct drm_device *dev)
6295{
6296 struct drm_i915_private *dev_priv = dev->dev_private;
6297
6298 /*
6299 * On Ibex Peak and Cougar Point, we need to disable clock
6300 * gating for the panel power sequencer or it will fail to
6301 * start up when no ports are active.
6302 */
6303 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6304}
6305
0e088b8f
VS		 6306static void g4x_disable_trickle_feed(struct drm_device *dev)
6307{
6308 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6309 enum pipe pipe;
0e088b8f 6310
055e393f 6311 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6312 I915_WRITE(DSPCNTR(pipe),
6313 I915_READ(DSPCNTR(pipe)) |
6314 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6315
6316 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6317 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6318 }
6319}
6320
017636cc
VS		 6321static void ilk_init_lp_watermarks(struct drm_device *dev)
6322{
6323 struct drm_i915_private *dev_priv = dev->dev_private;
6324
6325 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6326 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6327 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6328
6329 /*
6330 * Don't touch WM1S_LP_EN here.
6331 * Doing so could cause underruns.
6332 */
6333}
6334
1fa61106 6335static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6336{
6337 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6338 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6339
f1e8fa56
DL		 6340 /*
6341 * Required for FBC
6342 * WaFbcDisableDpfcClockGating:ilk
6343 */
4d47e4f5
DL		 6344 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6345 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6346 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6347
6348 I915_WRITE(PCH_3DCGDIS0,
6349 MARIUNIT_CLOCK_GATE_DISABLE |
6350 SVSMUNIT_CLOCK_GATE_DISABLE);
6351 I915_WRITE(PCH_3DCGDIS1,
6352 VFMUNIT_CLOCK_GATE_DISABLE);
6353
6f1d69b0
ED		 6354 /*
6355 * According to the spec the following bits should be set in
6356 * order to enable memory self-refresh
6357 * The bit 22/21 of 0x42004
6358 * The bit 5 of 0x42020
6359 * The bit 15 of 0x45000
6360 */
6361 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6362 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6363 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6364 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6365 I915_WRITE(DISP_ARB_CTL,
6366 (I915_READ(DISP_ARB_CTL) |
6367 DISP_FBC_WM_DIS));
017636cc
VS		 6368
6369 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6370
6371 /*
6372 * Based on the document from hardware guys the following bits
6373 * should be set unconditionally in order to enable FBC.
6374 * The bit 22 of 0x42000
6375 * The bit 22 of 0x42004
6376 * The bit 7,8,9 of 0x42020.
6377 */
6378 if (IS_IRONLAKE_M(dev)) {
4bb35334 6379 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6380 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6381 I915_READ(ILK_DISPLAY_CHICKEN1) |
6382 ILK_FBCQ_DIS);
6383 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6384 I915_READ(ILK_DISPLAY_CHICKEN2) |
6385 ILK_DPARB_GATE);
6f1d69b0
ED		 6386 }
6387
4d47e4f5
DL		 6388 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6389
6f1d69b0
ED		 6390 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6391 I915_READ(ILK_DISPLAY_CHICKEN2) |
6392 ILK_ELPIN_409_SELECT);
6393 I915_WRITE(_3D_CHICKEN2,
6394 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6395 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6396
ecdb4eb7 6397 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6398 I915_WRITE(CACHE_MODE_0,
6399 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6400
4e04632e
AG		 6401 /* WaDisable_RenderCache_OperationalFlush:ilk */
6402 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6403
0e088b8f 6404 g4x_disable_trickle_feed(dev);
bdad2b2f 6405
3107bd48
DV		 6406 ibx_init_clock_gating(dev);
6407}
6408
6409static void cpt_init_clock_gating(struct drm_device *dev)
6410{
6411 struct drm_i915_private *dev_priv = dev->dev_private;
6412 int pipe;
3f704fa2 6413 uint32_t val;
3107bd48
DV		 6414
6415 /*
6416 * On Ibex Peak and Cougar Point, we need to disable clock
6417 * gating for the panel power sequencer or it will fail to
6418 * start up when no ports are active.
6419 */
cd664078
JB		 6420 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6421 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6422 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6423 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6424 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6425 /* The below fixes the weird display corruption, a few pixels shifted
6426 * downward, on (only) LVDS of some HP laptops with IVY.
6427 */
055e393f 6428 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6429 val = I915_READ(TRANS_CHICKEN2(pipe));
6430 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6431 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6432 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6433 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6434 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6435 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6436 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6437 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6438 }
3107bd48 6439 /* WADP0ClockGatingDisable */
055e393f 6440 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6441 I915_WRITE(TRANS_CHICKEN1(pipe),
6442 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6443 }
6f1d69b0
ED		 6444}
6445
1d7aaa0c
DV		 6446static void gen6_check_mch_setup(struct drm_device *dev)
6447{
6448 struct drm_i915_private *dev_priv = dev->dev_private;
6449 uint32_t tmp;
6450
6451 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6452 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6453 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6454 tmp);
1d7aaa0c
DV		 6455}
6456
1fa61106 6457static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6458{
6459 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6460 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6461
231e54f6 6462 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6463
6464 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6465 I915_READ(ILK_DISPLAY_CHICKEN2) |
6466 ILK_ELPIN_409_SELECT);
6467
ecdb4eb7 6468 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6469 I915_WRITE(_3D_CHICKEN,
6470 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6471
4e04632e
AG		 6472 /* WaDisable_RenderCache_OperationalFlush:snb */
6473 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6474
8d85d272
VS		 6475 /*
6476 * BSpec recoomends 8x4 when MSAA is used,
6477 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6478 *
6479 * Note that PS/WM thread counts depend on the WIZ hashing
6480 * disable bit, which we don't touch here, but it's good
6481 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6482 */
6483 I915_WRITE(GEN6_GT_MODE,
98533251 6484 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6485
017636cc 6486 ilk_init_lp_watermarks(dev);
6f1d69b0 6487
6f1d69b0 6488 I915_WRITE(CACHE_MODE_0,
50743298 6489 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6490
6491 I915_WRITE(GEN6_UCGCTL1,
6492 I915_READ(GEN6_UCGCTL1) |
6493 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6494 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6495
6496 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6497 * gating disable must be set. Failure to set it results in
6498 * flickering pixels due to Z write ordering failures after
6499 * some amount of runtime in the Mesa "fire" demo, and Unigine
6500 * Sanctuary and Tropics, and apparently anything else with
6501 * alpha test or pixel discard.
6502 *
6503 * According to the spec, bit 11 (RCCUNIT) must also be set,
6504 * but we didn't debug actual testcases to find it out.
0f846f81 6505 *
ef59318c
VS		 6506 * WaDisableRCCUnitClockGating:snb
6507 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6508 */
6509 I915_WRITE(GEN6_UCGCTL2,
6510 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6511 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6512
5eb146dd 6513 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6514 I915_WRITE(_3D_CHICKEN3,
6515 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6516
e927ecde
VS		 6517 /*
6518 * Bspec says:
6519 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6520 * 3DSTATE_SF number of SF output attributes is more than 16."
6521 */
6522 I915_WRITE(_3D_CHICKEN3,
6523 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6524
6f1d69b0
ED		 6525 /*
6526 * According to the spec the following bits should be
6527 * set in order to enable memory self-refresh and fbc:
6528 * The bit21 and bit22 of 0x42000
6529 * The bit21 and bit22 of 0x42004
6530 * The bit5 and bit7 of 0x42020
6531 * The bit14 of 0x70180
6532 * The bit14 of 0x71180
4bb35334
DL		 6533 *
6534 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6535 */
6536 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6537 I915_READ(ILK_DISPLAY_CHICKEN1) |
6538 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6539 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6540 I915_READ(ILK_DISPLAY_CHICKEN2) |
6541 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6542 I915_WRITE(ILK_DSPCLK_GATE_D,
6543 I915_READ(ILK_DSPCLK_GATE_D) |
6544 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6545 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6546
0e088b8f 6547 g4x_disable_trickle_feed(dev);
f8f2ac9a 6548
3107bd48 6549 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6550
6551 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6552}
6553
6554static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6555{
6556 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6557
3aad9059 6558 /*
46680e0a 6559 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6560 *
6561 * This actually overrides the dispatch
6562 * mode for all thread types.
6563 */
6f1d69b0
ED		 6564 reg &= ~GEN7_FF_SCHED_MASK;
6565 reg |= GEN7_FF_TS_SCHED_HW;
6566 reg |= GEN7_FF_VS_SCHED_HW;
6567 reg |= GEN7_FF_DS_SCHED_HW;
6568
6569 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6570}
6571
17a303ec
PZ		 6572static void lpt_init_clock_gating(struct drm_device *dev)
6573{
6574 struct drm_i915_private *dev_priv = dev->dev_private;
6575
6576 /*
6577 * TODO: this bit should only be enabled when really needed, then
6578 * disabled when not needed anymore in order to save power.
6579 */
6580 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6581 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6582 I915_READ(SOUTH_DSPCLK_GATE_D) |
6583 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6584
6585 /* WADPOClockGatingDisable:hsw */
6586 I915_WRITE(_TRANSA_CHICKEN1,
6587 I915_READ(_TRANSA_CHICKEN1) |
6588 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6589}
6590
7d708ee4
ID		 6591static void lpt_suspend_hw(struct drm_device *dev)
6592{
6593 struct drm_i915_private *dev_priv = dev->dev_private;
6594
6595 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6596 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6597
6598 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6599 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6600 }
6601}
6602
47c2bd97 6603static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6604{
6605 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6606 enum pipe pipe;
4d487cff 6607 uint32_t misccpctl;
1020a5c2 6608
7ad0dbab 6609 ilk_init_lp_watermarks(dev);
50ed5fbd 6610
ab57fff1 6611 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6612 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6613
ab57fff1 6614 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6615 I915_WRITE(CHICKEN_PAR1_1,
6616 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6617
ab57fff1 6618 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6619 for_each_pipe(dev_priv, pipe) {
07d27e20 6620 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6621 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6622 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6623 }
63801f21 6624
ab57fff1
BW		 6625 /* WaVSRefCountFullforceMissDisable:bdw */
6626 /* WaDSRefCountFullforceMissDisable:bdw */
6627 I915_WRITE(GEN7_FF_THREAD_MODE,
6628 I915_READ(GEN7_FF_THREAD_MODE) &
6629 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6630
295e8bb7
VS		 6631 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6632 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6633
6634 /* WaDisableSDEUnitClockGating:bdw */
6635 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6636 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6637
4d487cff
VS		 6638 /*
6639 * WaProgramL3SqcReg1Default:bdw
6640 * WaTempDisableDOPClkGating:bdw
6641 */
6642 misccpctl = I915_READ(GEN7_MISCCPCTL);
6643 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6644 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6645 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6646
6d50b065
VS		 6647 /*
6648 * WaGttCachingOffByDefault:bdw
6649 * GTT cache may not work with big pages, so if those
6650 * are ever enabled GTT cache may need to be disabled.
6651 */
6652 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6653
89d6b2b8 6654 lpt_init_clock_gating(dev);
1020a5c2
BW		 6655}
6656
cad2a2d7
ED		 6657static void haswell_init_clock_gating(struct drm_device *dev)
6658{
6659 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6660
017636cc 6661 ilk_init_lp_watermarks(dev);
cad2a2d7 6662
f3fc4884
FJ		 6663 /* L3 caching of data atomics doesn't work -- disable it. */
6664 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6665 I915_WRITE(HSW_ROW_CHICKEN3,
6666 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6667
ecdb4eb7 6668 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6669 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6670 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6671 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6672
e36ea7ff
VS		 6673 /* WaVSRefCountFullforceMissDisable:hsw */
6674 I915_WRITE(GEN7_FF_THREAD_MODE,
6675 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6676
4e04632e
AG		 6677 /* WaDisable_RenderCache_OperationalFlush:hsw */
6678 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6679
fe27c606
CW		 6680 /* enable HiZ Raw Stall Optimization */
6681 I915_WRITE(CACHE_MODE_0_GEN7,
6682 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6683
ecdb4eb7 6684 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6685 I915_WRITE(CACHE_MODE_1,
6686 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6687
a12c4967
VS		 6688 /*
6689 * BSpec recommends 8x4 when MSAA is used,
6690 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6691 *
6692 * Note that PS/WM thread counts depend on the WIZ hashing
6693 * disable bit, which we don't touch here, but it's good
6694 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6695 */
6696 I915_WRITE(GEN7_GT_MODE,
98533251 6697 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6698
94411593
KG		 6699 /* WaSampleCChickenBitEnable:hsw */
6700 I915_WRITE(HALF_SLICE_CHICKEN3,
6701 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6702
ecdb4eb7 6703 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6704 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6705
90a88643
PZ		 6706 /* WaRsPkgCStateDisplayPMReq:hsw */
6707 I915_WRITE(CHICKEN_PAR1_1,
6708 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6709
17a303ec 6710 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6711}
6712
1fa61106 6713static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6714{
6715 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6716 uint32_t snpcr;
6f1d69b0 6717
017636cc 6718 ilk_init_lp_watermarks(dev);
6f1d69b0 6719
231e54f6 6720 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6721
ecdb4eb7 6722 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6723 I915_WRITE(_3D_CHICKEN3,
6724 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6725
ecdb4eb7 6726 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6727 I915_WRITE(IVB_CHICKEN3,
6728 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6729 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6730
ecdb4eb7 6731 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6732 if (IS_IVB_GT1(dev))
6733 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6734 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6735
4e04632e
AG		 6736 /* WaDisable_RenderCache_OperationalFlush:ivb */
6737 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6738
ecdb4eb7 6739 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6740 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6741 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6742
ecdb4eb7 6743 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6744 I915_WRITE(GEN7_L3CNTLREG1,
6745 GEN7_WA_FOR_GEN7_L3_CONTROL);
6746 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6747 GEN7_WA_L3_CHICKEN_MODE);
6748 if (IS_IVB_GT1(dev))
6749 I915_WRITE(GEN7_ROW_CHICKEN2,
6750 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6751 else {
6752 /* must write both registers */
6753 I915_WRITE(GEN7_ROW_CHICKEN2,
6754 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6755 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6756 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6757 }
6f1d69b0 6758
ecdb4eb7 6759 /* WaForceL3Serialization:ivb */
61939d97
JB		 6760 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6761 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6762
1b80a19a 6763 /*
0f846f81 6764 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6765 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6766 */
6767 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6768 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6769
ecdb4eb7 6770 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6771 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6772 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6773 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6774
0e088b8f 6775 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6776
6777 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6778
22721343
CW		 6779 if (0) { /* causes HiZ corruption on ivb:gt1 */
6780 /* enable HiZ Raw Stall Optimization */
6781 I915_WRITE(CACHE_MODE_0_GEN7,
6782 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6783 }
116f2b6d 6784
ecdb4eb7 6785 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6786 I915_WRITE(CACHE_MODE_1,
6787 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6788
a607c1a4
VS		 6789 /*
6790 * BSpec recommends 8x4 when MSAA is used,
6791 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6792 *
6793 * Note that PS/WM thread counts depend on the WIZ hashing
6794 * disable bit, which we don't touch here, but it's good
6795 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6796 */
6797 I915_WRITE(GEN7_GT_MODE,
98533251 6798 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6799
20848223
BW		 6800 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6801 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6802 snpcr |= GEN6_MBC_SNPCR_MED;
6803 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6804
ab5c608b
BW		 6805 if (!HAS_PCH_NOP(dev))
6806 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6807
6808 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6809}
6810
c6beb13e
VS		 6811static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6812{
6813 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6814
6815 /*
6816 * Disable trickle feed and enable pnd deadline calculation
6817 */
6818 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6819 I915_WRITE(CBR1_VLV, 0);
6820}
6821
1fa61106 6822static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6823{
6824 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6825
c6beb13e 6826 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6827
ecdb4eb7 6828 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6829 I915_WRITE(_3D_CHICKEN3,
6830 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6831
ecdb4eb7 6832 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6833 I915_WRITE(IVB_CHICKEN3,
6834 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6835 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6836
fad7d36e 6837 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6838 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6839 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6840 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6841 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6842
4e04632e
AG		 6843 /* WaDisable_RenderCache_OperationalFlush:vlv */
6844 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6845
ecdb4eb7 6846 /* WaForceL3Serialization:vlv */
61939d97
JB		 6847 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6848 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6849
ecdb4eb7 6850 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6851 I915_WRITE(GEN7_ROW_CHICKEN2,
6852 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6853
ecdb4eb7 6854 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6855 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6856 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6857 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6858
46680e0a
VS		 6859 gen7_setup_fixed_func_scheduler(dev_priv);
6860
3c0edaeb 6861 /*
0f846f81 6862 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6863 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6864 */
6865 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6866 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6867
c98f5062
AG		 6868 /* WaDisableL3Bank2xClockGate:vlv
6869 * Disabling L3 clock gating- MMIO 940c[25] = 1
6870 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6871 I915_WRITE(GEN7_UCGCTL4,
6872 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6873
afd58e79
VS		 6874 /*
6875 * BSpec says this must be set, even though
6876 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6877 */
6b26c86d
DV		 6878 I915_WRITE(CACHE_MODE_1,
6879 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6880
da2518f9
VS		 6881 /*
6882 * BSpec recommends 8x4 when MSAA is used,
6883 * however in practice 16x4 seems fastest.
6884 *
6885 * Note that PS/WM thread counts depend on the WIZ hashing
6886 * disable bit, which we don't touch here, but it's good
6887 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6888 */
6889 I915_WRITE(GEN7_GT_MODE,
6890 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6891
031994ee
VS		 6892 /*
6893 * WaIncreaseL3CreditsForVLVB0:vlv
6894 * This is the hardware default actually.
6895 */
6896 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6897
2d809570 6898 /*
ecdb4eb7 6899 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6900 * Disable clock gating on th GCFG unit to prevent a delay
6901 * in the reporting of vblank events.
6902 */
7a0d1eed 6903 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6904}
6905
a4565da8
VS		 6906static void cherryview_init_clock_gating(struct drm_device *dev)
6907{
6908 struct drm_i915_private *dev_priv = dev->dev_private;
6909
c6beb13e 6910 vlv_init_display_clock_gating(dev_priv);
dd811e70 6911
232ce337
VS		 6912 /* WaVSRefCountFullforceMissDisable:chv */
6913 /* WaDSRefCountFullforceMissDisable:chv */
6914 I915_WRITE(GEN7_FF_THREAD_MODE,
6915 I915_READ(GEN7_FF_THREAD_MODE) &
6916 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6917
6918 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6919 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6920 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6921
6922 /* WaDisableCSUnitClockGating:chv */
6923 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6924 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6925
6926 /* WaDisableSDEUnitClockGating:chv */
6927 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6928 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 6929
6930 /*
6931 * GTT cache may not work with big pages, so if those
6932 * are ever enabled GTT cache may need to be disabled.
6933 */
6934 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 6935}
6936
1fa61106 6937static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6938{
6939 struct drm_i915_private *dev_priv = dev->dev_private;
6940 uint32_t dspclk_gate;
6941
6942 I915_WRITE(RENCLK_GATE_D1, 0);
6943 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6944 GS_UNIT_CLOCK_GATE_DISABLE |
6945 CL_UNIT_CLOCK_GATE_DISABLE);
6946 I915_WRITE(RAMCLK_GATE_D, 0);
6947 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6948 OVRUNIT_CLOCK_GATE_DISABLE |
6949 OVCUNIT_CLOCK_GATE_DISABLE;
6950 if (IS_GM45(dev))
6951 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6952 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6953
6954 /* WaDisableRenderCachePipelinedFlush */
6955 I915_WRITE(CACHE_MODE_0,
6956 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6957
4e04632e
AG		 6958 /* WaDisable_RenderCache_OperationalFlush:g4x */
6959 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6960
0e088b8f 6961 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6962}
6963
1fa61106 6964static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6965{
6966 struct drm_i915_private *dev_priv = dev->dev_private;
6967
6968 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6969 I915_WRITE(RENCLK_GATE_D2, 0);
6970 I915_WRITE(DSPCLK_GATE_D, 0);
6971 I915_WRITE(RAMCLK_GATE_D, 0);
6972 I915_WRITE16(DEUC, 0);
20f94967
VS		 6973 I915_WRITE(MI_ARB_STATE,
6974 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6975
6976 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6977 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6978}
6979
1fa61106 6980static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6981{
6982 struct drm_i915_private *dev_priv = dev->dev_private;
6983
6984 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6985 I965_RCC_CLOCK_GATE_DISABLE |
6986 I965_RCPB_CLOCK_GATE_DISABLE |
6987 I965_ISC_CLOCK_GATE_DISABLE |
6988 I965_FBC_CLOCK_GATE_DISABLE);
6989 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6990 I915_WRITE(MI_ARB_STATE,
6991 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6992
6993 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6994 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6995}
6996
1fa61106 6997static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6998{
6999 struct drm_i915_private *dev_priv = dev->dev_private;
7000 u32 dstate = I915_READ(D_STATE);
7001
7002 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7003 DSTATE_DOT_CLOCK_GATING;
7004 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7005
7006 if (IS_PINEVIEW(dev))
7007 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7008
7009 /* IIR "flip pending" means done if this bit is set */
7010 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7011
7012 /* interrupts should cause a wake up from C3 */
3299254f 7013 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7014
7015 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7016 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7017
7018 I915_WRITE(MI_ARB_STATE,
7019 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7020}
7021
1fa61106 7022static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7023{
7024 struct drm_i915_private *dev_priv = dev->dev_private;
7025
7026 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7027
7028 /* interrupts should cause a wake up from C3 */
7029 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7030 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7031
7032 I915_WRITE(MEM_MODE,
7033 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7034}
7035
1fa61106 7036static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7037{
7038 struct drm_i915_private *dev_priv = dev->dev_private;
7039
7040 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7041
7042 I915_WRITE(MEM_MODE,
7043 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7044 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7045}
7046
6f1d69b0
ED		 7047void intel_init_clock_gating(struct drm_device *dev)
7048{
7049 struct drm_i915_private *dev_priv = dev->dev_private;
7050
c57e3551
DL		 7051 if (dev_priv->display.init_clock_gating)
7052 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7053}
7054
7d708ee4
ID		 7055void intel_suspend_hw(struct drm_device *dev)
7056{
7057 if (HAS_PCH_LPT(dev))
7058 lpt_suspend_hw(dev);
7059}
7060
1fa61106
ED		 7061/* Set up chip specific power management-related functions */
7062void intel_init_pm(struct drm_device *dev)
7063{
7064 struct drm_i915_private *dev_priv = dev->dev_private;
7065
7ff0ebcc 7066 intel_fbc_init(dev_priv);
1fa61106 7067
c921aba8
DV		 7068 /* For cxsr */
7069 if (IS_PINEVIEW(dev))
7070 i915_pineview_get_mem_freq(dev);
7071 else if (IS_GEN5(dev))
7072 i915_ironlake_get_mem_freq(dev);
7073
1fa61106 7074 /* For FIFO watermark updates */
f5ed50cb 7075 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 7076 skl_setup_wm_latency(dev);
7077
a82abe43
ID		 7078 if (IS_BROXTON(dev))
7079 dev_priv->display.init_clock_gating =
7080 bxt_init_clock_gating;
7081 else if (IS_SKYLAKE(dev))
7082 dev_priv->display.init_clock_gating =
7083 skl_init_clock_gating;
2d41c0b5
PB		 7084 dev_priv->display.update_wm = skl_update_wm;
7085 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 7086 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7087 ilk_setup_wm_latency(dev);
53615a5e 7088
bd602544
VS		 7089 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7090 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7091 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7092 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7093 dev_priv->display.update_wm = ilk_update_wm;
7094 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7095 } else {
7096 DRM_DEBUG_KMS("Failed to read display plane latency. "
7097 "Disable CxSR\n");
7098 }
7099
7100 if (IS_GEN5(dev))
1fa61106 7101 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7102 else if (IS_GEN6(dev))
1fa61106 7103 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7104 else if (IS_IVYBRIDGE(dev))
1fa61106 7105 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7106 else if (IS_HASWELL(dev))
cad2a2d7 7107 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7108 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 7109 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 7110 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 7111 vlv_setup_wm_latency(dev);
7112
7113 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 7114 dev_priv->display.init_clock_gating =
7115 cherryview_init_clock_gating;
1fa61106 7116 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 7117 vlv_setup_wm_latency(dev);
7118
7119 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7120 dev_priv->display.init_clock_gating =
7121 valleyview_init_clock_gating;
1fa61106
ED		 7122 } else if (IS_PINEVIEW(dev)) {
7123 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7124 dev_priv->is_ddr3,
7125 dev_priv->fsb_freq,
7126 dev_priv->mem_freq)) {
7127 DRM_INFO("failed to find known CxSR latency "
7128 "(found ddr%s fsb freq %d, mem freq %d), "
7129 "disabling CxSR\n",
7130 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7131 dev_priv->fsb_freq, dev_priv->mem_freq);
7132 /* Disable CxSR and never update its watermark again */
5209b1f4 7133 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7134 dev_priv->display.update_wm = NULL;
7135 } else
7136 dev_priv->display.update_wm = pineview_update_wm;
7137 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7138 } else if (IS_G4X(dev)) {
7139 dev_priv->display.update_wm = g4x_update_wm;
7140 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7141 } else if (IS_GEN4(dev)) {
7142 dev_priv->display.update_wm = i965_update_wm;
7143 if (IS_CRESTLINE(dev))
7144 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7145 else if (IS_BROADWATER(dev))
7146 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7147 } else if (IS_GEN3(dev)) {
7148 dev_priv->display.update_wm = i9xx_update_wm;
7149 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7150 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7151 } else if (IS_GEN2(dev)) {
7152 if (INTEL_INFO(dev)->num_pipes == 1) {
7153 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7154 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7155 } else {
7156 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7157 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7158 }
7159
7160 if (IS_I85X(dev) || IS_I865G(dev))
7161 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7162 else
7163 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7164 } else {
7165 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7166 }
7167}
7168
151a49d0 7169int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7170{
4fc688ce 7171 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7172
7173 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7174 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7175 return -EAGAIN;
7176 }
7177
7178 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7179 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7180 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7181
7182 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7183 500)) {
7184 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7185 return -ETIMEDOUT;
7186 }
7187
7188 *val = I915_READ(GEN6_PCODE_DATA);
7189 I915_WRITE(GEN6_PCODE_DATA, 0);
7190
7191 return 0;
7192}
7193
151a49d0 7194int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7195{
4fc688ce 7196 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7197
7198 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7199 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7200 return -EAGAIN;
7201 }
7202
7203 I915_WRITE(GEN6_PCODE_DATA, val);
7204 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7205
7206 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7207 500)) {
7208 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7209 return -ETIMEDOUT;
7210 }
7211
7212 I915_WRITE(GEN6_PCODE_DATA, 0);
7213
7214 return 0;
7215}
a0e4e199 7216
dd06f88c 7217static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7218{
dd06f88c
VS		 7219 switch (czclk_freq) {
7220 case 200:
7221 return 10;
7222 case 267:
7223 return 12;
7224 case 320:
7225 case 333:
dd06f88c 7226 return 16;
ab3fb157
VS		 7227 case 400:
7228 return 20;
855ba3be
JB		 7229 default:
7230 return -1;
7231 }
dd06f88c 7232}
855ba3be 7233
dd06f88c
VS		 7234static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7235{
7236 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7237
7238 div = vlv_gpu_freq_div(czclk_freq);
7239 if (div < 0)
7240 return div;
7241
7242 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7243}
7244
b55dd647 7245static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7246{
dd06f88c 7247 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
855ba3be 7248
dd06f88c
VS		 7249 mul = vlv_gpu_freq_div(czclk_freq);
7250 if (mul < 0)
7251 return mul;
855ba3be 7252
dd06f88c 7253 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7254}
7255
b55dd647 7256static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7257{
dd06f88c 7258 int div, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 7259
dd06f88c
VS		 7260 div = vlv_gpu_freq_div(czclk_freq) / 2;
7261 if (div < 0)
7262 return div;
22b1b2f8 7263
dd06f88c 7264 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7265}
7266
b55dd647 7267static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7268{
dd06f88c 7269 int mul, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 7270
dd06f88c
VS		 7271 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7272 if (mul < 0)
7273 return mul;
22b1b2f8 7274
1c14762d 7275 /* CHV needs even values */
dd06f88c 7276 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7277}
7278
616bc820 7279int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7280{
80b6dda4
AG		 7281 if (IS_GEN9(dev_priv->dev))
7282 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7283 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7284 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7285 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7286 return byt_gpu_freq(dev_priv, val);
7287 else
7288 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7289}
7290
616bc820
VS		 7291int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7292{
80b6dda4
AG		 7293 if (IS_GEN9(dev_priv->dev))
7294 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7295 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7296 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7297 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7298 return byt_freq_opcode(dev_priv, val);
7299 else
7300 return val / GT_FREQUENCY_MULTIPLIER;
7301}
22b1b2f8 7302
6ad790c0
CW		 7303struct request_boost {
7304 struct work_struct work;
eed29a5b 7305 struct drm_i915_gem_request *req;
6ad790c0
CW		 7306};
7307
7308static void __intel_rps_boost_work(struct work_struct *work)
7309{
7310 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7311 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7312
e61b9958
CW		 7313 if (!i915_gem_request_completed(req, true))
7314 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7315 req->emitted_jiffies);
6ad790c0 7316
e61b9958 7317 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7318 kfree(boost);
7319}
7320
7321void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7322 struct drm_i915_gem_request *req)
6ad790c0
CW		 7323{
7324 struct request_boost *boost;
7325
eed29a5b 7326 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7327 return;
7328
e61b9958
CW		 7329 if (i915_gem_request_completed(req, true))
7330 return;
7331
6ad790c0
CW		 7332 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7333 if (boost == NULL)
7334 return;
7335
eed29a5b
DV		 7336 i915_gem_request_reference(req);
7337 boost->req = req;
6ad790c0
CW		 7338
7339 INIT_WORK(&boost->work, __intel_rps_boost_work);
7340 queue_work(to_i915(dev)->wq, &boost->work);
7341}
7342
f742a552 7343void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7344{
7345 struct drm_i915_private *dev_priv = dev->dev_private;
7346
f742a552 7347 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7348 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7349
907b28c5
CW		 7350 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7351 intel_gen6_powersave_work);
1854d5ca 7352 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7353 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7354 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7355
33688d95 7356 dev_priv->pm.suspended = false;
907b28c5 7357}
Linux kernel - Deliverables
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