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drm/i915: Add chv port B and C TX wells
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f9dcb0df 33#include <linux/vgaarb.h>
f4db9321 34#include <drm/i915_powerwell.h>
8a187455 35#include <linux/pm_runtime.h>
85208be0 36
dc39fff7
BW		 37/**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
f6750b3c
ED		 58/* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 61 *
f6750b3c
ED		 62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
85208be0 64 *
f6750b3c
ED		 65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
85208be0
ED		 67 */
68
1fa61106 69static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89}
90
993495ae 91static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 92{
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 95 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 96 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0
ED		 97 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
98 int cfb_pitch;
7f2cf220 99 int i;
159f9875 100 u32 fbc_ctl;
85208be0 101
5c3fe8b0 102 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 103 if (fb->pitches[0] < cfb_pitch)
104 cfb_pitch = fb->pitches[0];
105
42a430f5
VS		 106 /* FBC_CTL wants 32B or 64B units */
107 if (IS_GEN2(dev))
108 cfb_pitch = (cfb_pitch / 32) - 1;
109 else
110 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 111
112 /* Clear old tags */
113 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
114 I915_WRITE(FBC_TAG + (i * 4), 0);
115
159f9875
VS		 116 if (IS_GEN4(dev)) {
117 u32 fbc_ctl2;
118
119 /* Set it up... */
120 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
7f2cf220 121 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
159f9875
VS		 122 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
123 I915_WRITE(FBC_FENCE_OFF, crtc->y);
124 }
85208be0
ED		 125
126 /* enable it... */
993495ae
VS		 127 fbc_ctl = I915_READ(FBC_CONTROL);
128 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
129 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 130 if (IS_I945GM(dev))
131 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
132 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 133 fbc_ctl |= obj->fence_reg;
134 I915_WRITE(FBC_CONTROL, fbc_ctl);
135
5cd5410e 136 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
84f44ce7 137 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 138}
139
1fa61106 140static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
145}
146
993495ae 147static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 148{
149 struct drm_device *dev = crtc->dev;
150 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 151 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 152 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0 153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 154 u32 dpfc_ctl;
155
3fa2e0ee
VS		 156 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
157 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
158 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
159 else
160 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
85208be0 161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
85208be0 162
85208be0
ED		 163 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
164
165 /* enable it... */
fe74c1a5 166 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
85208be0 167
84f44ce7 168 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 169}
170
1fa61106 171static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 172{
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 u32 dpfc_ctl;
175
176 /* Disable compression */
177 dpfc_ctl = I915_READ(DPFC_CONTROL);
178 if (dpfc_ctl & DPFC_CTL_EN) {
179 dpfc_ctl &= ~DPFC_CTL_EN;
180 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
181
182 DRM_DEBUG_KMS("disabled FBC\n");
183 }
184}
185
1fa61106 186static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 187{
188 struct drm_i915_private *dev_priv = dev->dev_private;
189
190 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
191}
192
193static void sandybridge_blit_fbc_update(struct drm_device *dev)
194{
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 u32 blt_ecoskpd;
197
198 /* Make sure blitter notifies FBC of writes */
940aece4
D		 199
200 /* Blitter is part of Media powerwell on VLV. No impact of
201 * his param in other platforms for now */
202 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 203
85208be0
ED		 204 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
205 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
206 GEN6_BLITTER_LOCK_SHIFT;
207 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
208 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
211 GEN6_BLITTER_LOCK_SHIFT);
212 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
213 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 214
940aece4 215 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 216}
217
993495ae 218static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 219{
220 struct drm_device *dev = crtc->dev;
221 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 222 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 223 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0 224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 225 u32 dpfc_ctl;
226
46f3dab9 227 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
3fa2e0ee 228 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
5e59f717
BW		 229 dev_priv->fbc.threshold++;
230
231 switch (dev_priv->fbc.threshold) {
232 case 4:
233 case 3:
234 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
235 break;
236 case 2:
3fa2e0ee 237 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
5e59f717
BW		 238 break;
239 case 1:
3fa2e0ee 240 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
5e59f717
BW		 241 break;
242 }
d629336b
VS		 243 dpfc_ctl |= DPFC_CTL_FENCE_EN;
244 if (IS_GEN5(dev))
245 dpfc_ctl |= obj->fence_reg;
85208be0 246
85208be0 247 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 248 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 249 /* enable it... */
250 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
251
252 if (IS_GEN6(dev)) {
253 I915_WRITE(SNB_DPFC_CTL_SA,
254 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
255 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
256 sandybridge_blit_fbc_update(dev);
257 }
258
84f44ce7 259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 260}
261
1fa61106 262static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 263{
264 struct drm_i915_private *dev_priv = dev->dev_private;
265 u32 dpfc_ctl;
266
267 /* Disable compression */
268 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
269 if (dpfc_ctl & DPFC_CTL_EN) {
270 dpfc_ctl &= ~DPFC_CTL_EN;
271 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
272
273 DRM_DEBUG_KMS("disabled FBC\n");
274 }
275}
276
1fa61106 277static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 278{
279 struct drm_i915_private *dev_priv = dev->dev_private;
280
281 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
282}
283
993495ae 284static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 285{
286 struct drm_device *dev = crtc->dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 288 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 289 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
abe959c7 290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3fa2e0ee 291 u32 dpfc_ctl;
abe959c7 292
3fa2e0ee
VS		 293 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
294 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
5e59f717
BW		 295 dev_priv->fbc.threshold++;
296
297 switch (dev_priv->fbc.threshold) {
298 case 4:
299 case 3:
300 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
301 break;
302 case 2:
3fa2e0ee 303 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
5e59f717
BW		 304 break;
305 case 1:
3fa2e0ee 306 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
5e59f717
BW		 307 break;
308 }
309
3fa2e0ee
VS		 310 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
311
312 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
abe959c7 313
891348b2 314 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 315 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
2adb6db8
VS		 316 I915_WRITE(ILK_DISPLAY_CHICKEN1,
317 I915_READ(ILK_DISPLAY_CHICKEN1) |
318 ILK_FBCQ_DIS);
28554164 319 } else {
2adb6db8 320 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
8f670bb1
VS		 321 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
322 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
323 HSW_FBCQ_DIS);
891348b2 324 }
b74ea102 325
abe959c7
RV		 326 I915_WRITE(SNB_DPFC_CTL_SA,
327 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
328 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
329
330 sandybridge_blit_fbc_update(dev);
331
b19870ee 332 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 333}
334
85208be0
ED		 335bool intel_fbc_enabled(struct drm_device *dev)
336{
337 struct drm_i915_private *dev_priv = dev->dev_private;
338
339 if (!dev_priv->display.fbc_enabled)
340 return false;
341
342 return dev_priv->display.fbc_enabled(dev);
343}
344
345static void intel_fbc_work_fn(struct work_struct *__work)
346{
347 struct intel_fbc_work *work =
348 container_of(to_delayed_work(__work),
349 struct intel_fbc_work, work);
350 struct drm_device *dev = work->crtc->dev;
351 struct drm_i915_private *dev_priv = dev->dev_private;
352
353 mutex_lock(&dev->struct_mutex);
5c3fe8b0 354 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 355 /* Double check that we haven't switched fb without cancelling
356 * the prior work.
357 */
f4510a27 358 if (work->crtc->primary->fb == work->fb) {
993495ae 359 dev_priv->display.enable_fbc(work->crtc);
85208be0 360
5c3fe8b0 361 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
f4510a27 362 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
5c3fe8b0 363 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 364 }
365
5c3fe8b0 366 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 367 }
368 mutex_unlock(&dev->struct_mutex);
369
370 kfree(work);
371}
372
373static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
374{
5c3fe8b0 375 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 376 return;
377
378 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
379
380 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 381 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 382 * entirely asynchronously.
383 */
5c3fe8b0 384 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 385 /* tasklet was killed before being run, clean up */
5c3fe8b0 386 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 387
388 /* Mark the work as no longer wanted so that if it does
389 * wake-up (because the work was already running and waiting
390 * for our mutex), it will discover that is no longer
391 * necessary to run.
392 */
5c3fe8b0 393 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 394}
395
993495ae 396static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 397{
398 struct intel_fbc_work *work;
399 struct drm_device *dev = crtc->dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401
402 if (!dev_priv->display.enable_fbc)
403 return;
404
405 intel_cancel_fbc_work(dev_priv);
406
b14c5679 407 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 408 if (work == NULL) {
6cdcb5e7 409 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 410 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 411 return;
412 }
413
414 work->crtc = crtc;
f4510a27 415 work->fb = crtc->primary->fb;
85208be0
ED		 416 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
417
5c3fe8b0 418 dev_priv->fbc.fbc_work = work;
85208be0 419
85208be0
ED		 420 /* Delay the actual enabling to let pageflipping cease and the
421 * display to settle before starting the compression. Note that
422 * this delay also serves a second purpose: it allows for a
423 * vblank to pass after disabling the FBC before we attempt
424 * to modify the control registers.
425 *
426 * A more complicated solution would involve tracking vblanks
427 * following the termination of the page-flipping sequence
428 * and indeed performing the enable as a co-routine and not
429 * waiting synchronously upon the vblank.
7457d617
DL		 430 *
431 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 432 */
433 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
434}
435
436void intel_disable_fbc(struct drm_device *dev)
437{
438 struct drm_i915_private *dev_priv = dev->dev_private;
439
440 intel_cancel_fbc_work(dev_priv);
441
442 if (!dev_priv->display.disable_fbc)
443 return;
444
445 dev_priv->display.disable_fbc(dev);
5c3fe8b0 446 dev_priv->fbc.plane = -1;
85208be0
ED		 447}
448
29ebf90f
CW		 449static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
450 enum no_fbc_reason reason)
451{
452 if (dev_priv->fbc.no_fbc_reason == reason)
453 return false;
454
455 dev_priv->fbc.no_fbc_reason = reason;
456 return true;
457}
458
85208be0
ED		 459/**
460 * intel_update_fbc - enable/disable FBC as needed
461 * @dev: the drm_device
462 *
463 * Set up the framebuffer compression hardware at mode set time. We
464 * enable it if possible:
465 * - plane A only (on pre-965)
466 * - no pixel mulitply/line duplication
467 * - no alpha buffer discard
468 * - no dual wide
f85da868 469 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 470 *
471 * We can't assume that any compression will take place (worst case),
472 * so the compressed buffer has to be the same size as the uncompressed
473 * one. It also must reside (along with the line length buffer) in
474 * stolen memory.
475 *
476 * We need to enable/disable FBC on a global basis.
477 */
478void intel_update_fbc(struct drm_device *dev)
479{
480 struct drm_i915_private *dev_priv = dev->dev_private;
481 struct drm_crtc *crtc = NULL, *tmp_crtc;
482 struct intel_crtc *intel_crtc;
483 struct drm_framebuffer *fb;
85208be0 484 struct drm_i915_gem_object *obj;
ef644fda 485 const struct drm_display_mode *adjusted_mode;
37327abd 486 unsigned int max_width, max_height;
85208be0 487
3a77c4c4 488 if (!HAS_FBC(dev)) {
29ebf90f 489 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 490 return;
29ebf90f 491 }
85208be0 492
d330a953 493 if (!i915.powersave) {
29ebf90f
CW		 494 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
495 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 496 return;
29ebf90f 497 }
85208be0
ED		 498
499 /*
500 * If FBC is already on, we just have to verify that we can
501 * keep it that way...
502 * Need to disable if:
503 * - more than one pipe is active
504 * - changing FBC params (stride, fence, mode)
505 * - new fb is too large to fit in compressed buffer
506 * - going to an unsupported config (interlace, pixel multiply, etc.)
507 */
70e1e0ec 508 for_each_crtc(dev, tmp_crtc) {
3490ea5d 509 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 510 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 511 if (crtc) {
29ebf90f
CW		 512 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
513 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 514 goto out_disable;
515 }
516 crtc = tmp_crtc;
517 }
518 }
519
f4510a27 520 if (!crtc || crtc->primary->fb == NULL) {
29ebf90f
CW		 521 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
522 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 523 goto out_disable;
524 }
525
526 intel_crtc = to_intel_crtc(crtc);
f4510a27 527 fb = crtc->primary->fb;
2ff8fde1 528 obj = intel_fb_obj(fb);
ef644fda 529 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 530
0368920e 531 if (i915.enable_fbc < 0) {
29ebf90f
CW		 532 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
533 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 534 goto out_disable;
85208be0 535 }
d330a953 536 if (!i915.enable_fbc) {
29ebf90f
CW		 537 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
538 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 539 goto out_disable;
540 }
ef644fda
VS		 541 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
542 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 543 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
544 DRM_DEBUG_KMS("mode incompatible with compression, "
545 "disabling\n");
85208be0
ED		 546 goto out_disable;
547 }
f85da868 548
032843a5
DS		 549 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
550 max_width = 4096;
551 max_height = 4096;
552 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 553 max_width = 4096;
554 max_height = 2048;
f85da868 555 } else {
37327abd
VS		 556 max_width = 2048;
557 max_height = 1536;
f85da868 558 }
37327abd
VS		 559 if (intel_crtc->config.pipe_src_w > max_width ||
560 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 561 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
562 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 563 goto out_disable;
564 }
8f94d24b 565 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
c5a44aa0 566 intel_crtc->plane != PLANE_A) {
29ebf90f 567 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 568 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 569 goto out_disable;
570 }
571
572 /* The use of a CPU fence is mandatory in order to detect writes
573 * by the CPU to the scanout and trigger updates to the FBC.
574 */
575 if (obj->tiling_mode != I915_TILING_X ||
576 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 577 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
578 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 579 goto out_disable;
580 }
581
582 /* If the kernel debugger is active, always disable compression */
583 if (in_dbg_master())
584 goto out_disable;
585
2ff8fde1 586 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
5e59f717 587 drm_format_plane_cpp(fb->pixel_format, 0))) {
29ebf90f
CW		 588 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
589 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 590 goto out_disable;
591 }
592
85208be0
ED		 593 /* If the scanout has not changed, don't modify the FBC settings.
594 * Note that we make the fundamental assumption that the fb->obj
595 * cannot be unpinned (and have its GTT offset and fence revoked)
596 * without first being decoupled from the scanout and FBC disabled.
597 */
5c3fe8b0
BW		 598 if (dev_priv->fbc.plane == intel_crtc->plane &&
599 dev_priv->fbc.fb_id == fb->base.id &&
600 dev_priv->fbc.y == crtc->y)
85208be0
ED		 601 return;
602
603 if (intel_fbc_enabled(dev)) {
604 /* We update FBC along two paths, after changing fb/crtc
605 * configuration (modeswitching) and after page-flipping
606 * finishes. For the latter, we know that not only did
607 * we disable the FBC at the start of the page-flip
608 * sequence, but also more than one vblank has passed.
609 *
610 * For the former case of modeswitching, it is possible
611 * to switch between two FBC valid configurations
612 * instantaneously so we do need to disable the FBC
613 * before we can modify its control registers. We also
614 * have to wait for the next vblank for that to take
615 * effect. However, since we delay enabling FBC we can
616 * assume that a vblank has passed since disabling and
617 * that we can safely alter the registers in the deferred
618 * callback.
619 *
620 * In the scenario that we go from a valid to invalid
621 * and then back to valid FBC configuration we have
622 * no strict enforcement that a vblank occurred since
623 * disabling the FBC. However, along all current pipe
624 * disabling paths we do need to wait for a vblank at
625 * some point. And we wait before enabling FBC anyway.
626 */
627 DRM_DEBUG_KMS("disabling active FBC for update\n");
628 intel_disable_fbc(dev);
629 }
630
993495ae 631 intel_enable_fbc(crtc);
29ebf90f 632 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 633 return;
634
635out_disable:
636 /* Multiple disables should be harmless */
637 if (intel_fbc_enabled(dev)) {
638 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
639 intel_disable_fbc(dev);
640 }
11be49eb 641 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 642}
643
c921aba8
DV		 644static void i915_pineview_get_mem_freq(struct drm_device *dev)
645{
50227e1c 646 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 647 u32 tmp;
648
649 tmp = I915_READ(CLKCFG);
650
651 switch (tmp & CLKCFG_FSB_MASK) {
652 case CLKCFG_FSB_533:
653 dev_priv->fsb_freq = 533; /* 133*4 */
654 break;
655 case CLKCFG_FSB_800:
656 dev_priv->fsb_freq = 800; /* 200*4 */
657 break;
658 case CLKCFG_FSB_667:
659 dev_priv->fsb_freq = 667; /* 167*4 */
660 break;
661 case CLKCFG_FSB_400:
662 dev_priv->fsb_freq = 400; /* 100*4 */
663 break;
664 }
665
666 switch (tmp & CLKCFG_MEM_MASK) {
667 case CLKCFG_MEM_533:
668 dev_priv->mem_freq = 533;
669 break;
670 case CLKCFG_MEM_667:
671 dev_priv->mem_freq = 667;
672 break;
673 case CLKCFG_MEM_800:
674 dev_priv->mem_freq = 800;
675 break;
676 }
677
678 /* detect pineview DDR3 setting */
679 tmp = I915_READ(CSHRDDR3CTL);
680 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
681}
682
683static void i915_ironlake_get_mem_freq(struct drm_device *dev)
684{
50227e1c 685 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 686 u16 ddrpll, csipll;
687
688 ddrpll = I915_READ16(DDRMPLL1);
689 csipll = I915_READ16(CSIPLL0);
690
691 switch (ddrpll & 0xff) {
692 case 0xc:
693 dev_priv->mem_freq = 800;
694 break;
695 case 0x10:
696 dev_priv->mem_freq = 1066;
697 break;
698 case 0x14:
699 dev_priv->mem_freq = 1333;
700 break;
701 case 0x18:
702 dev_priv->mem_freq = 1600;
703 break;
704 default:
705 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
706 ddrpll & 0xff);
707 dev_priv->mem_freq = 0;
708 break;
709 }
710
20e4d407 711 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 712
713 switch (csipll & 0x3ff) {
714 case 0x00c:
715 dev_priv->fsb_freq = 3200;
716 break;
717 case 0x00e:
718 dev_priv->fsb_freq = 3733;
719 break;
720 case 0x010:
721 dev_priv->fsb_freq = 4266;
722 break;
723 case 0x012:
724 dev_priv->fsb_freq = 4800;
725 break;
726 case 0x014:
727 dev_priv->fsb_freq = 5333;
728 break;
729 case 0x016:
730 dev_priv->fsb_freq = 5866;
731 break;
732 case 0x018:
733 dev_priv->fsb_freq = 6400;
734 break;
735 default:
736 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
737 csipll & 0x3ff);
738 dev_priv->fsb_freq = 0;
739 break;
740 }
741
742 if (dev_priv->fsb_freq == 3200) {
20e4d407 743 dev_priv->ips.c_m = 0;
c921aba8 744 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 745 dev_priv->ips.c_m = 1;
c921aba8 746 } else {
20e4d407 747 dev_priv->ips.c_m = 2;
c921aba8
DV		 748 }
749}
750
b445e3b0
ED		 751static const struct cxsr_latency cxsr_latency_table[] = {
752 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
753 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
754 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
755 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
756 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
757
758 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
759 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
760 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
761 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
762 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
763
764 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
765 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
766 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
767 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
768 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
769
770 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
771 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
772 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
773 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
774 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
775
776 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
777 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
778 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
779 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
780 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
781
782 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
783 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
784 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
785 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
786 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
787};
788
63c62275 789static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 790 int is_ddr3,
791 int fsb,
792 int mem)
793{
794 const struct cxsr_latency *latency;
795 int i;
796
797 if (fsb == 0 || mem == 0)
798 return NULL;
799
800 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
801 latency = &cxsr_latency_table[i];
802 if (is_desktop == latency->is_desktop &&
803 is_ddr3 == latency->is_ddr3 &&
804 fsb == latency->fsb_freq && mem == latency->mem_freq)
805 return latency;
806 }
807
808 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
809
810 return NULL;
811}
812
5209b1f4 813void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 814{
5209b1f4
ID		 815 struct drm_device *dev = dev_priv->dev;
816 u32 val;
b445e3b0 817
5209b1f4
ID		 818 if (IS_VALLEYVIEW(dev)) {
819 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
820 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
821 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
822 } else if (IS_PINEVIEW(dev)) {
823 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
824 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
825 I915_WRITE(DSPFW3, val);
826 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
827 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
828 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
829 I915_WRITE(FW_BLC_SELF, val);
830 } else if (IS_I915GM(dev)) {
831 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
832 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
833 I915_WRITE(INSTPM, val);
834 } else {
835 return;
836 }
837
838 DRM_DEBUG_KMS("memory self-refresh is %s\n",
839 enable ? "enabled" : "disabled");
b445e3b0
ED		 840}
841
842/*
843 * Latency for FIFO fetches is dependent on several factors:
844 * - memory configuration (speed, channels)
845 * - chipset
846 * - current MCH state
847 * It can be fairly high in some situations, so here we assume a fairly
848 * pessimal value. It's a tradeoff between extra memory fetches (if we
849 * set this value too high, the FIFO will fetch frequently to stay full)
850 * and power consumption (set it too low to save power and we might see
851 * FIFO underruns and display "flicker").
852 *
853 * A value of 5us seems to be a good balance; safe for very low end
854 * platforms but not overly aggressive on lower latency configs.
855 */
856static const int latency_ns = 5000;
857
1fa61106 858static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 859{
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 uint32_t dsparb = I915_READ(DSPARB);
862 int size;
863
864 size = dsparb & 0x7f;
865 if (plane)
866 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
867
868 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
869 plane ? "B" : "A", size);
870
871 return size;
872}
873
feb56b93 874static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 875{
876 struct drm_i915_private *dev_priv = dev->dev_private;
877 uint32_t dsparb = I915_READ(DSPARB);
878 int size;
879
880 size = dsparb & 0x1ff;
881 if (plane)
882 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
883 size >>= 1; /* Convert to cachelines */
884
885 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
886 plane ? "B" : "A", size);
887
888 return size;
889}
890
1fa61106 891static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 892{
893 struct drm_i915_private *dev_priv = dev->dev_private;
894 uint32_t dsparb = I915_READ(DSPARB);
895 int size;
896
897 size = dsparb & 0x7f;
898 size >>= 2; /* Convert to cachelines */
899
900 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
901 plane ? "B" : "A",
902 size);
903
904 return size;
905}
906
b445e3b0
ED		 907/* Pineview has different values for various configs */
908static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 909 .fifo_size = PINEVIEW_DISPLAY_FIFO,
910 .max_wm = PINEVIEW_MAX_WM,
911 .default_wm = PINEVIEW_DFT_WM,
912 .guard_size = PINEVIEW_GUARD_WM,
913 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 914};
915static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 916 .fifo_size = PINEVIEW_DISPLAY_FIFO,
917 .max_wm = PINEVIEW_MAX_WM,
918 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
919 .guard_size = PINEVIEW_GUARD_WM,
920 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 921};
922static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 923 .fifo_size = PINEVIEW_CURSOR_FIFO,
924 .max_wm = PINEVIEW_CURSOR_MAX_WM,
925 .default_wm = PINEVIEW_CURSOR_DFT_WM,
926 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
927 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 928};
929static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 930 .fifo_size = PINEVIEW_CURSOR_FIFO,
931 .max_wm = PINEVIEW_CURSOR_MAX_WM,
932 .default_wm = PINEVIEW_CURSOR_DFT_WM,
933 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
934 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 935};
936static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 937 .fifo_size = G4X_FIFO_SIZE,
938 .max_wm = G4X_MAX_WM,
939 .default_wm = G4X_MAX_WM,
940 .guard_size = 2,
941 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 942};
943static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 944 .fifo_size = I965_CURSOR_FIFO,
945 .max_wm = I965_CURSOR_MAX_WM,
946 .default_wm = I965_CURSOR_DFT_WM,
947 .guard_size = 2,
948 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 949};
950static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 951 .fifo_size = VALLEYVIEW_FIFO_SIZE,
952 .max_wm = VALLEYVIEW_MAX_WM,
953 .default_wm = VALLEYVIEW_MAX_WM,
954 .guard_size = 2,
955 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 956};
957static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 958 .fifo_size = I965_CURSOR_FIFO,
959 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
960 .default_wm = I965_CURSOR_DFT_WM,
961 .guard_size = 2,
962 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 963};
964static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 965 .fifo_size = I965_CURSOR_FIFO,
966 .max_wm = I965_CURSOR_MAX_WM,
967 .default_wm = I965_CURSOR_DFT_WM,
968 .guard_size = 2,
969 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 970};
971static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 972 .fifo_size = I945_FIFO_SIZE,
973 .max_wm = I915_MAX_WM,
974 .default_wm = 1,
975 .guard_size = 2,
976 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 977};
978static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 979 .fifo_size = I915_FIFO_SIZE,
980 .max_wm = I915_MAX_WM,
981 .default_wm = 1,
982 .guard_size = 2,
983 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 984};
feb56b93 985static const struct intel_watermark_params i830_wm_info = {
e0f0273e
VS		 986 .fifo_size = I855GM_FIFO_SIZE,
987 .max_wm = I915_MAX_WM,
988 .default_wm = 1,
989 .guard_size = 2,
990 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 991};
feb56b93 992static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 993 .fifo_size = I830_FIFO_SIZE,
994 .max_wm = I915_MAX_WM,
995 .default_wm = 1,
996 .guard_size = 2,
997 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 998};
999
b445e3b0
ED		 1000/**
1001 * intel_calculate_wm - calculate watermark level
1002 * @clock_in_khz: pixel clock
1003 * @wm: chip FIFO params
1004 * @pixel_size: display pixel size
1005 * @latency_ns: memory latency for the platform
1006 *
1007 * Calculate the watermark level (the level at which the display plane will
1008 * start fetching from memory again). Each chip has a different display
1009 * FIFO size and allocation, so the caller needs to figure that out and pass
1010 * in the correct intel_watermark_params structure.
1011 *
1012 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1013 * on the pixel size. When it reaches the watermark level, it'll start
1014 * fetching FIFO line sized based chunks from memory until the FIFO fills
1015 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1016 * will occur, and a display engine hang could result.
1017 */
1018static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1019 const struct intel_watermark_params *wm,
1020 int fifo_size,
1021 int pixel_size,
1022 unsigned long latency_ns)
1023{
1024 long entries_required, wm_size;
1025
1026 /*
1027 * Note: we need to make sure we don't overflow for various clock &
1028 * latency values.
1029 * clocks go from a few thousand to several hundred thousand.
1030 * latency is usually a few thousand
1031 */
1032 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1033 1000;
1034 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1035
1036 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1037
1038 wm_size = fifo_size - (entries_required + wm->guard_size);
1039
1040 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1041
1042 /* Don't promote wm_size to unsigned... */
1043 if (wm_size > (long)wm->max_wm)
1044 wm_size = wm->max_wm;
1045 if (wm_size <= 0)
1046 wm_size = wm->default_wm;
1047 return wm_size;
1048}
1049
1050static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1051{
1052 struct drm_crtc *crtc, *enabled = NULL;
1053
70e1e0ec 1054 for_each_crtc(dev, crtc) {
3490ea5d 1055 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1056 if (enabled)
1057 return NULL;
1058 enabled = crtc;
1059 }
1060 }
1061
1062 return enabled;
1063}
1064
46ba614c 1065static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1066{
46ba614c 1067 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1068 struct drm_i915_private *dev_priv = dev->dev_private;
1069 struct drm_crtc *crtc;
1070 const struct cxsr_latency *latency;
1071 u32 reg;
1072 unsigned long wm;
1073
1074 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1075 dev_priv->fsb_freq, dev_priv->mem_freq);
1076 if (!latency) {
1077 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 1078 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1079 return;
1080 }
1081
1082 crtc = single_enabled_crtc(dev);
1083 if (crtc) {
241bfc38 1084 const struct drm_display_mode *adjusted_mode;
f4510a27 1085 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
241bfc38
DL		 1086 int clock;
1087
1088 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1089 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1090
1091 /* Display SR */
1092 wm = intel_calculate_wm(clock, &pineview_display_wm,
1093 pineview_display_wm.fifo_size,
1094 pixel_size, latency->display_sr);
1095 reg = I915_READ(DSPFW1);
1096 reg &= ~DSPFW_SR_MASK;
1097 reg |= wm << DSPFW_SR_SHIFT;
1098 I915_WRITE(DSPFW1, reg);
1099 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1100
1101 /* cursor SR */
1102 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1103 pineview_display_wm.fifo_size,
1104 pixel_size, latency->cursor_sr);
1105 reg = I915_READ(DSPFW3);
1106 reg &= ~DSPFW_CURSOR_SR_MASK;
1107 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1108 I915_WRITE(DSPFW3, reg);
1109
1110 /* Display HPLL off SR */
1111 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1112 pineview_display_hplloff_wm.fifo_size,
1113 pixel_size, latency->display_hpll_disable);
1114 reg = I915_READ(DSPFW3);
1115 reg &= ~DSPFW_HPLL_SR_MASK;
1116 reg |= wm & DSPFW_HPLL_SR_MASK;
1117 I915_WRITE(DSPFW3, reg);
1118
1119 /* cursor HPLL off SR */
1120 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1121 pineview_display_hplloff_wm.fifo_size,
1122 pixel_size, latency->cursor_hpll_disable);
1123 reg = I915_READ(DSPFW3);
1124 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1125 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1126 I915_WRITE(DSPFW3, reg);
1127 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1128
5209b1f4 1129 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 1130 } else {
5209b1f4 1131 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1132 }
1133}
1134
1135static bool g4x_compute_wm0(struct drm_device *dev,
1136 int plane,
1137 const struct intel_watermark_params *display,
1138 int display_latency_ns,
1139 const struct intel_watermark_params *cursor,
1140 int cursor_latency_ns,
1141 int *plane_wm,
1142 int *cursor_wm)
1143{
1144 struct drm_crtc *crtc;
4fe8590a 1145 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1146 int htotal, hdisplay, clock, pixel_size;
1147 int line_time_us, line_count;
1148 int entries, tlb_miss;
1149
1150 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1151 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1152 *cursor_wm = cursor->guard_size;
1153 *plane_wm = display->guard_size;
1154 return false;
1155 }
1156
4fe8590a 1157 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1158 clock = adjusted_mode->crtc_clock;
fec8cba3 1159 htotal = adjusted_mode->crtc_htotal;
37327abd 1160 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1161 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1162
1163 /* Use the small buffer method to calculate plane watermark */
1164 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1165 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1166 if (tlb_miss > 0)
1167 entries += tlb_miss;
1168 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1169 *plane_wm = entries + display->guard_size;
1170 if (*plane_wm > (int)display->max_wm)
1171 *plane_wm = display->max_wm;
1172
1173 /* Use the large buffer method to calculate cursor watermark */
922044c9 1174 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 1175 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
7bb836dd 1176 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
b445e3b0
ED		 1177 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1178 if (tlb_miss > 0)
1179 entries += tlb_miss;
1180 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1181 *cursor_wm = entries + cursor->guard_size;
1182 if (*cursor_wm > (int)cursor->max_wm)
1183 *cursor_wm = (int)cursor->max_wm;
1184
1185 return true;
1186}
1187
1188/*
1189 * Check the wm result.
1190 *
1191 * If any calculated watermark values is larger than the maximum value that
1192 * can be programmed into the associated watermark register, that watermark
1193 * must be disabled.
1194 */
1195static bool g4x_check_srwm(struct drm_device *dev,
1196 int display_wm, int cursor_wm,
1197 const struct intel_watermark_params *display,
1198 const struct intel_watermark_params *cursor)
1199{
1200 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1201 display_wm, cursor_wm);
1202
1203 if (display_wm > display->max_wm) {
1204 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1205 display_wm, display->max_wm);
1206 return false;
1207 }
1208
1209 if (cursor_wm > cursor->max_wm) {
1210 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1211 cursor_wm, cursor->max_wm);
1212 return false;
1213 }
1214
1215 if (!(display_wm || cursor_wm)) {
1216 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1217 return false;
1218 }
1219
1220 return true;
1221}
1222
1223static bool g4x_compute_srwm(struct drm_device *dev,
1224 int plane,
1225 int latency_ns,
1226 const struct intel_watermark_params *display,
1227 const struct intel_watermark_params *cursor,
1228 int *display_wm, int *cursor_wm)
1229{
1230 struct drm_crtc *crtc;
4fe8590a 1231 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1232 int hdisplay, htotal, pixel_size, clock;
1233 unsigned long line_time_us;
1234 int line_count, line_size;
1235 int small, large;
1236 int entries;
1237
1238 if (!latency_ns) {
1239 *display_wm = *cursor_wm = 0;
1240 return false;
1241 }
1242
1243 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1244 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1245 clock = adjusted_mode->crtc_clock;
fec8cba3 1246 htotal = adjusted_mode->crtc_htotal;
37327abd 1247 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1248 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0 1249
922044c9 1250 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1251 line_count = (latency_ns / line_time_us + 1000) / 1000;
1252 line_size = hdisplay * pixel_size;
1253
1254 /* Use the minimum of the small and large buffer method for primary */
1255 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1256 large = line_count * line_size;
1257
1258 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1259 *display_wm = entries + display->guard_size;
1260
1261 /* calculate the self-refresh watermark for display cursor */
7bb836dd 1262 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1263 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1264 *cursor_wm = entries + cursor->guard_size;
1265
1266 return g4x_check_srwm(dev,
1267 *display_wm, *cursor_wm,
1268 display, cursor);
1269}
1270
1271static bool vlv_compute_drain_latency(struct drm_device *dev,
1272 int plane,
1273 int *plane_prec_mult,
1274 int *plane_dl,
1275 int *cursor_prec_mult,
1276 int *cursor_dl)
1277{
1278 struct drm_crtc *crtc;
1279 int clock, pixel_size;
1280 int entries;
1281
1282 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1283 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1284 return false;
1285
241bfc38 1286 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
f4510a27 1287 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
b445e3b0
ED		 1288
1289 entries = (clock / 1000) * pixel_size;
69bbeb4a 1290 *plane_prec_mult = (entries > 128) ?
22c5aee3 1291 DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
69bbeb4a 1292 *plane_dl = (64 * (*plane_prec_mult) * 4) / entries;
b445e3b0
ED		 1293
1294 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
69bbeb4a 1295 *cursor_prec_mult = (entries > 128) ?
22c5aee3 1296 DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
69bbeb4a 1297 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / entries;
b445e3b0
ED		 1298
1299 return true;
1300}
1301
1302/*
1303 * Update drain latency registers of memory arbiter
1304 *
1305 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1306 * to be programmed. Each plane has a drain latency multiplier and a drain
1307 * latency value.
1308 */
1309
1310static void vlv_update_drain_latency(struct drm_device *dev)
1311{
1312 struct drm_i915_private *dev_priv = dev->dev_private;
1313 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1314 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1315 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1316 either 16 or 32 */
1317
1318 /* For plane A, Cursor A */
1319 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1320 &cursor_prec_mult, &cursora_dl)) {
1321 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
22c5aee3 1322 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64;
b445e3b0 1323 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
22c5aee3 1324 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64;
b445e3b0
ED		 1325
1326 I915_WRITE(VLV_DDL1, cursora_prec |
1327 (cursora_dl << DDL_CURSORA_SHIFT) |
1328 planea_prec | planea_dl);
1329 }
1330
1331 /* For plane B, Cursor B */
1332 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1333 &cursor_prec_mult, &cursorb_dl)) {
1334 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
22c5aee3 1335 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64;
b445e3b0 1336 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
22c5aee3 1337 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64;
b445e3b0
ED		 1338
1339 I915_WRITE(VLV_DDL2, cursorb_prec |
1340 (cursorb_dl << DDL_CURSORB_SHIFT) |
1341 planeb_prec | planeb_dl);
1342 }
1343}
1344
1345#define single_plane_enabled(mask) is_power_of_2(mask)
1346
46ba614c 1347static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1348{
46ba614c 1349 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1350 static const int sr_latency_ns = 12000;
1351 struct drm_i915_private *dev_priv = dev->dev_private;
1352 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1353 int plane_sr, cursor_sr;
af6c4575 1354 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0 1355 unsigned int enabled = 0;
9858425c 1356 bool cxsr_enabled;
b445e3b0
ED		 1357
1358 vlv_update_drain_latency(dev);
1359
51cea1f4 1360 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1361 &valleyview_wm_info, latency_ns,
1362 &valleyview_cursor_wm_info, latency_ns,
1363 &planea_wm, &cursora_wm))
51cea1f4 1364 enabled |= 1 << PIPE_A;
b445e3b0 1365
51cea1f4 1366 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1367 &valleyview_wm_info, latency_ns,
1368 &valleyview_cursor_wm_info, latency_ns,
1369 &planeb_wm, &cursorb_wm))
51cea1f4 1370 enabled |= 1 << PIPE_B;
b445e3b0 1371
b445e3b0
ED		 1372 if (single_plane_enabled(enabled) &&
1373 g4x_compute_srwm(dev, ffs(enabled) - 1,
1374 sr_latency_ns,
1375 &valleyview_wm_info,
1376 &valleyview_cursor_wm_info,
af6c4575
CW		 1377 &plane_sr, &ignore_cursor_sr) &&
1378 g4x_compute_srwm(dev, ffs(enabled) - 1,
1379 2*sr_latency_ns,
1380 &valleyview_wm_info,
1381 &valleyview_cursor_wm_info,
52bd02d8 1382 &ignore_plane_sr, &cursor_sr)) {
9858425c 1383 cxsr_enabled = true;
52bd02d8 1384 } else {
9858425c 1385 cxsr_enabled = false;
5209b1f4 1386 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1387 plane_sr = cursor_sr = 0;
1388 }
b445e3b0
ED		 1389
1390 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1391 planea_wm, cursora_wm,
1392 planeb_wm, cursorb_wm,
1393 plane_sr, cursor_sr);
1394
1395 I915_WRITE(DSPFW1,
1396 (plane_sr << DSPFW_SR_SHIFT) |
1397 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1398 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1399 planea_wm);
1400 I915_WRITE(DSPFW2,
8c919b28 1401 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1402 (cursora_wm << DSPFW_CURSORA_SHIFT));
1403 I915_WRITE(DSPFW3,
8c919b28
CW		 1404 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1405 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1406
1407 if (cxsr_enabled)
1408 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1409}
1410
46ba614c 1411static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1412{
46ba614c 1413 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1414 static const int sr_latency_ns = 12000;
1415 struct drm_i915_private *dev_priv = dev->dev_private;
1416 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1417 int plane_sr, cursor_sr;
1418 unsigned int enabled = 0;
9858425c 1419 bool cxsr_enabled;
b445e3b0 1420
51cea1f4 1421 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1422 &g4x_wm_info, latency_ns,
1423 &g4x_cursor_wm_info, latency_ns,
1424 &planea_wm, &cursora_wm))
51cea1f4 1425 enabled |= 1 << PIPE_A;
b445e3b0 1426
51cea1f4 1427 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1428 &g4x_wm_info, latency_ns,
1429 &g4x_cursor_wm_info, latency_ns,
1430 &planeb_wm, &cursorb_wm))
51cea1f4 1431 enabled |= 1 << PIPE_B;
b445e3b0 1432
b445e3b0
ED		 1433 if (single_plane_enabled(enabled) &&
1434 g4x_compute_srwm(dev, ffs(enabled) - 1,
1435 sr_latency_ns,
1436 &g4x_wm_info,
1437 &g4x_cursor_wm_info,
52bd02d8 1438 &plane_sr, &cursor_sr)) {
9858425c 1439 cxsr_enabled = true;
52bd02d8 1440 } else {
9858425c 1441 cxsr_enabled = false;
5209b1f4 1442 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1443 plane_sr = cursor_sr = 0;
1444 }
b445e3b0
ED		 1445
1446 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1447 planea_wm, cursora_wm,
1448 planeb_wm, cursorb_wm,
1449 plane_sr, cursor_sr);
1450
1451 I915_WRITE(DSPFW1,
1452 (plane_sr << DSPFW_SR_SHIFT) |
1453 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1454 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1455 planea_wm);
1456 I915_WRITE(DSPFW2,
8c919b28 1457 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1458 (cursora_wm << DSPFW_CURSORA_SHIFT));
1459 /* HPLL off in SR has some issues on G4x... disable it */
1460 I915_WRITE(DSPFW3,
8c919b28 1461 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0 1462 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1463
1464 if (cxsr_enabled)
1465 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1466}
1467
46ba614c 1468static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1469{
46ba614c 1470 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1471 struct drm_i915_private *dev_priv = dev->dev_private;
1472 struct drm_crtc *crtc;
1473 int srwm = 1;
1474 int cursor_sr = 16;
9858425c 1475 bool cxsr_enabled;
b445e3b0
ED		 1476
1477 /* Calc sr entries for one plane configs */
1478 crtc = single_enabled_crtc(dev);
1479 if (crtc) {
1480 /* self-refresh has much higher latency */
1481 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1482 const struct drm_display_mode *adjusted_mode =
1483 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1484 int clock = adjusted_mode->crtc_clock;
fec8cba3 1485 int htotal = adjusted_mode->crtc_htotal;
37327abd 1486 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1487 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1488 unsigned long line_time_us;
1489 int entries;
1490
922044c9 1491 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1492
1493 /* Use ns/us then divide to preserve precision */
1494 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1495 pixel_size * hdisplay;
1496 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1497 srwm = I965_FIFO_SIZE - entries;
1498 if (srwm < 0)
1499 srwm = 1;
1500 srwm &= 0x1ff;
1501 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1502 entries, srwm);
1503
1504 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
7bb836dd 1505 pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1506 entries = DIV_ROUND_UP(entries,
1507 i965_cursor_wm_info.cacheline_size);
1508 cursor_sr = i965_cursor_wm_info.fifo_size -
1509 (entries + i965_cursor_wm_info.guard_size);
1510
1511 if (cursor_sr > i965_cursor_wm_info.max_wm)
1512 cursor_sr = i965_cursor_wm_info.max_wm;
1513
1514 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1515 "cursor %d\n", srwm, cursor_sr);
1516
9858425c 1517 cxsr_enabled = true;
b445e3b0 1518 } else {
9858425c 1519 cxsr_enabled = false;
b445e3b0 1520 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1521 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1522 }
1523
1524 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1525 srwm);
1526
1527 /* 965 has limitations... */
1528 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1529 (8 << 16) | (8 << 8) | (8 << 0));
1530 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1531 /* update cursor SR watermark */
1532 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1533
1534 if (cxsr_enabled)
1535 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1536}
1537
46ba614c 1538static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1539{
46ba614c 1540 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1541 struct drm_i915_private *dev_priv = dev->dev_private;
1542 const struct intel_watermark_params *wm_info;
1543 uint32_t fwater_lo;
1544 uint32_t fwater_hi;
1545 int cwm, srwm = 1;
1546 int fifo_size;
1547 int planea_wm, planeb_wm;
1548 struct drm_crtc *crtc, *enabled = NULL;
1549
1550 if (IS_I945GM(dev))
1551 wm_info = &i945_wm_info;
1552 else if (!IS_GEN2(dev))
1553 wm_info = &i915_wm_info;
1554 else
feb56b93 1555 wm_info = &i830_wm_info;
b445e3b0
ED		 1556
1557 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1558 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1559 if (intel_crtc_active(crtc)) {
241bfc38 1560 const struct drm_display_mode *adjusted_mode;
f4510a27 1561 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1562 if (IS_GEN2(dev))
1563 cpp = 4;
1564
241bfc38
DL		 1565 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1566 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1567 wm_info, fifo_size, cpp,
b445e3b0
ED		 1568 latency_ns);
1569 enabled = crtc;
1570 } else
1571 planea_wm = fifo_size - wm_info->guard_size;
1572
1573 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1574 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1575 if (intel_crtc_active(crtc)) {
241bfc38 1576 const struct drm_display_mode *adjusted_mode;
f4510a27 1577 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1578 if (IS_GEN2(dev))
1579 cpp = 4;
1580
241bfc38
DL		 1581 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1582 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1583 wm_info, fifo_size, cpp,
b445e3b0
ED		 1584 latency_ns);
1585 if (enabled == NULL)
1586 enabled = crtc;
1587 else
1588 enabled = NULL;
1589 } else
1590 planeb_wm = fifo_size - wm_info->guard_size;
1591
1592 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1593
2ab1bc9d 1594 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1595 struct drm_i915_gem_object *obj;
2ab1bc9d 1596
2ff8fde1 1597 obj = intel_fb_obj(enabled->primary->fb);
2ab1bc9d
DV		 1598
1599 /* self-refresh seems busted with untiled */
2ff8fde1 1600 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1601 enabled = NULL;
1602 }
1603
b445e3b0
ED		 1604 /*
1605 * Overlay gets an aggressive default since video jitter is bad.
1606 */
1607 cwm = 2;
1608
1609 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1610 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1611
1612 /* Calc sr entries for one plane configs */
1613 if (HAS_FW_BLC(dev) && enabled) {
1614 /* self-refresh has much higher latency */
1615 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1616 const struct drm_display_mode *adjusted_mode =
1617 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1618 int clock = adjusted_mode->crtc_clock;
fec8cba3 1619 int htotal = adjusted_mode->crtc_htotal;
f727b490 1620 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
f4510a27 1621 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1622 unsigned long line_time_us;
1623 int entries;
1624
922044c9 1625 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1626
1627 /* Use ns/us then divide to preserve precision */
1628 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1629 pixel_size * hdisplay;
1630 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1631 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1632 srwm = wm_info->fifo_size - entries;
1633 if (srwm < 0)
1634 srwm = 1;
1635
1636 if (IS_I945G(dev) || IS_I945GM(dev))
1637 I915_WRITE(FW_BLC_SELF,
1638 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1639 else if (IS_I915GM(dev))
1640 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1641 }
1642
1643 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1644 planea_wm, planeb_wm, cwm, srwm);
1645
1646 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1647 fwater_hi = (cwm & 0x1f);
1648
1649 /* Set request length to 8 cachelines per fetch */
1650 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1651 fwater_hi = fwater_hi | (1 << 8);
1652
1653 I915_WRITE(FW_BLC, fwater_lo);
1654 I915_WRITE(FW_BLC2, fwater_hi);
1655
5209b1f4
ID		 1656 if (enabled)
1657 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1658}
1659
feb56b93 1660static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1661{
46ba614c 1662 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664 struct drm_crtc *crtc;
241bfc38 1665 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1666 uint32_t fwater_lo;
1667 int planea_wm;
1668
1669 crtc = single_enabled_crtc(dev);
1670 if (crtc == NULL)
1671 return;
1672
241bfc38
DL		 1673 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1674 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1675 &i845_wm_info,
b445e3b0 1676 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1677 4, latency_ns);
b445e3b0
ED		 1678 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1679 fwater_lo |= (3<<8) | planea_wm;
1680
1681 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1682
1683 I915_WRITE(FW_BLC, fwater_lo);
1684}
1685
3658729a
VS		 1686static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1687 struct drm_crtc *crtc)
801bcfff
PZ		 1688{
1689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1690 uint32_t pixel_rate;
801bcfff 1691
241bfc38 1692 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 1693
1694 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1695 * adjust the pixel_rate here. */
1696
fd4daa9c 1697 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1698 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1699 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1700
37327abd
VS		 1701 pipe_w = intel_crtc->config.pipe_src_w;
1702 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 1703 pfit_w = (pfit_size >> 16) & 0xFFFF;
1704 pfit_h = pfit_size & 0xFFFF;
1705 if (pipe_w < pfit_w)
1706 pipe_w = pfit_w;
1707 if (pipe_h < pfit_h)
1708 pipe_h = pfit_h;
1709
1710 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1711 pfit_w * pfit_h);
1712 }
1713
1714 return pixel_rate;
1715}
1716
37126462 1717/* latency must be in 0.1us units. */
23297044 1718static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1719 uint32_t latency)
1720{
1721 uint64_t ret;
1722
3312ba65
VS		 1723 if (WARN(latency == 0, "Latency value missing\n"))
1724 return UINT_MAX;
1725
801bcfff
PZ		 1726 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1727 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1728
1729 return ret;
1730}
1731
37126462 1732/* latency must be in 0.1us units. */
23297044 1733static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1734 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1735 uint32_t latency)
1736{
1737 uint32_t ret;
1738
3312ba65
VS		 1739 if (WARN(latency == 0, "Latency value missing\n"))
1740 return UINT_MAX;
1741
801bcfff
PZ		 1742 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1743 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1744 ret = DIV_ROUND_UP(ret, 64) + 2;
1745 return ret;
1746}
1747
23297044 1748static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1749 uint8_t bytes_per_pixel)
1750{
1751 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1752}
1753
820c1980 1754struct ilk_pipe_wm_parameters {
801bcfff 1755 bool active;
801bcfff
PZ		 1756 uint32_t pipe_htotal;
1757 uint32_t pixel_rate;
c35426d2
VS		 1758 struct intel_plane_wm_parameters pri;
1759 struct intel_plane_wm_parameters spr;
1760 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1761};
1762
820c1980 1763struct ilk_wm_maximums {
cca32e9a
PZ		 1764 uint16_t pri;
1765 uint16_t spr;
1766 uint16_t cur;
1767 uint16_t fbc;
1768};
1769
240264f4
VS		 1770/* used in computing the new watermarks state */
1771struct intel_wm_config {
1772 unsigned int num_pipes_active;
1773 bool sprites_enabled;
1774 bool sprites_scaled;
240264f4
VS		 1775};
1776
37126462
VS		 1777/*
1778 * For both WM_PIPE and WM_LP.
1779 * mem_value must be in 0.1us units.
1780 */
820c1980 1781static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1782 uint32_t mem_value,
1783 bool is_lp)
801bcfff 1784{
cca32e9a
PZ		 1785 uint32_t method1, method2;
1786
c35426d2 1787 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1788 return 0;
1789
23297044 1790 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1791 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1792 mem_value);
1793
1794 if (!is_lp)
1795 return method1;
1796
23297044 1797 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1798 params->pipe_htotal,
c35426d2
VS		 1799 params->pri.horiz_pixels,
1800 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1801 mem_value);
1802
1803 return min(method1, method2);
801bcfff
PZ		 1804}
1805
37126462
VS		 1806/*
1807 * For both WM_PIPE and WM_LP.
1808 * mem_value must be in 0.1us units.
1809 */
820c1980 1810static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1811 uint32_t mem_value)
1812{
1813 uint32_t method1, method2;
1814
c35426d2 1815 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1816 return 0;
1817
23297044 1818 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1819 params->spr.bytes_per_pixel,
801bcfff 1820 mem_value);
23297044 1821 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1822 params->pipe_htotal,
c35426d2
VS		 1823 params->spr.horiz_pixels,
1824 params->spr.bytes_per_pixel,
801bcfff
PZ		 1825 mem_value);
1826 return min(method1, method2);
1827}
1828
37126462
VS		 1829/*
1830 * For both WM_PIPE and WM_LP.
1831 * mem_value must be in 0.1us units.
1832 */
820c1980 1833static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1834 uint32_t mem_value)
1835{
c35426d2 1836 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1837 return 0;
1838
23297044 1839 return ilk_wm_method2(params->pixel_rate,
801bcfff 1840 params->pipe_htotal,
c35426d2
VS		 1841 params->cur.horiz_pixels,
1842 params->cur.bytes_per_pixel,
801bcfff
PZ		 1843 mem_value);
1844}
1845
cca32e9a 1846/* Only for WM_LP. */
820c1980 1847static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1848 uint32_t pri_val)
cca32e9a 1849{
c35426d2 1850 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1851 return 0;
1852
23297044 1853 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1854 params->pri.horiz_pixels,
1855 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1856}
1857
158ae64f
VS		 1858static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1859{
416f4727
VS		 1860 if (INTEL_INFO(dev)->gen >= 8)
1861 return 3072;
1862 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1863 return 768;
1864 else
1865 return 512;
1866}
1867
4e975081
VS		 1868static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1869 int level, bool is_sprite)
1870{
1871 if (INTEL_INFO(dev)->gen >= 8)
1872 /* BDW primary/sprite plane watermarks */
1873 return level == 0 ? 255 : 2047;
1874 else if (INTEL_INFO(dev)->gen >= 7)
1875 /* IVB/HSW primary/sprite plane watermarks */
1876 return level == 0 ? 127 : 1023;
1877 else if (!is_sprite)
1878 /* ILK/SNB primary plane watermarks */
1879 return level == 0 ? 127 : 511;
1880 else
1881 /* ILK/SNB sprite plane watermarks */
1882 return level == 0 ? 63 : 255;
1883}
1884
1885static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1886 int level)
1887{
1888 if (INTEL_INFO(dev)->gen >= 7)
1889 return level == 0 ? 63 : 255;
1890 else
1891 return level == 0 ? 31 : 63;
1892}
1893
1894static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1895{
1896 if (INTEL_INFO(dev)->gen >= 8)
1897 return 31;
1898 else
1899 return 15;
1900}
1901
158ae64f
VS		 1902/* Calculate the maximum primary/sprite plane watermark */
1903static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1904 int level,
240264f4 1905 const struct intel_wm_config *config,
158ae64f
VS		 1906 enum intel_ddb_partitioning ddb_partitioning,
1907 bool is_sprite)
1908{
1909 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1910
1911 /* if sprites aren't enabled, sprites get nothing */
240264f4 1912 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1913 return 0;
1914
1915 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1916 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1917 fifo_size /= INTEL_INFO(dev)->num_pipes;
1918
1919 /*
1920 * For some reason the non self refresh
1921 * FIFO size is only half of the self
1922 * refresh FIFO size on ILK/SNB.
1923 */
1924 if (INTEL_INFO(dev)->gen <= 6)
1925 fifo_size /= 2;
1926 }
1927
240264f4 1928 if (config->sprites_enabled) {
158ae64f
VS		 1929 /* level 0 is always calculated with 1:1 split */
1930 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1931 if (is_sprite)
1932 fifo_size *= 5;
1933 fifo_size /= 6;
1934 } else {
1935 fifo_size /= 2;
1936 }
1937 }
1938
1939 /* clamp to max that the registers can hold */
4e975081 1940 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1941}
1942
1943/* Calculate the maximum cursor plane watermark */
1944static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1945 int level,
1946 const struct intel_wm_config *config)
158ae64f
VS		 1947{
1948 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1949 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1950 return 64;
1951
1952 /* otherwise just report max that registers can hold */
4e975081 1953 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1954}
1955
d34ff9c6 1956static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1957 int level,
1958 const struct intel_wm_config *config,
1959 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1960 struct ilk_wm_maximums *max)
158ae64f 1961{
240264f4
VS		 1962 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1963 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1964 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1965 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1966}
1967
a3cb4048
VS		 1968static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1969 int level,
1970 struct ilk_wm_maximums *max)
1971{
1972 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1973 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1974 max->cur = ilk_cursor_wm_reg_max(dev, level);
1975 max->fbc = ilk_fbc_wm_reg_max(dev);
1976}
1977
d9395655 1978static bool ilk_validate_wm_level(int level,
820c1980 1979 const struct ilk_wm_maximums *max,
d9395655 1980 struct intel_wm_level *result)
a9786a11
VS		 1981{
1982 bool ret;
1983
1984 /* already determined to be invalid? */
1985 if (!result->enable)
1986 return false;
1987
1988 result->enable = result->pri_val <= max->pri &&
1989 result->spr_val <= max->spr &&
1990 result->cur_val <= max->cur;
1991
1992 ret = result->enable;
1993
1994 /*
1995 * HACK until we can pre-compute everything,
1996 * and thus fail gracefully if LP0 watermarks
1997 * are exceeded...
1998 */
1999 if (level == 0 && !result->enable) {
2000 if (result->pri_val > max->pri)
2001 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2002 level, result->pri_val, max->pri);
2003 if (result->spr_val > max->spr)
2004 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2005 level, result->spr_val, max->spr);
2006 if (result->cur_val > max->cur)
2007 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2008 level, result->cur_val, max->cur);
2009
2010 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2011 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2012 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2013 result->enable = true;
2014 }
2015
a9786a11
VS		 2016 return ret;
2017}
2018
d34ff9c6 2019static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 2020 int level,
820c1980 2021 const struct ilk_pipe_wm_parameters *p,
1fd527cc 2022 struct intel_wm_level *result)
6f5ddd17
VS		 2023{
2024 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2025 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2026 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2027
2028 /* WM1+ latency values stored in 0.5us units */
2029 if (level > 0) {
2030 pri_latency *= 5;
2031 spr_latency *= 5;
2032 cur_latency *= 5;
2033 }
2034
2035 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2036 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2037 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2038 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2039 result->enable = true;
2040}
2041
801bcfff
PZ		 2042static uint32_t
2043hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2044{
2045 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2047 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2048 u32 linetime, ips_linetime;
1f8eeabf 2049
801bcfff
PZ		 2050 if (!intel_crtc_active(crtc))
2051 return 0;
1011d8c4 2052
1f8eeabf
ED		 2053 /* The WM are computed with base on how long it takes to fill a single
2054 * row at the given clock rate, multiplied by 8.
2055 * */
fec8cba3
JB		 2056 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2057 mode->crtc_clock);
2058 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 2059 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2060
801bcfff
PZ		 2061 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2062 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2063}
2064
12b134df
VS		 2065static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2066{
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068
a42a5719 2069 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2070 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2071
2072 wm[0] = (sskpd >> 56) & 0xFF;
2073 if (wm[0] == 0)
2074 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2075 wm[1] = (sskpd >> 4) & 0xFF;
2076 wm[2] = (sskpd >> 12) & 0xFF;
2077 wm[3] = (sskpd >> 20) & 0x1FF;
2078 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2079 } else if (INTEL_INFO(dev)->gen >= 6) {
2080 uint32_t sskpd = I915_READ(MCH_SSKPD);
2081
2082 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2083 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2084 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2085 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2086 } else if (INTEL_INFO(dev)->gen >= 5) {
2087 uint32_t mltr = I915_READ(MLTR_ILK);
2088
2089 /* ILK primary LP0 latency is 700 ns */
2090 wm[0] = 7;
2091 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2092 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2093 }
2094}
2095
53615a5e
VS		 2096static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2097{
2098 /* ILK sprite LP0 latency is 1300 ns */
2099 if (INTEL_INFO(dev)->gen == 5)
2100 wm[0] = 13;
2101}
2102
2103static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2104{
2105 /* ILK cursor LP0 latency is 1300 ns */
2106 if (INTEL_INFO(dev)->gen == 5)
2107 wm[0] = 13;
2108
2109 /* WaDoubleCursorLP3Latency:ivb */
2110 if (IS_IVYBRIDGE(dev))
2111 wm[3] *= 2;
2112}
2113
546c81fd 2114int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2115{
26ec971e 2116 /* how many WM levels are we expecting */
a42a5719 2117 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2118 return 4;
26ec971e 2119 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2120 return 3;
26ec971e 2121 else
ad0d6dc4
VS		 2122 return 2;
2123}
2124
2125static void intel_print_wm_latency(struct drm_device *dev,
2126 const char *name,
2127 const uint16_t wm[5])
2128{
2129 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2130
2131 for (level = 0; level <= max_level; level++) {
2132 unsigned int latency = wm[level];
2133
2134 if (latency == 0) {
2135 DRM_ERROR("%s WM%d latency not provided\n",
2136 name, level);
2137 continue;
2138 }
2139
2140 /* WM1+ latency values in 0.5us units */
2141 if (level > 0)
2142 latency *= 5;
2143
2144 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2145 name, level, wm[level],
2146 latency / 10, latency % 10);
2147 }
2148}
2149
e95a2f75
VS		 2150static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2151 uint16_t wm[5], uint16_t min)
2152{
2153 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2154
2155 if (wm[0] >= min)
2156 return false;
2157
2158 wm[0] = max(wm[0], min);
2159 for (level = 1; level <= max_level; level++)
2160 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2161
2162 return true;
2163}
2164
2165static void snb_wm_latency_quirk(struct drm_device *dev)
2166{
2167 struct drm_i915_private *dev_priv = dev->dev_private;
2168 bool changed;
2169
2170 /*
2171 * The BIOS provided WM memory latency values are often
2172 * inadequate for high resolution displays. Adjust them.
2173 */
2174 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2175 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2176 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2177
2178 if (!changed)
2179 return;
2180
2181 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2182 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2183 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2184 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2185}
2186
fa50ad61 2187static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2188{
2189 struct drm_i915_private *dev_priv = dev->dev_private;
2190
2191 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2192
2193 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2194 sizeof(dev_priv->wm.pri_latency));
2195 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2196 sizeof(dev_priv->wm.pri_latency));
2197
2198 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2199 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2200
2201 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2202 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2203 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2204
2205 if (IS_GEN6(dev))
2206 snb_wm_latency_quirk(dev);
53615a5e
VS		 2207}
2208
820c1980 2209static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2210 struct ilk_pipe_wm_parameters *p)
1011d8c4 2211{
7c4a395f
VS		 2212 struct drm_device *dev = crtc->dev;
2213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2214 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2215 struct drm_plane *plane;
1011d8c4 2216
2a44b76b
VS		 2217 if (!intel_crtc_active(crtc))
2218 return;
801bcfff 2219
2a44b76b
VS		 2220 p->active = true;
2221 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2222 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2223 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2224 p->cur.bytes_per_pixel = 4;
2225 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2226 p->cur.horiz_pixels = intel_crtc->cursor_width;
2227 /* TODO: for now, assume primary and cursor planes are always enabled. */
2228 p->pri.enabled = true;
2229 p->cur.enabled = true;
7c4a395f 2230
af2b653b 2231 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2232 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2233
2a44b76b 2234 if (intel_plane->pipe == pipe) {
7c4a395f 2235 p->spr = intel_plane->wm;
2a44b76b
VS		 2236 break;
2237 }
2238 }
2239}
2240
2241static void ilk_compute_wm_config(struct drm_device *dev,
2242 struct intel_wm_config *config)
2243{
2244 struct intel_crtc *intel_crtc;
2245
2246 /* Compute the currently _active_ config */
d3fcc808 2247 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2248 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2249
2a44b76b
VS		 2250 if (!wm->pipe_enabled)
2251 continue;
cca32e9a 2252
2a44b76b
VS		 2253 config->sprites_enabled |= wm->sprites_enabled;
2254 config->sprites_scaled |= wm->sprites_scaled;
2255 config->num_pipes_active++;
cca32e9a 2256 }
801bcfff
PZ		 2257}
2258
0b2ae6d7
VS		 2259/* Compute new watermarks for the pipe */
2260static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2261 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2262 struct intel_pipe_wm *pipe_wm)
2263{
2264 struct drm_device *dev = crtc->dev;
d34ff9c6 2265 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2266 int level, max_level = ilk_wm_max_level(dev);
2267 /* LP0 watermark maximums depend on this pipe alone */
2268 struct intel_wm_config config = {
2269 .num_pipes_active = 1,
2270 .sprites_enabled = params->spr.enabled,
2271 .sprites_scaled = params->spr.scaled,
2272 };
820c1980 2273 struct ilk_wm_maximums max;
0b2ae6d7 2274
2a44b76b
VS		 2275 pipe_wm->pipe_enabled = params->active;
2276 pipe_wm->sprites_enabled = params->spr.enabled;
2277 pipe_wm->sprites_scaled = params->spr.scaled;
2278
7b39a0b7
VS		 2279 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2280 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2281 max_level = 1;
2282
2283 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2284 if (params->spr.scaled)
2285 max_level = 0;
2286
a3cb4048 2287 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2288
a42a5719 2289 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2290 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2291
a3cb4048
VS		 2292 /* LP0 watermarks always use 1/2 DDB partitioning */
2293 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2294
0b2ae6d7 2295 /* At least LP0 must be valid */
a3cb4048
VS		 2296 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2297 return false;
2298
2299 ilk_compute_wm_reg_maximums(dev, 1, &max);
2300
2301 for (level = 1; level <= max_level; level++) {
2302 struct intel_wm_level wm = {};
2303
2304 ilk_compute_wm_level(dev_priv, level, params, &wm);
2305
2306 /*
2307 * Disable any watermark level that exceeds the
2308 * register maximums since such watermarks are
2309 * always invalid.
2310 */
2311 if (!ilk_validate_wm_level(level, &max, &wm))
2312 break;
2313
2314 pipe_wm->wm[level] = wm;
2315 }
2316
2317 return true;
0b2ae6d7
VS		 2318}
2319
2320/*
2321 * Merge the watermarks from all active pipes for a specific level.
2322 */
2323static void ilk_merge_wm_level(struct drm_device *dev,
2324 int level,
2325 struct intel_wm_level *ret_wm)
2326{
2327 const struct intel_crtc *intel_crtc;
2328
d52fea5b
VS		 2329 ret_wm->enable = true;
2330
d3fcc808 2331 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2332 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2333 const struct intel_wm_level *wm = &active->wm[level];
2334
2335 if (!active->pipe_enabled)
2336 continue;
0b2ae6d7 2337
d52fea5b
VS		 2338 /*
2339 * The watermark values may have been used in the past,
2340 * so we must maintain them in the registers for some
2341 * time even if the level is now disabled.
2342 */
0b2ae6d7 2343 if (!wm->enable)
d52fea5b 2344 ret_wm->enable = false;
0b2ae6d7
VS		 2345
2346 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2347 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2348 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2349 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2350 }
0b2ae6d7
VS		 2351}
2352
2353/*
2354 * Merge all low power watermarks for all active pipes.
2355 */
2356static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2357 const struct intel_wm_config *config,
820c1980 2358 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2359 struct intel_pipe_wm *merged)
2360{
2361 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2362 int last_enabled_level = max_level;
0b2ae6d7 2363
0ba22e26
VS		 2364 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2365 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2366 config->num_pipes_active > 1)
2367 return;
2368
6c8b6c28
VS		 2369 /* ILK: FBC WM must be disabled always */
2370 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2371
2372 /* merge each WM1+ level */
2373 for (level = 1; level <= max_level; level++) {
2374 struct intel_wm_level *wm = &merged->wm[level];
2375
2376 ilk_merge_wm_level(dev, level, wm);
2377
d52fea5b
VS		 2378 if (level > last_enabled_level)
2379 wm->enable = false;
2380 else if (!ilk_validate_wm_level(level, max, wm))
2381 /* make sure all following levels get disabled */
2382 last_enabled_level = level - 1;
0b2ae6d7
VS		 2383
2384 /*
2385 * The spec says it is preferred to disable
2386 * FBC WMs instead of disabling a WM level.
2387 */
2388 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2389 if (wm->enable)
2390 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2391 wm->fbc_val = 0;
2392 }
2393 }
6c8b6c28
VS		 2394
2395 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2396 /*
2397 * FIXME this is racy. FBC might get enabled later.
2398 * What we should check here is whether FBC can be
2399 * enabled sometime later.
2400 */
2401 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2402 for (level = 2; level <= max_level; level++) {
2403 struct intel_wm_level *wm = &merged->wm[level];
2404
2405 wm->enable = false;
2406 }
2407 }
0b2ae6d7
VS		 2408}
2409
b380ca3c
VS		 2410static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2411{
2412 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2413 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2414}
2415
a68d68ee
VS		 2416/* The value we need to program into the WM_LPx latency field */
2417static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2418{
2419 struct drm_i915_private *dev_priv = dev->dev_private;
2420
a42a5719 2421 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2422 return 2 * level;
2423 else
2424 return dev_priv->wm.pri_latency[level];
2425}
2426
820c1980 2427static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2428 const struct intel_pipe_wm *merged,
609cedef 2429 enum intel_ddb_partitioning partitioning,
820c1980 2430 struct ilk_wm_values *results)
801bcfff 2431{
0b2ae6d7
VS		 2432 struct intel_crtc *intel_crtc;
2433 int level, wm_lp;
cca32e9a 2434
0362c781 2435 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2436 results->partitioning = partitioning;
cca32e9a 2437
0b2ae6d7 2438 /* LP1+ register values */
cca32e9a 2439 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2440 const struct intel_wm_level *r;
801bcfff 2441
b380ca3c 2442 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2443
0362c781 2444 r = &merged->wm[level];
cca32e9a 2445
d52fea5b
VS		 2446 /*
2447 * Maintain the watermark values even if the level is
2448 * disabled. Doing otherwise could cause underruns.
2449 */
2450 results->wm_lp[wm_lp - 1] =
a68d68ee 2451 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2452 (r->pri_val << WM1_LP_SR_SHIFT) |
2453 r->cur_val;
2454
d52fea5b
VS		 2455 if (r->enable)
2456 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2457
416f4727
VS		 2458 if (INTEL_INFO(dev)->gen >= 8)
2459 results->wm_lp[wm_lp - 1] |=
2460 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2461 else
2462 results->wm_lp[wm_lp - 1] |=
2463 r->fbc_val << WM1_LP_FBC_SHIFT;
2464
d52fea5b
VS		 2465 /*
2466 * Always set WM1S_LP_EN when spr_val != 0, even if the
2467 * level is disabled. Doing otherwise could cause underruns.
2468 */
6cef2b8a
VS		 2469 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2470 WARN_ON(wm_lp != 1);
2471 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2472 } else
2473 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2474 }
801bcfff 2475
0b2ae6d7 2476 /* LP0 register values */
d3fcc808 2477 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2478 enum pipe pipe = intel_crtc->pipe;
2479 const struct intel_wm_level *r =
2480 &intel_crtc->wm.active.wm[0];
2481
2482 if (WARN_ON(!r->enable))
2483 continue;
2484
2485 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2486
0b2ae6d7
VS		 2487 results->wm_pipe[pipe] =
2488 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2489 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2490 r->cur_val;
801bcfff
PZ		 2491 }
2492}
2493
861f3389
PZ		 2494/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2495 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2496static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2497 struct intel_pipe_wm *r1,
2498 struct intel_pipe_wm *r2)
861f3389 2499{
198a1e9b
VS		 2500 int level, max_level = ilk_wm_max_level(dev);
2501 int level1 = 0, level2 = 0;
861f3389 2502
198a1e9b
VS		 2503 for (level = 1; level <= max_level; level++) {
2504 if (r1->wm[level].enable)
2505 level1 = level;
2506 if (r2->wm[level].enable)
2507 level2 = level;
861f3389
PZ		 2508 }
2509
198a1e9b
VS		 2510 if (level1 == level2) {
2511 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2512 return r2;
2513 else
2514 return r1;
198a1e9b 2515 } else if (level1 > level2) {
861f3389
PZ		 2516 return r1;
2517 } else {
2518 return r2;
2519 }
2520}
2521
49a687c4
VS		 2522/* dirty bits used to track which watermarks need changes */
2523#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2524#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2525#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2526#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2527#define WM_DIRTY_FBC (1 << 24)
2528#define WM_DIRTY_DDB (1 << 25)
2529
2530static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
820c1980
ID		 2531 const struct ilk_wm_values *old,
2532 const struct ilk_wm_values *new)
49a687c4
VS		 2533{
2534 unsigned int dirty = 0;
2535 enum pipe pipe;
2536 int wm_lp;
2537
2538 for_each_pipe(pipe) {
2539 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2540 dirty |= WM_DIRTY_LINETIME(pipe);
2541 /* Must disable LP1+ watermarks too */
2542 dirty |= WM_DIRTY_LP_ALL;
2543 }
2544
2545 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2546 dirty |= WM_DIRTY_PIPE(pipe);
2547 /* Must disable LP1+ watermarks too */
2548 dirty |= WM_DIRTY_LP_ALL;
2549 }
2550 }
2551
2552 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2553 dirty |= WM_DIRTY_FBC;
2554 /* Must disable LP1+ watermarks too */
2555 dirty |= WM_DIRTY_LP_ALL;
2556 }
2557
2558 if (old->partitioning != new->partitioning) {
2559 dirty |= WM_DIRTY_DDB;
2560 /* Must disable LP1+ watermarks too */
2561 dirty |= WM_DIRTY_LP_ALL;
2562 }
2563
2564 /* LP1+ watermarks already deemed dirty, no need to continue */
2565 if (dirty & WM_DIRTY_LP_ALL)
2566 return dirty;
2567
2568 /* Find the lowest numbered LP1+ watermark in need of an update... */
2569 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2570 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2571 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2572 break;
2573 }
2574
2575 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2576 for (; wm_lp <= 3; wm_lp++)
2577 dirty |= WM_DIRTY_LP(wm_lp);
2578
2579 return dirty;
2580}
2581
8553c18e
VS		 2582static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2583 unsigned int dirty)
801bcfff 2584{
820c1980 2585 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2586 bool changed = false;
801bcfff 2587
facd619b
VS		 2588 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2589 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2590 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2591 changed = true;
facd619b
VS		 2592 }
2593 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2594 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2595 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2596 changed = true;
facd619b
VS		 2597 }
2598 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2599 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2600 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2601 changed = true;
facd619b 2602 }
801bcfff 2603
facd619b
VS		 2604 /*
2605 * Don't touch WM1S_LP_EN here.
2606 * Doing so could cause underruns.
2607 */
6cef2b8a 2608
8553c18e
VS		 2609 return changed;
2610}
2611
2612/*
2613 * The spec says we shouldn't write when we don't need, because every write
2614 * causes WMs to be re-evaluated, expending some power.
2615 */
820c1980
ID		 2616static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2617 struct ilk_wm_values *results)
8553c18e
VS		 2618{
2619 struct drm_device *dev = dev_priv->dev;
820c1980 2620 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2621 unsigned int dirty;
2622 uint32_t val;
2623
2624 dirty = ilk_compute_wm_dirty(dev, previous, results);
2625 if (!dirty)
2626 return;
2627
2628 _ilk_disable_lp_wm(dev_priv, dirty);
2629
49a687c4 2630 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2631 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2632 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2633 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2634 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2635 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2636
49a687c4 2637 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2638 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2639 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2640 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2641 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2642 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2643
49a687c4 2644 if (dirty & WM_DIRTY_DDB) {
a42a5719 2645 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2646 val = I915_READ(WM_MISC);
2647 if (results->partitioning == INTEL_DDB_PART_1_2)
2648 val &= ~WM_MISC_DATA_PARTITION_5_6;
2649 else
2650 val |= WM_MISC_DATA_PARTITION_5_6;
2651 I915_WRITE(WM_MISC, val);
2652 } else {
2653 val = I915_READ(DISP_ARB_CTL2);
2654 if (results->partitioning == INTEL_DDB_PART_1_2)
2655 val &= ~DISP_DATA_PARTITION_5_6;
2656 else
2657 val |= DISP_DATA_PARTITION_5_6;
2658 I915_WRITE(DISP_ARB_CTL2, val);
2659 }
1011d8c4
PZ		 2660 }
2661
49a687c4 2662 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2663 val = I915_READ(DISP_ARB_CTL);
2664 if (results->enable_fbc_wm)
2665 val &= ~DISP_FBC_WM_DIS;
2666 else
2667 val |= DISP_FBC_WM_DIS;
2668 I915_WRITE(DISP_ARB_CTL, val);
2669 }
2670
954911eb
ID		 2671 if (dirty & WM_DIRTY_LP(1) &&
2672 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2673 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2674
2675 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2676 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2677 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2678 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2679 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2680 }
801bcfff 2681
facd619b 2682 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2683 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2684 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2685 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2686 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2687 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2688
2689 dev_priv->wm.hw = *results;
801bcfff
PZ		 2690}
2691
8553c18e
VS		 2692static bool ilk_disable_lp_wm(struct drm_device *dev)
2693{
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695
2696 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2697}
2698
820c1980 2699static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 2700{
7c4a395f 2701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2702 struct drm_device *dev = crtc->dev;
801bcfff 2703 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 2704 struct ilk_wm_maximums max;
2705 struct ilk_pipe_wm_parameters params = {};
2706 struct ilk_wm_values results = {};
77c122bc 2707 enum intel_ddb_partitioning partitioning;
7c4a395f 2708 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2709 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2710 struct intel_wm_config config = {};
7c4a395f 2711
2a44b76b 2712 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 2713
2714 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2715
2716 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2717 return;
861f3389 2718
7c4a395f 2719 intel_crtc->wm.active = pipe_wm;
861f3389 2720
2a44b76b
VS		 2721 ilk_compute_wm_config(dev, &config);
2722
34982fe1 2723 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 2724 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 2725
2726 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2727 if (INTEL_INFO(dev)->gen >= 7 &&
2728 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2729 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 2730 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 2731
820c1980 2732 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2733 } else {
198a1e9b 2734 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2735 }
2736
198a1e9b 2737 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2738 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2739
820c1980 2740 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 2741
820c1980 2742 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2743}
2744
ed57cb8a
DL		 2745static void
2746ilk_update_sprite_wm(struct drm_plane *plane,
2747 struct drm_crtc *crtc,
2748 uint32_t sprite_width, uint32_t sprite_height,
2749 int pixel_size, bool enabled, bool scaled)
526682e9 2750{
8553c18e 2751 struct drm_device *dev = plane->dev;
adf3d35e 2752 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2753
adf3d35e
VS		 2754 intel_plane->wm.enabled = enabled;
2755 intel_plane->wm.scaled = scaled;
2756 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 2757 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 2758 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2759
8553c18e
VS		 2760 /*
2761 * IVB workaround: must disable low power watermarks for at least
2762 * one frame before enabling scaling. LP watermarks can be re-enabled
2763 * when scaling is disabled.
2764 *
2765 * WaCxSRDisabledForSpriteScaling:ivb
2766 */
2767 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2768 intel_wait_for_vblank(dev, intel_plane->pipe);
2769
820c1980 2770 ilk_update_wm(crtc);
526682e9
PZ		 2771}
2772
243e6a44
VS		 2773static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2774{
2775 struct drm_device *dev = crtc->dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2777 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2779 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2780 enum pipe pipe = intel_crtc->pipe;
2781 static const unsigned int wm0_pipe_reg[] = {
2782 [PIPE_A] = WM0_PIPEA_ILK,
2783 [PIPE_B] = WM0_PIPEB_ILK,
2784 [PIPE_C] = WM0_PIPEC_IVB,
2785 };
2786
2787 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 2788 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2789 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 2790
2a44b76b
VS		 2791 active->pipe_enabled = intel_crtc_active(crtc);
2792
2793 if (active->pipe_enabled) {
243e6a44
VS		 2794 u32 tmp = hw->wm_pipe[pipe];
2795
2796 /*
2797 * For active pipes LP0 watermark is marked as
2798 * enabled, and LP1+ watermaks as disabled since
2799 * we can't really reverse compute them in case
2800 * multiple pipes are active.
2801 */
2802 active->wm[0].enable = true;
2803 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2804 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2805 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2806 active->linetime = hw->wm_linetime[pipe];
2807 } else {
2808 int level, max_level = ilk_wm_max_level(dev);
2809
2810 /*
2811 * For inactive pipes, all watermark levels
2812 * should be marked as enabled but zeroed,
2813 * which is what we'd compute them to.
2814 */
2815 for (level = 0; level <= max_level; level++)
2816 active->wm[level].enable = true;
2817 }
2818}
2819
2820void ilk_wm_get_hw_state(struct drm_device *dev)
2821{
2822 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2823 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2824 struct drm_crtc *crtc;
2825
70e1e0ec 2826 for_each_crtc(dev, crtc)
243e6a44
VS		 2827 ilk_pipe_wm_get_hw_state(crtc);
2828
2829 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2830 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2831 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2832
2833 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 2834 if (INTEL_INFO(dev)->gen >= 7) {
2835 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2836 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2837 }
243e6a44 2838
a42a5719 2839 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 2840 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2841 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2842 else if (IS_IVYBRIDGE(dev))
2843 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2844 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 2845
2846 hw->enable_fbc_wm =
2847 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2848}
2849
b445e3b0
ED		 2850/**
2851 * intel_update_watermarks - update FIFO watermark values based on current modes
2852 *
2853 * Calculate watermark values for the various WM regs based on current mode
2854 * and plane configuration.
2855 *
2856 * There are several cases to deal with here:
2857 * - normal (i.e. non-self-refresh)
2858 * - self-refresh (SR) mode
2859 * - lines are large relative to FIFO size (buffer can hold up to 2)
2860 * - lines are small relative to FIFO size (buffer can hold more than 2
2861 * lines), so need to account for TLB latency
2862 *
2863 * The normal calculation is:
2864 * watermark = dotclock * bytes per pixel * latency
2865 * where latency is platform & configuration dependent (we assume pessimal
2866 * values here).
2867 *
2868 * The SR calculation is:
2869 * watermark = (trunc(latency/line time)+1) * surface width *
2870 * bytes per pixel
2871 * where
2872 * line time = htotal / dotclock
2873 * surface width = hdisplay for normal plane and 64 for cursor
2874 * and latency is assumed to be high, as above.
2875 *
2876 * The final value programmed to the register should always be rounded up,
2877 * and include an extra 2 entries to account for clock crossings.
2878 *
2879 * We don't use the sprite, so we can ignore that. And on Crestline we have
2880 * to set the non-SR watermarks to 8.
2881 */
46ba614c 2882void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 2883{
46ba614c 2884 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 2885
2886 if (dev_priv->display.update_wm)
46ba614c 2887 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 2888}
2889
adf3d35e
VS		 2890void intel_update_sprite_watermarks(struct drm_plane *plane,
2891 struct drm_crtc *crtc,
ed57cb8a
DL		 2892 uint32_t sprite_width,
2893 uint32_t sprite_height,
2894 int pixel_size,
39db4a4d 2895 bool enabled, bool scaled)
b445e3b0 2896{
adf3d35e 2897 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 2898
2899 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 2900 dev_priv->display.update_sprite_wm(plane, crtc,
2901 sprite_width, sprite_height,
39db4a4d 2902 pixel_size, enabled, scaled);
b445e3b0
ED		 2903}
2904
2b4e57bd
ED		 2905static struct drm_i915_gem_object *
2906intel_alloc_context_page(struct drm_device *dev)
2907{
2908 struct drm_i915_gem_object *ctx;
2909 int ret;
2910
2911 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2912
2913 ctx = i915_gem_alloc_object(dev, 4096);
2914 if (!ctx) {
2915 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2916 return NULL;
2917 }
2918
c69766f2 2919 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2b4e57bd
ED		 2920 if (ret) {
2921 DRM_ERROR("failed to pin power context: %d\n", ret);
2922 goto err_unref;
2923 }
2924
2925 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2926 if (ret) {
2927 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2928 goto err_unpin;
2929 }
2930
2931 return ctx;
2932
2933err_unpin:
d7f46fc4 2934 i915_gem_object_ggtt_unpin(ctx);
2b4e57bd
ED		 2935err_unref:
2936 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2937 return NULL;
2938}
2939
9270388e
DV		 2940/**
2941 * Lock protecting IPS related data structures
9270388e
DV		 2942 */
2943DEFINE_SPINLOCK(mchdev_lock);
2944
2945/* Global for IPS driver to get at the current i915 device. Protected by
2946 * mchdev_lock. */
2947static struct drm_i915_private *i915_mch_dev;
2948
2b4e57bd
ED		 2949bool ironlake_set_drps(struct drm_device *dev, u8 val)
2950{
2951 struct drm_i915_private *dev_priv = dev->dev_private;
2952 u16 rgvswctl;
2953
9270388e
DV		 2954 assert_spin_locked(&mchdev_lock);
2955
2b4e57bd
ED		 2956 rgvswctl = I915_READ16(MEMSWCTL);
2957 if (rgvswctl & MEMCTL_CMD_STS) {
2958 DRM_DEBUG("gpu busy, RCS change rejected\n");
2959 return false; /* still busy with another command */
2960 }
2961
2962 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2963 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2964 I915_WRITE16(MEMSWCTL, rgvswctl);
2965 POSTING_READ16(MEMSWCTL);
2966
2967 rgvswctl |= MEMCTL_CMD_STS;
2968 I915_WRITE16(MEMSWCTL, rgvswctl);
2969
2970 return true;
2971}
2972
8090c6b9 2973static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2974{
2975 struct drm_i915_private *dev_priv = dev->dev_private;
2976 u32 rgvmodectl = I915_READ(MEMMODECTL);
2977 u8 fmax, fmin, fstart, vstart;
2978
9270388e
DV		 2979 spin_lock_irq(&mchdev_lock);
2980
2b4e57bd
ED		 2981 /* Enable temp reporting */
2982 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2983 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2984
2985 /* 100ms RC evaluation intervals */
2986 I915_WRITE(RCUPEI, 100000);
2987 I915_WRITE(RCDNEI, 100000);
2988
2989 /* Set max/min thresholds to 90ms and 80ms respectively */
2990 I915_WRITE(RCBMAXAVG, 90000);
2991 I915_WRITE(RCBMINAVG, 80000);
2992
2993 I915_WRITE(MEMIHYST, 1);
2994
2995 /* Set up min, max, and cur for interrupt handling */
2996 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2997 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2998 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2999 MEMMODE_FSTART_SHIFT;
3000
3001 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3002 PXVFREQ_PX_SHIFT;
3003
20e4d407
DV		 3004 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3005 dev_priv->ips.fstart = fstart;
2b4e57bd 3006
20e4d407
DV		 3007 dev_priv->ips.max_delay = fstart;
3008 dev_priv->ips.min_delay = fmin;
3009 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3010
3011 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3012 fmax, fmin, fstart);
3013
3014 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3015
3016 /*
3017 * Interrupts will be enabled in ironlake_irq_postinstall
3018 */
3019
3020 I915_WRITE(VIDSTART, vstart);
3021 POSTING_READ(VIDSTART);
3022
3023 rgvmodectl |= MEMMODE_SWMODE_EN;
3024 I915_WRITE(MEMMODECTL, rgvmodectl);
3025
9270388e 3026 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3027 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3028 mdelay(1);
2b4e57bd
ED		 3029
3030 ironlake_set_drps(dev, fstart);
3031
20e4d407 3032 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3033 I915_READ(0x112e0);
20e4d407
DV		 3034 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3035 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3036 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 3037
3038 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3039}
3040
8090c6b9 3041static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3042{
3043 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3044 u16 rgvswctl;
3045
3046 spin_lock_irq(&mchdev_lock);
3047
3048 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3049
3050 /* Ack interrupts, disable EFC interrupt */
3051 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3052 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3053 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3054 I915_WRITE(DEIIR, DE_PCU_EVENT);
3055 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3056
3057 /* Go back to the starting frequency */
20e4d407 3058 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3059 mdelay(1);
2b4e57bd
ED		 3060 rgvswctl |= MEMCTL_CMD_STS;
3061 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3062 mdelay(1);
2b4e57bd 3063
9270388e 3064 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3065}
3066
acbe9475
DV		 3067/* There's a funny hw issue where the hw returns all 0 when reading from
3068 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3069 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3070 * all limits and the gpu stuck at whatever frequency it is at atm).
3071 */
6917c7b9 3072static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3073{
7b9e0ae6 3074 u32 limits;
2b4e57bd 3075
20b46e59
DV		 3076 /* Only set the down limit when we've reached the lowest level to avoid
3077 * getting more interrupts, otherwise leave this clear. This prevents a
3078 * race in the hw when coming out of rc6: There's a tiny window where
3079 * the hw runs at the minimal clock before selecting the desired
3080 * frequency, if the down threshold expires in that window we will not
3081 * receive a down interrupt. */
b39fb297
BW		 3082 limits = dev_priv->rps.max_freq_softlimit << 24;
3083 if (val <= dev_priv->rps.min_freq_softlimit)
3084 limits |= dev_priv->rps.min_freq_softlimit << 16;
20b46e59
DV		 3085
3086 return limits;
3087}
3088
dd75fdc8
CW		 3089static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3090{
3091 int new_power;
3092
3093 new_power = dev_priv->rps.power;
3094 switch (dev_priv->rps.power) {
3095 case LOW_POWER:
b39fb297 3096 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3097 new_power = BETWEEN;
3098 break;
3099
3100 case BETWEEN:
b39fb297 3101 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3102 new_power = LOW_POWER;
b39fb297 3103 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3104 new_power = HIGH_POWER;
3105 break;
3106
3107 case HIGH_POWER:
b39fb297 3108 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3109 new_power = BETWEEN;
3110 break;
3111 }
3112 /* Max/min bins are special */
b39fb297 3113 if (val == dev_priv->rps.min_freq_softlimit)
dd75fdc8 3114 new_power = LOW_POWER;
b39fb297 3115 if (val == dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3116 new_power = HIGH_POWER;
3117 if (new_power == dev_priv->rps.power)
3118 return;
3119
3120 /* Note the units here are not exactly 1us, but 1280ns. */
3121 switch (new_power) {
3122 case LOW_POWER:
3123 /* Upclock if more than 95% busy over 16ms */
3124 I915_WRITE(GEN6_RP_UP_EI, 12500);
3125 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3126
3127 /* Downclock if less than 85% busy over 32ms */
3128 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3129 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3130
3131 I915_WRITE(GEN6_RP_CONTROL,
3132 GEN6_RP_MEDIA_TURBO |
3133 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3134 GEN6_RP_MEDIA_IS_GFX |
3135 GEN6_RP_ENABLE |
3136 GEN6_RP_UP_BUSY_AVG |
3137 GEN6_RP_DOWN_IDLE_AVG);
3138 break;
3139
3140 case BETWEEN:
3141 /* Upclock if more than 90% busy over 13ms */
3142 I915_WRITE(GEN6_RP_UP_EI, 10250);
3143 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3144
3145 /* Downclock if less than 75% busy over 32ms */
3146 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3147 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3148
3149 I915_WRITE(GEN6_RP_CONTROL,
3150 GEN6_RP_MEDIA_TURBO |
3151 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3152 GEN6_RP_MEDIA_IS_GFX |
3153 GEN6_RP_ENABLE |
3154 GEN6_RP_UP_BUSY_AVG |
3155 GEN6_RP_DOWN_IDLE_AVG);
3156 break;
3157
3158 case HIGH_POWER:
3159 /* Upclock if more than 85% busy over 10ms */
3160 I915_WRITE(GEN6_RP_UP_EI, 8000);
3161 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3162
3163 /* Downclock if less than 60% busy over 32ms */
3164 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3165 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3166
3167 I915_WRITE(GEN6_RP_CONTROL,
3168 GEN6_RP_MEDIA_TURBO |
3169 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3170 GEN6_RP_MEDIA_IS_GFX |
3171 GEN6_RP_ENABLE |
3172 GEN6_RP_UP_BUSY_AVG |
3173 GEN6_RP_DOWN_IDLE_AVG);
3174 break;
3175 }
3176
3177 dev_priv->rps.power = new_power;
3178 dev_priv->rps.last_adj = 0;
3179}
3180
2876ce73
CW		 3181static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3182{
3183 u32 mask = 0;
3184
3185 if (val > dev_priv->rps.min_freq_softlimit)
3186 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3187 if (val < dev_priv->rps.max_freq_softlimit)
3188 mask |= GEN6_PM_RP_UP_THRESHOLD;
3189
7b3c29f6
CW		 3190 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3191 mask &= dev_priv->pm_rps_events;
3192
2876ce73
CW		 3193 /* IVB and SNB hard hangs on looping batchbuffer
3194 * if GEN6_PM_UP_EI_EXPIRED is masked.
3195 */
3196 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3197 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3198
baccd458
D		 3199 if (IS_GEN8(dev_priv->dev))
3200 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3201
2876ce73
CW		 3202 return ~mask;
3203}
3204
b8a5ff8d
JM		 3205/* gen6_set_rps is called to update the frequency request, but should also be
3206 * called when the range (min_delay and max_delay) is modified so that we can
3207 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
20b46e59
DV		 3208void gen6_set_rps(struct drm_device *dev, u8 val)
3209{
3210 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3211
4fc688ce 3212 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3213 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3214 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
004777cb 3215
eb64cad1
CW		 3216 /* min/max delay may still have been modified so be sure to
3217 * write the limits value.
3218 */
3219 if (val != dev_priv->rps.cur_freq) {
3220 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3221
50e6a2a7 3222 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3223 I915_WRITE(GEN6_RPNSWREQ,
3224 HSW_FREQUENCY(val));
3225 else
3226 I915_WRITE(GEN6_RPNSWREQ,
3227 GEN6_FREQUENCY(val) |
3228 GEN6_OFFSET(0) |
3229 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3230 }
7b9e0ae6 3231
7b9e0ae6
CW		 3232 /* Make sure we continue to get interrupts
3233 * until we hit the minimum or maximum frequencies.
3234 */
eb64cad1 3235 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
2876ce73 3236 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3237
d5570a72
BW		 3238 POSTING_READ(GEN6_RPNSWREQ);
3239
b39fb297 3240 dev_priv->rps.cur_freq = val;
be2cde9a 3241 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3242}
3243
76c3552f
D		 3244/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3245 *
3246 * * If Gfx is Idle, then
3247 * 1. Mask Turbo interrupts
3248 * 2. Bring up Gfx clock
3249 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3250 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3251 * 5. Unmask Turbo interrupts
3252*/
3253static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3254{
5549d25f
D		 3255 struct drm_device *dev = dev_priv->dev;
3256
3257 /* Latest VLV doesn't need to force the gfx clock */
3258 if (dev->pdev->revision >= 0xd) {
3259 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3260 return;
3261 }
3262
76c3552f
D		 3263 /*
3264 * When we are idle. Drop to min voltage state.
3265 */
3266
b39fb297 3267 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
76c3552f
D		 3268 return;
3269
3270 /* Mask turbo interrupt so that they will not come in between */
3271 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3272
650ad970 3273 vlv_force_gfx_clock(dev_priv, true);
76c3552f 3274
b39fb297 3275 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
76c3552f
D		 3276
3277 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
b39fb297 3278 dev_priv->rps.min_freq_softlimit);
76c3552f
D		 3279
3280 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3281 & GENFREQSTATUS) == 0, 5))
3282 DRM_ERROR("timed out waiting for Punit\n");
3283
650ad970 3284 vlv_force_gfx_clock(dev_priv, false);
76c3552f 3285
7b3c29f6
CW		 3286 I915_WRITE(GEN6_PMINTRMSK,
3287 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
76c3552f
D		 3288}
3289
b29c19b6
CW		 3290void gen6_rps_idle(struct drm_i915_private *dev_priv)
3291{
691bb717
DL		 3292 struct drm_device *dev = dev_priv->dev;
3293
b29c19b6 3294 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3295 if (dev_priv->rps.enabled) {
34638118
D		 3296 if (IS_CHERRYVIEW(dev))
3297 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3298 else if (IS_VALLEYVIEW(dev))
76c3552f 3299 vlv_set_rps_idle(dev_priv);
c0951f0c 3300 else
b39fb297 3301 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
c0951f0c
CW		 3302 dev_priv->rps.last_adj = 0;
3303 }
b29c19b6
CW		 3304 mutex_unlock(&dev_priv->rps.hw_lock);
3305}
3306
3307void gen6_rps_boost(struct drm_i915_private *dev_priv)
3308{
691bb717
DL		 3309 struct drm_device *dev = dev_priv->dev;
3310
b29c19b6 3311 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3312 if (dev_priv->rps.enabled) {
691bb717 3313 if (IS_VALLEYVIEW(dev))
b39fb297 3314 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c 3315 else
b39fb297 3316 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c
CW		 3317 dev_priv->rps.last_adj = 0;
3318 }
b29c19b6
CW		 3319 mutex_unlock(&dev_priv->rps.hw_lock);
3320}
3321
0a073b84
JB		 3322void valleyview_set_rps(struct drm_device *dev, u8 val)
3323{
3324 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3325
0a073b84 3326 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3327 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3328 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
0a073b84 3329
73008b98 3330 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
b39fb297
BW		 3331 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3332 dev_priv->rps.cur_freq,
2ec3815f 3333 vlv_gpu_freq(dev_priv, val), val);
0a073b84 3334
2876ce73
CW		 3335 if (val != dev_priv->rps.cur_freq)
3336 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3337
09c87db8 3338 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
0a073b84 3339
b39fb297 3340 dev_priv->rps.cur_freq = val;
2ec3815f 3341 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3342}
3343
0961021a
BW		 3344static void gen8_disable_rps_interrupts(struct drm_device *dev)
3345{
3346 struct drm_i915_private *dev_priv = dev->dev_private;
3347
992f191f 3348 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
0961021a
BW		 3349 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3350 ~dev_priv->pm_rps_events);
3351 /* Complete PM interrupt masking here doesn't race with the rps work
3352 * item again unmasking PM interrupts because that is using a different
3353 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3354 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3355 * gen8_enable_rps will clean up. */
3356
3357 spin_lock_irq(&dev_priv->irq_lock);
3358 dev_priv->rps.pm_iir = 0;
3359 spin_unlock_irq(&dev_priv->irq_lock);
3360
3361 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3362}
3363
44fc7d5c 3364static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3365{
3366 struct drm_i915_private *dev_priv = dev->dev_private;
3367
2b4e57bd 3368 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
a6706b45
D		 3369 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3370 ~dev_priv->pm_rps_events);
2b4e57bd
ED		 3371 /* Complete PM interrupt masking here doesn't race with the rps work
3372 * item again unmasking PM interrupts because that is using a different
3373 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3374 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3375
59cdb63d 3376 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3377 dev_priv->rps.pm_iir = 0;
59cdb63d 3378 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3379
a6706b45 3380 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
2b4e57bd
ED		 3381}
3382
44fc7d5c 3383static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3384{
3385 struct drm_i915_private *dev_priv = dev->dev_private;
3386
3387 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3388 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3389
0961021a
BW		 3390 if (IS_BROADWELL(dev))
3391 gen8_disable_rps_interrupts(dev);
3392 else
3393 gen6_disable_rps_interrupts(dev);
44fc7d5c
DV		 3394}
3395
38807746
D		 3396static void cherryview_disable_rps(struct drm_device *dev)
3397{
3398 struct drm_i915_private *dev_priv = dev->dev_private;
3399
3400 I915_WRITE(GEN6_RC_CONTROL, 0);
3497a562
D		 3401
3402 gen8_disable_rps_interrupts(dev);
38807746
D		 3403}
3404
44fc7d5c
DV		 3405static void valleyview_disable_rps(struct drm_device *dev)
3406{
3407 struct drm_i915_private *dev_priv = dev->dev_private;
3408
3409 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3410
44fc7d5c 3411 gen6_disable_rps_interrupts(dev);
d20d4f0c
JB		 3412}
3413
dc39fff7
BW		 3414static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3415{
91ca689a
ID		 3416 if (IS_VALLEYVIEW(dev)) {
3417 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3418 mode = GEN6_RC_CTL_RC6_ENABLE;
3419 else
3420 mode = 0;
3421 }
8dfd1f04
DV		 3422 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3423 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3424 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3425 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
dc39fff7
BW		 3426}
3427
e6069ca8 3428static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 3429{
eb4926e4
DL		 3430 /* No RC6 before Ironlake */
3431 if (INTEL_INFO(dev)->gen < 5)
3432 return 0;
3433
e6069ca8
ID		 3434 /* RC6 is only on Ironlake mobile not on desktop */
3435 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3436 return 0;
3437
456470eb 3438 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 3439 if (enable_rc6 >= 0) {
3440 int mask;
3441
3442 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3443 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3444 INTEL_RC6pp_ENABLE;
3445 else
3446 mask = INTEL_RC6_ENABLE;
3447
3448 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 3449 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3450 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 3451
3452 return enable_rc6 & mask;
3453 }
2b4e57bd 3454
6567d748
CW		 3455 /* Disable RC6 on Ironlake */
3456 if (INTEL_INFO(dev)->gen == 5)
3457 return 0;
2b4e57bd 3458
8bade1ad 3459 if (IS_IVYBRIDGE(dev))
cca84a1f 3460 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 3461
3462 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 3463}
3464
e6069ca8
ID		 3465int intel_enable_rc6(const struct drm_device *dev)
3466{
3467 return i915.enable_rc6;
3468}
3469
0961021a
BW		 3470static void gen8_enable_rps_interrupts(struct drm_device *dev)
3471{
3472 struct drm_i915_private *dev_priv = dev->dev_private;
3473
3474 spin_lock_irq(&dev_priv->irq_lock);
3475 WARN_ON(dev_priv->rps.pm_iir);
480c8033 3476 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
0961021a
BW		 3477 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3478 spin_unlock_irq(&dev_priv->irq_lock);
3479}
3480
44fc7d5c
DV		 3481static void gen6_enable_rps_interrupts(struct drm_device *dev)
3482{
3483 struct drm_i915_private *dev_priv = dev->dev_private;
3484
3485 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3486 WARN_ON(dev_priv->rps.pm_iir);
480c8033 3487 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
a6706b45 3488 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
44fc7d5c 3489 spin_unlock_irq(&dev_priv->irq_lock);
44fc7d5c
DV		 3490}
3491
3280e8b0
BW		 3492static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3493{
3494 /* All of these values are in units of 50MHz */
3495 dev_priv->rps.cur_freq = 0;
3496 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3497 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3498 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3499 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3500 /* XXX: only BYT has a special efficient freq */
3501 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3502 /* hw_max = RP0 until we check for overclocking */
3503 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3504
3505 /* Preserve min/max settings in case of re-init */
3506 if (dev_priv->rps.max_freq_softlimit == 0)
3507 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3508
3509 if (dev_priv->rps.min_freq_softlimit == 0)
3510 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3511}
3512
6edee7f3
BW		 3513static void gen8_enable_rps(struct drm_device *dev)
3514{
3515 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3516 struct intel_engine_cs *ring;
6edee7f3
BW		 3517 uint32_t rc6_mask = 0, rp_state_cap;
3518 int unused;
3519
3520 /* 1a: Software RC state - RC0 */
3521 I915_WRITE(GEN6_RC_STATE, 0);
3522
3523 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3524 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3525 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3526
3527 /* 2a: Disable RC states. */
3528 I915_WRITE(GEN6_RC_CONTROL, 0);
3529
3530 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0 3531 parse_rp_state_cap(dev_priv, rp_state_cap);
6edee7f3
BW		 3532
3533 /* 2b: Program RC6 thresholds.*/
3534 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3535 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3536 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3537 for_each_ring(ring, dev_priv, unused)
3538 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3539 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 3540 if (IS_BROADWELL(dev))
3541 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3542 else
3543 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 3544
3545 /* 3: Enable RC6 */
3546 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3547 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 3548 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 3549 if (IS_BROADWELL(dev))
3550 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3551 GEN7_RC_CTL_TO_MODE |
3552 rc6_mask);
3553 else
3554 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3555 GEN6_RC_CTL_EI_MODE(1) |
3556 rc6_mask);
6edee7f3
BW		 3557
3558 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 3559 I915_WRITE(GEN6_RPNSWREQ,
3560 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3561 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3562 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
6edee7f3
BW		 3563 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3564 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3565
3566 /* Docs recommend 900MHz, and 300 MHz respectively */
3567 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
b39fb297
BW		 3568 dev_priv->rps.max_freq_softlimit << 24 |
3569 dev_priv->rps.min_freq_softlimit << 16);
6edee7f3
BW		 3570
3571 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3572 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3573 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3574 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3575
3576 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3577
3578 /* 5: Enable RPS */
3579 I915_WRITE(GEN6_RP_CONTROL,
3580 GEN6_RP_MEDIA_TURBO |
3581 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7405f42c 3582 GEN6_RP_MEDIA_IS_GFX |
6edee7f3
BW		 3583 GEN6_RP_ENABLE |
3584 GEN6_RP_UP_BUSY_AVG |
3585 GEN6_RP_DOWN_IDLE_AVG);
3586
3587 /* 6: Ring frequency + overclocking (our driver does this later */
3588
3589 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3590
0961021a 3591 gen8_enable_rps_interrupts(dev);
6edee7f3 3592
c8d9a590 3593 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3594}
3595
79f5b2c7 3596static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3597{
79f5b2c7 3598 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3599 struct intel_engine_cs *ring;
2a5913a8 3600 u32 rp_state_cap;
7b9e0ae6 3601 u32 gt_perf_status;
d060c169 3602 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 3603 u32 gtfifodbg;
2b4e57bd 3604 int rc6_mode;
42c0526c 3605 int i, ret;
2b4e57bd 3606
4fc688ce 3607 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3608
2b4e57bd
ED		 3609 /* Here begins a magic sequence of register writes to enable
3610 * auto-downclocking.
3611 *
3612 * Perhaps there might be some value in exposing these to
3613 * userspace...
3614 */
3615 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3616
3617 /* Clear the DBG now so we don't confuse earlier errors */
3618 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3619 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3620 I915_WRITE(GTFIFODBG, gtfifodbg);
3621 }
3622
c8d9a590 3623 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3624
7b9e0ae6
CW		 3625 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3626 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3627
3280e8b0 3628 parse_rp_state_cap(dev_priv, rp_state_cap);
dd0a1aa1 3629
2b4e57bd
ED		 3630 /* disable the counters and set deterministic thresholds */
3631 I915_WRITE(GEN6_RC_CONTROL, 0);
3632
3633 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3634 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3635 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3636 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3637 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3638
b4519513
CW		 3639 for_each_ring(ring, dev_priv, i)
3640 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3641
3642 I915_WRITE(GEN6_RC_SLEEP, 0);
3643 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3644 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3645 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3646 else
3647 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3648 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3649 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3650
5a7dc92a 3651 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3652 rc6_mode = intel_enable_rc6(dev_priv->dev);
3653 if (rc6_mode & INTEL_RC6_ENABLE)
3654 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3655
5a7dc92a
ED		 3656 /* We don't use those on Haswell */
3657 if (!IS_HASWELL(dev)) {
3658 if (rc6_mode & INTEL_RC6p_ENABLE)
3659 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3660
5a7dc92a
ED		 3661 if (rc6_mode & INTEL_RC6pp_ENABLE)
3662 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3663 }
2b4e57bd 3664
dc39fff7 3665 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3666
3667 I915_WRITE(GEN6_RC_CONTROL,
3668 rc6_mask |
3669 GEN6_RC_CTL_EI_MODE(1) |
3670 GEN6_RC_CTL_HW_ENABLE);
3671
dd75fdc8
CW		 3672 /* Power down if completely idle for over 50ms */
3673 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3674 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3675
42c0526c 3676 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 3677 if (ret)
42c0526c 3678 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 3679
3680 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3681 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3682 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 3683 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 3684 (pcu_mbox & 0xff) * 50);
b39fb297 3685 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 3686 }
3687
dd75fdc8 3688 dev_priv->rps.power = HIGH_POWER; /* force a reset */
b39fb297 3689 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
2b4e57bd 3690
44fc7d5c 3691 gen6_enable_rps_interrupts(dev);
2b4e57bd 3692
31643d54
BW		 3693 rc6vids = 0;
3694 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3695 if (IS_GEN6(dev) && ret) {
3696 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3697 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3698 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3699 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3700 rc6vids &= 0xffff00;
3701 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3702 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3703 if (ret)
3704 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3705 }
3706
c8d9a590 3707 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 3708}
3709
c2bc2fc5 3710static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3711{
79f5b2c7 3712 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3713 int min_freq = 15;
3ebecd07
CW		 3714 unsigned int gpu_freq;
3715 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3716 int scaling_factor = 180;
eda79642 3717 struct cpufreq_policy *policy;
2b4e57bd 3718
4fc688ce 3719 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3720
eda79642
BW		 3721 policy = cpufreq_cpu_get(0);
3722 if (policy) {
3723 max_ia_freq = policy->cpuinfo.max_freq;
3724 cpufreq_cpu_put(policy);
3725 } else {
3726 /*
3727 * Default to measured freq if none found, PCU will ensure we
3728 * don't go over
3729 */
2b4e57bd 3730 max_ia_freq = tsc_khz;
eda79642 3731 }
2b4e57bd
ED		 3732
3733 /* Convert from kHz to MHz */
3734 max_ia_freq /= 1000;
3735
153b4b95 3736 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3737 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3738 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3739
2b4e57bd
ED		 3740 /*
3741 * For each potential GPU frequency, load a ring frequency we'd like
3742 * to use for memory access. We do this by specifying the IA frequency
3743 * the PCU should use as a reference to determine the ring frequency.
3744 */
b39fb297 3745 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
2b4e57bd 3746 gpu_freq--) {
b39fb297 3747 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3ebecd07
CW		 3748 unsigned int ia_freq = 0, ring_freq = 0;
3749
46c764d4
BW		 3750 if (INTEL_INFO(dev)->gen >= 8) {
3751 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3752 ring_freq = max(min_ring_freq, gpu_freq);
3753 } else if (IS_HASWELL(dev)) {
f6aca45c 3754 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3755 ring_freq = max(min_ring_freq, ring_freq);
3756 /* leave ia_freq as the default, chosen by cpufreq */
3757 } else {
3758 /* On older processors, there is no separate ring
3759 * clock domain, so in order to boost the bandwidth
3760 * of the ring, we need to upclock the CPU (ia_freq).
3761 *
3762 * For GPU frequencies less than 750MHz,
3763 * just use the lowest ring freq.
3764 */
3765 if (gpu_freq < min_freq)
3766 ia_freq = 800;
3767 else
3768 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3769 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3770 }
2b4e57bd 3771
42c0526c
BW		 3772 sandybridge_pcode_write(dev_priv,
3773 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3774 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3775 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3776 gpu_freq);
2b4e57bd 3777 }
2b4e57bd
ED		 3778}
3779
c2bc2fc5
ID		 3780void gen6_update_ring_freq(struct drm_device *dev)
3781{
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783
3784 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3785 return;
3786
3787 mutex_lock(&dev_priv->rps.hw_lock);
3788 __gen6_update_ring_freq(dev);
3789 mutex_unlock(&dev_priv->rps.hw_lock);
3790}
3791
03af2045 3792static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 3793{
3794 u32 val, rp0;
3795
3796 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3797 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3798
3799 return rp0;
3800}
3801
3802static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3803{
3804 u32 val, rpe;
3805
3806 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
3807 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
3808
3809 return rpe;
3810}
3811
7707df4a
D		 3812static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
3813{
3814 u32 val, rp1;
3815
3816 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3817 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3818
3819 return rp1;
3820}
3821
03af2045 3822static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 3823{
3824 u32 val, rpn;
3825
3826 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3827 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
3828 return rpn;
3829}
3830
f8f2b001
D		 3831static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
3832{
3833 u32 val, rp1;
3834
3835 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3836
3837 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
3838
3839 return rp1;
3840}
3841
03af2045 3842static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 3843{
3844 u32 val, rp0;
3845
64936258 3846 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3847
3848 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3849 /* Clamp to max */
3850 rp0 = min_t(u32, rp0, 0xea);
3851
3852 return rp0;
3853}
3854
3855static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3856{
3857 u32 val, rpe;
3858
64936258 3859 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3860 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3861 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3862 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3863
3864 return rpe;
3865}
3866
03af2045 3867static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 3868{
64936258 3869 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3870}
3871
ae48434c
ID		 3872/* Check that the pctx buffer wasn't move under us. */
3873static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3874{
3875 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3876
3877 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3878 dev_priv->vlv_pctx->stolen->start);
3879}
3880
38807746
D		 3881
3882/* Check that the pcbr address is not empty. */
3883static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
3884{
3885 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3886
3887 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
3888}
3889
3890static void cherryview_setup_pctx(struct drm_device *dev)
3891{
3892 struct drm_i915_private *dev_priv = dev->dev_private;
3893 unsigned long pctx_paddr, paddr;
3894 struct i915_gtt *gtt = &dev_priv->gtt;
3895 u32 pcbr;
3896 int pctx_size = 32*1024;
3897
3898 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3899
3900 pcbr = I915_READ(VLV_PCBR);
3901 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
3902 paddr = (dev_priv->mm.stolen_base +
3903 (gtt->stolen_size - pctx_size));
3904
3905 pctx_paddr = (paddr & (~4095));
3906 I915_WRITE(VLV_PCBR, pctx_paddr);
3907 }
3908}
3909
c9cddffc
JB		 3910static void valleyview_setup_pctx(struct drm_device *dev)
3911{
3912 struct drm_i915_private *dev_priv = dev->dev_private;
3913 struct drm_i915_gem_object *pctx;
3914 unsigned long pctx_paddr;
3915 u32 pcbr;
3916 int pctx_size = 24*1024;
3917
17b0c1f7
ID		 3918 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3919
c9cddffc
JB		 3920 pcbr = I915_READ(VLV_PCBR);
3921 if (pcbr) {
3922 /* BIOS set it up already, grab the pre-alloc'd space */
3923 int pcbr_offset;
3924
3925 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3926 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3927 pcbr_offset,
190d6cd5 3928 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3929 pctx_size);
3930 goto out;
3931 }
3932
3933 /*
3934 * From the Gunit register HAS:
3935 * The Gfx driver is expected to program this register and ensure
3936 * proper allocation within Gfx stolen memory. For example, this
3937 * register should be programmed such than the PCBR range does not
3938 * overlap with other ranges, such as the frame buffer, protected
3939 * memory, or any other relevant ranges.
3940 */
3941 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3942 if (!pctx) {
3943 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3944 return;
3945 }
3946
3947 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3948 I915_WRITE(VLV_PCBR, pctx_paddr);
3949
3950out:
3951 dev_priv->vlv_pctx = pctx;
3952}
3953
ae48434c
ID		 3954static void valleyview_cleanup_pctx(struct drm_device *dev)
3955{
3956 struct drm_i915_private *dev_priv = dev->dev_private;
3957
3958 if (WARN_ON(!dev_priv->vlv_pctx))
3959 return;
3960
3961 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3962 dev_priv->vlv_pctx = NULL;
3963}
3964
4e80519e
ID		 3965static void valleyview_init_gt_powersave(struct drm_device *dev)
3966{
3967 struct drm_i915_private *dev_priv = dev->dev_private;
3968
3969 valleyview_setup_pctx(dev);
3970
3971 mutex_lock(&dev_priv->rps.hw_lock);
3972
3973 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3974 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3975 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3976 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3977 dev_priv->rps.max_freq);
3978
3979 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3980 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3981 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3982 dev_priv->rps.efficient_freq);
3983
f8f2b001
D		 3984 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
3985 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
3986 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
3987 dev_priv->rps.rp1_freq);
3988
4e80519e
ID		 3989 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3990 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3991 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3992 dev_priv->rps.min_freq);
3993
3994 /* Preserve min/max settings in case of re-init */
3995 if (dev_priv->rps.max_freq_softlimit == 0)
3996 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3997
3998 if (dev_priv->rps.min_freq_softlimit == 0)
3999 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4000
4001 mutex_unlock(&dev_priv->rps.hw_lock);
4002}
4003
38807746
D		 4004static void cherryview_init_gt_powersave(struct drm_device *dev)
4005{
2b6b3a09
D		 4006 struct drm_i915_private *dev_priv = dev->dev_private;
4007
38807746 4008 cherryview_setup_pctx(dev);
2b6b3a09
D		 4009
4010 mutex_lock(&dev_priv->rps.hw_lock);
4011
4012 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4013 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4014 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4015 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4016 dev_priv->rps.max_freq);
4017
4018 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4019 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4020 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4021 dev_priv->rps.efficient_freq);
4022
7707df4a
D		 4023 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4024 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4025 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4026 dev_priv->rps.rp1_freq);
4027
2b6b3a09
D		 4028 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4029 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4030 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4031 dev_priv->rps.min_freq);
4032
4033 /* Preserve min/max settings in case of re-init */
4034 if (dev_priv->rps.max_freq_softlimit == 0)
4035 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4036
4037 if (dev_priv->rps.min_freq_softlimit == 0)
4038 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4039
4040 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 4041}
4042
4e80519e
ID		 4043static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4044{
4045 valleyview_cleanup_pctx(dev);
4046}
4047
38807746
D		 4048static void cherryview_enable_rps(struct drm_device *dev)
4049{
4050 struct drm_i915_private *dev_priv = dev->dev_private;
4051 struct intel_engine_cs *ring;
2b6b3a09 4052 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 4053 int i;
4054
4055 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4056
4057 gtfifodbg = I915_READ(GTFIFODBG);
4058 if (gtfifodbg) {
4059 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4060 gtfifodbg);
4061 I915_WRITE(GTFIFODBG, gtfifodbg);
4062 }
4063
4064 cherryview_check_pctx(dev_priv);
4065
4066 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4067 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4068 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4069
4070 /* 2a: Program RC6 thresholds.*/
4071 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4072 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4073 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4074
4075 for_each_ring(ring, dev_priv, i)
4076 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4077 I915_WRITE(GEN6_RC_SLEEP, 0);
4078
4079 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4080
4081 /* allows RC6 residency counter to work */
4082 I915_WRITE(VLV_COUNTER_CONTROL,
4083 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4084 VLV_MEDIA_RC6_COUNT_EN |
4085 VLV_RENDER_RC6_COUNT_EN));
4086
4087 /* For now we assume BIOS is allocating and populating the PCBR */
4088 pcbr = I915_READ(VLV_PCBR);
4089
4090 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4091
4092 /* 3: Enable RC6 */
4093 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4094 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4095 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4096
4097 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4098
2b6b3a09
D		 4099 /* 4 Program defaults and thresholds for RPS*/
4100 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4101 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4102 I915_WRITE(GEN6_RP_UP_EI, 66000);
4103 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4104
4105 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4106
7405f42c
TR		 4107 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4108 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4109 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4110
2b6b3a09
D		 4111 /* 5: Enable RPS */
4112 I915_WRITE(GEN6_RP_CONTROL,
4113 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7405f42c 4114 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
2b6b3a09
D		 4115 GEN6_RP_ENABLE |
4116 GEN6_RP_UP_BUSY_AVG |
4117 GEN6_RP_DOWN_IDLE_AVG);
4118
4119 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4120
4121 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4122 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4123
4124 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4125 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4126 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4127 dev_priv->rps.cur_freq);
4128
4129 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4130 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4131 dev_priv->rps.efficient_freq);
4132
4133 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4134
3497a562
D		 4135 gen8_enable_rps_interrupts(dev);
4136
38807746
D		 4137 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4138}
4139
0a073b84
JB		 4140static void valleyview_enable_rps(struct drm_device *dev)
4141{
4142 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4143 struct intel_engine_cs *ring;
2a5913a8 4144 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 4145 int i;
4146
4147 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4148
ae48434c
ID		 4149 valleyview_check_pctx(dev_priv);
4150
0a073b84 4151 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 4152 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4153 gtfifodbg);
0a073b84
JB		 4154 I915_WRITE(GTFIFODBG, gtfifodbg);
4155 }
4156
c8d9a590
D		 4157 /* If VLV, Forcewake all wells, else re-direct to regular path */
4158 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4159
4160 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4161 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4162 I915_WRITE(GEN6_RP_UP_EI, 66000);
4163 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4164
4165 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
31685c25 4166 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
0a073b84
JB		 4167
4168 I915_WRITE(GEN6_RP_CONTROL,
4169 GEN6_RP_MEDIA_TURBO |
4170 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4171 GEN6_RP_MEDIA_IS_GFX |
4172 GEN6_RP_ENABLE |
4173 GEN6_RP_UP_BUSY_AVG |
4174 GEN6_RP_DOWN_IDLE_CONT);
4175
4176 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4177 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4178 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4179
4180 for_each_ring(ring, dev_priv, i)
4181 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4182
2f0aa304 4183 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 4184
4185 /* allows RC6 residency counter to work */
49798eb2 4186 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 4187 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4188 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 4189 VLV_MEDIA_RC6_COUNT_EN |
4190 VLV_RENDER_RC6_COUNT_EN));
31685c25 4191
a2b23fe0 4192 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 4193 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 4194
4195 intel_print_rc6_info(dev, rc6_mode);
4196
a2b23fe0 4197 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 4198
64936258 4199 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 4200
4201 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4202 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4203
b39fb297 4204 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 4205 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
b39fb297
BW		 4206 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4207 dev_priv->rps.cur_freq);
0a073b84 4208
73008b98 4209 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
b39fb297
BW		 4210 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4211 dev_priv->rps.efficient_freq);
0a073b84 4212
b39fb297 4213 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 4214
44fc7d5c 4215 gen6_enable_rps_interrupts(dev);
0a073b84 4216
c8d9a590 4217 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4218}
4219
930ebb46 4220void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 4221{
4222 struct drm_i915_private *dev_priv = dev->dev_private;
4223
3e373948 4224 if (dev_priv->ips.renderctx) {
d7f46fc4 4225 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3e373948
DV		 4226 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4227 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 4228 }
4229
3e373948 4230 if (dev_priv->ips.pwrctx) {
d7f46fc4 4231 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3e373948
DV		 4232 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4233 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 4234 }
4235}
4236
930ebb46 4237static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4238{
4239 struct drm_i915_private *dev_priv = dev->dev_private;
4240
4241 if (I915_READ(PWRCTXA)) {
4242 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4243 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4244 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4245 50);
4246
4247 I915_WRITE(PWRCTXA, 0);
4248 POSTING_READ(PWRCTXA);
4249
4250 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4251 POSTING_READ(RSTDBYCTL);
4252 }
2b4e57bd
ED		 4253}
4254
4255static int ironlake_setup_rc6(struct drm_device *dev)
4256{
4257 struct drm_i915_private *dev_priv = dev->dev_private;
4258
3e373948
DV		 4259 if (dev_priv->ips.renderctx == NULL)
4260 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4261 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 4262 return -ENOMEM;
4263
3e373948
DV		 4264 if (dev_priv->ips.pwrctx == NULL)
4265 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4266 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 4267 ironlake_teardown_rc6(dev);
4268 return -ENOMEM;
4269 }
4270
4271 return 0;
4272}
4273
930ebb46 4274static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4275{
4276 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4277 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e960501 4278 bool was_interruptible;
2b4e57bd
ED		 4279 int ret;
4280
4281 /* rc6 disabled by default due to repeated reports of hanging during
4282 * boot and resume.
4283 */
4284 if (!intel_enable_rc6(dev))
4285 return;
4286
79f5b2c7
DV		 4287 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4288
2b4e57bd 4289 ret = ironlake_setup_rc6(dev);
79f5b2c7 4290 if (ret)
2b4e57bd 4291 return;
2b4e57bd 4292
3e960501
CW		 4293 was_interruptible = dev_priv->mm.interruptible;
4294 dev_priv->mm.interruptible = false;
4295
2b4e57bd
ED		 4296 /*
4297 * GPU can automatically power down the render unit if given a page
4298 * to save state.
4299 */
6d90c952 4300 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 4301 if (ret) {
4302 ironlake_teardown_rc6(dev);
3e960501 4303 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 4304 return;
4305 }
4306
6d90c952
DV		 4307 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4308 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 4309 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 4310 MI_MM_SPACE_GTT |
4311 MI_SAVE_EXT_STATE_EN |
4312 MI_RESTORE_EXT_STATE_EN |
4313 MI_RESTORE_INHIBIT);
4314 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4315 intel_ring_emit(ring, MI_NOOP);
4316 intel_ring_emit(ring, MI_FLUSH);
4317 intel_ring_advance(ring);
2b4e57bd
ED		 4318
4319 /*
4320 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4321 * does an implicit flush, combined with MI_FLUSH above, it should be
4322 * safe to assume that renderctx is valid
4323 */
3e960501
CW		 4324 ret = intel_ring_idle(ring);
4325 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 4326 if (ret) {
def27a58 4327 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4328 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4329 return;
4330 }
4331
f343c5f6 4332 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4333 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7 4334
91ca689a 4335 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
2b4e57bd
ED		 4336}
4337
dde18883
ED		 4338static unsigned long intel_pxfreq(u32 vidfreq)
4339{
4340 unsigned long freq;
4341 int div = (vidfreq & 0x3f0000) >> 16;
4342 int post = (vidfreq & 0x3000) >> 12;
4343 int pre = (vidfreq & 0x7);
4344
4345 if (!pre)
4346 return 0;
4347
4348 freq = ((div * 133333) / ((1<<post) * pre));
4349
4350 return freq;
4351}
4352
eb48eb00
DV		 4353static const struct cparams {
4354 u16 i;
4355 u16 t;
4356 u16 m;
4357 u16 c;
4358} cparams[] = {
4359 { 1, 1333, 301, 28664 },
4360 { 1, 1066, 294, 24460 },
4361 { 1, 800, 294, 25192 },
4362 { 0, 1333, 276, 27605 },
4363 { 0, 1066, 276, 27605 },
4364 { 0, 800, 231, 23784 },
4365};
4366
f531dcb2 4367static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4368{
4369 u64 total_count, diff, ret;
4370 u32 count1, count2, count3, m = 0, c = 0;
4371 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4372 int i;
4373
02d71956
DV		 4374 assert_spin_locked(&mchdev_lock);
4375
20e4d407 4376 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4377
4378 /* Prevent division-by-zero if we are asking too fast.
4379 * Also, we don't get interesting results if we are polling
4380 * faster than once in 10ms, so just return the saved value
4381 * in such cases.
4382 */
4383 if (diff1 <= 10)
20e4d407 4384 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4385
4386 count1 = I915_READ(DMIEC);
4387 count2 = I915_READ(DDREC);
4388 count3 = I915_READ(CSIEC);
4389
4390 total_count = count1 + count2 + count3;
4391
4392 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4393 if (total_count < dev_priv->ips.last_count1) {
4394 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4395 diff += total_count;
4396 } else {
20e4d407 4397 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4398 }
4399
4400 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4401 if (cparams[i].i == dev_priv->ips.c_m &&
4402 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4403 m = cparams[i].m;
4404 c = cparams[i].c;
4405 break;
4406 }
4407 }
4408
4409 diff = div_u64(diff, diff1);
4410 ret = ((m * diff) + c);
4411 ret = div_u64(ret, 10);
4412
20e4d407
DV		 4413 dev_priv->ips.last_count1 = total_count;
4414 dev_priv->ips.last_time1 = now;
eb48eb00 4415
20e4d407 4416 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4417
4418 return ret;
4419}
4420
f531dcb2
CW		 4421unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4422{
3d13ef2e 4423 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4424 unsigned long val;
4425
3d13ef2e 4426 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4427 return 0;
4428
4429 spin_lock_irq(&mchdev_lock);
4430
4431 val = __i915_chipset_val(dev_priv);
4432
4433 spin_unlock_irq(&mchdev_lock);
4434
4435 return val;
4436}
4437
eb48eb00
DV		 4438unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4439{
4440 unsigned long m, x, b;
4441 u32 tsfs;
4442
4443 tsfs = I915_READ(TSFS);
4444
4445 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4446 x = I915_READ8(TR1);
4447
4448 b = tsfs & TSFS_INTR_MASK;
4449
4450 return ((m * x) / 127) - b;
4451}
4452
4453static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4454{
3d13ef2e 4455 struct drm_device *dev = dev_priv->dev;
eb48eb00
DV		 4456 static const struct v_table {
4457 u16 vd; /* in .1 mil */
4458 u16 vm; /* in .1 mil */
4459 } v_table[] = {
4460 { 0, 0, },
4461 { 375, 0, },
4462 { 500, 0, },
4463 { 625, 0, },
4464 { 750, 0, },
4465 { 875, 0, },
4466 { 1000, 0, },
4467 { 1125, 0, },
4468 { 4125, 3000, },
4469 { 4125, 3000, },
4470 { 4125, 3000, },
4471 { 4125, 3000, },
4472 { 4125, 3000, },
4473 { 4125, 3000, },
4474 { 4125, 3000, },
4475 { 4125, 3000, },
4476 { 4125, 3000, },
4477 { 4125, 3000, },
4478 { 4125, 3000, },
4479 { 4125, 3000, },
4480 { 4125, 3000, },
4481 { 4125, 3000, },
4482 { 4125, 3000, },
4483 { 4125, 3000, },
4484 { 4125, 3000, },
4485 { 4125, 3000, },
4486 { 4125, 3000, },
4487 { 4125, 3000, },
4488 { 4125, 3000, },
4489 { 4125, 3000, },
4490 { 4125, 3000, },
4491 { 4125, 3000, },
4492 { 4250, 3125, },
4493 { 4375, 3250, },
4494 { 4500, 3375, },
4495 { 4625, 3500, },
4496 { 4750, 3625, },
4497 { 4875, 3750, },
4498 { 5000, 3875, },
4499 { 5125, 4000, },
4500 { 5250, 4125, },
4501 { 5375, 4250, },
4502 { 5500, 4375, },
4503 { 5625, 4500, },
4504 { 5750, 4625, },
4505 { 5875, 4750, },
4506 { 6000, 4875, },
4507 { 6125, 5000, },
4508 { 6250, 5125, },
4509 { 6375, 5250, },
4510 { 6500, 5375, },
4511 { 6625, 5500, },
4512 { 6750, 5625, },
4513 { 6875, 5750, },
4514 { 7000, 5875, },
4515 { 7125, 6000, },
4516 { 7250, 6125, },
4517 { 7375, 6250, },
4518 { 7500, 6375, },
4519 { 7625, 6500, },
4520 { 7750, 6625, },
4521 { 7875, 6750, },
4522 { 8000, 6875, },
4523 { 8125, 7000, },
4524 { 8250, 7125, },
4525 { 8375, 7250, },
4526 { 8500, 7375, },
4527 { 8625, 7500, },
4528 { 8750, 7625, },
4529 { 8875, 7750, },
4530 { 9000, 7875, },
4531 { 9125, 8000, },
4532 { 9250, 8125, },
4533 { 9375, 8250, },
4534 { 9500, 8375, },
4535 { 9625, 8500, },
4536 { 9750, 8625, },
4537 { 9875, 8750, },
4538 { 10000, 8875, },
4539 { 10125, 9000, },
4540 { 10250, 9125, },
4541 { 10375, 9250, },
4542 { 10500, 9375, },
4543 { 10625, 9500, },
4544 { 10750, 9625, },
4545 { 10875, 9750, },
4546 { 11000, 9875, },
4547 { 11125, 10000, },
4548 { 11250, 10125, },
4549 { 11375, 10250, },
4550 { 11500, 10375, },
4551 { 11625, 10500, },
4552 { 11750, 10625, },
4553 { 11875, 10750, },
4554 { 12000, 10875, },
4555 { 12125, 11000, },
4556 { 12250, 11125, },
4557 { 12375, 11250, },
4558 { 12500, 11375, },
4559 { 12625, 11500, },
4560 { 12750, 11625, },
4561 { 12875, 11750, },
4562 { 13000, 11875, },
4563 { 13125, 12000, },
4564 { 13250, 12125, },
4565 { 13375, 12250, },
4566 { 13500, 12375, },
4567 { 13625, 12500, },
4568 { 13750, 12625, },
4569 { 13875, 12750, },
4570 { 14000, 12875, },
4571 { 14125, 13000, },
4572 { 14250, 13125, },
4573 { 14375, 13250, },
4574 { 14500, 13375, },
4575 { 14625, 13500, },
4576 { 14750, 13625, },
4577 { 14875, 13750, },
4578 { 15000, 13875, },
4579 { 15125, 14000, },
4580 { 15250, 14125, },
4581 { 15375, 14250, },
4582 { 15500, 14375, },
4583 { 15625, 14500, },
4584 { 15750, 14625, },
4585 { 15875, 14750, },
4586 { 16000, 14875, },
4587 { 16125, 15000, },
4588 };
3d13ef2e 4589 if (INTEL_INFO(dev)->is_mobile)
eb48eb00
DV		 4590 return v_table[pxvid].vm;
4591 else
4592 return v_table[pxvid].vd;
4593}
4594
02d71956 4595static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4596{
4597 struct timespec now, diff1;
4598 u64 diff;
4599 unsigned long diffms;
4600 u32 count;
4601
02d71956 4602 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4603
4604 getrawmonotonic(&now);
20e4d407 4605 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4606
4607 /* Don't divide by 0 */
4608 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4609 if (!diffms)
4610 return;
4611
4612 count = I915_READ(GFXEC);
4613
20e4d407
DV		 4614 if (count < dev_priv->ips.last_count2) {
4615 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4616 diff += count;
4617 } else {
20e4d407 4618 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4619 }
4620
20e4d407
DV		 4621 dev_priv->ips.last_count2 = count;
4622 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4623
4624 /* More magic constants... */
4625 diff = diff * 1181;
4626 diff = div_u64(diff, diffms * 10);
20e4d407 4627 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4628}
4629
02d71956
DV		 4630void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4631{
3d13ef2e
DL		 4632 struct drm_device *dev = dev_priv->dev;
4633
4634 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 4635 return;
4636
9270388e 4637 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4638
4639 __i915_update_gfx_val(dev_priv);
4640
9270388e 4641 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4642}
4643
f531dcb2 4644static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4645{
4646 unsigned long t, corr, state1, corr2, state2;
4647 u32 pxvid, ext_v;
4648
02d71956
DV		 4649 assert_spin_locked(&mchdev_lock);
4650
b39fb297 4651 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 4652 pxvid = (pxvid >> 24) & 0x7f;
4653 ext_v = pvid_to_extvid(dev_priv, pxvid);
4654
4655 state1 = ext_v;
4656
4657 t = i915_mch_val(dev_priv);
4658
4659 /* Revel in the empirically derived constants */
4660
4661 /* Correction factor in 1/100000 units */
4662 if (t > 80)
4663 corr = ((t * 2349) + 135940);
4664 else if (t >= 50)
4665 corr = ((t * 964) + 29317);
4666 else /* < 50 */
4667 corr = ((t * 301) + 1004);
4668
4669 corr = corr * ((150142 * state1) / 10000 - 78642);
4670 corr /= 100000;
20e4d407 4671 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4672
4673 state2 = (corr2 * state1) / 10000;
4674 state2 /= 100; /* convert to mW */
4675
02d71956 4676 __i915_update_gfx_val(dev_priv);
eb48eb00 4677
20e4d407 4678 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4679}
4680
f531dcb2
CW		 4681unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4682{
3d13ef2e 4683 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4684 unsigned long val;
4685
3d13ef2e 4686 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4687 return 0;
4688
4689 spin_lock_irq(&mchdev_lock);
4690
4691 val = __i915_gfx_val(dev_priv);
4692
4693 spin_unlock_irq(&mchdev_lock);
4694
4695 return val;
4696}
4697
eb48eb00
DV		 4698/**
4699 * i915_read_mch_val - return value for IPS use
4700 *
4701 * Calculate and return a value for the IPS driver to use when deciding whether
4702 * we have thermal and power headroom to increase CPU or GPU power budget.
4703 */
4704unsigned long i915_read_mch_val(void)
4705{
4706 struct drm_i915_private *dev_priv;
4707 unsigned long chipset_val, graphics_val, ret = 0;
4708
9270388e 4709 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4710 if (!i915_mch_dev)
4711 goto out_unlock;
4712 dev_priv = i915_mch_dev;
4713
f531dcb2
CW		 4714 chipset_val = __i915_chipset_val(dev_priv);
4715 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4716
4717 ret = chipset_val + graphics_val;
4718
4719out_unlock:
9270388e 4720 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4721
4722 return ret;
4723}
4724EXPORT_SYMBOL_GPL(i915_read_mch_val);
4725
4726/**
4727 * i915_gpu_raise - raise GPU frequency limit
4728 *
4729 * Raise the limit; IPS indicates we have thermal headroom.
4730 */
4731bool i915_gpu_raise(void)
4732{
4733 struct drm_i915_private *dev_priv;
4734 bool ret = true;
4735
9270388e 4736 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4737 if (!i915_mch_dev) {
4738 ret = false;
4739 goto out_unlock;
4740 }
4741 dev_priv = i915_mch_dev;
4742
20e4d407
DV		 4743 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4744 dev_priv->ips.max_delay--;
eb48eb00
DV		 4745
4746out_unlock:
9270388e 4747 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4748
4749 return ret;
4750}
4751EXPORT_SYMBOL_GPL(i915_gpu_raise);
4752
4753/**
4754 * i915_gpu_lower - lower GPU frequency limit
4755 *
4756 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4757 * frequency maximum.
4758 */
4759bool i915_gpu_lower(void)
4760{
4761 struct drm_i915_private *dev_priv;
4762 bool ret = true;
4763
9270388e 4764 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4765 if (!i915_mch_dev) {
4766 ret = false;
4767 goto out_unlock;
4768 }
4769 dev_priv = i915_mch_dev;
4770
20e4d407
DV		 4771 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4772 dev_priv->ips.max_delay++;
eb48eb00
DV		 4773
4774out_unlock:
9270388e 4775 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4776
4777 return ret;
4778}
4779EXPORT_SYMBOL_GPL(i915_gpu_lower);
4780
4781/**
4782 * i915_gpu_busy - indicate GPU business to IPS
4783 *
4784 * Tell the IPS driver whether or not the GPU is busy.
4785 */
4786bool i915_gpu_busy(void)
4787{
4788 struct drm_i915_private *dev_priv;
a4872ba6 4789 struct intel_engine_cs *ring;
eb48eb00 4790 bool ret = false;
f047e395 4791 int i;
eb48eb00 4792
9270388e 4793 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4794 if (!i915_mch_dev)
4795 goto out_unlock;
4796 dev_priv = i915_mch_dev;
4797
f047e395
CW		 4798 for_each_ring(ring, dev_priv, i)
4799 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4800
4801out_unlock:
9270388e 4802 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4803
4804 return ret;
4805}
4806EXPORT_SYMBOL_GPL(i915_gpu_busy);
4807
4808/**
4809 * i915_gpu_turbo_disable - disable graphics turbo
4810 *
4811 * Disable graphics turbo by resetting the max frequency and setting the
4812 * current frequency to the default.
4813 */
4814bool i915_gpu_turbo_disable(void)
4815{
4816 struct drm_i915_private *dev_priv;
4817 bool ret = true;
4818
9270388e 4819 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4820 if (!i915_mch_dev) {
4821 ret = false;
4822 goto out_unlock;
4823 }
4824 dev_priv = i915_mch_dev;
4825
20e4d407 4826 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4827
20e4d407 4828 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4829 ret = false;
4830
4831out_unlock:
9270388e 4832 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4833
4834 return ret;
4835}
4836EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4837
4838/**
4839 * Tells the intel_ips driver that the i915 driver is now loaded, if
4840 * IPS got loaded first.
4841 *
4842 * This awkward dance is so that neither module has to depend on the
4843 * other in order for IPS to do the appropriate communication of
4844 * GPU turbo limits to i915.
4845 */
4846static void
4847ips_ping_for_i915_load(void)
4848{
4849 void (*link)(void);
4850
4851 link = symbol_get(ips_link_to_i915_driver);
4852 if (link) {
4853 link();
4854 symbol_put(ips_link_to_i915_driver);
4855 }
4856}
4857
4858void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4859{
02d71956
DV		 4860 /* We only register the i915 ips part with intel-ips once everything is
4861 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4862 spin_lock_irq(&mchdev_lock);
eb48eb00 4863 i915_mch_dev = dev_priv;
9270388e 4864 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4865
4866 ips_ping_for_i915_load();
4867}
4868
4869void intel_gpu_ips_teardown(void)
4870{
9270388e 4871 spin_lock_irq(&mchdev_lock);
eb48eb00 4872 i915_mch_dev = NULL;
9270388e 4873 spin_unlock_irq(&mchdev_lock);
eb48eb00 4874}
76c3552f 4875
8090c6b9 4876static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4877{
4878 struct drm_i915_private *dev_priv = dev->dev_private;
4879 u32 lcfuse;
4880 u8 pxw[16];
4881 int i;
4882
4883 /* Disable to program */
4884 I915_WRITE(ECR, 0);
4885 POSTING_READ(ECR);
4886
4887 /* Program energy weights for various events */
4888 I915_WRITE(SDEW, 0x15040d00);
4889 I915_WRITE(CSIEW0, 0x007f0000);
4890 I915_WRITE(CSIEW1, 0x1e220004);
4891 I915_WRITE(CSIEW2, 0x04000004);
4892
4893 for (i = 0; i < 5; i++)
4894 I915_WRITE(PEW + (i * 4), 0);
4895 for (i = 0; i < 3; i++)
4896 I915_WRITE(DEW + (i * 4), 0);
4897
4898 /* Program P-state weights to account for frequency power adjustment */
4899 for (i = 0; i < 16; i++) {
4900 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4901 unsigned long freq = intel_pxfreq(pxvidfreq);
4902 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4903 PXVFREQ_PX_SHIFT;
4904 unsigned long val;
4905
4906 val = vid * vid;
4907 val *= (freq / 1000);
4908 val *= 255;
4909 val /= (127*127*900);
4910 if (val > 0xff)
4911 DRM_ERROR("bad pxval: %ld\n", val);
4912 pxw[i] = val;
4913 }
4914 /* Render standby states get 0 weight */
4915 pxw[14] = 0;
4916 pxw[15] = 0;
4917
4918 for (i = 0; i < 4; i++) {
4919 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4920 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4921 I915_WRITE(PXW + (i * 4), val);
4922 }
4923
4924 /* Adjust magic regs to magic values (more experimental results) */
4925 I915_WRITE(OGW0, 0);
4926 I915_WRITE(OGW1, 0);
4927 I915_WRITE(EG0, 0x00007f00);
4928 I915_WRITE(EG1, 0x0000000e);
4929 I915_WRITE(EG2, 0x000e0000);
4930 I915_WRITE(EG3, 0x68000300);
4931 I915_WRITE(EG4, 0x42000000);
4932 I915_WRITE(EG5, 0x00140031);
4933 I915_WRITE(EG6, 0);
4934 I915_WRITE(EG7, 0);
4935
4936 for (i = 0; i < 8; i++)
4937 I915_WRITE(PXWL + (i * 4), 0);
4938
4939 /* Enable PMON + select events */
4940 I915_WRITE(ECR, 0x80000019);
4941
4942 lcfuse = I915_READ(LCFUSE02);
4943
20e4d407 4944 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4945}
4946
ae48434c
ID		 4947void intel_init_gt_powersave(struct drm_device *dev)
4948{
e6069ca8
ID		 4949 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4950
38807746
D		 4951 if (IS_CHERRYVIEW(dev))
4952 cherryview_init_gt_powersave(dev);
4953 else if (IS_VALLEYVIEW(dev))
4e80519e 4954 valleyview_init_gt_powersave(dev);
ae48434c
ID		 4955}
4956
4957void intel_cleanup_gt_powersave(struct drm_device *dev)
4958{
38807746
D		 4959 if (IS_CHERRYVIEW(dev))
4960 return;
4961 else if (IS_VALLEYVIEW(dev))
4e80519e 4962 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 4963}
4964
156c7ca0
JB		 4965/**
4966 * intel_suspend_gt_powersave - suspend PM work and helper threads
4967 * @dev: drm device
4968 *
4969 * We don't want to disable RC6 or other features here, we just want
4970 * to make sure any work we've queued has finished and won't bother
4971 * us while we're suspended.
4972 */
4973void intel_suspend_gt_powersave(struct drm_device *dev)
4974{
4975 struct drm_i915_private *dev_priv = dev->dev_private;
4976
4977 /* Interrupts should be disabled already to avoid re-arming. */
9df7575f 4978 WARN_ON(intel_irqs_enabled(dev_priv));
156c7ca0
JB		 4979
4980 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4981
4982 cancel_work_sync(&dev_priv->rps.work);
b47adc17
D		 4983
4984 /* Force GPU to min freq during suspend */
4985 gen6_rps_idle(dev_priv);
156c7ca0
JB		 4986}
4987
8090c6b9
DV		 4988void intel_disable_gt_powersave(struct drm_device *dev)
4989{
1a01ab3b
JB		 4990 struct drm_i915_private *dev_priv = dev->dev_private;
4991
fd0c0642 4992 /* Interrupts should be disabled already to avoid re-arming. */
9df7575f 4993 WARN_ON(intel_irqs_enabled(dev_priv));
fd0c0642 4994
930ebb46 4995 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4996 ironlake_disable_drps(dev);
930ebb46 4997 ironlake_disable_rc6(dev);
38807746 4998 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 4999 intel_suspend_gt_powersave(dev);
e494837a 5000
4fc688ce 5001 mutex_lock(&dev_priv->rps.hw_lock);
38807746
D		 5002 if (IS_CHERRYVIEW(dev))
5003 cherryview_disable_rps(dev);
5004 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 5005 valleyview_disable_rps(dev);
5006 else
5007 gen6_disable_rps(dev);
c0951f0c 5008 dev_priv->rps.enabled = false;
4fc688ce 5009 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 5010 }
8090c6b9
DV		 5011}
5012
1a01ab3b
JB		 5013static void intel_gen6_powersave_work(struct work_struct *work)
5014{
5015 struct drm_i915_private *dev_priv =
5016 container_of(work, struct drm_i915_private,
5017 rps.delayed_resume_work.work);
5018 struct drm_device *dev = dev_priv->dev;
5019
4fc688ce 5020 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 5021
38807746
D		 5022 if (IS_CHERRYVIEW(dev)) {
5023 cherryview_enable_rps(dev);
5024 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 5025 valleyview_enable_rps(dev);
6edee7f3
BW		 5026 } else if (IS_BROADWELL(dev)) {
5027 gen8_enable_rps(dev);
c2bc2fc5 5028 __gen6_update_ring_freq(dev);
0a073b84
JB		 5029 } else {
5030 gen6_enable_rps(dev);
c2bc2fc5 5031 __gen6_update_ring_freq(dev);
0a073b84 5032 }
c0951f0c 5033 dev_priv->rps.enabled = true;
4fc688ce 5034 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 5035
5036 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 5037}
5038
8090c6b9
DV		 5039void intel_enable_gt_powersave(struct drm_device *dev)
5040{
1a01ab3b
JB		 5041 struct drm_i915_private *dev_priv = dev->dev_private;
5042
8090c6b9 5043 if (IS_IRONLAKE_M(dev)) {
dc1d0136 5044 mutex_lock(&dev->struct_mutex);
8090c6b9
DV		 5045 ironlake_enable_drps(dev);
5046 ironlake_enable_rc6(dev);
5047 intel_init_emon(dev);
dc1d0136 5048 mutex_unlock(&dev->struct_mutex);
38807746 5049 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 5050 /*
5051 * PCU communication is slow and this doesn't need to be
5052 * done at any specific time, so do this out of our fast path
5053 * to make resume and init faster.
c6df39b5
ID		 5054 *
5055 * We depend on the HW RC6 power context save/restore
5056 * mechanism when entering D3 through runtime PM suspend. So
5057 * disable RPM until RPS/RC6 is properly setup. We can only
5058 * get here via the driver load/system resume/runtime resume
5059 * paths, so the _noresume version is enough (and in case of
5060 * runtime resume it's necessary).
1a01ab3b 5061 */
c6df39b5
ID		 5062 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5063 round_jiffies_up_relative(HZ)))
5064 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 5065 }
5066}
5067
c6df39b5
ID		 5068void intel_reset_gt_powersave(struct drm_device *dev)
5069{
5070 struct drm_i915_private *dev_priv = dev->dev_private;
5071
5072 dev_priv->rps.enabled = false;
5073 intel_enable_gt_powersave(dev);
5074}
5075
3107bd48
DV		 5076static void ibx_init_clock_gating(struct drm_device *dev)
5077{
5078 struct drm_i915_private *dev_priv = dev->dev_private;
5079
5080 /*
5081 * On Ibex Peak and Cougar Point, we need to disable clock
5082 * gating for the panel power sequencer or it will fail to
5083 * start up when no ports are active.
5084 */
5085 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5086}
5087
0e088b8f
VS		 5088static void g4x_disable_trickle_feed(struct drm_device *dev)
5089{
5090 struct drm_i915_private *dev_priv = dev->dev_private;
5091 int pipe;
5092
5093 for_each_pipe(pipe) {
5094 I915_WRITE(DSPCNTR(pipe),
5095 I915_READ(DSPCNTR(pipe)) |
5096 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 5097 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 5098 }
5099}
5100
017636cc
VS		 5101static void ilk_init_lp_watermarks(struct drm_device *dev)
5102{
5103 struct drm_i915_private *dev_priv = dev->dev_private;
5104
5105 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5106 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5107 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5108
5109 /*
5110 * Don't touch WM1S_LP_EN here.
5111 * Doing so could cause underruns.
5112 */
5113}
5114
1fa61106 5115static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5116{
5117 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5118 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5119
f1e8fa56
DL		 5120 /*
5121 * Required for FBC
5122 * WaFbcDisableDpfcClockGating:ilk
5123 */
4d47e4f5
DL		 5124 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5125 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5126 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5127
5128 I915_WRITE(PCH_3DCGDIS0,
5129 MARIUNIT_CLOCK_GATE_DISABLE |
5130 SVSMUNIT_CLOCK_GATE_DISABLE);
5131 I915_WRITE(PCH_3DCGDIS1,
5132 VFMUNIT_CLOCK_GATE_DISABLE);
5133
6f1d69b0
ED		 5134 /*
5135 * According to the spec the following bits should be set in
5136 * order to enable memory self-refresh
5137 * The bit 22/21 of 0x42004
5138 * The bit 5 of 0x42020
5139 * The bit 15 of 0x45000
5140 */
5141 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5142 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5143 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5144 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5145 I915_WRITE(DISP_ARB_CTL,
5146 (I915_READ(DISP_ARB_CTL) |
5147 DISP_FBC_WM_DIS));
017636cc
VS		 5148
5149 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 5150
5151 /*
5152 * Based on the document from hardware guys the following bits
5153 * should be set unconditionally in order to enable FBC.
5154 * The bit 22 of 0x42000
5155 * The bit 22 of 0x42004
5156 * The bit 7,8,9 of 0x42020.
5157 */
5158 if (IS_IRONLAKE_M(dev)) {
4bb35334 5159 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5160 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5161 I915_READ(ILK_DISPLAY_CHICKEN1) |
5162 ILK_FBCQ_DIS);
5163 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5164 I915_READ(ILK_DISPLAY_CHICKEN2) |
5165 ILK_DPARB_GATE);
6f1d69b0
ED		 5166 }
5167
4d47e4f5
DL		 5168 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5169
6f1d69b0
ED		 5170 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5171 I915_READ(ILK_DISPLAY_CHICKEN2) |
5172 ILK_ELPIN_409_SELECT);
5173 I915_WRITE(_3D_CHICKEN2,
5174 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5175 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5176
ecdb4eb7 5177 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5178 I915_WRITE(CACHE_MODE_0,
5179 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5180
4e04632e
AG		 5181 /* WaDisable_RenderCache_OperationalFlush:ilk */
5182 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5183
0e088b8f 5184 g4x_disable_trickle_feed(dev);
bdad2b2f 5185
3107bd48
DV		 5186 ibx_init_clock_gating(dev);
5187}
5188
5189static void cpt_init_clock_gating(struct drm_device *dev)
5190{
5191 struct drm_i915_private *dev_priv = dev->dev_private;
5192 int pipe;
3f704fa2 5193 uint32_t val;
3107bd48
DV		 5194
5195 /*
5196 * On Ibex Peak and Cougar Point, we need to disable clock
5197 * gating for the panel power sequencer or it will fail to
5198 * start up when no ports are active.
5199 */
cd664078
JB		 5200 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5201 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5202 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5203 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5204 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5205 /* The below fixes the weird display corruption, a few pixels shifted
5206 * downward, on (only) LVDS of some HP laptops with IVY.
5207 */
3f704fa2 5208 for_each_pipe(pipe) {
dc4bd2d1
PZ		 5209 val = I915_READ(TRANS_CHICKEN2(pipe));
5210 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5211 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5212 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5213 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5214 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5215 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5216 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5217 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5218 }
3107bd48
DV		 5219 /* WADP0ClockGatingDisable */
5220 for_each_pipe(pipe) {
5221 I915_WRITE(TRANS_CHICKEN1(pipe),
5222 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5223 }
6f1d69b0
ED		 5224}
5225
1d7aaa0c
DV		 5226static void gen6_check_mch_setup(struct drm_device *dev)
5227{
5228 struct drm_i915_private *dev_priv = dev->dev_private;
5229 uint32_t tmp;
5230
5231 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 5232 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5233 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5234 tmp);
1d7aaa0c
DV		 5235}
5236
1fa61106 5237static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5238{
5239 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5240 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5241
231e54f6 5242 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5243
5244 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5245 I915_READ(ILK_DISPLAY_CHICKEN2) |
5246 ILK_ELPIN_409_SELECT);
5247
ecdb4eb7 5248 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5249 I915_WRITE(_3D_CHICKEN,
5250 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5251
ecdb4eb7 5252 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 5253 if (IS_SNB_GT1(dev))
5254 I915_WRITE(GEN6_GT_MODE,
5255 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5256
4e04632e
AG		 5257 /* WaDisable_RenderCache_OperationalFlush:snb */
5258 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5259
8d85d272
VS		 5260 /*
5261 * BSpec recoomends 8x4 when MSAA is used,
5262 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5263 *
5264 * Note that PS/WM thread counts depend on the WIZ hashing
5265 * disable bit, which we don't touch here, but it's good
5266 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 5267 */
5268 I915_WRITE(GEN6_GT_MODE,
5269 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5270
017636cc 5271 ilk_init_lp_watermarks(dev);
6f1d69b0 5272
6f1d69b0 5273 I915_WRITE(CACHE_MODE_0,
50743298 5274 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5275
5276 I915_WRITE(GEN6_UCGCTL1,
5277 I915_READ(GEN6_UCGCTL1) |
5278 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5279 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5280
5281 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5282 * gating disable must be set. Failure to set it results in
5283 * flickering pixels due to Z write ordering failures after
5284 * some amount of runtime in the Mesa "fire" demo, and Unigine
5285 * Sanctuary and Tropics, and apparently anything else with
5286 * alpha test or pixel discard.
5287 *
5288 * According to the spec, bit 11 (RCCUNIT) must also be set,
5289 * but we didn't debug actual testcases to find it out.
0f846f81 5290 *
ef59318c
VS		 5291 * WaDisableRCCUnitClockGating:snb
5292 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 5293 */
5294 I915_WRITE(GEN6_UCGCTL2,
5295 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5296 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5297
5eb146dd 5298 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 5299 I915_WRITE(_3D_CHICKEN3,
5300 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 5301
e927ecde
VS		 5302 /*
5303 * Bspec says:
5304 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5305 * 3DSTATE_SF number of SF output attributes is more than 16."
5306 */
5307 I915_WRITE(_3D_CHICKEN3,
5308 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5309
6f1d69b0
ED		 5310 /*
5311 * According to the spec the following bits should be
5312 * set in order to enable memory self-refresh and fbc:
5313 * The bit21 and bit22 of 0x42000
5314 * The bit21 and bit22 of 0x42004
5315 * The bit5 and bit7 of 0x42020
5316 * The bit14 of 0x70180
5317 * The bit14 of 0x71180
4bb35334
DL		 5318 *
5319 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 5320 */
5321 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5322 I915_READ(ILK_DISPLAY_CHICKEN1) |
5323 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5324 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5325 I915_READ(ILK_DISPLAY_CHICKEN2) |
5326 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 5327 I915_WRITE(ILK_DSPCLK_GATE_D,
5328 I915_READ(ILK_DSPCLK_GATE_D) |
5329 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5330 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 5331
0e088b8f 5332 g4x_disable_trickle_feed(dev);
f8f2ac9a 5333
3107bd48 5334 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5335
5336 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5337}
5338
5339static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5340{
5341 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5342
3aad9059 5343 /*
46680e0a 5344 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 5345 *
5346 * This actually overrides the dispatch
5347 * mode for all thread types.
5348 */
6f1d69b0
ED		 5349 reg &= ~GEN7_FF_SCHED_MASK;
5350 reg |= GEN7_FF_TS_SCHED_HW;
5351 reg |= GEN7_FF_VS_SCHED_HW;
5352 reg |= GEN7_FF_DS_SCHED_HW;
5353
5354 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5355}
5356
17a303ec
PZ		 5357static void lpt_init_clock_gating(struct drm_device *dev)
5358{
5359 struct drm_i915_private *dev_priv = dev->dev_private;
5360
5361 /*
5362 * TODO: this bit should only be enabled when really needed, then
5363 * disabled when not needed anymore in order to save power.
5364 */
5365 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5366 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5367 I915_READ(SOUTH_DSPCLK_GATE_D) |
5368 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 5369
5370 /* WADPOClockGatingDisable:hsw */
5371 I915_WRITE(_TRANSA_CHICKEN1,
5372 I915_READ(_TRANSA_CHICKEN1) |
5373 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 5374}
5375
7d708ee4
ID		 5376static void lpt_suspend_hw(struct drm_device *dev)
5377{
5378 struct drm_i915_private *dev_priv = dev->dev_private;
5379
5380 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5381 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5382
5383 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5384 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5385 }
5386}
5387
1020a5c2
BW		 5388static void gen8_init_clock_gating(struct drm_device *dev)
5389{
5390 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 5391 enum pipe pipe;
1020a5c2
BW		 5392
5393 I915_WRITE(WM3_LP_ILK, 0);
5394 I915_WRITE(WM2_LP_ILK, 0);
5395 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 5396
5397 /* FIXME(BDW): Check all the w/a, some might only apply to
5398 * pre-production hw. */
5399
c8966e10
KG		 5400 /* WaDisablePartialInstShootdown:bdw */
5401 I915_WRITE(GEN8_ROW_CHICKEN,
5402 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5403
1411e6a5
KG		 5404 /* WaDisableThreadStallDopClockGating:bdw */
5405 /* FIXME: Unclear whether we really need this on production bdw. */
5406 I915_WRITE(GEN8_ROW_CHICKEN,
5407 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5408
4167e32c
DL		 5409 /*
5410 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5411 * pre-production hardware
5412 */
fd392b60
BW		 5413 I915_WRITE(HALF_SLICE_CHICKEN3,
5414 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 5415 I915_WRITE(HALF_SLICE_CHICKEN3,
5416 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 5417 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5418
7f88da0c 5419 I915_WRITE(_3D_CHICKEN3,
b3f9ad93 5420 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
7f88da0c 5421
a75f3628
BW		 5422 I915_WRITE(COMMON_SLICE_CHICKEN2,
5423 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5424
4c2e7a5f
BW		 5425 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5426 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5427
242a4018
BW		 5428 /* WaDisableDopClockGating:bdw May not be needed for production */
5429 I915_WRITE(GEN7_ROW_CHICKEN2,
5430 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5431
ab57fff1 5432 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 5433 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 5434
ab57fff1 5435 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 5436 I915_WRITE(CHICKEN_PAR1_1,
5437 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5438
ab57fff1 5439 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
07d27e20
DL		 5440 for_each_pipe(pipe) {
5441 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 5442 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 5443 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 5444 }
63801f21
BW		 5445
5446 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5447 * workaround for for a possible hang in the unlikely event a TLB
5448 * invalidation occurs during a PSD flush.
5449 */
5450 I915_WRITE(HDC_CHICKEN0,
5451 I915_READ(HDC_CHICKEN0) |
5452 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
ab57fff1
BW		 5453
5454 /* WaVSRefCountFullforceMissDisable:bdw */
5455 /* WaDSRefCountFullforceMissDisable:bdw */
5456 I915_WRITE(GEN7_FF_THREAD_MODE,
5457 I915_READ(GEN7_FF_THREAD_MODE) &
5458 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c
VS		 5459
5460 /*
5461 * BSpec recommends 8x4 when MSAA is used,
5462 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5463 *
5464 * Note that PS/WM thread counts depend on the WIZ hashing
5465 * disable bit, which we don't touch here, but it's good
5466 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
36075a4c
VS		 5467 */
5468 I915_WRITE(GEN7_GT_MODE,
5469 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
295e8bb7
VS		 5470
5471 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5472 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 5473
5474 /* WaDisableSDEUnitClockGating:bdw */
5475 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5476 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680
DL		 5477
5478 /* Wa4x4STCOptimizationDisable:bdw */
5479 I915_WRITE(CACHE_MODE_1,
5480 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
1020a5c2
BW		 5481}
5482
cad2a2d7
ED		 5483static void haswell_init_clock_gating(struct drm_device *dev)
5484{
5485 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 5486
017636cc 5487 ilk_init_lp_watermarks(dev);
cad2a2d7 5488
f3fc4884
FJ		 5489 /* L3 caching of data atomics doesn't work -- disable it. */
5490 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5491 I915_WRITE(HSW_ROW_CHICKEN3,
5492 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5493
ecdb4eb7 5494 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5495 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5496 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5497 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5498
e36ea7ff
VS		 5499 /* WaVSRefCountFullforceMissDisable:hsw */
5500 I915_WRITE(GEN7_FF_THREAD_MODE,
5501 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 5502
4e04632e
AG		 5503 /* WaDisable_RenderCache_OperationalFlush:hsw */
5504 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5505
fe27c606
CW		 5506 /* enable HiZ Raw Stall Optimization */
5507 I915_WRITE(CACHE_MODE_0_GEN7,
5508 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5509
ecdb4eb7 5510 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5511 I915_WRITE(CACHE_MODE_1,
5512 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5513
a12c4967
VS		 5514 /*
5515 * BSpec recommends 8x4 when MSAA is used,
5516 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5517 *
5518 * Note that PS/WM thread counts depend on the WIZ hashing
5519 * disable bit, which we don't touch here, but it's good
5520 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 5521 */
5522 I915_WRITE(GEN7_GT_MODE,
5523 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5524
ecdb4eb7 5525 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5526 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5527
90a88643
PZ		 5528 /* WaRsPkgCStateDisplayPMReq:hsw */
5529 I915_WRITE(CHICKEN_PAR1_1,
5530 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5531
17a303ec 5532 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5533}
5534
1fa61106 5535static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5536{
5537 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5538 uint32_t snpcr;
6f1d69b0 5539
017636cc 5540 ilk_init_lp_watermarks(dev);
6f1d69b0 5541
231e54f6 5542 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5543
ecdb4eb7 5544 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5545 I915_WRITE(_3D_CHICKEN3,
5546 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5547
ecdb4eb7 5548 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5549 I915_WRITE(IVB_CHICKEN3,
5550 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5551 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5552
ecdb4eb7 5553 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5554 if (IS_IVB_GT1(dev))
5555 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5556 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5557
4e04632e
AG		 5558 /* WaDisable_RenderCache_OperationalFlush:ivb */
5559 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5560
ecdb4eb7 5561 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5562 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5563 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5564
ecdb4eb7 5565 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5566 I915_WRITE(GEN7_L3CNTLREG1,
5567 GEN7_WA_FOR_GEN7_L3_CONTROL);
5568 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5569 GEN7_WA_L3_CHICKEN_MODE);
5570 if (IS_IVB_GT1(dev))
5571 I915_WRITE(GEN7_ROW_CHICKEN2,
5572 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 5573 else {
5574 /* must write both registers */
5575 I915_WRITE(GEN7_ROW_CHICKEN2,
5576 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 5577 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5578 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 5579 }
6f1d69b0 5580
ecdb4eb7 5581 /* WaForceL3Serialization:ivb */
61939d97
JB		 5582 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5583 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5584
1b80a19a 5585 /*
0f846f81 5586 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5587 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5588 */
5589 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 5590 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5591
ecdb4eb7 5592 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5593 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5594 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5595 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5596
0e088b8f 5597 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5598
5599 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5600
22721343
CW		 5601 if (0) { /* causes HiZ corruption on ivb:gt1 */
5602 /* enable HiZ Raw Stall Optimization */
5603 I915_WRITE(CACHE_MODE_0_GEN7,
5604 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5605 }
116f2b6d 5606
ecdb4eb7 5607 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5608 I915_WRITE(CACHE_MODE_1,
5609 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 5610
a607c1a4
VS		 5611 /*
5612 * BSpec recommends 8x4 when MSAA is used,
5613 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5614 *
5615 * Note that PS/WM thread counts depend on the WIZ hashing
5616 * disable bit, which we don't touch here, but it's good
5617 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 5618 */
5619 I915_WRITE(GEN7_GT_MODE,
5620 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5621
20848223
BW		 5622 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5623 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5624 snpcr |= GEN6_MBC_SNPCR_MED;
5625 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5626
ab5c608b
BW		 5627 if (!HAS_PCH_NOP(dev))
5628 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5629
5630 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5631}
5632
1fa61106 5633static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5634{
5635 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 5636 u32 val;
5637
5638 mutex_lock(&dev_priv->rps.hw_lock);
5639 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5640 mutex_unlock(&dev_priv->rps.hw_lock);
5641 switch ((val >> 6) & 3) {
5642 case 0:
f64a28a7 5643 case 1:
f6d51948 5644 dev_priv->mem_freq = 800;
85b1d7b3 5645 break;
f64a28a7 5646 case 2:
f6d51948 5647 dev_priv->mem_freq = 1066;
85b1d7b3 5648 break;
f64a28a7 5649 case 3:
2325991e 5650 dev_priv->mem_freq = 1333;
f64a28a7 5651 break;
85b1d7b3
JB		 5652 }
5653 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 5654
d7fe0cc0 5655 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5656
ecdb4eb7 5657 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5658 I915_WRITE(_3D_CHICKEN3,
5659 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5660
ecdb4eb7 5661 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5662 I915_WRITE(IVB_CHICKEN3,
5663 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5664 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5665
fad7d36e 5666 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 5667 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5668 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5669 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5670 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5671
4e04632e
AG		 5672 /* WaDisable_RenderCache_OperationalFlush:vlv */
5673 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5674
ecdb4eb7 5675 /* WaForceL3Serialization:vlv */
61939d97
JB		 5676 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5677 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5678
ecdb4eb7 5679 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5680 I915_WRITE(GEN7_ROW_CHICKEN2,
5681 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5682
ecdb4eb7 5683 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5684 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5685 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5686 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5687
46680e0a
VS		 5688 gen7_setup_fixed_func_scheduler(dev_priv);
5689
3c0edaeb 5690 /*
0f846f81 5691 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5692 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 5693 */
5694 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 5695 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5696
c98f5062
AG		 5697 /* WaDisableL3Bank2xClockGate:vlv
5698 * Disabling L3 clock gating- MMIO 940c[25] = 1
5699 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5700 I915_WRITE(GEN7_UCGCTL4,
5701 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 5702
e0d8d59b 5703 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5704
afd58e79
VS		 5705 /*
5706 * BSpec says this must be set, even though
5707 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5708 */
6b26c86d
DV		 5709 I915_WRITE(CACHE_MODE_1,
5710 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5711
031994ee
VS		 5712 /*
5713 * WaIncreaseL3CreditsForVLVB0:vlv
5714 * This is the hardware default actually.
5715 */
5716 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5717
2d809570 5718 /*
ecdb4eb7 5719 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5720 * Disable clock gating on th GCFG unit to prevent a delay
5721 * in the reporting of vblank events.
5722 */
7a0d1eed 5723 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 5724}
5725
a4565da8
VS		 5726static void cherryview_init_clock_gating(struct drm_device *dev)
5727{
5728 struct drm_i915_private *dev_priv = dev->dev_private;
67c3bf6f
D		 5729 u32 val;
5730
5731 mutex_lock(&dev_priv->rps.hw_lock);
5732 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
5733 mutex_unlock(&dev_priv->rps.hw_lock);
5734 switch ((val >> 2) & 0x7) {
5735 case 0:
5736 case 1:
5737 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;
5738 dev_priv->mem_freq = 1600;
5739 break;
5740 case 2:
5741 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;
5742 dev_priv->mem_freq = 1600;
5743 break;
5744 case 3:
5745 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;
5746 dev_priv->mem_freq = 2000;
5747 break;
5748 case 4:
5749 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;
5750 dev_priv->mem_freq = 1600;
5751 break;
5752 case 5:
5753 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;
5754 dev_priv->mem_freq = 1600;
5755 break;
5756 }
5757 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
a4565da8
VS		 5758
5759 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5760
5761 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
dd811e70
VS		 5762
5763 /* WaDisablePartialInstShootdown:chv */
5764 I915_WRITE(GEN8_ROW_CHICKEN,
5765 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
a7068025
VS		 5766
5767 /* WaDisableThreadStallDopClockGating:chv */
5768 I915_WRITE(GEN8_ROW_CHICKEN,
5769 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
232ce337
VS		 5770
5771 /* WaVSRefCountFullforceMissDisable:chv */
5772 /* WaDSRefCountFullforceMissDisable:chv */
5773 I915_WRITE(GEN7_FF_THREAD_MODE,
5774 I915_READ(GEN7_FF_THREAD_MODE) &
5775 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 5776
5777 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5778 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5779 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 5780
5781 /* WaDisableCSUnitClockGating:chv */
5782 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5783 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 5784
5785 /* WaDisableSDEUnitClockGating:chv */
5786 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5787 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
e0d34ce7
RB		 5788
5789 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5790 I915_WRITE(HALF_SLICE_CHICKEN3,
5791 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
e4443e45
VS		 5792
5793 /* WaDisableGunitClockGating:chv (pre-production hw) */
5794 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5795 GINT_DIS);
5796
5797 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5798 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5799 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5800
5801 /* WaDisableDopClockGating:chv (pre-production hw) */
5802 I915_WRITE(GEN7_ROW_CHICKEN2,
5803 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5804 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5805 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS		 5806}
5807
1fa61106 5808static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5809{
5810 struct drm_i915_private *dev_priv = dev->dev_private;
5811 uint32_t dspclk_gate;
5812
5813 I915_WRITE(RENCLK_GATE_D1, 0);
5814 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5815 GS_UNIT_CLOCK_GATE_DISABLE |
5816 CL_UNIT_CLOCK_GATE_DISABLE);
5817 I915_WRITE(RAMCLK_GATE_D, 0);
5818 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5819 OVRUNIT_CLOCK_GATE_DISABLE |
5820 OVCUNIT_CLOCK_GATE_DISABLE;
5821 if (IS_GM45(dev))
5822 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5823 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5824
5825 /* WaDisableRenderCachePipelinedFlush */
5826 I915_WRITE(CACHE_MODE_0,
5827 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5828
4e04632e
AG		 5829 /* WaDisable_RenderCache_OperationalFlush:g4x */
5830 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5831
0e088b8f 5832 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5833}
5834
1fa61106 5835static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5836{
5837 struct drm_i915_private *dev_priv = dev->dev_private;
5838
5839 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5840 I915_WRITE(RENCLK_GATE_D2, 0);
5841 I915_WRITE(DSPCLK_GATE_D, 0);
5842 I915_WRITE(RAMCLK_GATE_D, 0);
5843 I915_WRITE16(DEUC, 0);
20f94967
VS		 5844 I915_WRITE(MI_ARB_STATE,
5845 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5846
5847 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5848 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5849}
5850
1fa61106 5851static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5852{
5853 struct drm_i915_private *dev_priv = dev->dev_private;
5854
5855 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5856 I965_RCC_CLOCK_GATE_DISABLE |
5857 I965_RCPB_CLOCK_GATE_DISABLE |
5858 I965_ISC_CLOCK_GATE_DISABLE |
5859 I965_FBC_CLOCK_GATE_DISABLE);
5860 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5861 I915_WRITE(MI_ARB_STATE,
5862 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5863
5864 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5865 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5866}
5867
1fa61106 5868static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5869{
5870 struct drm_i915_private *dev_priv = dev->dev_private;
5871 u32 dstate = I915_READ(D_STATE);
5872
5873 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5874 DSTATE_DOT_CLOCK_GATING;
5875 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5876
5877 if (IS_PINEVIEW(dev))
5878 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5879
5880 /* IIR "flip pending" means done if this bit is set */
5881 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 5882
5883 /* interrupts should cause a wake up from C3 */
3299254f 5884 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 5885
5886 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5887 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6f1d69b0
ED		 5888}
5889
1fa61106 5890static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5891{
5892 struct drm_i915_private *dev_priv = dev->dev_private;
5893
5894 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 5895
5896 /* interrupts should cause a wake up from C3 */
5897 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
5898 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6f1d69b0
ED		 5899}
5900
1fa61106 5901static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5902{
5903 struct drm_i915_private *dev_priv = dev->dev_private;
5904
5905 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5906}
5907
6f1d69b0
ED		 5908void intel_init_clock_gating(struct drm_device *dev)
5909{
5910 struct drm_i915_private *dev_priv = dev->dev_private;
5911
5912 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5913}
5914
7d708ee4
ID		 5915void intel_suspend_hw(struct drm_device *dev)
5916{
5917 if (HAS_PCH_LPT(dev))
5918 lpt_suspend_hw(dev);
5919}
5920
c1ca727f
ID		 5921#define for_each_power_well(i, power_well, domain_mask, power_domains) \
5922 for (i = 0; \
5923 i < (power_domains)->power_well_count && \
5924 ((power_well) = &(power_domains)->power_wells[i]); \
5925 i++) \
5926 if ((power_well)->domains & (domain_mask))
5927
5928#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5929 for (i = (power_domains)->power_well_count - 1; \
5930 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5931 i--) \
5932 if ((power_well)->domains & (domain_mask))
5933
15d199ea
PZ		 5934/**
5935 * We should only use the power well if we explicitly asked the hardware to
5936 * enable it, so check if it's enabled and also check if we've requested it to
5937 * be enabled.
5938 */
da7e29bd 5939static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
c1ca727f
ID		 5940 struct i915_power_well *power_well)
5941{
c1ca727f
ID		 5942 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5943 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5944}
5945
bfafe93a
ID		 5946bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
5947 enum intel_display_power_domain domain)
ddf9c536 5948{
ddf9c536 5949 struct i915_power_domains *power_domains;
b8c000d9
ID		 5950 struct i915_power_well *power_well;
5951 bool is_enabled;
5952 int i;
5953
5954 if (dev_priv->pm.suspended)
5955 return false;
ddf9c536
ID		 5956
5957 power_domains = &dev_priv->power_domains;
bfafe93a 5958
b8c000d9 5959 is_enabled = true;
bfafe93a 5960
b8c000d9
ID		 5961 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5962 if (power_well->always_on)
5963 continue;
ddf9c536 5964
bfafe93a 5965 if (!power_well->hw_enabled) {
b8c000d9
ID		 5966 is_enabled = false;
5967 break;
5968 }
5969 }
bfafe93a 5970
b8c000d9 5971 return is_enabled;
ddf9c536
ID		 5972}
5973
da7e29bd 5974bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
b97186f0 5975 enum intel_display_power_domain domain)
15d199ea 5976{
c1ca727f 5977 struct i915_power_domains *power_domains;
bfafe93a 5978 bool ret;
882244a3 5979
c1ca727f
ID		 5980 power_domains = &dev_priv->power_domains;
5981
c1ca727f 5982 mutex_lock(&power_domains->lock);
bfafe93a 5983 ret = intel_display_power_enabled_unlocked(dev_priv, domain);
c1ca727f
ID		 5984 mutex_unlock(&power_domains->lock);
5985
bfafe93a 5986 return ret;
15d199ea
PZ		 5987}
5988
93c73e8c
ID		 5989/*
5990 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5991 * when not needed anymore. We have 4 registers that can request the power well
5992 * to be enabled, and it will only be disabled if none of the registers is
5993 * requesting it to be enabled.
5994 */
d5e8fdc8
PZ		 5995static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5996{
5997 struct drm_device *dev = dev_priv->dev;
d5e8fdc8 5998
f9dcb0df
PZ		 5999 /*
6000 * After we re-enable the power well, if we touch VGA register 0x3d5
6001 * we'll get unclaimed register interrupts. This stops after we write
6002 * anything to the VGA MSR register. The vgacon module uses this
6003 * register all the time, so if we unbind our driver and, as a
6004 * consequence, bind vgacon, we'll get stuck in an infinite loop at
6005 * console_unlock(). So make here we touch the VGA MSR register, making
6006 * sure vgacon can keep working normally without triggering interrupts
6007 * and error messages.
6008 */
6009 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6010 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
6011 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6012
d49bdb0e
PZ		 6013 if (IS_BROADWELL(dev))
6014 gen8_irq_power_well_post_enable(dev_priv);
d5e8fdc8
PZ		 6015}
6016
da7e29bd 6017static void hsw_set_power_well(struct drm_i915_private *dev_priv,
c1ca727f 6018 struct i915_power_well *power_well, bool enable)
d0d3e513 6019{
fa42e23c
PZ		 6020 bool is_enabled, enable_requested;
6021 uint32_t tmp;
d0d3e513 6022
fa42e23c 6023 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 6024 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
6025 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 6026
fa42e23c
PZ		 6027 if (enable) {
6028 if (!enable_requested)
6aedd1f5
PZ		 6029 I915_WRITE(HSW_PWR_WELL_DRIVER,
6030 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 6031
fa42e23c
PZ		 6032 if (!is_enabled) {
6033 DRM_DEBUG_KMS("Enabling power well\n");
6034 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 6035 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 6036 DRM_ERROR("Timeout enabling power well\n");
6037 }
596cc11e 6038
d5e8fdc8 6039 hsw_power_well_post_enable(dev_priv);
fa42e23c
PZ		 6040 } else {
6041 if (enable_requested) {
6042 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 6043 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 6044 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 6045 }
6046 }
fa42e23c 6047}
d0d3e513 6048
c6cb582e
ID		 6049static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
6050 struct i915_power_well *power_well)
6051{
6052 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
6053
6054 /*
6055 * We're taking over the BIOS, so clear any requests made by it since
6056 * the driver is in charge now.
6057 */
6058 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6059 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6060}
6061
6062static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
6063 struct i915_power_well *power_well)
6064{
c6cb582e
ID		 6065 hsw_set_power_well(dev_priv, power_well, true);
6066}
6067
6068static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
6069 struct i915_power_well *power_well)
6070{
6071 hsw_set_power_well(dev_priv, power_well, false);
c6cb582e
ID		 6072}
6073
a45f4466
ID		 6074static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
6075 struct i915_power_well *power_well)
6076{
6077}
6078
6079static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
6080 struct i915_power_well *power_well)
6081{
6082 return true;
6083}
6084
d2011dc8
VS		 6085static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6086 struct i915_power_well *power_well, bool enable)
77961eb9 6087{
d2011dc8 6088 enum punit_power_well power_well_id = power_well->data;
77961eb9
ID		 6089 u32 mask;
6090 u32 state;
6091 u32 ctrl;
6092
6093 mask = PUNIT_PWRGT_MASK(power_well_id);
6094 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6095 PUNIT_PWRGT_PWR_GATE(power_well_id);
6096
6097 mutex_lock(&dev_priv->rps.hw_lock);
6098
6099#define COND \
6100 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6101
6102 if (COND)
6103 goto out;
6104
6105 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6106 ctrl &= ~mask;
6107 ctrl |= state;
6108 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6109
6110 if (wait_for(COND, 100))
6111 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6112 state,
6113 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6114
6115#undef COND
6116
6117out:
6118 mutex_unlock(&dev_priv->rps.hw_lock);
6119}
6120
6121static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6122 struct i915_power_well *power_well)
6123{
6124 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6125}
6126
6127static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6128 struct i915_power_well *power_well)
6129{
6130 vlv_set_power_well(dev_priv, power_well, true);
6131}
6132
6133static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6134 struct i915_power_well *power_well)
6135{
6136 vlv_set_power_well(dev_priv, power_well, false);
6137}
6138
6139static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6140 struct i915_power_well *power_well)
6141{
6142 int power_well_id = power_well->data;
6143 bool enabled = false;
6144 u32 mask;
6145 u32 state;
6146 u32 ctrl;
6147
6148 mask = PUNIT_PWRGT_MASK(power_well_id);
6149 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6150
6151 mutex_lock(&dev_priv->rps.hw_lock);
6152
6153 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6154 /*
6155 * We only ever set the power-on and power-gate states, anything
6156 * else is unexpected.
6157 */
6158 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6159 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6160 if (state == ctrl)
6161 enabled = true;
6162
6163 /*
6164 * A transient state at this point would mean some unexpected party
6165 * is poking at the power controls too.
6166 */
6167 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6168 WARN_ON(ctrl != state);
6169
6170 mutex_unlock(&dev_priv->rps.hw_lock);
6171
6172 return enabled;
6173}
6174
6175static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6176 struct i915_power_well *power_well)
6177{
6178 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6179
6180 vlv_set_power_well(dev_priv, power_well, true);
6181
6182 spin_lock_irq(&dev_priv->irq_lock);
6183 valleyview_enable_display_irqs(dev_priv);
6184 spin_unlock_irq(&dev_priv->irq_lock);
6185
6186 /*
0d116a29
ID		 6187 * During driver initialization/resume we can avoid restoring the
6188 * part of the HW/SW state that will be inited anyway explicitly.
77961eb9 6189 */
0d116a29
ID		 6190 if (dev_priv->power_domains.initializing)
6191 return;
6192
6193 intel_hpd_init(dev_priv->dev);
77961eb9
ID		 6194
6195 i915_redisable_vga_power_on(dev_priv->dev);
6196}
6197
6198static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6199 struct i915_power_well *power_well)
6200{
77961eb9
ID		 6201 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6202
6203 spin_lock_irq(&dev_priv->irq_lock);
77961eb9
ID		 6204 valleyview_disable_display_irqs(dev_priv);
6205 spin_unlock_irq(&dev_priv->irq_lock);
6206
77961eb9
ID		 6207 vlv_set_power_well(dev_priv, power_well, false);
6208}
6209
aa519f23
VS		 6210static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6211 struct i915_power_well *power_well)
6212{
6213 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6214
6215 /*
6216 * Enable the CRI clock source so we can get at the
6217 * display and the reference clock for VGA
6218 * hotplug / manual detection.
6219 */
6220 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6221 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6222 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6223
6224 vlv_set_power_well(dev_priv, power_well, true);
6225
6226 /*
6227 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6228 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6229 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6230 * b. The other bits such as sfr settings / modesel may all
6231 * be set to 0.
6232 *
6233 * This should only be done on init and resume from S3 with
6234 * both PLLs disabled, or we risk losing DPIO and PLL
6235 * synchronization.
6236 */
6237 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
6238}
6239
6240static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6241 struct i915_power_well *power_well)
6242{
6243 struct drm_device *dev = dev_priv->dev;
6244 enum pipe pipe;
6245
6246 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6247
6248 for_each_pipe(pipe)
6249 assert_pll_disabled(dev_priv, pipe);
6250
6251 /* Assert common reset */
6252 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
6253
6254 vlv_set_power_well(dev_priv, power_well, false);
6255}
6256
5d6f7ea7
VS		 6257static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6258 struct i915_power_well *power_well)
6259{
6260 enum dpio_phy phy;
6261
6262 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6263 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6264
6265 /*
6266 * Enable the CRI clock source so we can get at the
6267 * display and the reference clock for VGA
6268 * hotplug / manual detection.
6269 */
6270 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6271 phy = DPIO_PHY0;
6272 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6273 DPLL_REFA_CLK_ENABLE_VLV);
6274 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6275 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6276 } else {
6277 phy = DPIO_PHY1;
6278 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
6279 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6280 }
6281 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6282 vlv_set_power_well(dev_priv, power_well, true);
6283
6284 /* Poll for phypwrgood signal */
6285 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
6286 DRM_ERROR("Display PHY %d is not power up\n", phy);
6287
6288 I915_WRITE(DISPLAY_PHY_CONTROL,
6289 PHY_COM_LANE_RESET_DEASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL)));
6290}
6291
6292static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6293 struct i915_power_well *power_well)
6294{
6295 enum dpio_phy phy;
6296
6297 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6298 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6299
6300 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6301 phy = DPIO_PHY0;
6302 assert_pll_disabled(dev_priv, PIPE_A);
6303 assert_pll_disabled(dev_priv, PIPE_B);
6304 } else {
6305 phy = DPIO_PHY1;
6306 assert_pll_disabled(dev_priv, PIPE_C);
6307 }
6308
6309 I915_WRITE(DISPLAY_PHY_CONTROL,
6310 PHY_COM_LANE_RESET_ASSERT(phy, I915_READ(DISPLAY_PHY_CONTROL)));
6311
6312 vlv_set_power_well(dev_priv, power_well, false);
6313}
6314
26972b0a
VS		 6315static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
6316 struct i915_power_well *power_well)
6317{
6318 enum pipe pipe = power_well->data;
6319 bool enabled;
6320 u32 state, ctrl;
6321
6322 mutex_lock(&dev_priv->rps.hw_lock);
6323
6324 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
6325 /*
6326 * We only ever set the power-on and power-gate states, anything
6327 * else is unexpected.
6328 */
6329 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
6330 enabled = state == DP_SSS_PWR_ON(pipe);
6331
6332 /*
6333 * A transient state at this point would mean some unexpected party
6334 * is poking at the power controls too.
6335 */
6336 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
6337 WARN_ON(ctrl << 16 != state);
6338
6339 mutex_unlock(&dev_priv->rps.hw_lock);
6340
6341 return enabled;
6342}
6343
6344static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
6345 struct i915_power_well *power_well,
6346 bool enable)
6347{
6348 enum pipe pipe = power_well->data;
6349 u32 state;
6350 u32 ctrl;
6351
6352 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
6353
6354 mutex_lock(&dev_priv->rps.hw_lock);
6355
6356#define COND \
6357 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
6358
6359 if (COND)
6360 goto out;
6361
6362 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6363 ctrl &= ~DP_SSC_MASK(pipe);
6364 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
6365 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
6366
6367 if (wait_for(COND, 100))
6368 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6369 state,
6370 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
6371
6372#undef COND
6373
6374out:
6375 mutex_unlock(&dev_priv->rps.hw_lock);
6376}
6377
6378static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
6379 struct i915_power_well *power_well)
6380{
6381 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
6382}
6383
6384static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
6385 struct i915_power_well *power_well)
6386{
6387 WARN_ON_ONCE(power_well->data != PIPE_A &&
6388 power_well->data != PIPE_B &&
6389 power_well->data != PIPE_C);
6390
6391 chv_set_pipe_power_well(dev_priv, power_well, true);
6392}
6393
6394static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
6395 struct i915_power_well *power_well)
6396{
6397 WARN_ON_ONCE(power_well->data != PIPE_A &&
6398 power_well->data != PIPE_B &&
6399 power_well->data != PIPE_C);
6400
6401 chv_set_pipe_power_well(dev_priv, power_well, false);
6402}
6403
25eaa003
ID		 6404static void check_power_well_state(struct drm_i915_private *dev_priv,
6405 struct i915_power_well *power_well)
6406{
6407 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6408
6409 if (power_well->always_on || !i915.disable_power_well) {
6410 if (!enabled)
6411 goto mismatch;
6412
6413 return;
6414 }
6415
6416 if (enabled != (power_well->count > 0))
6417 goto mismatch;
6418
6419 return;
6420
6421mismatch:
6422 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6423 power_well->name, power_well->always_on, enabled,
6424 power_well->count, i915.disable_power_well);
6425}
6426
da7e29bd 6427void intel_display_power_get(struct drm_i915_private *dev_priv,
6765625e
VS		 6428 enum intel_display_power_domain domain)
6429{
83c00f55 6430 struct i915_power_domains *power_domains;
c1ca727f
ID		 6431 struct i915_power_well *power_well;
6432 int i;
6765625e 6433
9e6ea71a
PZ		 6434 intel_runtime_pm_get(dev_priv);
6435
83c00f55
ID		 6436 power_domains = &dev_priv->power_domains;
6437
6438 mutex_lock(&power_domains->lock);
1da51581 6439
25eaa003
ID		 6440 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6441 if (!power_well->count++) {
6442 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
c6cb582e 6443 power_well->ops->enable(dev_priv, power_well);
bfafe93a 6444 power_well->hw_enabled = true;
25eaa003
ID		 6445 }
6446
6447 check_power_well_state(dev_priv, power_well);
6448 }
1da51581 6449
ddf9c536
ID		 6450 power_domains->domain_use_count[domain]++;
6451
83c00f55 6452 mutex_unlock(&power_domains->lock);
6765625e
VS		 6453}
6454
da7e29bd 6455void intel_display_power_put(struct drm_i915_private *dev_priv,
6765625e
VS		 6456 enum intel_display_power_domain domain)
6457{
83c00f55 6458 struct i915_power_domains *power_domains;
c1ca727f
ID		 6459 struct i915_power_well *power_well;
6460 int i;
6765625e 6461
83c00f55
ID		 6462 power_domains = &dev_priv->power_domains;
6463
6464 mutex_lock(&power_domains->lock);
1da51581 6465
1da51581
ID		 6466 WARN_ON(!power_domains->domain_use_count[domain]);
6467 power_domains->domain_use_count[domain]--;
ddf9c536 6468
70bf407c
ID		 6469 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6470 WARN_ON(!power_well->count);
6471
25eaa003
ID		 6472 if (!--power_well->count && i915.disable_power_well) {
6473 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
bfafe93a 6474 power_well->hw_enabled = false;
c6cb582e 6475 power_well->ops->disable(dev_priv, power_well);
25eaa003
ID		 6476 }
6477
6478 check_power_well_state(dev_priv, power_well);
70bf407c 6479 }
1da51581 6480
83c00f55 6481 mutex_unlock(&power_domains->lock);
9e6ea71a
PZ		 6482
6483 intel_runtime_pm_put(dev_priv);
6765625e
VS		 6484}
6485
83c00f55 6486static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 6487
6488/* Display audio driver power well request */
74b0c2d7 6489int i915_request_power_well(void)
a38911a3 6490{
b4ed4484
ID		 6491 struct drm_i915_private *dev_priv;
6492
74b0c2d7
TI		 6493 if (!hsw_pwr)
6494 return -ENODEV;
a38911a3 6495
b4ed4484
ID		 6496 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6497 power_domains);
da7e29bd 6498 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
74b0c2d7 6499 return 0;
a38911a3
WX		 6500}
6501EXPORT_SYMBOL_GPL(i915_request_power_well);
6502
6503/* Display audio driver power well release */
74b0c2d7 6504int i915_release_power_well(void)
a38911a3 6505{
b4ed4484
ID		 6506 struct drm_i915_private *dev_priv;
6507
74b0c2d7
TI		 6508 if (!hsw_pwr)
6509 return -ENODEV;
a38911a3 6510
b4ed4484
ID		 6511 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6512 power_domains);
da7e29bd 6513 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
74b0c2d7 6514 return 0;
a38911a3
WX		 6515}
6516EXPORT_SYMBOL_GPL(i915_release_power_well);
6517
c149dcb5
JN		 6518/*
6519 * Private interface for the audio driver to get CDCLK in kHz.
6520 *
6521 * Caller must request power well using i915_request_power_well() prior to
6522 * making the call.
6523 */
6524int i915_get_cdclk_freq(void)
6525{
6526 struct drm_i915_private *dev_priv;
6527
6528 if (!hsw_pwr)
6529 return -ENODEV;
6530
6531 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6532 power_domains);
6533
6534 return intel_ddi_get_cdclk_freq(dev_priv);
6535}
6536EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6537
6538
efcad917
ID		 6539#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6540
6541#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6542 BIT(POWER_DOMAIN_PIPE_A) | \
f5938f36 6543 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
319be8ae
ID		 6544 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6545 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6546 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6547 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6548 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6549 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6550 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6551 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6552 BIT(POWER_DOMAIN_PORT_CRT) | \
bd2bb1b9 6553 BIT(POWER_DOMAIN_PLLS) | \
f5938f36 6554 BIT(POWER_DOMAIN_INIT))
efcad917
ID		 6555#define HSW_DISPLAY_POWER_DOMAINS ( \
6556 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6557 BIT(POWER_DOMAIN_INIT))
6558
6559#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6560 HSW_ALWAYS_ON_POWER_DOMAINS | \
6561 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6562#define BDW_DISPLAY_POWER_DOMAINS ( \
6563 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6564 BIT(POWER_DOMAIN_INIT))
6565
77961eb9
ID		 6566#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6567#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6568
6569#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6570 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6571 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6572 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6573 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6574 BIT(POWER_DOMAIN_PORT_CRT) | \
6575 BIT(POWER_DOMAIN_INIT))
6576
6577#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6578 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6579 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6580 BIT(POWER_DOMAIN_INIT))
6581
6582#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6583 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6584 BIT(POWER_DOMAIN_INIT))
6585
6586#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6587 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6588 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6589 BIT(POWER_DOMAIN_INIT))
6590
6591#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6592 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6593 BIT(POWER_DOMAIN_INIT))
6594
26972b0a
VS		 6595#define CHV_PIPE_A_POWER_DOMAINS ( \
6596 BIT(POWER_DOMAIN_PIPE_A) | \
6597 BIT(POWER_DOMAIN_INIT))
6598
6599#define CHV_PIPE_B_POWER_DOMAINS ( \
6600 BIT(POWER_DOMAIN_PIPE_B) | \
6601 BIT(POWER_DOMAIN_INIT))
6602
6603#define CHV_PIPE_C_POWER_DOMAINS ( \
6604 BIT(POWER_DOMAIN_PIPE_C) | \
6605 BIT(POWER_DOMAIN_INIT))
6606
5d6f7ea7
VS		 6607#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6608 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6609 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6610 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6611 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6612 BIT(POWER_DOMAIN_INIT))
6613
6614#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6615 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6616 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6617 BIT(POWER_DOMAIN_INIT))
6618
a45f4466
ID		 6619static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6620 .sync_hw = i9xx_always_on_power_well_noop,
6621 .enable = i9xx_always_on_power_well_noop,
6622 .disable = i9xx_always_on_power_well_noop,
6623 .is_enabled = i9xx_always_on_power_well_enabled,
6624};
c6cb582e 6625
26972b0a
VS		 6626static const struct i915_power_well_ops chv_pipe_power_well_ops = {
6627 .sync_hw = chv_pipe_power_well_sync_hw,
6628 .enable = chv_pipe_power_well_enable,
6629 .disable = chv_pipe_power_well_disable,
6630 .is_enabled = chv_pipe_power_well_enabled,
6631};
6632
5d6f7ea7
VS		 6633static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
6634 .sync_hw = vlv_power_well_sync_hw,
6635 .enable = chv_dpio_cmn_power_well_enable,
6636 .disable = chv_dpio_cmn_power_well_disable,
6637 .is_enabled = vlv_power_well_enabled,
6638};
6639
1c2256df
ID		 6640static struct i915_power_well i9xx_always_on_power_well[] = {
6641 {
6642 .name = "always-on",
6643 .always_on = 1,
6644 .domains = POWER_DOMAIN_MASK,
c6cb582e 6645 .ops = &i9xx_always_on_power_well_ops,
1c2256df
ID		 6646 },
6647};
6648
c6cb582e
ID		 6649static const struct i915_power_well_ops hsw_power_well_ops = {
6650 .sync_hw = hsw_power_well_sync_hw,
6651 .enable = hsw_power_well_enable,
6652 .disable = hsw_power_well_disable,
6653 .is_enabled = hsw_power_well_enabled,
6654};
6655
c1ca727f 6656static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 6657 {
6658 .name = "always-on",
6659 .always_on = 1,
6660 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 6661 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 6662 },
c1ca727f
ID		 6663 {
6664 .name = "display",
efcad917 6665 .domains = HSW_DISPLAY_POWER_DOMAINS,
c6cb582e 6666 .ops = &hsw_power_well_ops,
c1ca727f
ID		 6667 },
6668};
6669
6670static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 6671 {
6672 .name = "always-on",
6673 .always_on = 1,
6674 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 6675 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 6676 },
c1ca727f
ID		 6677 {
6678 .name = "display",
efcad917 6679 .domains = BDW_DISPLAY_POWER_DOMAINS,
c6cb582e 6680 .ops = &hsw_power_well_ops,
c1ca727f
ID		 6681 },
6682};
6683
77961eb9
ID		 6684static const struct i915_power_well_ops vlv_display_power_well_ops = {
6685 .sync_hw = vlv_power_well_sync_hw,
6686 .enable = vlv_display_power_well_enable,
6687 .disable = vlv_display_power_well_disable,
6688 .is_enabled = vlv_power_well_enabled,
6689};
6690
aa519f23
VS		 6691static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
6692 .sync_hw = vlv_power_well_sync_hw,
6693 .enable = vlv_dpio_cmn_power_well_enable,
6694 .disable = vlv_dpio_cmn_power_well_disable,
6695 .is_enabled = vlv_power_well_enabled,
6696};
6697
77961eb9
ID		 6698static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6699 .sync_hw = vlv_power_well_sync_hw,
6700 .enable = vlv_power_well_enable,
6701 .disable = vlv_power_well_disable,
6702 .is_enabled = vlv_power_well_enabled,
6703};
6704
6705static struct i915_power_well vlv_power_wells[] = {
6706 {
6707 .name = "always-on",
6708 .always_on = 1,
6709 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6710 .ops = &i9xx_always_on_power_well_ops,
6711 },
6712 {
6713 .name = "display",
6714 .domains = VLV_DISPLAY_POWER_DOMAINS,
6715 .data = PUNIT_POWER_WELL_DISP2D,
6716 .ops = &vlv_display_power_well_ops,
6717 },
77961eb9
ID		 6718 {
6719 .name = "dpio-tx-b-01",
6720 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6721 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6722 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6723 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6724 .ops = &vlv_dpio_power_well_ops,
6725 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6726 },
6727 {
6728 .name = "dpio-tx-b-23",
6729 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6730 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6731 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6732 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6733 .ops = &vlv_dpio_power_well_ops,
6734 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6735 },
6736 {
6737 .name = "dpio-tx-c-01",
6738 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6739 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6740 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6741 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6742 .ops = &vlv_dpio_power_well_ops,
6743 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6744 },
6745 {
6746 .name = "dpio-tx-c-23",
6747 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6748 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6749 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6750 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6751 .ops = &vlv_dpio_power_well_ops,
6752 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6753 },
f099a3c6
JB		 6754 {
6755 .name = "dpio-common",
6756 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6757 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
aa519f23 6758 .ops = &vlv_dpio_cmn_power_well_ops,
f099a3c6 6759 },
77961eb9
ID		 6760};
6761
4811ff4f
VS		 6762static struct i915_power_well chv_power_wells[] = {
6763 {
6764 .name = "always-on",
6765 .always_on = 1,
6766 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6767 .ops = &i9xx_always_on_power_well_ops,
6768 },
f07057d1
VS		 6769#if 0
6770 {
6771 .name = "display",
6772 .domains = VLV_DISPLAY_POWER_DOMAINS,
6773 .data = PUNIT_POWER_WELL_DISP2D,
6774 .ops = &vlv_display_power_well_ops,
6775 },
26972b0a
VS		 6776 {
6777 .name = "pipe-a",
6778 .domains = CHV_PIPE_A_POWER_DOMAINS,
6779 .data = PIPE_A,
6780 .ops = &chv_pipe_power_well_ops,
6781 },
6782 {
6783 .name = "pipe-b",
6784 .domains = CHV_PIPE_B_POWER_DOMAINS,
6785 .data = PIPE_B,
6786 .ops = &chv_pipe_power_well_ops,
6787 },
6788 {
6789 .name = "pipe-c",
6790 .domains = CHV_PIPE_C_POWER_DOMAINS,
6791 .data = PIPE_C,
6792 .ops = &chv_pipe_power_well_ops,
6793 },
f07057d1 6794#endif
5d6f7ea7
VS		 6795 {
6796 .name = "dpio-common-bc",
6797 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
6798 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6799 .ops = &chv_dpio_cmn_power_well_ops,
6800 },
6801 {
6802 .name = "dpio-common-d",
6803 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
6804 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
6805 .ops = &chv_dpio_cmn_power_well_ops,
6806 },
82583565
VS		 6807#if 0
6808 {
6809 .name = "dpio-tx-b-01",
6810 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6811 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
6812 .ops = &vlv_dpio_power_well_ops,
6813 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6814 },
6815 {
6816 .name = "dpio-tx-b-23",
6817 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6818 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
6819 .ops = &vlv_dpio_power_well_ops,
6820 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6821 },
6822 {
6823 .name = "dpio-tx-c-01",
6824 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6825 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6826 .ops = &vlv_dpio_power_well_ops,
6827 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6828 },
6829 {
6830 .name = "dpio-tx-c-23",
6831 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6832 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6833 .ops = &vlv_dpio_power_well_ops,
6834 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6835 },
6836#endif
4811ff4f
VS		 6837};
6838
d2011dc8
VS		 6839static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
6840 enum punit_power_well power_well_id)
6841{
6842 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6843 struct i915_power_well *power_well;
6844 int i;
6845
6846 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
6847 if (power_well->data == power_well_id)
6848 return power_well;
6849 }
6850
6851 return NULL;
6852}
6853
c1ca727f
ID		 6854#define set_power_wells(power_domains, __power_wells) ({ \
6855 (power_domains)->power_wells = (__power_wells); \
6856 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6857})
6858
da7e29bd 6859int intel_power_domains_init(struct drm_i915_private *dev_priv)
a38911a3 6860{
83c00f55 6861 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 6862
83c00f55 6863 mutex_init(&power_domains->lock);
a38911a3 6864
c1ca727f
ID		 6865 /*
6866 * The enabling order will be from lower to higher indexed wells,
6867 * the disabling order is reversed.
6868 */
da7e29bd 6869 if (IS_HASWELL(dev_priv->dev)) {
c1ca727f
ID		 6870 set_power_wells(power_domains, hsw_power_wells);
6871 hsw_pwr = power_domains;
da7e29bd 6872 } else if (IS_BROADWELL(dev_priv->dev)) {
c1ca727f
ID		 6873 set_power_wells(power_domains, bdw_power_wells);
6874 hsw_pwr = power_domains;
4811ff4f
VS		 6875 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
6876 set_power_wells(power_domains, chv_power_wells);
77961eb9
ID		 6877 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6878 set_power_wells(power_domains, vlv_power_wells);
c1ca727f 6879 } else {
1c2256df 6880 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 6881 }
a38911a3
WX		 6882
6883 return 0;
6884}
6885
da7e29bd 6886void intel_power_domains_remove(struct drm_i915_private *dev_priv)
a38911a3
WX		 6887{
6888 hsw_pwr = NULL;
6889}
6890
da7e29bd 6891static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
9cdb826c 6892{
83c00f55
ID		 6893 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6894 struct i915_power_well *power_well;
c1ca727f 6895 int i;
9cdb826c 6896
83c00f55 6897 mutex_lock(&power_domains->lock);
bfafe93a 6898 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
a45f4466 6899 power_well->ops->sync_hw(dev_priv, power_well);
bfafe93a
ID		 6900 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
6901 power_well);
6902 }
83c00f55 6903 mutex_unlock(&power_domains->lock);
a38911a3
WX		 6904}
6905
d2011dc8
VS		 6906static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
6907{
6908 struct i915_power_well *cmn =
6909 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
6910 struct i915_power_well *disp2d =
6911 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
6912
6913 /* nothing to do if common lane is already off */
6914 if (!cmn->ops->is_enabled(dev_priv, cmn))
6915 return;
6916
6917 /* If the display might be already active skip this */
6918 if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
6919 I915_READ(DPIO_CTL) & DPIO_CMNRST)
6920 return;
6921
6922 DRM_DEBUG_KMS("toggling display PHY side reset\n");
6923
6924 /* cmnlane needs DPLL registers */
6925 disp2d->ops->enable(dev_priv, disp2d);
6926
6927 /*
6928 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
6929 * Need to assert and de-assert PHY SB reset by gating the
6930 * common lane power, then un-gating it.
6931 * Simply ungating isn't enough to reset the PHY enough to get
6932 * ports and lanes running.
6933 */
6934 cmn->ops->disable(dev_priv, cmn);
6935}
6936
da7e29bd 6937void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
d0d3e513 6938{
d2011dc8 6939 struct drm_device *dev = dev_priv->dev;
0d116a29
ID		 6940 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6941
6942 power_domains->initializing = true;
d2011dc8
VS		 6943
6944 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
6945 mutex_lock(&power_domains->lock);
6946 vlv_cmnlane_wa(dev_priv);
6947 mutex_unlock(&power_domains->lock);
6948 }
6949
fa42e23c 6950 /* For now, we need the power well to be always enabled. */
da7e29bd
ID		 6951 intel_display_set_init_power(dev_priv, true);
6952 intel_power_domains_resume(dev_priv);
0d116a29 6953 power_domains->initializing = false;
d0d3e513
ED		 6954}
6955
c67a470b
PZ		 6956void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6957{
d361ae26 6958 intel_runtime_pm_get(dev_priv);
c67a470b
PZ		 6959}
6960
6961void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6962{
d361ae26 6963 intel_runtime_pm_put(dev_priv);
c67a470b
PZ		 6964}
6965
8a187455
PZ		 6966void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6967{
6968 struct drm_device *dev = dev_priv->dev;
6969 struct device *device = &dev->pdev->dev;
6970
6971 if (!HAS_RUNTIME_PM(dev))
6972 return;
6973
6974 pm_runtime_get_sync(device);
6975 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6976}
6977
c6df39b5
ID		 6978void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
6979{
6980 struct drm_device *dev = dev_priv->dev;
6981 struct device *device = &dev->pdev->dev;
6982
6983 if (!HAS_RUNTIME_PM(dev))
6984 return;
6985
6986 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
6987 pm_runtime_get_noresume(device);
6988}
6989
8a187455
PZ		 6990void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6991{
6992 struct drm_device *dev = dev_priv->dev;
6993 struct device *device = &dev->pdev->dev;
6994
6995 if (!HAS_RUNTIME_PM(dev))
6996 return;
6997
6998 pm_runtime_mark_last_busy(device);
6999 pm_runtime_put_autosuspend(device);
7000}
7001
7002void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
7003{
7004 struct drm_device *dev = dev_priv->dev;
7005 struct device *device = &dev->pdev->dev;
7006
8a187455
PZ		 7007 if (!HAS_RUNTIME_PM(dev))
7008 return;
7009
7010 pm_runtime_set_active(device);
7011
aeab0b5a
ID		 7012 /*
7013 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7014 * requirement.
7015 */
7016 if (!intel_enable_rc6(dev)) {
7017 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7018 return;
7019 }
7020
8a187455
PZ		 7021 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
7022 pm_runtime_mark_last_busy(device);
7023 pm_runtime_use_autosuspend(device);
ba0239e0
PZ		 7024
7025 pm_runtime_put_autosuspend(device);
8a187455
PZ		 7026}
7027
7028void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
7029{
7030 struct drm_device *dev = dev_priv->dev;
7031 struct device *device = &dev->pdev->dev;
7032
7033 if (!HAS_RUNTIME_PM(dev))
7034 return;
7035
aeab0b5a
ID		 7036 if (!intel_enable_rc6(dev))
7037 return;
7038
8a187455
PZ		 7039 /* Make sure we're not suspended first. */
7040 pm_runtime_get_sync(device);
7041 pm_runtime_disable(device);
7042}
7043
1fa61106
ED		 7044/* Set up chip specific power management-related functions */
7045void intel_init_pm(struct drm_device *dev)
7046{
7047 struct drm_i915_private *dev_priv = dev->dev_private;
7048
3a77c4c4 7049 if (HAS_FBC(dev)) {
40045465 7050 if (INTEL_INFO(dev)->gen >= 7) {
1fa61106 7051 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
40045465
VS		 7052 dev_priv->display.enable_fbc = gen7_enable_fbc;
7053 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7054 } else if (INTEL_INFO(dev)->gen >= 5) {
7055 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7056 dev_priv->display.enable_fbc = ironlake_enable_fbc;
1fa61106
ED		 7057 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7058 } else if (IS_GM45(dev)) {
7059 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7060 dev_priv->display.enable_fbc = g4x_enable_fbc;
7061 dev_priv->display.disable_fbc = g4x_disable_fbc;
40045465 7062 } else {
1fa61106
ED		 7063 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7064 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7065 dev_priv->display.disable_fbc = i8xx_disable_fbc;
993495ae
VS		 7066
7067 /* This value was pulled out of someone's hat */
7068 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1fa61106 7069 }
1fa61106
ED		 7070 }
7071
c921aba8
DV		 7072 /* For cxsr */
7073 if (IS_PINEVIEW(dev))
7074 i915_pineview_get_mem_freq(dev);
7075 else if (IS_GEN5(dev))
7076 i915_ironlake_get_mem_freq(dev);
7077
1fa61106
ED		 7078 /* For FIFO watermark updates */
7079 if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7080 ilk_setup_wm_latency(dev);
53615a5e 7081
bd602544
VS		 7082 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7083 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7084 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7085 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7086 dev_priv->display.update_wm = ilk_update_wm;
7087 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7088 } else {
7089 DRM_DEBUG_KMS("Failed to read display plane latency. "
7090 "Disable CxSR\n");
7091 }
7092
7093 if (IS_GEN5(dev))
1fa61106 7094 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7095 else if (IS_GEN6(dev))
1fa61106 7096 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7097 else if (IS_IVYBRIDGE(dev))
1fa61106 7098 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7099 else if (IS_HASWELL(dev))
cad2a2d7 7100 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7101 else if (INTEL_INFO(dev)->gen == 8)
1020a5c2 7102 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
a4565da8
VS		 7103 } else if (IS_CHERRYVIEW(dev)) {
7104 dev_priv->display.update_wm = valleyview_update_wm;
7105 dev_priv->display.init_clock_gating =
7106 cherryview_init_clock_gating;
1fa61106
ED		 7107 } else if (IS_VALLEYVIEW(dev)) {
7108 dev_priv->display.update_wm = valleyview_update_wm;
7109 dev_priv->display.init_clock_gating =
7110 valleyview_init_clock_gating;
1fa61106
ED		 7111 } else if (IS_PINEVIEW(dev)) {
7112 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7113 dev_priv->is_ddr3,
7114 dev_priv->fsb_freq,
7115 dev_priv->mem_freq)) {
7116 DRM_INFO("failed to find known CxSR latency "
7117 "(found ddr%s fsb freq %d, mem freq %d), "
7118 "disabling CxSR\n",
7119 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7120 dev_priv->fsb_freq, dev_priv->mem_freq);
7121 /* Disable CxSR and never update its watermark again */
5209b1f4 7122 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7123 dev_priv->display.update_wm = NULL;
7124 } else
7125 dev_priv->display.update_wm = pineview_update_wm;
7126 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7127 } else if (IS_G4X(dev)) {
7128 dev_priv->display.update_wm = g4x_update_wm;
7129 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7130 } else if (IS_GEN4(dev)) {
7131 dev_priv->display.update_wm = i965_update_wm;
7132 if (IS_CRESTLINE(dev))
7133 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7134 else if (IS_BROADWATER(dev))
7135 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7136 } else if (IS_GEN3(dev)) {
7137 dev_priv->display.update_wm = i9xx_update_wm;
7138 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7139 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7140 } else if (IS_GEN2(dev)) {
7141 if (INTEL_INFO(dev)->num_pipes == 1) {
7142 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7143 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7144 } else {
7145 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7146 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7147 }
7148
7149 if (IS_I85X(dev) || IS_I865G(dev))
7150 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7151 else
7152 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7153 } else {
7154 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7155 }
7156}
7157
42c0526c
BW		 7158int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
7159{
4fc688ce 7160 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7161
7162 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7163 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7164 return -EAGAIN;
7165 }
7166
7167 I915_WRITE(GEN6_PCODE_DATA, *val);
7168 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7169
7170 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7171 500)) {
7172 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7173 return -ETIMEDOUT;
7174 }
7175
7176 *val = I915_READ(GEN6_PCODE_DATA);
7177 I915_WRITE(GEN6_PCODE_DATA, 0);
7178
7179 return 0;
7180}
7181
7182int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
7183{
4fc688ce 7184 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7185
7186 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7187 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7188 return -EAGAIN;
7189 }
7190
7191 I915_WRITE(GEN6_PCODE_DATA, val);
7192 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7193
7194 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7195 500)) {
7196 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7197 return -ETIMEDOUT;
7198 }
7199
7200 I915_WRITE(GEN6_PCODE_DATA, 0);
7201
7202 return 0;
7203}
a0e4e199 7204
b55dd647 7205static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 7206{
07ab118b 7207 int div;
855ba3be 7208
07ab118b 7209 /* 4 x czclk */
2ec3815f 7210 switch (dev_priv->mem_freq) {
855ba3be 7211 case 800:
07ab118b 7212 div = 10;
855ba3be
JB		 7213 break;
7214 case 1066:
07ab118b 7215 div = 12;
855ba3be
JB		 7216 break;
7217 case 1333:
07ab118b 7218 div = 16;
855ba3be
JB		 7219 break;
7220 default:
7221 return -1;
7222 }
7223
2ec3815f 7224 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 7225}
7226
b55dd647 7227static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7228{
07ab118b 7229 int mul;
855ba3be 7230
07ab118b 7231 /* 4 x czclk */
2ec3815f 7232 switch (dev_priv->mem_freq) {
855ba3be 7233 case 800:
07ab118b 7234 mul = 10;
855ba3be
JB		 7235 break;
7236 case 1066:
07ab118b 7237 mul = 12;
855ba3be
JB		 7238 break;
7239 case 1333:
07ab118b 7240 mul = 16;
855ba3be
JB		 7241 break;
7242 default:
7243 return -1;
7244 }
7245
2ec3815f 7246 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 7247}
7248
b55dd647 7249static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8
D		 7250{
7251 int div, freq;
7252
7253 switch (dev_priv->rps.cz_freq) {
7254 case 200:
7255 div = 5;
7256 break;
7257 case 267:
7258 div = 6;
7259 break;
7260 case 320:
7261 case 333:
7262 case 400:
7263 div = 8;
7264 break;
7265 default:
7266 return -1;
7267 }
7268
7269 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
7270
7271 return freq;
7272}
7273
b55dd647 7274static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8
D		 7275{
7276 int mul, opcode;
7277
7278 switch (dev_priv->rps.cz_freq) {
7279 case 200:
7280 mul = 5;
7281 break;
7282 case 267:
7283 mul = 6;
7284 break;
7285 case 320:
7286 case 333:
7287 case 400:
7288 mul = 8;
7289 break;
7290 default:
7291 return -1;
7292 }
7293
7294 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7295
7296 return opcode;
7297}
7298
7299int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7300{
7301 int ret = -1;
7302
7303 if (IS_CHERRYVIEW(dev_priv->dev))
7304 ret = chv_gpu_freq(dev_priv, val);
7305 else if (IS_VALLEYVIEW(dev_priv->dev))
7306 ret = byt_gpu_freq(dev_priv, val);
7307
7308 return ret;
7309}
7310
7311int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7312{
7313 int ret = -1;
7314
7315 if (IS_CHERRYVIEW(dev_priv->dev))
7316 ret = chv_freq_opcode(dev_priv, val);
7317 else if (IS_VALLEYVIEW(dev_priv->dev))
7318 ret = byt_freq_opcode(dev_priv, val);
7319
7320 return ret;
7321}
7322
f742a552 7323void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7324{
7325 struct drm_i915_private *dev_priv = dev->dev_private;
7326
f742a552
DV		 7327 mutex_init(&dev_priv->rps.hw_lock);
7328
907b28c5
CW		 7329 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7330 intel_gen6_powersave_work);
5d584b2e 7331
33688d95 7332 dev_priv->pm.suspended = false;
9df7575f 7333 dev_priv->pm._irqs_disabled = false;
907b28c5 7334}
Linux kernel - Deliverables
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