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drm/i915: Document that the pll->mode_set hook is optional
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f9dcb0df 33#include <linux/vgaarb.h>
f4db9321 34#include <drm/i915_powerwell.h>
8a187455 35#include <linux/pm_runtime.h>
85208be0 36
dc39fff7
BW		 37/**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
f6750b3c
ED		 58/* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 61 *
f6750b3c
ED		 62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
85208be0 64 *
f6750b3c
ED		 65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
85208be0
ED		 67 */
68
1fa61106 69static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89}
90
993495ae 91static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 92{
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 95 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 96 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0
ED		 97 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
98 int cfb_pitch;
7f2cf220 99 int i;
159f9875 100 u32 fbc_ctl;
85208be0 101
5c3fe8b0 102 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 103 if (fb->pitches[0] < cfb_pitch)
104 cfb_pitch = fb->pitches[0];
105
42a430f5
VS		 106 /* FBC_CTL wants 32B or 64B units */
107 if (IS_GEN2(dev))
108 cfb_pitch = (cfb_pitch / 32) - 1;
109 else
110 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 111
112 /* Clear old tags */
113 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
114 I915_WRITE(FBC_TAG + (i * 4), 0);
115
159f9875
VS		 116 if (IS_GEN4(dev)) {
117 u32 fbc_ctl2;
118
119 /* Set it up... */
120 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
7f2cf220 121 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
159f9875
VS		 122 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
123 I915_WRITE(FBC_FENCE_OFF, crtc->y);
124 }
85208be0
ED		 125
126 /* enable it... */
993495ae
VS		 127 fbc_ctl = I915_READ(FBC_CONTROL);
128 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
129 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 130 if (IS_I945GM(dev))
131 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
132 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 133 fbc_ctl |= obj->fence_reg;
134 I915_WRITE(FBC_CONTROL, fbc_ctl);
135
5cd5410e 136 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
84f44ce7 137 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 138}
139
1fa61106 140static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
145}
146
993495ae 147static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 148{
149 struct drm_device *dev = crtc->dev;
150 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 151 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 152 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0 153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 154 u32 dpfc_ctl;
155
3fa2e0ee
VS		 156 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
157 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
158 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
159 else
160 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
85208be0 161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
85208be0 162
85208be0
ED		 163 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
164
165 /* enable it... */
fe74c1a5 166 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
85208be0 167
84f44ce7 168 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 169}
170
1fa61106 171static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 172{
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 u32 dpfc_ctl;
175
176 /* Disable compression */
177 dpfc_ctl = I915_READ(DPFC_CONTROL);
178 if (dpfc_ctl & DPFC_CTL_EN) {
179 dpfc_ctl &= ~DPFC_CTL_EN;
180 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
181
182 DRM_DEBUG_KMS("disabled FBC\n");
183 }
184}
185
1fa61106 186static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 187{
188 struct drm_i915_private *dev_priv = dev->dev_private;
189
190 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
191}
192
193static void sandybridge_blit_fbc_update(struct drm_device *dev)
194{
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 u32 blt_ecoskpd;
197
198 /* Make sure blitter notifies FBC of writes */
940aece4
D		 199
200 /* Blitter is part of Media powerwell on VLV. No impact of
201 * his param in other platforms for now */
202 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 203
85208be0
ED		 204 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
205 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
206 GEN6_BLITTER_LOCK_SHIFT;
207 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
208 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
211 GEN6_BLITTER_LOCK_SHIFT);
212 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
213 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 214
940aece4 215 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 216}
217
993495ae 218static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 219{
220 struct drm_device *dev = crtc->dev;
221 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 222 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 223 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0 224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 225 u32 dpfc_ctl;
226
46f3dab9 227 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
3fa2e0ee 228 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
5e59f717
BW		 229 dev_priv->fbc.threshold++;
230
231 switch (dev_priv->fbc.threshold) {
232 case 4:
233 case 3:
234 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
235 break;
236 case 2:
3fa2e0ee 237 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
5e59f717
BW		 238 break;
239 case 1:
3fa2e0ee 240 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
5e59f717
BW		 241 break;
242 }
d629336b
VS		 243 dpfc_ctl |= DPFC_CTL_FENCE_EN;
244 if (IS_GEN5(dev))
245 dpfc_ctl |= obj->fence_reg;
85208be0 246
85208be0 247 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 248 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 249 /* enable it... */
250 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
251
252 if (IS_GEN6(dev)) {
253 I915_WRITE(SNB_DPFC_CTL_SA,
254 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
255 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
256 sandybridge_blit_fbc_update(dev);
257 }
258
84f44ce7 259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 260}
261
1fa61106 262static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 263{
264 struct drm_i915_private *dev_priv = dev->dev_private;
265 u32 dpfc_ctl;
266
267 /* Disable compression */
268 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
269 if (dpfc_ctl & DPFC_CTL_EN) {
270 dpfc_ctl &= ~DPFC_CTL_EN;
271 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
272
273 DRM_DEBUG_KMS("disabled FBC\n");
274 }
275}
276
1fa61106 277static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 278{
279 struct drm_i915_private *dev_priv = dev->dev_private;
280
281 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
282}
283
993495ae 284static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 285{
286 struct drm_device *dev = crtc->dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 288 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 289 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
abe959c7 290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3fa2e0ee 291 u32 dpfc_ctl;
abe959c7 292
3fa2e0ee
VS		 293 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
294 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
5e59f717
BW		 295 dev_priv->fbc.threshold++;
296
297 switch (dev_priv->fbc.threshold) {
298 case 4:
299 case 3:
300 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
301 break;
302 case 2:
3fa2e0ee 303 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
5e59f717
BW		 304 break;
305 case 1:
3fa2e0ee 306 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
5e59f717
BW		 307 break;
308 }
309
3fa2e0ee
VS		 310 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
311
312 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
abe959c7 313
891348b2 314 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 315 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
2adb6db8
VS		 316 I915_WRITE(ILK_DISPLAY_CHICKEN1,
317 I915_READ(ILK_DISPLAY_CHICKEN1) |
318 ILK_FBCQ_DIS);
28554164 319 } else {
2adb6db8 320 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
8f670bb1
VS		 321 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
322 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
323 HSW_FBCQ_DIS);
891348b2 324 }
b74ea102 325
abe959c7
RV		 326 I915_WRITE(SNB_DPFC_CTL_SA,
327 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
328 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
329
330 sandybridge_blit_fbc_update(dev);
331
b19870ee 332 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 333}
334
85208be0
ED		 335bool intel_fbc_enabled(struct drm_device *dev)
336{
337 struct drm_i915_private *dev_priv = dev->dev_private;
338
339 if (!dev_priv->display.fbc_enabled)
340 return false;
341
342 return dev_priv->display.fbc_enabled(dev);
343}
344
345static void intel_fbc_work_fn(struct work_struct *__work)
346{
347 struct intel_fbc_work *work =
348 container_of(to_delayed_work(__work),
349 struct intel_fbc_work, work);
350 struct drm_device *dev = work->crtc->dev;
351 struct drm_i915_private *dev_priv = dev->dev_private;
352
353 mutex_lock(&dev->struct_mutex);
5c3fe8b0 354 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 355 /* Double check that we haven't switched fb without cancelling
356 * the prior work.
357 */
f4510a27 358 if (work->crtc->primary->fb == work->fb) {
993495ae 359 dev_priv->display.enable_fbc(work->crtc);
85208be0 360
5c3fe8b0 361 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
f4510a27 362 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
5c3fe8b0 363 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 364 }
365
5c3fe8b0 366 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 367 }
368 mutex_unlock(&dev->struct_mutex);
369
370 kfree(work);
371}
372
373static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
374{
5c3fe8b0 375 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 376 return;
377
378 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
379
380 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 381 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 382 * entirely asynchronously.
383 */
5c3fe8b0 384 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 385 /* tasklet was killed before being run, clean up */
5c3fe8b0 386 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 387
388 /* Mark the work as no longer wanted so that if it does
389 * wake-up (because the work was already running and waiting
390 * for our mutex), it will discover that is no longer
391 * necessary to run.
392 */
5c3fe8b0 393 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 394}
395
993495ae 396static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 397{
398 struct intel_fbc_work *work;
399 struct drm_device *dev = crtc->dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401
402 if (!dev_priv->display.enable_fbc)
403 return;
404
405 intel_cancel_fbc_work(dev_priv);
406
b14c5679 407 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 408 if (work == NULL) {
6cdcb5e7 409 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 410 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 411 return;
412 }
413
414 work->crtc = crtc;
f4510a27 415 work->fb = crtc->primary->fb;
85208be0
ED		 416 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
417
5c3fe8b0 418 dev_priv->fbc.fbc_work = work;
85208be0 419
85208be0
ED		 420 /* Delay the actual enabling to let pageflipping cease and the
421 * display to settle before starting the compression. Note that
422 * this delay also serves a second purpose: it allows for a
423 * vblank to pass after disabling the FBC before we attempt
424 * to modify the control registers.
425 *
426 * A more complicated solution would involve tracking vblanks
427 * following the termination of the page-flipping sequence
428 * and indeed performing the enable as a co-routine and not
429 * waiting synchronously upon the vblank.
7457d617
DL		 430 *
431 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 432 */
433 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
434}
435
436void intel_disable_fbc(struct drm_device *dev)
437{
438 struct drm_i915_private *dev_priv = dev->dev_private;
439
440 intel_cancel_fbc_work(dev_priv);
441
442 if (!dev_priv->display.disable_fbc)
443 return;
444
445 dev_priv->display.disable_fbc(dev);
5c3fe8b0 446 dev_priv->fbc.plane = -1;
85208be0
ED		 447}
448
29ebf90f
CW		 449static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
450 enum no_fbc_reason reason)
451{
452 if (dev_priv->fbc.no_fbc_reason == reason)
453 return false;
454
455 dev_priv->fbc.no_fbc_reason = reason;
456 return true;
457}
458
85208be0
ED		 459/**
460 * intel_update_fbc - enable/disable FBC as needed
461 * @dev: the drm_device
462 *
463 * Set up the framebuffer compression hardware at mode set time. We
464 * enable it if possible:
465 * - plane A only (on pre-965)
466 * - no pixel mulitply/line duplication
467 * - no alpha buffer discard
468 * - no dual wide
f85da868 469 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 470 *
471 * We can't assume that any compression will take place (worst case),
472 * so the compressed buffer has to be the same size as the uncompressed
473 * one. It also must reside (along with the line length buffer) in
474 * stolen memory.
475 *
476 * We need to enable/disable FBC on a global basis.
477 */
478void intel_update_fbc(struct drm_device *dev)
479{
480 struct drm_i915_private *dev_priv = dev->dev_private;
481 struct drm_crtc *crtc = NULL, *tmp_crtc;
482 struct intel_crtc *intel_crtc;
483 struct drm_framebuffer *fb;
85208be0 484 struct drm_i915_gem_object *obj;
ef644fda 485 const struct drm_display_mode *adjusted_mode;
37327abd 486 unsigned int max_width, max_height;
85208be0 487
3a77c4c4 488 if (!HAS_FBC(dev)) {
29ebf90f 489 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 490 return;
29ebf90f 491 }
85208be0 492
d330a953 493 if (!i915.powersave) {
29ebf90f
CW		 494 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
495 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 496 return;
29ebf90f 497 }
85208be0
ED		 498
499 /*
500 * If FBC is already on, we just have to verify that we can
501 * keep it that way...
502 * Need to disable if:
503 * - more than one pipe is active
504 * - changing FBC params (stride, fence, mode)
505 * - new fb is too large to fit in compressed buffer
506 * - going to an unsupported config (interlace, pixel multiply, etc.)
507 */
70e1e0ec 508 for_each_crtc(dev, tmp_crtc) {
3490ea5d 509 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 510 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 511 if (crtc) {
29ebf90f
CW		 512 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
513 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 514 goto out_disable;
515 }
516 crtc = tmp_crtc;
517 }
518 }
519
f4510a27 520 if (!crtc || crtc->primary->fb == NULL) {
29ebf90f
CW		 521 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
522 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 523 goto out_disable;
524 }
525
526 intel_crtc = to_intel_crtc(crtc);
f4510a27 527 fb = crtc->primary->fb;
2ff8fde1 528 obj = intel_fb_obj(fb);
ef644fda 529 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 530
0368920e 531 if (i915.enable_fbc < 0) {
29ebf90f
CW		 532 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
533 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 534 goto out_disable;
85208be0 535 }
d330a953 536 if (!i915.enable_fbc) {
29ebf90f
CW		 537 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
538 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 539 goto out_disable;
540 }
ef644fda
VS		 541 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
542 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 543 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
544 DRM_DEBUG_KMS("mode incompatible with compression, "
545 "disabling\n");
85208be0
ED		 546 goto out_disable;
547 }
f85da868 548
032843a5
DS		 549 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
550 max_width = 4096;
551 max_height = 4096;
552 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 553 max_width = 4096;
554 max_height = 2048;
f85da868 555 } else {
37327abd
VS		 556 max_width = 2048;
557 max_height = 1536;
f85da868 558 }
37327abd
VS		 559 if (intel_crtc->config.pipe_src_w > max_width ||
560 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 561 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
562 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 563 goto out_disable;
564 }
8f94d24b 565 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
c5a44aa0 566 intel_crtc->plane != PLANE_A) {
29ebf90f 567 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 568 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 569 goto out_disable;
570 }
571
572 /* The use of a CPU fence is mandatory in order to detect writes
573 * by the CPU to the scanout and trigger updates to the FBC.
574 */
575 if (obj->tiling_mode != I915_TILING_X ||
576 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 577 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
578 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 579 goto out_disable;
580 }
581
582 /* If the kernel debugger is active, always disable compression */
583 if (in_dbg_master())
584 goto out_disable;
585
2ff8fde1 586 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
5e59f717 587 drm_format_plane_cpp(fb->pixel_format, 0))) {
29ebf90f
CW		 588 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
589 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 590 goto out_disable;
591 }
592
85208be0
ED		 593 /* If the scanout has not changed, don't modify the FBC settings.
594 * Note that we make the fundamental assumption that the fb->obj
595 * cannot be unpinned (and have its GTT offset and fence revoked)
596 * without first being decoupled from the scanout and FBC disabled.
597 */
5c3fe8b0
BW		 598 if (dev_priv->fbc.plane == intel_crtc->plane &&
599 dev_priv->fbc.fb_id == fb->base.id &&
600 dev_priv->fbc.y == crtc->y)
85208be0
ED		 601 return;
602
603 if (intel_fbc_enabled(dev)) {
604 /* We update FBC along two paths, after changing fb/crtc
605 * configuration (modeswitching) and after page-flipping
606 * finishes. For the latter, we know that not only did
607 * we disable the FBC at the start of the page-flip
608 * sequence, but also more than one vblank has passed.
609 *
610 * For the former case of modeswitching, it is possible
611 * to switch between two FBC valid configurations
612 * instantaneously so we do need to disable the FBC
613 * before we can modify its control registers. We also
614 * have to wait for the next vblank for that to take
615 * effect. However, since we delay enabling FBC we can
616 * assume that a vblank has passed since disabling and
617 * that we can safely alter the registers in the deferred
618 * callback.
619 *
620 * In the scenario that we go from a valid to invalid
621 * and then back to valid FBC configuration we have
622 * no strict enforcement that a vblank occurred since
623 * disabling the FBC. However, along all current pipe
624 * disabling paths we do need to wait for a vblank at
625 * some point. And we wait before enabling FBC anyway.
626 */
627 DRM_DEBUG_KMS("disabling active FBC for update\n");
628 intel_disable_fbc(dev);
629 }
630
993495ae 631 intel_enable_fbc(crtc);
29ebf90f 632 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 633 return;
634
635out_disable:
636 /* Multiple disables should be harmless */
637 if (intel_fbc_enabled(dev)) {
638 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
639 intel_disable_fbc(dev);
640 }
11be49eb 641 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 642}
643
c921aba8
DV		 644static void i915_pineview_get_mem_freq(struct drm_device *dev)
645{
50227e1c 646 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 647 u32 tmp;
648
649 tmp = I915_READ(CLKCFG);
650
651 switch (tmp & CLKCFG_FSB_MASK) {
652 case CLKCFG_FSB_533:
653 dev_priv->fsb_freq = 533; /* 133*4 */
654 break;
655 case CLKCFG_FSB_800:
656 dev_priv->fsb_freq = 800; /* 200*4 */
657 break;
658 case CLKCFG_FSB_667:
659 dev_priv->fsb_freq = 667; /* 167*4 */
660 break;
661 case CLKCFG_FSB_400:
662 dev_priv->fsb_freq = 400; /* 100*4 */
663 break;
664 }
665
666 switch (tmp & CLKCFG_MEM_MASK) {
667 case CLKCFG_MEM_533:
668 dev_priv->mem_freq = 533;
669 break;
670 case CLKCFG_MEM_667:
671 dev_priv->mem_freq = 667;
672 break;
673 case CLKCFG_MEM_800:
674 dev_priv->mem_freq = 800;
675 break;
676 }
677
678 /* detect pineview DDR3 setting */
679 tmp = I915_READ(CSHRDDR3CTL);
680 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
681}
682
683static void i915_ironlake_get_mem_freq(struct drm_device *dev)
684{
50227e1c 685 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 686 u16 ddrpll, csipll;
687
688 ddrpll = I915_READ16(DDRMPLL1);
689 csipll = I915_READ16(CSIPLL0);
690
691 switch (ddrpll & 0xff) {
692 case 0xc:
693 dev_priv->mem_freq = 800;
694 break;
695 case 0x10:
696 dev_priv->mem_freq = 1066;
697 break;
698 case 0x14:
699 dev_priv->mem_freq = 1333;
700 break;
701 case 0x18:
702 dev_priv->mem_freq = 1600;
703 break;
704 default:
705 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
706 ddrpll & 0xff);
707 dev_priv->mem_freq = 0;
708 break;
709 }
710
20e4d407 711 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 712
713 switch (csipll & 0x3ff) {
714 case 0x00c:
715 dev_priv->fsb_freq = 3200;
716 break;
717 case 0x00e:
718 dev_priv->fsb_freq = 3733;
719 break;
720 case 0x010:
721 dev_priv->fsb_freq = 4266;
722 break;
723 case 0x012:
724 dev_priv->fsb_freq = 4800;
725 break;
726 case 0x014:
727 dev_priv->fsb_freq = 5333;
728 break;
729 case 0x016:
730 dev_priv->fsb_freq = 5866;
731 break;
732 case 0x018:
733 dev_priv->fsb_freq = 6400;
734 break;
735 default:
736 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
737 csipll & 0x3ff);
738 dev_priv->fsb_freq = 0;
739 break;
740 }
741
742 if (dev_priv->fsb_freq == 3200) {
20e4d407 743 dev_priv->ips.c_m = 0;
c921aba8 744 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 745 dev_priv->ips.c_m = 1;
c921aba8 746 } else {
20e4d407 747 dev_priv->ips.c_m = 2;
c921aba8
DV		 748 }
749}
750
b445e3b0
ED		 751static const struct cxsr_latency cxsr_latency_table[] = {
752 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
753 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
754 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
755 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
756 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
757
758 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
759 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
760 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
761 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
762 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
763
764 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
765 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
766 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
767 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
768 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
769
770 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
771 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
772 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
773 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
774 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
775
776 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
777 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
778 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
779 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
780 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
781
782 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
783 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
784 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
785 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
786 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
787};
788
63c62275 789static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 790 int is_ddr3,
791 int fsb,
792 int mem)
793{
794 const struct cxsr_latency *latency;
795 int i;
796
797 if (fsb == 0 || mem == 0)
798 return NULL;
799
800 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
801 latency = &cxsr_latency_table[i];
802 if (is_desktop == latency->is_desktop &&
803 is_ddr3 == latency->is_ddr3 &&
804 fsb == latency->fsb_freq && mem == latency->mem_freq)
805 return latency;
806 }
807
808 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
809
810 return NULL;
811}
812
5209b1f4 813void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 814{
5209b1f4
ID		 815 struct drm_device *dev = dev_priv->dev;
816 u32 val;
b445e3b0 817
5209b1f4
ID		 818 if (IS_VALLEYVIEW(dev)) {
819 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
820 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
821 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
822 } else if (IS_PINEVIEW(dev)) {
823 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
824 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
825 I915_WRITE(DSPFW3, val);
826 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
827 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
828 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
829 I915_WRITE(FW_BLC_SELF, val);
830 } else if (IS_I915GM(dev)) {
831 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
832 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
833 I915_WRITE(INSTPM, val);
834 } else {
835 return;
836 }
837
838 DRM_DEBUG_KMS("memory self-refresh is %s\n",
839 enable ? "enabled" : "disabled");
b445e3b0
ED		 840}
841
842/*
843 * Latency for FIFO fetches is dependent on several factors:
844 * - memory configuration (speed, channels)
845 * - chipset
846 * - current MCH state
847 * It can be fairly high in some situations, so here we assume a fairly
848 * pessimal value. It's a tradeoff between extra memory fetches (if we
849 * set this value too high, the FIFO will fetch frequently to stay full)
850 * and power consumption (set it too low to save power and we might see
851 * FIFO underruns and display "flicker").
852 *
853 * A value of 5us seems to be a good balance; safe for very low end
854 * platforms but not overly aggressive on lower latency configs.
855 */
856static const int latency_ns = 5000;
857
1fa61106 858static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 859{
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 uint32_t dsparb = I915_READ(DSPARB);
862 int size;
863
864 size = dsparb & 0x7f;
865 if (plane)
866 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
867
868 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
869 plane ? "B" : "A", size);
870
871 return size;
872}
873
feb56b93 874static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 875{
876 struct drm_i915_private *dev_priv = dev->dev_private;
877 uint32_t dsparb = I915_READ(DSPARB);
878 int size;
879
880 size = dsparb & 0x1ff;
881 if (plane)
882 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
883 size >>= 1; /* Convert to cachelines */
884
885 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
886 plane ? "B" : "A", size);
887
888 return size;
889}
890
1fa61106 891static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 892{
893 struct drm_i915_private *dev_priv = dev->dev_private;
894 uint32_t dsparb = I915_READ(DSPARB);
895 int size;
896
897 size = dsparb & 0x7f;
898 size >>= 2; /* Convert to cachelines */
899
900 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
901 plane ? "B" : "A",
902 size);
903
904 return size;
905}
906
b445e3b0
ED		 907/* Pineview has different values for various configs */
908static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 909 .fifo_size = PINEVIEW_DISPLAY_FIFO,
910 .max_wm = PINEVIEW_MAX_WM,
911 .default_wm = PINEVIEW_DFT_WM,
912 .guard_size = PINEVIEW_GUARD_WM,
913 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 914};
915static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 916 .fifo_size = PINEVIEW_DISPLAY_FIFO,
917 .max_wm = PINEVIEW_MAX_WM,
918 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
919 .guard_size = PINEVIEW_GUARD_WM,
920 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 921};
922static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 923 .fifo_size = PINEVIEW_CURSOR_FIFO,
924 .max_wm = PINEVIEW_CURSOR_MAX_WM,
925 .default_wm = PINEVIEW_CURSOR_DFT_WM,
926 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
927 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 928};
929static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 930 .fifo_size = PINEVIEW_CURSOR_FIFO,
931 .max_wm = PINEVIEW_CURSOR_MAX_WM,
932 .default_wm = PINEVIEW_CURSOR_DFT_WM,
933 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
934 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 935};
936static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 937 .fifo_size = G4X_FIFO_SIZE,
938 .max_wm = G4X_MAX_WM,
939 .default_wm = G4X_MAX_WM,
940 .guard_size = 2,
941 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 942};
943static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 944 .fifo_size = I965_CURSOR_FIFO,
945 .max_wm = I965_CURSOR_MAX_WM,
946 .default_wm = I965_CURSOR_DFT_WM,
947 .guard_size = 2,
948 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 949};
950static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 951 .fifo_size = VALLEYVIEW_FIFO_SIZE,
952 .max_wm = VALLEYVIEW_MAX_WM,
953 .default_wm = VALLEYVIEW_MAX_WM,
954 .guard_size = 2,
955 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 956};
957static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 958 .fifo_size = I965_CURSOR_FIFO,
959 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
960 .default_wm = I965_CURSOR_DFT_WM,
961 .guard_size = 2,
962 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 963};
964static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 965 .fifo_size = I965_CURSOR_FIFO,
966 .max_wm = I965_CURSOR_MAX_WM,
967 .default_wm = I965_CURSOR_DFT_WM,
968 .guard_size = 2,
969 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 970};
971static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 972 .fifo_size = I945_FIFO_SIZE,
973 .max_wm = I915_MAX_WM,
974 .default_wm = 1,
975 .guard_size = 2,
976 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 977};
978static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 979 .fifo_size = I915_FIFO_SIZE,
980 .max_wm = I915_MAX_WM,
981 .default_wm = 1,
982 .guard_size = 2,
983 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 984};
feb56b93 985static const struct intel_watermark_params i830_wm_info = {
e0f0273e
VS		 986 .fifo_size = I855GM_FIFO_SIZE,
987 .max_wm = I915_MAX_WM,
988 .default_wm = 1,
989 .guard_size = 2,
990 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 991};
feb56b93 992static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 993 .fifo_size = I830_FIFO_SIZE,
994 .max_wm = I915_MAX_WM,
995 .default_wm = 1,
996 .guard_size = 2,
997 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 998};
999
b445e3b0
ED		 1000/**
1001 * intel_calculate_wm - calculate watermark level
1002 * @clock_in_khz: pixel clock
1003 * @wm: chip FIFO params
1004 * @pixel_size: display pixel size
1005 * @latency_ns: memory latency for the platform
1006 *
1007 * Calculate the watermark level (the level at which the display plane will
1008 * start fetching from memory again). Each chip has a different display
1009 * FIFO size and allocation, so the caller needs to figure that out and pass
1010 * in the correct intel_watermark_params structure.
1011 *
1012 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1013 * on the pixel size. When it reaches the watermark level, it'll start
1014 * fetching FIFO line sized based chunks from memory until the FIFO fills
1015 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1016 * will occur, and a display engine hang could result.
1017 */
1018static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1019 const struct intel_watermark_params *wm,
1020 int fifo_size,
1021 int pixel_size,
1022 unsigned long latency_ns)
1023{
1024 long entries_required, wm_size;
1025
1026 /*
1027 * Note: we need to make sure we don't overflow for various clock &
1028 * latency values.
1029 * clocks go from a few thousand to several hundred thousand.
1030 * latency is usually a few thousand
1031 */
1032 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1033 1000;
1034 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1035
1036 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1037
1038 wm_size = fifo_size - (entries_required + wm->guard_size);
1039
1040 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1041
1042 /* Don't promote wm_size to unsigned... */
1043 if (wm_size > (long)wm->max_wm)
1044 wm_size = wm->max_wm;
1045 if (wm_size <= 0)
1046 wm_size = wm->default_wm;
1047 return wm_size;
1048}
1049
1050static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1051{
1052 struct drm_crtc *crtc, *enabled = NULL;
1053
70e1e0ec 1054 for_each_crtc(dev, crtc) {
3490ea5d 1055 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1056 if (enabled)
1057 return NULL;
1058 enabled = crtc;
1059 }
1060 }
1061
1062 return enabled;
1063}
1064
46ba614c 1065static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1066{
46ba614c 1067 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1068 struct drm_i915_private *dev_priv = dev->dev_private;
1069 struct drm_crtc *crtc;
1070 const struct cxsr_latency *latency;
1071 u32 reg;
1072 unsigned long wm;
1073
1074 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1075 dev_priv->fsb_freq, dev_priv->mem_freq);
1076 if (!latency) {
1077 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 1078 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1079 return;
1080 }
1081
1082 crtc = single_enabled_crtc(dev);
1083 if (crtc) {
241bfc38 1084 const struct drm_display_mode *adjusted_mode;
f4510a27 1085 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
241bfc38
DL		 1086 int clock;
1087
1088 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1089 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1090
1091 /* Display SR */
1092 wm = intel_calculate_wm(clock, &pineview_display_wm,
1093 pineview_display_wm.fifo_size,
1094 pixel_size, latency->display_sr);
1095 reg = I915_READ(DSPFW1);
1096 reg &= ~DSPFW_SR_MASK;
1097 reg |= wm << DSPFW_SR_SHIFT;
1098 I915_WRITE(DSPFW1, reg);
1099 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1100
1101 /* cursor SR */
1102 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1103 pineview_display_wm.fifo_size,
1104 pixel_size, latency->cursor_sr);
1105 reg = I915_READ(DSPFW3);
1106 reg &= ~DSPFW_CURSOR_SR_MASK;
1107 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1108 I915_WRITE(DSPFW3, reg);
1109
1110 /* Display HPLL off SR */
1111 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1112 pineview_display_hplloff_wm.fifo_size,
1113 pixel_size, latency->display_hpll_disable);
1114 reg = I915_READ(DSPFW3);
1115 reg &= ~DSPFW_HPLL_SR_MASK;
1116 reg |= wm & DSPFW_HPLL_SR_MASK;
1117 I915_WRITE(DSPFW3, reg);
1118
1119 /* cursor HPLL off SR */
1120 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1121 pineview_display_hplloff_wm.fifo_size,
1122 pixel_size, latency->cursor_hpll_disable);
1123 reg = I915_READ(DSPFW3);
1124 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1125 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1126 I915_WRITE(DSPFW3, reg);
1127 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1128
5209b1f4 1129 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 1130 } else {
5209b1f4 1131 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1132 }
1133}
1134
1135static bool g4x_compute_wm0(struct drm_device *dev,
1136 int plane,
1137 const struct intel_watermark_params *display,
1138 int display_latency_ns,
1139 const struct intel_watermark_params *cursor,
1140 int cursor_latency_ns,
1141 int *plane_wm,
1142 int *cursor_wm)
1143{
1144 struct drm_crtc *crtc;
4fe8590a 1145 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1146 int htotal, hdisplay, clock, pixel_size;
1147 int line_time_us, line_count;
1148 int entries, tlb_miss;
1149
1150 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1151 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1152 *cursor_wm = cursor->guard_size;
1153 *plane_wm = display->guard_size;
1154 return false;
1155 }
1156
4fe8590a 1157 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1158 clock = adjusted_mode->crtc_clock;
fec8cba3 1159 htotal = adjusted_mode->crtc_htotal;
37327abd 1160 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1161 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1162
1163 /* Use the small buffer method to calculate plane watermark */
1164 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1165 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1166 if (tlb_miss > 0)
1167 entries += tlb_miss;
1168 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1169 *plane_wm = entries + display->guard_size;
1170 if (*plane_wm > (int)display->max_wm)
1171 *plane_wm = display->max_wm;
1172
1173 /* Use the large buffer method to calculate cursor watermark */
922044c9 1174 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 1175 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
7bb836dd 1176 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
b445e3b0
ED		 1177 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1178 if (tlb_miss > 0)
1179 entries += tlb_miss;
1180 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1181 *cursor_wm = entries + cursor->guard_size;
1182 if (*cursor_wm > (int)cursor->max_wm)
1183 *cursor_wm = (int)cursor->max_wm;
1184
1185 return true;
1186}
1187
1188/*
1189 * Check the wm result.
1190 *
1191 * If any calculated watermark values is larger than the maximum value that
1192 * can be programmed into the associated watermark register, that watermark
1193 * must be disabled.
1194 */
1195static bool g4x_check_srwm(struct drm_device *dev,
1196 int display_wm, int cursor_wm,
1197 const struct intel_watermark_params *display,
1198 const struct intel_watermark_params *cursor)
1199{
1200 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1201 display_wm, cursor_wm);
1202
1203 if (display_wm > display->max_wm) {
1204 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1205 display_wm, display->max_wm);
1206 return false;
1207 }
1208
1209 if (cursor_wm > cursor->max_wm) {
1210 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1211 cursor_wm, cursor->max_wm);
1212 return false;
1213 }
1214
1215 if (!(display_wm || cursor_wm)) {
1216 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1217 return false;
1218 }
1219
1220 return true;
1221}
1222
1223static bool g4x_compute_srwm(struct drm_device *dev,
1224 int plane,
1225 int latency_ns,
1226 const struct intel_watermark_params *display,
1227 const struct intel_watermark_params *cursor,
1228 int *display_wm, int *cursor_wm)
1229{
1230 struct drm_crtc *crtc;
4fe8590a 1231 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1232 int hdisplay, htotal, pixel_size, clock;
1233 unsigned long line_time_us;
1234 int line_count, line_size;
1235 int small, large;
1236 int entries;
1237
1238 if (!latency_ns) {
1239 *display_wm = *cursor_wm = 0;
1240 return false;
1241 }
1242
1243 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1244 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1245 clock = adjusted_mode->crtc_clock;
fec8cba3 1246 htotal = adjusted_mode->crtc_htotal;
37327abd 1247 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1248 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0 1249
922044c9 1250 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1251 line_count = (latency_ns / line_time_us + 1000) / 1000;
1252 line_size = hdisplay * pixel_size;
1253
1254 /* Use the minimum of the small and large buffer method for primary */
1255 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1256 large = line_count * line_size;
1257
1258 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1259 *display_wm = entries + display->guard_size;
1260
1261 /* calculate the self-refresh watermark for display cursor */
7bb836dd 1262 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1263 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1264 *cursor_wm = entries + cursor->guard_size;
1265
1266 return g4x_check_srwm(dev,
1267 *display_wm, *cursor_wm,
1268 display, cursor);
1269}
1270
1271static bool vlv_compute_drain_latency(struct drm_device *dev,
1272 int plane,
1273 int *plane_prec_mult,
1274 int *plane_dl,
1275 int *cursor_prec_mult,
1276 int *cursor_dl)
1277{
1278 struct drm_crtc *crtc;
1279 int clock, pixel_size;
1280 int entries;
1281
1282 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1283 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1284 return false;
1285
241bfc38 1286 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
f4510a27 1287 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
b445e3b0
ED		 1288
1289 entries = (clock / 1000) * pixel_size;
1290 *plane_prec_mult = (entries > 256) ?
1291 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1292 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1293 pixel_size);
1294
1295 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1296 *cursor_prec_mult = (entries > 256) ?
1297 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1298 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1299
1300 return true;
1301}
1302
1303/*
1304 * Update drain latency registers of memory arbiter
1305 *
1306 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1307 * to be programmed. Each plane has a drain latency multiplier and a drain
1308 * latency value.
1309 */
1310
1311static void vlv_update_drain_latency(struct drm_device *dev)
1312{
1313 struct drm_i915_private *dev_priv = dev->dev_private;
1314 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1315 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1316 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1317 either 16 or 32 */
1318
1319 /* For plane A, Cursor A */
1320 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1321 &cursor_prec_mult, &cursora_dl)) {
1322 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1323 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1324 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1325 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1326
1327 I915_WRITE(VLV_DDL1, cursora_prec |
1328 (cursora_dl << DDL_CURSORA_SHIFT) |
1329 planea_prec | planea_dl);
1330 }
1331
1332 /* For plane B, Cursor B */
1333 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1334 &cursor_prec_mult, &cursorb_dl)) {
1335 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1336 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1337 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1338 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1339
1340 I915_WRITE(VLV_DDL2, cursorb_prec |
1341 (cursorb_dl << DDL_CURSORB_SHIFT) |
1342 planeb_prec | planeb_dl);
1343 }
1344}
1345
1346#define single_plane_enabled(mask) is_power_of_2(mask)
1347
46ba614c 1348static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1349{
46ba614c 1350 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1351 static const int sr_latency_ns = 12000;
1352 struct drm_i915_private *dev_priv = dev->dev_private;
1353 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1354 int plane_sr, cursor_sr;
af6c4575 1355 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0 1356 unsigned int enabled = 0;
9858425c 1357 bool cxsr_enabled;
b445e3b0
ED		 1358
1359 vlv_update_drain_latency(dev);
1360
51cea1f4 1361 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1362 &valleyview_wm_info, latency_ns,
1363 &valleyview_cursor_wm_info, latency_ns,
1364 &planea_wm, &cursora_wm))
51cea1f4 1365 enabled |= 1 << PIPE_A;
b445e3b0 1366
51cea1f4 1367 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1368 &valleyview_wm_info, latency_ns,
1369 &valleyview_cursor_wm_info, latency_ns,
1370 &planeb_wm, &cursorb_wm))
51cea1f4 1371 enabled |= 1 << PIPE_B;
b445e3b0 1372
b445e3b0
ED		 1373 if (single_plane_enabled(enabled) &&
1374 g4x_compute_srwm(dev, ffs(enabled) - 1,
1375 sr_latency_ns,
1376 &valleyview_wm_info,
1377 &valleyview_cursor_wm_info,
af6c4575
CW		 1378 &plane_sr, &ignore_cursor_sr) &&
1379 g4x_compute_srwm(dev, ffs(enabled) - 1,
1380 2*sr_latency_ns,
1381 &valleyview_wm_info,
1382 &valleyview_cursor_wm_info,
52bd02d8 1383 &ignore_plane_sr, &cursor_sr)) {
9858425c 1384 cxsr_enabled = true;
52bd02d8 1385 } else {
9858425c 1386 cxsr_enabled = false;
5209b1f4 1387 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1388 plane_sr = cursor_sr = 0;
1389 }
b445e3b0
ED		 1390
1391 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1392 planea_wm, cursora_wm,
1393 planeb_wm, cursorb_wm,
1394 plane_sr, cursor_sr);
1395
1396 I915_WRITE(DSPFW1,
1397 (plane_sr << DSPFW_SR_SHIFT) |
1398 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1399 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1400 planea_wm);
1401 I915_WRITE(DSPFW2,
8c919b28 1402 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1403 (cursora_wm << DSPFW_CURSORA_SHIFT));
1404 I915_WRITE(DSPFW3,
8c919b28
CW		 1405 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1406 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1407
1408 if (cxsr_enabled)
1409 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1410}
1411
46ba614c 1412static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1413{
46ba614c 1414 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1415 static const int sr_latency_ns = 12000;
1416 struct drm_i915_private *dev_priv = dev->dev_private;
1417 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1418 int plane_sr, cursor_sr;
1419 unsigned int enabled = 0;
9858425c 1420 bool cxsr_enabled;
b445e3b0 1421
51cea1f4 1422 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1423 &g4x_wm_info, latency_ns,
1424 &g4x_cursor_wm_info, latency_ns,
1425 &planea_wm, &cursora_wm))
51cea1f4 1426 enabled |= 1 << PIPE_A;
b445e3b0 1427
51cea1f4 1428 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1429 &g4x_wm_info, latency_ns,
1430 &g4x_cursor_wm_info, latency_ns,
1431 &planeb_wm, &cursorb_wm))
51cea1f4 1432 enabled |= 1 << PIPE_B;
b445e3b0 1433
b445e3b0
ED		 1434 if (single_plane_enabled(enabled) &&
1435 g4x_compute_srwm(dev, ffs(enabled) - 1,
1436 sr_latency_ns,
1437 &g4x_wm_info,
1438 &g4x_cursor_wm_info,
52bd02d8 1439 &plane_sr, &cursor_sr)) {
9858425c 1440 cxsr_enabled = true;
52bd02d8 1441 } else {
9858425c 1442 cxsr_enabled = false;
5209b1f4 1443 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1444 plane_sr = cursor_sr = 0;
1445 }
b445e3b0
ED		 1446
1447 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1448 planea_wm, cursora_wm,
1449 planeb_wm, cursorb_wm,
1450 plane_sr, cursor_sr);
1451
1452 I915_WRITE(DSPFW1,
1453 (plane_sr << DSPFW_SR_SHIFT) |
1454 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1455 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1456 planea_wm);
1457 I915_WRITE(DSPFW2,
8c919b28 1458 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1459 (cursora_wm << DSPFW_CURSORA_SHIFT));
1460 /* HPLL off in SR has some issues on G4x... disable it */
1461 I915_WRITE(DSPFW3,
8c919b28 1462 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0 1463 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1464
1465 if (cxsr_enabled)
1466 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1467}
1468
46ba614c 1469static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1470{
46ba614c 1471 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1472 struct drm_i915_private *dev_priv = dev->dev_private;
1473 struct drm_crtc *crtc;
1474 int srwm = 1;
1475 int cursor_sr = 16;
9858425c 1476 bool cxsr_enabled;
b445e3b0
ED		 1477
1478 /* Calc sr entries for one plane configs */
1479 crtc = single_enabled_crtc(dev);
1480 if (crtc) {
1481 /* self-refresh has much higher latency */
1482 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1483 const struct drm_display_mode *adjusted_mode =
1484 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1485 int clock = adjusted_mode->crtc_clock;
fec8cba3 1486 int htotal = adjusted_mode->crtc_htotal;
37327abd 1487 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1488 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1489 unsigned long line_time_us;
1490 int entries;
1491
922044c9 1492 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1493
1494 /* Use ns/us then divide to preserve precision */
1495 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1496 pixel_size * hdisplay;
1497 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1498 srwm = I965_FIFO_SIZE - entries;
1499 if (srwm < 0)
1500 srwm = 1;
1501 srwm &= 0x1ff;
1502 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1503 entries, srwm);
1504
1505 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
7bb836dd 1506 pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1507 entries = DIV_ROUND_UP(entries,
1508 i965_cursor_wm_info.cacheline_size);
1509 cursor_sr = i965_cursor_wm_info.fifo_size -
1510 (entries + i965_cursor_wm_info.guard_size);
1511
1512 if (cursor_sr > i965_cursor_wm_info.max_wm)
1513 cursor_sr = i965_cursor_wm_info.max_wm;
1514
1515 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1516 "cursor %d\n", srwm, cursor_sr);
1517
9858425c 1518 cxsr_enabled = true;
b445e3b0 1519 } else {
9858425c 1520 cxsr_enabled = false;
b445e3b0 1521 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1522 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1523 }
1524
1525 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1526 srwm);
1527
1528 /* 965 has limitations... */
1529 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1530 (8 << 16) | (8 << 8) | (8 << 0));
1531 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1532 /* update cursor SR watermark */
1533 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1534
1535 if (cxsr_enabled)
1536 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1537}
1538
46ba614c 1539static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1540{
46ba614c 1541 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1542 struct drm_i915_private *dev_priv = dev->dev_private;
1543 const struct intel_watermark_params *wm_info;
1544 uint32_t fwater_lo;
1545 uint32_t fwater_hi;
1546 int cwm, srwm = 1;
1547 int fifo_size;
1548 int planea_wm, planeb_wm;
1549 struct drm_crtc *crtc, *enabled = NULL;
1550
1551 if (IS_I945GM(dev))
1552 wm_info = &i945_wm_info;
1553 else if (!IS_GEN2(dev))
1554 wm_info = &i915_wm_info;
1555 else
feb56b93 1556 wm_info = &i830_wm_info;
b445e3b0
ED		 1557
1558 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1559 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1560 if (intel_crtc_active(crtc)) {
241bfc38 1561 const struct drm_display_mode *adjusted_mode;
f4510a27 1562 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1563 if (IS_GEN2(dev))
1564 cpp = 4;
1565
241bfc38
DL		 1566 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1567 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1568 wm_info, fifo_size, cpp,
b445e3b0
ED		 1569 latency_ns);
1570 enabled = crtc;
1571 } else
1572 planea_wm = fifo_size - wm_info->guard_size;
1573
1574 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1575 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1576 if (intel_crtc_active(crtc)) {
241bfc38 1577 const struct drm_display_mode *adjusted_mode;
f4510a27 1578 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1579 if (IS_GEN2(dev))
1580 cpp = 4;
1581
241bfc38
DL		 1582 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1583 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1584 wm_info, fifo_size, cpp,
b445e3b0
ED		 1585 latency_ns);
1586 if (enabled == NULL)
1587 enabled = crtc;
1588 else
1589 enabled = NULL;
1590 } else
1591 planeb_wm = fifo_size - wm_info->guard_size;
1592
1593 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1594
2ab1bc9d 1595 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1596 struct drm_i915_gem_object *obj;
2ab1bc9d 1597
2ff8fde1 1598 obj = intel_fb_obj(enabled->primary->fb);
2ab1bc9d
DV		 1599
1600 /* self-refresh seems busted with untiled */
2ff8fde1 1601 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1602 enabled = NULL;
1603 }
1604
b445e3b0
ED		 1605 /*
1606 * Overlay gets an aggressive default since video jitter is bad.
1607 */
1608 cwm = 2;
1609
1610 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1611 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1612
1613 /* Calc sr entries for one plane configs */
1614 if (HAS_FW_BLC(dev) && enabled) {
1615 /* self-refresh has much higher latency */
1616 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1617 const struct drm_display_mode *adjusted_mode =
1618 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1619 int clock = adjusted_mode->crtc_clock;
fec8cba3 1620 int htotal = adjusted_mode->crtc_htotal;
f727b490 1621 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
f4510a27 1622 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1623 unsigned long line_time_us;
1624 int entries;
1625
922044c9 1626 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1627
1628 /* Use ns/us then divide to preserve precision */
1629 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1630 pixel_size * hdisplay;
1631 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1632 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1633 srwm = wm_info->fifo_size - entries;
1634 if (srwm < 0)
1635 srwm = 1;
1636
1637 if (IS_I945G(dev) || IS_I945GM(dev))
1638 I915_WRITE(FW_BLC_SELF,
1639 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1640 else if (IS_I915GM(dev))
1641 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1642 }
1643
1644 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1645 planea_wm, planeb_wm, cwm, srwm);
1646
1647 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1648 fwater_hi = (cwm & 0x1f);
1649
1650 /* Set request length to 8 cachelines per fetch */
1651 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1652 fwater_hi = fwater_hi | (1 << 8);
1653
1654 I915_WRITE(FW_BLC, fwater_lo);
1655 I915_WRITE(FW_BLC2, fwater_hi);
1656
5209b1f4
ID		 1657 if (enabled)
1658 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1659}
1660
feb56b93 1661static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1662{
46ba614c 1663 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1664 struct drm_i915_private *dev_priv = dev->dev_private;
1665 struct drm_crtc *crtc;
241bfc38 1666 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1667 uint32_t fwater_lo;
1668 int planea_wm;
1669
1670 crtc = single_enabled_crtc(dev);
1671 if (crtc == NULL)
1672 return;
1673
241bfc38
DL		 1674 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1675 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1676 &i845_wm_info,
b445e3b0 1677 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1678 4, latency_ns);
b445e3b0
ED		 1679 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1680 fwater_lo |= (3<<8) | planea_wm;
1681
1682 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1683
1684 I915_WRITE(FW_BLC, fwater_lo);
1685}
1686
3658729a
VS		 1687static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1688 struct drm_crtc *crtc)
801bcfff
PZ		 1689{
1690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1691 uint32_t pixel_rate;
801bcfff 1692
241bfc38 1693 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 1694
1695 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1696 * adjust the pixel_rate here. */
1697
fd4daa9c 1698 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1699 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1700 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1701
37327abd
VS		 1702 pipe_w = intel_crtc->config.pipe_src_w;
1703 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 1704 pfit_w = (pfit_size >> 16) & 0xFFFF;
1705 pfit_h = pfit_size & 0xFFFF;
1706 if (pipe_w < pfit_w)
1707 pipe_w = pfit_w;
1708 if (pipe_h < pfit_h)
1709 pipe_h = pfit_h;
1710
1711 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1712 pfit_w * pfit_h);
1713 }
1714
1715 return pixel_rate;
1716}
1717
37126462 1718/* latency must be in 0.1us units. */
23297044 1719static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1720 uint32_t latency)
1721{
1722 uint64_t ret;
1723
3312ba65
VS		 1724 if (WARN(latency == 0, "Latency value missing\n"))
1725 return UINT_MAX;
1726
801bcfff
PZ		 1727 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1728 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1729
1730 return ret;
1731}
1732
37126462 1733/* latency must be in 0.1us units. */
23297044 1734static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1735 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1736 uint32_t latency)
1737{
1738 uint32_t ret;
1739
3312ba65
VS		 1740 if (WARN(latency == 0, "Latency value missing\n"))
1741 return UINT_MAX;
1742
801bcfff
PZ		 1743 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1744 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1745 ret = DIV_ROUND_UP(ret, 64) + 2;
1746 return ret;
1747}
1748
23297044 1749static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1750 uint8_t bytes_per_pixel)
1751{
1752 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1753}
1754
820c1980 1755struct ilk_pipe_wm_parameters {
801bcfff 1756 bool active;
801bcfff
PZ		 1757 uint32_t pipe_htotal;
1758 uint32_t pixel_rate;
c35426d2
VS		 1759 struct intel_plane_wm_parameters pri;
1760 struct intel_plane_wm_parameters spr;
1761 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1762};
1763
820c1980 1764struct ilk_wm_maximums {
cca32e9a
PZ		 1765 uint16_t pri;
1766 uint16_t spr;
1767 uint16_t cur;
1768 uint16_t fbc;
1769};
1770
240264f4
VS		 1771/* used in computing the new watermarks state */
1772struct intel_wm_config {
1773 unsigned int num_pipes_active;
1774 bool sprites_enabled;
1775 bool sprites_scaled;
240264f4
VS		 1776};
1777
37126462
VS		 1778/*
1779 * For both WM_PIPE and WM_LP.
1780 * mem_value must be in 0.1us units.
1781 */
820c1980 1782static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1783 uint32_t mem_value,
1784 bool is_lp)
801bcfff 1785{
cca32e9a
PZ		 1786 uint32_t method1, method2;
1787
c35426d2 1788 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1789 return 0;
1790
23297044 1791 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1792 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1793 mem_value);
1794
1795 if (!is_lp)
1796 return method1;
1797
23297044 1798 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1799 params->pipe_htotal,
c35426d2
VS		 1800 params->pri.horiz_pixels,
1801 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1802 mem_value);
1803
1804 return min(method1, method2);
801bcfff
PZ		 1805}
1806
37126462
VS		 1807/*
1808 * For both WM_PIPE and WM_LP.
1809 * mem_value must be in 0.1us units.
1810 */
820c1980 1811static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1812 uint32_t mem_value)
1813{
1814 uint32_t method1, method2;
1815
c35426d2 1816 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1817 return 0;
1818
23297044 1819 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1820 params->spr.bytes_per_pixel,
801bcfff 1821 mem_value);
23297044 1822 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1823 params->pipe_htotal,
c35426d2
VS		 1824 params->spr.horiz_pixels,
1825 params->spr.bytes_per_pixel,
801bcfff
PZ		 1826 mem_value);
1827 return min(method1, method2);
1828}
1829
37126462
VS		 1830/*
1831 * For both WM_PIPE and WM_LP.
1832 * mem_value must be in 0.1us units.
1833 */
820c1980 1834static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1835 uint32_t mem_value)
1836{
c35426d2 1837 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1838 return 0;
1839
23297044 1840 return ilk_wm_method2(params->pixel_rate,
801bcfff 1841 params->pipe_htotal,
c35426d2
VS		 1842 params->cur.horiz_pixels,
1843 params->cur.bytes_per_pixel,
801bcfff
PZ		 1844 mem_value);
1845}
1846
cca32e9a 1847/* Only for WM_LP. */
820c1980 1848static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1849 uint32_t pri_val)
cca32e9a 1850{
c35426d2 1851 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1852 return 0;
1853
23297044 1854 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1855 params->pri.horiz_pixels,
1856 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1857}
1858
158ae64f
VS		 1859static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1860{
416f4727
VS		 1861 if (INTEL_INFO(dev)->gen >= 8)
1862 return 3072;
1863 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1864 return 768;
1865 else
1866 return 512;
1867}
1868
4e975081
VS		 1869static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1870 int level, bool is_sprite)
1871{
1872 if (INTEL_INFO(dev)->gen >= 8)
1873 /* BDW primary/sprite plane watermarks */
1874 return level == 0 ? 255 : 2047;
1875 else if (INTEL_INFO(dev)->gen >= 7)
1876 /* IVB/HSW primary/sprite plane watermarks */
1877 return level == 0 ? 127 : 1023;
1878 else if (!is_sprite)
1879 /* ILK/SNB primary plane watermarks */
1880 return level == 0 ? 127 : 511;
1881 else
1882 /* ILK/SNB sprite plane watermarks */
1883 return level == 0 ? 63 : 255;
1884}
1885
1886static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1887 int level)
1888{
1889 if (INTEL_INFO(dev)->gen >= 7)
1890 return level == 0 ? 63 : 255;
1891 else
1892 return level == 0 ? 31 : 63;
1893}
1894
1895static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1896{
1897 if (INTEL_INFO(dev)->gen >= 8)
1898 return 31;
1899 else
1900 return 15;
1901}
1902
158ae64f
VS		 1903/* Calculate the maximum primary/sprite plane watermark */
1904static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1905 int level,
240264f4 1906 const struct intel_wm_config *config,
158ae64f
VS		 1907 enum intel_ddb_partitioning ddb_partitioning,
1908 bool is_sprite)
1909{
1910 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1911
1912 /* if sprites aren't enabled, sprites get nothing */
240264f4 1913 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1914 return 0;
1915
1916 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1917 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1918 fifo_size /= INTEL_INFO(dev)->num_pipes;
1919
1920 /*
1921 * For some reason the non self refresh
1922 * FIFO size is only half of the self
1923 * refresh FIFO size on ILK/SNB.
1924 */
1925 if (INTEL_INFO(dev)->gen <= 6)
1926 fifo_size /= 2;
1927 }
1928
240264f4 1929 if (config->sprites_enabled) {
158ae64f
VS		 1930 /* level 0 is always calculated with 1:1 split */
1931 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1932 if (is_sprite)
1933 fifo_size *= 5;
1934 fifo_size /= 6;
1935 } else {
1936 fifo_size /= 2;
1937 }
1938 }
1939
1940 /* clamp to max that the registers can hold */
4e975081 1941 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1942}
1943
1944/* Calculate the maximum cursor plane watermark */
1945static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1946 int level,
1947 const struct intel_wm_config *config)
158ae64f
VS		 1948{
1949 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1950 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1951 return 64;
1952
1953 /* otherwise just report max that registers can hold */
4e975081 1954 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1955}
1956
d34ff9c6 1957static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1958 int level,
1959 const struct intel_wm_config *config,
1960 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1961 struct ilk_wm_maximums *max)
158ae64f 1962{
240264f4
VS		 1963 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1964 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1965 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1966 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1967}
1968
a3cb4048
VS		 1969static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1970 int level,
1971 struct ilk_wm_maximums *max)
1972{
1973 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1974 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1975 max->cur = ilk_cursor_wm_reg_max(dev, level);
1976 max->fbc = ilk_fbc_wm_reg_max(dev);
1977}
1978
d9395655 1979static bool ilk_validate_wm_level(int level,
820c1980 1980 const struct ilk_wm_maximums *max,
d9395655 1981 struct intel_wm_level *result)
a9786a11
VS		 1982{
1983 bool ret;
1984
1985 /* already determined to be invalid? */
1986 if (!result->enable)
1987 return false;
1988
1989 result->enable = result->pri_val <= max->pri &&
1990 result->spr_val <= max->spr &&
1991 result->cur_val <= max->cur;
1992
1993 ret = result->enable;
1994
1995 /*
1996 * HACK until we can pre-compute everything,
1997 * and thus fail gracefully if LP0 watermarks
1998 * are exceeded...
1999 */
2000 if (level == 0 && !result->enable) {
2001 if (result->pri_val > max->pri)
2002 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2003 level, result->pri_val, max->pri);
2004 if (result->spr_val > max->spr)
2005 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2006 level, result->spr_val, max->spr);
2007 if (result->cur_val > max->cur)
2008 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2009 level, result->cur_val, max->cur);
2010
2011 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2012 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2013 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2014 result->enable = true;
2015 }
2016
a9786a11
VS		 2017 return ret;
2018}
2019
d34ff9c6 2020static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 2021 int level,
820c1980 2022 const struct ilk_pipe_wm_parameters *p,
1fd527cc 2023 struct intel_wm_level *result)
6f5ddd17
VS		 2024{
2025 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2026 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2027 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2028
2029 /* WM1+ latency values stored in 0.5us units */
2030 if (level > 0) {
2031 pri_latency *= 5;
2032 spr_latency *= 5;
2033 cur_latency *= 5;
2034 }
2035
2036 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2037 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2038 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2039 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2040 result->enable = true;
2041}
2042
801bcfff
PZ		 2043static uint32_t
2044hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2045{
2046 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2048 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2049 u32 linetime, ips_linetime;
1f8eeabf 2050
801bcfff
PZ		 2051 if (!intel_crtc_active(crtc))
2052 return 0;
1011d8c4 2053
1f8eeabf
ED		 2054 /* The WM are computed with base on how long it takes to fill a single
2055 * row at the given clock rate, multiplied by 8.
2056 * */
fec8cba3
JB		 2057 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2058 mode->crtc_clock);
2059 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 2060 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2061
801bcfff
PZ		 2062 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2063 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2064}
2065
12b134df
VS		 2066static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2067{
2068 struct drm_i915_private *dev_priv = dev->dev_private;
2069
a42a5719 2070 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2071 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2072
2073 wm[0] = (sskpd >> 56) & 0xFF;
2074 if (wm[0] == 0)
2075 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2076 wm[1] = (sskpd >> 4) & 0xFF;
2077 wm[2] = (sskpd >> 12) & 0xFF;
2078 wm[3] = (sskpd >> 20) & 0x1FF;
2079 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2080 } else if (INTEL_INFO(dev)->gen >= 6) {
2081 uint32_t sskpd = I915_READ(MCH_SSKPD);
2082
2083 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2084 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2085 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2086 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2087 } else if (INTEL_INFO(dev)->gen >= 5) {
2088 uint32_t mltr = I915_READ(MLTR_ILK);
2089
2090 /* ILK primary LP0 latency is 700 ns */
2091 wm[0] = 7;
2092 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2093 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2094 }
2095}
2096
53615a5e
VS		 2097static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2098{
2099 /* ILK sprite LP0 latency is 1300 ns */
2100 if (INTEL_INFO(dev)->gen == 5)
2101 wm[0] = 13;
2102}
2103
2104static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2105{
2106 /* ILK cursor LP0 latency is 1300 ns */
2107 if (INTEL_INFO(dev)->gen == 5)
2108 wm[0] = 13;
2109
2110 /* WaDoubleCursorLP3Latency:ivb */
2111 if (IS_IVYBRIDGE(dev))
2112 wm[3] *= 2;
2113}
2114
546c81fd 2115int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2116{
26ec971e 2117 /* how many WM levels are we expecting */
a42a5719 2118 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2119 return 4;
26ec971e 2120 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2121 return 3;
26ec971e 2122 else
ad0d6dc4
VS		 2123 return 2;
2124}
2125
2126static void intel_print_wm_latency(struct drm_device *dev,
2127 const char *name,
2128 const uint16_t wm[5])
2129{
2130 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2131
2132 for (level = 0; level <= max_level; level++) {
2133 unsigned int latency = wm[level];
2134
2135 if (latency == 0) {
2136 DRM_ERROR("%s WM%d latency not provided\n",
2137 name, level);
2138 continue;
2139 }
2140
2141 /* WM1+ latency values in 0.5us units */
2142 if (level > 0)
2143 latency *= 5;
2144
2145 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2146 name, level, wm[level],
2147 latency / 10, latency % 10);
2148 }
2149}
2150
e95a2f75
VS		 2151static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2152 uint16_t wm[5], uint16_t min)
2153{
2154 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2155
2156 if (wm[0] >= min)
2157 return false;
2158
2159 wm[0] = max(wm[0], min);
2160 for (level = 1; level <= max_level; level++)
2161 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2162
2163 return true;
2164}
2165
2166static void snb_wm_latency_quirk(struct drm_device *dev)
2167{
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 bool changed;
2170
2171 /*
2172 * The BIOS provided WM memory latency values are often
2173 * inadequate for high resolution displays. Adjust them.
2174 */
2175 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2176 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2177 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2178
2179 if (!changed)
2180 return;
2181
2182 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2183 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2184 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2185 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2186}
2187
fa50ad61 2188static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2189{
2190 struct drm_i915_private *dev_priv = dev->dev_private;
2191
2192 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2193
2194 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2195 sizeof(dev_priv->wm.pri_latency));
2196 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2197 sizeof(dev_priv->wm.pri_latency));
2198
2199 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2200 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2201
2202 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2203 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2204 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2205
2206 if (IS_GEN6(dev))
2207 snb_wm_latency_quirk(dev);
53615a5e
VS		 2208}
2209
820c1980 2210static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2211 struct ilk_pipe_wm_parameters *p)
1011d8c4 2212{
7c4a395f
VS		 2213 struct drm_device *dev = crtc->dev;
2214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2215 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2216 struct drm_plane *plane;
1011d8c4 2217
2a44b76b
VS		 2218 if (!intel_crtc_active(crtc))
2219 return;
801bcfff 2220
2a44b76b
VS		 2221 p->active = true;
2222 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2223 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2224 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2225 p->cur.bytes_per_pixel = 4;
2226 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2227 p->cur.horiz_pixels = intel_crtc->cursor_width;
2228 /* TODO: for now, assume primary and cursor planes are always enabled. */
2229 p->pri.enabled = true;
2230 p->cur.enabled = true;
7c4a395f 2231
af2b653b 2232 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2233 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2234
2a44b76b 2235 if (intel_plane->pipe == pipe) {
7c4a395f 2236 p->spr = intel_plane->wm;
2a44b76b
VS		 2237 break;
2238 }
2239 }
2240}
2241
2242static void ilk_compute_wm_config(struct drm_device *dev,
2243 struct intel_wm_config *config)
2244{
2245 struct intel_crtc *intel_crtc;
2246
2247 /* Compute the currently _active_ config */
d3fcc808 2248 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2249 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2250
2a44b76b
VS		 2251 if (!wm->pipe_enabled)
2252 continue;
cca32e9a 2253
2a44b76b
VS		 2254 config->sprites_enabled |= wm->sprites_enabled;
2255 config->sprites_scaled |= wm->sprites_scaled;
2256 config->num_pipes_active++;
cca32e9a 2257 }
801bcfff
PZ		 2258}
2259
0b2ae6d7
VS		 2260/* Compute new watermarks for the pipe */
2261static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2262 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2263 struct intel_pipe_wm *pipe_wm)
2264{
2265 struct drm_device *dev = crtc->dev;
d34ff9c6 2266 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2267 int level, max_level = ilk_wm_max_level(dev);
2268 /* LP0 watermark maximums depend on this pipe alone */
2269 struct intel_wm_config config = {
2270 .num_pipes_active = 1,
2271 .sprites_enabled = params->spr.enabled,
2272 .sprites_scaled = params->spr.scaled,
2273 };
820c1980 2274 struct ilk_wm_maximums max;
0b2ae6d7 2275
2a44b76b
VS		 2276 pipe_wm->pipe_enabled = params->active;
2277 pipe_wm->sprites_enabled = params->spr.enabled;
2278 pipe_wm->sprites_scaled = params->spr.scaled;
2279
7b39a0b7
VS		 2280 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2281 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2282 max_level = 1;
2283
2284 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2285 if (params->spr.scaled)
2286 max_level = 0;
2287
a3cb4048 2288 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2289
a42a5719 2290 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2291 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2292
a3cb4048
VS		 2293 /* LP0 watermarks always use 1/2 DDB partitioning */
2294 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2295
0b2ae6d7 2296 /* At least LP0 must be valid */
a3cb4048
VS		 2297 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2298 return false;
2299
2300 ilk_compute_wm_reg_maximums(dev, 1, &max);
2301
2302 for (level = 1; level <= max_level; level++) {
2303 struct intel_wm_level wm = {};
2304
2305 ilk_compute_wm_level(dev_priv, level, params, &wm);
2306
2307 /*
2308 * Disable any watermark level that exceeds the
2309 * register maximums since such watermarks are
2310 * always invalid.
2311 */
2312 if (!ilk_validate_wm_level(level, &max, &wm))
2313 break;
2314
2315 pipe_wm->wm[level] = wm;
2316 }
2317
2318 return true;
0b2ae6d7
VS		 2319}
2320
2321/*
2322 * Merge the watermarks from all active pipes for a specific level.
2323 */
2324static void ilk_merge_wm_level(struct drm_device *dev,
2325 int level,
2326 struct intel_wm_level *ret_wm)
2327{
2328 const struct intel_crtc *intel_crtc;
2329
d52fea5b
VS		 2330 ret_wm->enable = true;
2331
d3fcc808 2332 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2333 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2334 const struct intel_wm_level *wm = &active->wm[level];
2335
2336 if (!active->pipe_enabled)
2337 continue;
0b2ae6d7 2338
d52fea5b
VS		 2339 /*
2340 * The watermark values may have been used in the past,
2341 * so we must maintain them in the registers for some
2342 * time even if the level is now disabled.
2343 */
0b2ae6d7 2344 if (!wm->enable)
d52fea5b 2345 ret_wm->enable = false;
0b2ae6d7
VS		 2346
2347 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2348 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2349 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2350 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2351 }
0b2ae6d7
VS		 2352}
2353
2354/*
2355 * Merge all low power watermarks for all active pipes.
2356 */
2357static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2358 const struct intel_wm_config *config,
820c1980 2359 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2360 struct intel_pipe_wm *merged)
2361{
2362 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2363 int last_enabled_level = max_level;
0b2ae6d7 2364
0ba22e26
VS		 2365 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2366 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2367 config->num_pipes_active > 1)
2368 return;
2369
6c8b6c28
VS		 2370 /* ILK: FBC WM must be disabled always */
2371 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2372
2373 /* merge each WM1+ level */
2374 for (level = 1; level <= max_level; level++) {
2375 struct intel_wm_level *wm = &merged->wm[level];
2376
2377 ilk_merge_wm_level(dev, level, wm);
2378
d52fea5b
VS		 2379 if (level > last_enabled_level)
2380 wm->enable = false;
2381 else if (!ilk_validate_wm_level(level, max, wm))
2382 /* make sure all following levels get disabled */
2383 last_enabled_level = level - 1;
0b2ae6d7
VS		 2384
2385 /*
2386 * The spec says it is preferred to disable
2387 * FBC WMs instead of disabling a WM level.
2388 */
2389 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2390 if (wm->enable)
2391 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2392 wm->fbc_val = 0;
2393 }
2394 }
6c8b6c28
VS		 2395
2396 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2397 /*
2398 * FIXME this is racy. FBC might get enabled later.
2399 * What we should check here is whether FBC can be
2400 * enabled sometime later.
2401 */
2402 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2403 for (level = 2; level <= max_level; level++) {
2404 struct intel_wm_level *wm = &merged->wm[level];
2405
2406 wm->enable = false;
2407 }
2408 }
0b2ae6d7
VS		 2409}
2410
b380ca3c
VS		 2411static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2412{
2413 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2414 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2415}
2416
a68d68ee
VS		 2417/* The value we need to program into the WM_LPx latency field */
2418static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2419{
2420 struct drm_i915_private *dev_priv = dev->dev_private;
2421
a42a5719 2422 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2423 return 2 * level;
2424 else
2425 return dev_priv->wm.pri_latency[level];
2426}
2427
820c1980 2428static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2429 const struct intel_pipe_wm *merged,
609cedef 2430 enum intel_ddb_partitioning partitioning,
820c1980 2431 struct ilk_wm_values *results)
801bcfff 2432{
0b2ae6d7
VS		 2433 struct intel_crtc *intel_crtc;
2434 int level, wm_lp;
cca32e9a 2435
0362c781 2436 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2437 results->partitioning = partitioning;
cca32e9a 2438
0b2ae6d7 2439 /* LP1+ register values */
cca32e9a 2440 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2441 const struct intel_wm_level *r;
801bcfff 2442
b380ca3c 2443 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2444
0362c781 2445 r = &merged->wm[level];
cca32e9a 2446
d52fea5b
VS		 2447 /*
2448 * Maintain the watermark values even if the level is
2449 * disabled. Doing otherwise could cause underruns.
2450 */
2451 results->wm_lp[wm_lp - 1] =
a68d68ee 2452 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2453 (r->pri_val << WM1_LP_SR_SHIFT) |
2454 r->cur_val;
2455
d52fea5b
VS		 2456 if (r->enable)
2457 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2458
416f4727
VS		 2459 if (INTEL_INFO(dev)->gen >= 8)
2460 results->wm_lp[wm_lp - 1] |=
2461 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2462 else
2463 results->wm_lp[wm_lp - 1] |=
2464 r->fbc_val << WM1_LP_FBC_SHIFT;
2465
d52fea5b
VS		 2466 /*
2467 * Always set WM1S_LP_EN when spr_val != 0, even if the
2468 * level is disabled. Doing otherwise could cause underruns.
2469 */
6cef2b8a
VS		 2470 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2471 WARN_ON(wm_lp != 1);
2472 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2473 } else
2474 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2475 }
801bcfff 2476
0b2ae6d7 2477 /* LP0 register values */
d3fcc808 2478 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2479 enum pipe pipe = intel_crtc->pipe;
2480 const struct intel_wm_level *r =
2481 &intel_crtc->wm.active.wm[0];
2482
2483 if (WARN_ON(!r->enable))
2484 continue;
2485
2486 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2487
0b2ae6d7
VS		 2488 results->wm_pipe[pipe] =
2489 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2490 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2491 r->cur_val;
801bcfff
PZ		 2492 }
2493}
2494
861f3389
PZ		 2495/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2496 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2497static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2498 struct intel_pipe_wm *r1,
2499 struct intel_pipe_wm *r2)
861f3389 2500{
198a1e9b
VS		 2501 int level, max_level = ilk_wm_max_level(dev);
2502 int level1 = 0, level2 = 0;
861f3389 2503
198a1e9b
VS		 2504 for (level = 1; level <= max_level; level++) {
2505 if (r1->wm[level].enable)
2506 level1 = level;
2507 if (r2->wm[level].enable)
2508 level2 = level;
861f3389
PZ		 2509 }
2510
198a1e9b
VS		 2511 if (level1 == level2) {
2512 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2513 return r2;
2514 else
2515 return r1;
198a1e9b 2516 } else if (level1 > level2) {
861f3389
PZ		 2517 return r1;
2518 } else {
2519 return r2;
2520 }
2521}
2522
49a687c4
VS		 2523/* dirty bits used to track which watermarks need changes */
2524#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2525#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2526#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2527#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2528#define WM_DIRTY_FBC (1 << 24)
2529#define WM_DIRTY_DDB (1 << 25)
2530
2531static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
820c1980
ID		 2532 const struct ilk_wm_values *old,
2533 const struct ilk_wm_values *new)
49a687c4
VS		 2534{
2535 unsigned int dirty = 0;
2536 enum pipe pipe;
2537 int wm_lp;
2538
2539 for_each_pipe(pipe) {
2540 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2541 dirty |= WM_DIRTY_LINETIME(pipe);
2542 /* Must disable LP1+ watermarks too */
2543 dirty |= WM_DIRTY_LP_ALL;
2544 }
2545
2546 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2547 dirty |= WM_DIRTY_PIPE(pipe);
2548 /* Must disable LP1+ watermarks too */
2549 dirty |= WM_DIRTY_LP_ALL;
2550 }
2551 }
2552
2553 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2554 dirty |= WM_DIRTY_FBC;
2555 /* Must disable LP1+ watermarks too */
2556 dirty |= WM_DIRTY_LP_ALL;
2557 }
2558
2559 if (old->partitioning != new->partitioning) {
2560 dirty |= WM_DIRTY_DDB;
2561 /* Must disable LP1+ watermarks too */
2562 dirty |= WM_DIRTY_LP_ALL;
2563 }
2564
2565 /* LP1+ watermarks already deemed dirty, no need to continue */
2566 if (dirty & WM_DIRTY_LP_ALL)
2567 return dirty;
2568
2569 /* Find the lowest numbered LP1+ watermark in need of an update... */
2570 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2571 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2572 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2573 break;
2574 }
2575
2576 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2577 for (; wm_lp <= 3; wm_lp++)
2578 dirty |= WM_DIRTY_LP(wm_lp);
2579
2580 return dirty;
2581}
2582
8553c18e
VS		 2583static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2584 unsigned int dirty)
801bcfff 2585{
820c1980 2586 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2587 bool changed = false;
801bcfff 2588
facd619b
VS		 2589 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2590 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2591 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2592 changed = true;
facd619b
VS		 2593 }
2594 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2595 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2596 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2597 changed = true;
facd619b
VS		 2598 }
2599 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2600 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2601 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2602 changed = true;
facd619b 2603 }
801bcfff 2604
facd619b
VS		 2605 /*
2606 * Don't touch WM1S_LP_EN here.
2607 * Doing so could cause underruns.
2608 */
6cef2b8a 2609
8553c18e
VS		 2610 return changed;
2611}
2612
2613/*
2614 * The spec says we shouldn't write when we don't need, because every write
2615 * causes WMs to be re-evaluated, expending some power.
2616 */
820c1980
ID		 2617static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2618 struct ilk_wm_values *results)
8553c18e
VS		 2619{
2620 struct drm_device *dev = dev_priv->dev;
820c1980 2621 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2622 unsigned int dirty;
2623 uint32_t val;
2624
2625 dirty = ilk_compute_wm_dirty(dev, previous, results);
2626 if (!dirty)
2627 return;
2628
2629 _ilk_disable_lp_wm(dev_priv, dirty);
2630
49a687c4 2631 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2632 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2633 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2634 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2635 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2636 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2637
49a687c4 2638 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2639 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2640 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2641 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2642 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2643 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2644
49a687c4 2645 if (dirty & WM_DIRTY_DDB) {
a42a5719 2646 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2647 val = I915_READ(WM_MISC);
2648 if (results->partitioning == INTEL_DDB_PART_1_2)
2649 val &= ~WM_MISC_DATA_PARTITION_5_6;
2650 else
2651 val |= WM_MISC_DATA_PARTITION_5_6;
2652 I915_WRITE(WM_MISC, val);
2653 } else {
2654 val = I915_READ(DISP_ARB_CTL2);
2655 if (results->partitioning == INTEL_DDB_PART_1_2)
2656 val &= ~DISP_DATA_PARTITION_5_6;
2657 else
2658 val |= DISP_DATA_PARTITION_5_6;
2659 I915_WRITE(DISP_ARB_CTL2, val);
2660 }
1011d8c4
PZ		 2661 }
2662
49a687c4 2663 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2664 val = I915_READ(DISP_ARB_CTL);
2665 if (results->enable_fbc_wm)
2666 val &= ~DISP_FBC_WM_DIS;
2667 else
2668 val |= DISP_FBC_WM_DIS;
2669 I915_WRITE(DISP_ARB_CTL, val);
2670 }
2671
954911eb
ID		 2672 if (dirty & WM_DIRTY_LP(1) &&
2673 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2674 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2675
2676 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2677 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2678 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2679 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2680 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2681 }
801bcfff 2682
facd619b 2683 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2684 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2685 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2686 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2687 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2688 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2689
2690 dev_priv->wm.hw = *results;
801bcfff
PZ		 2691}
2692
8553c18e
VS		 2693static bool ilk_disable_lp_wm(struct drm_device *dev)
2694{
2695 struct drm_i915_private *dev_priv = dev->dev_private;
2696
2697 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2698}
2699
820c1980 2700static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 2701{
7c4a395f 2702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2703 struct drm_device *dev = crtc->dev;
801bcfff 2704 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 2705 struct ilk_wm_maximums max;
2706 struct ilk_pipe_wm_parameters params = {};
2707 struct ilk_wm_values results = {};
77c122bc 2708 enum intel_ddb_partitioning partitioning;
7c4a395f 2709 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2710 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2711 struct intel_wm_config config = {};
7c4a395f 2712
2a44b76b 2713 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 2714
2715 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2716
2717 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2718 return;
861f3389 2719
7c4a395f 2720 intel_crtc->wm.active = pipe_wm;
861f3389 2721
2a44b76b
VS		 2722 ilk_compute_wm_config(dev, &config);
2723
34982fe1 2724 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 2725 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 2726
2727 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2728 if (INTEL_INFO(dev)->gen >= 7 &&
2729 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2730 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 2731 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 2732
820c1980 2733 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2734 } else {
198a1e9b 2735 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2736 }
2737
198a1e9b 2738 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2739 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2740
820c1980 2741 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 2742
820c1980 2743 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2744}
2745
820c1980 2746static void ilk_update_sprite_wm(struct drm_plane *plane,
adf3d35e 2747 struct drm_crtc *crtc,
526682e9 2748 uint32_t sprite_width, int pixel_size,
bdd57d03 2749 bool enabled, bool scaled)
526682e9 2750{
8553c18e 2751 struct drm_device *dev = plane->dev;
adf3d35e 2752 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2753
adf3d35e
VS		 2754 intel_plane->wm.enabled = enabled;
2755 intel_plane->wm.scaled = scaled;
2756 intel_plane->wm.horiz_pixels = sprite_width;
2757 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2758
8553c18e
VS		 2759 /*
2760 * IVB workaround: must disable low power watermarks for at least
2761 * one frame before enabling scaling. LP watermarks can be re-enabled
2762 * when scaling is disabled.
2763 *
2764 * WaCxSRDisabledForSpriteScaling:ivb
2765 */
2766 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2767 intel_wait_for_vblank(dev, intel_plane->pipe);
2768
820c1980 2769 ilk_update_wm(crtc);
526682e9
PZ		 2770}
2771
243e6a44
VS		 2772static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2773{
2774 struct drm_device *dev = crtc->dev;
2775 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2776 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2779 enum pipe pipe = intel_crtc->pipe;
2780 static const unsigned int wm0_pipe_reg[] = {
2781 [PIPE_A] = WM0_PIPEA_ILK,
2782 [PIPE_B] = WM0_PIPEB_ILK,
2783 [PIPE_C] = WM0_PIPEC_IVB,
2784 };
2785
2786 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 2787 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2788 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 2789
2a44b76b
VS		 2790 active->pipe_enabled = intel_crtc_active(crtc);
2791
2792 if (active->pipe_enabled) {
243e6a44
VS		 2793 u32 tmp = hw->wm_pipe[pipe];
2794
2795 /*
2796 * For active pipes LP0 watermark is marked as
2797 * enabled, and LP1+ watermaks as disabled since
2798 * we can't really reverse compute them in case
2799 * multiple pipes are active.
2800 */
2801 active->wm[0].enable = true;
2802 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2803 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2804 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2805 active->linetime = hw->wm_linetime[pipe];
2806 } else {
2807 int level, max_level = ilk_wm_max_level(dev);
2808
2809 /*
2810 * For inactive pipes, all watermark levels
2811 * should be marked as enabled but zeroed,
2812 * which is what we'd compute them to.
2813 */
2814 for (level = 0; level <= max_level; level++)
2815 active->wm[level].enable = true;
2816 }
2817}
2818
2819void ilk_wm_get_hw_state(struct drm_device *dev)
2820{
2821 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2822 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2823 struct drm_crtc *crtc;
2824
70e1e0ec 2825 for_each_crtc(dev, crtc)
243e6a44
VS		 2826 ilk_pipe_wm_get_hw_state(crtc);
2827
2828 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2829 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2830 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2831
2832 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 2833 if (INTEL_INFO(dev)->gen >= 7) {
2834 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2835 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2836 }
243e6a44 2837
a42a5719 2838 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 2839 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2840 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2841 else if (IS_IVYBRIDGE(dev))
2842 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2843 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 2844
2845 hw->enable_fbc_wm =
2846 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2847}
2848
b445e3b0
ED		 2849/**
2850 * intel_update_watermarks - update FIFO watermark values based on current modes
2851 *
2852 * Calculate watermark values for the various WM regs based on current mode
2853 * and plane configuration.
2854 *
2855 * There are several cases to deal with here:
2856 * - normal (i.e. non-self-refresh)
2857 * - self-refresh (SR) mode
2858 * - lines are large relative to FIFO size (buffer can hold up to 2)
2859 * - lines are small relative to FIFO size (buffer can hold more than 2
2860 * lines), so need to account for TLB latency
2861 *
2862 * The normal calculation is:
2863 * watermark = dotclock * bytes per pixel * latency
2864 * where latency is platform & configuration dependent (we assume pessimal
2865 * values here).
2866 *
2867 * The SR calculation is:
2868 * watermark = (trunc(latency/line time)+1) * surface width *
2869 * bytes per pixel
2870 * where
2871 * line time = htotal / dotclock
2872 * surface width = hdisplay for normal plane and 64 for cursor
2873 * and latency is assumed to be high, as above.
2874 *
2875 * The final value programmed to the register should always be rounded up,
2876 * and include an extra 2 entries to account for clock crossings.
2877 *
2878 * We don't use the sprite, so we can ignore that. And on Crestline we have
2879 * to set the non-SR watermarks to 8.
2880 */
46ba614c 2881void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 2882{
46ba614c 2883 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 2884
2885 if (dev_priv->display.update_wm)
46ba614c 2886 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 2887}
2888
adf3d35e
VS		 2889void intel_update_sprite_watermarks(struct drm_plane *plane,
2890 struct drm_crtc *crtc,
4c4ff43a 2891 uint32_t sprite_width, int pixel_size,
39db4a4d 2892 bool enabled, bool scaled)
b445e3b0 2893{
adf3d35e 2894 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 2895
2896 if (dev_priv->display.update_sprite_wm)
adf3d35e 2897 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 2898 pixel_size, enabled, scaled);
b445e3b0
ED		 2899}
2900
2b4e57bd
ED		 2901static struct drm_i915_gem_object *
2902intel_alloc_context_page(struct drm_device *dev)
2903{
2904 struct drm_i915_gem_object *ctx;
2905 int ret;
2906
2907 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2908
2909 ctx = i915_gem_alloc_object(dev, 4096);
2910 if (!ctx) {
2911 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2912 return NULL;
2913 }
2914
c69766f2 2915 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2b4e57bd
ED		 2916 if (ret) {
2917 DRM_ERROR("failed to pin power context: %d\n", ret);
2918 goto err_unref;
2919 }
2920
2921 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2922 if (ret) {
2923 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2924 goto err_unpin;
2925 }
2926
2927 return ctx;
2928
2929err_unpin:
d7f46fc4 2930 i915_gem_object_ggtt_unpin(ctx);
2b4e57bd
ED		 2931err_unref:
2932 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2933 return NULL;
2934}
2935
9270388e
DV		 2936/**
2937 * Lock protecting IPS related data structures
9270388e
DV		 2938 */
2939DEFINE_SPINLOCK(mchdev_lock);
2940
2941/* Global for IPS driver to get at the current i915 device. Protected by
2942 * mchdev_lock. */
2943static struct drm_i915_private *i915_mch_dev;
2944
2b4e57bd
ED		 2945bool ironlake_set_drps(struct drm_device *dev, u8 val)
2946{
2947 struct drm_i915_private *dev_priv = dev->dev_private;
2948 u16 rgvswctl;
2949
9270388e
DV		 2950 assert_spin_locked(&mchdev_lock);
2951
2b4e57bd
ED		 2952 rgvswctl = I915_READ16(MEMSWCTL);
2953 if (rgvswctl & MEMCTL_CMD_STS) {
2954 DRM_DEBUG("gpu busy, RCS change rejected\n");
2955 return false; /* still busy with another command */
2956 }
2957
2958 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2959 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2960 I915_WRITE16(MEMSWCTL, rgvswctl);
2961 POSTING_READ16(MEMSWCTL);
2962
2963 rgvswctl |= MEMCTL_CMD_STS;
2964 I915_WRITE16(MEMSWCTL, rgvswctl);
2965
2966 return true;
2967}
2968
8090c6b9 2969static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2970{
2971 struct drm_i915_private *dev_priv = dev->dev_private;
2972 u32 rgvmodectl = I915_READ(MEMMODECTL);
2973 u8 fmax, fmin, fstart, vstart;
2974
9270388e
DV		 2975 spin_lock_irq(&mchdev_lock);
2976
2b4e57bd
ED		 2977 /* Enable temp reporting */
2978 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2979 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2980
2981 /* 100ms RC evaluation intervals */
2982 I915_WRITE(RCUPEI, 100000);
2983 I915_WRITE(RCDNEI, 100000);
2984
2985 /* Set max/min thresholds to 90ms and 80ms respectively */
2986 I915_WRITE(RCBMAXAVG, 90000);
2987 I915_WRITE(RCBMINAVG, 80000);
2988
2989 I915_WRITE(MEMIHYST, 1);
2990
2991 /* Set up min, max, and cur for interrupt handling */
2992 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2993 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2994 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2995 MEMMODE_FSTART_SHIFT;
2996
2997 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2998 PXVFREQ_PX_SHIFT;
2999
20e4d407
DV		 3000 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3001 dev_priv->ips.fstart = fstart;
2b4e57bd 3002
20e4d407
DV		 3003 dev_priv->ips.max_delay = fstart;
3004 dev_priv->ips.min_delay = fmin;
3005 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3006
3007 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3008 fmax, fmin, fstart);
3009
3010 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3011
3012 /*
3013 * Interrupts will be enabled in ironlake_irq_postinstall
3014 */
3015
3016 I915_WRITE(VIDSTART, vstart);
3017 POSTING_READ(VIDSTART);
3018
3019 rgvmodectl |= MEMMODE_SWMODE_EN;
3020 I915_WRITE(MEMMODECTL, rgvmodectl);
3021
9270388e 3022 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3023 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3024 mdelay(1);
2b4e57bd
ED		 3025
3026 ironlake_set_drps(dev, fstart);
3027
20e4d407 3028 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3029 I915_READ(0x112e0);
20e4d407
DV		 3030 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3031 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3032 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 3033
3034 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3035}
3036
8090c6b9 3037static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3038{
3039 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3040 u16 rgvswctl;
3041
3042 spin_lock_irq(&mchdev_lock);
3043
3044 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3045
3046 /* Ack interrupts, disable EFC interrupt */
3047 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3048 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3049 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3050 I915_WRITE(DEIIR, DE_PCU_EVENT);
3051 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3052
3053 /* Go back to the starting frequency */
20e4d407 3054 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3055 mdelay(1);
2b4e57bd
ED		 3056 rgvswctl |= MEMCTL_CMD_STS;
3057 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3058 mdelay(1);
2b4e57bd 3059
9270388e 3060 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3061}
3062
acbe9475
DV		 3063/* There's a funny hw issue where the hw returns all 0 when reading from
3064 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3065 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3066 * all limits and the gpu stuck at whatever frequency it is at atm).
3067 */
6917c7b9 3068static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3069{
7b9e0ae6 3070 u32 limits;
2b4e57bd 3071
20b46e59
DV		 3072 /* Only set the down limit when we've reached the lowest level to avoid
3073 * getting more interrupts, otherwise leave this clear. This prevents a
3074 * race in the hw when coming out of rc6: There's a tiny window where
3075 * the hw runs at the minimal clock before selecting the desired
3076 * frequency, if the down threshold expires in that window we will not
3077 * receive a down interrupt. */
b39fb297
BW		 3078 limits = dev_priv->rps.max_freq_softlimit << 24;
3079 if (val <= dev_priv->rps.min_freq_softlimit)
3080 limits |= dev_priv->rps.min_freq_softlimit << 16;
20b46e59
DV		 3081
3082 return limits;
3083}
3084
dd75fdc8
CW		 3085static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3086{
3087 int new_power;
3088
3089 new_power = dev_priv->rps.power;
3090 switch (dev_priv->rps.power) {
3091 case LOW_POWER:
b39fb297 3092 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3093 new_power = BETWEEN;
3094 break;
3095
3096 case BETWEEN:
b39fb297 3097 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3098 new_power = LOW_POWER;
b39fb297 3099 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3100 new_power = HIGH_POWER;
3101 break;
3102
3103 case HIGH_POWER:
b39fb297 3104 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3105 new_power = BETWEEN;
3106 break;
3107 }
3108 /* Max/min bins are special */
b39fb297 3109 if (val == dev_priv->rps.min_freq_softlimit)
dd75fdc8 3110 new_power = LOW_POWER;
b39fb297 3111 if (val == dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3112 new_power = HIGH_POWER;
3113 if (new_power == dev_priv->rps.power)
3114 return;
3115
3116 /* Note the units here are not exactly 1us, but 1280ns. */
3117 switch (new_power) {
3118 case LOW_POWER:
3119 /* Upclock if more than 95% busy over 16ms */
3120 I915_WRITE(GEN6_RP_UP_EI, 12500);
3121 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3122
3123 /* Downclock if less than 85% busy over 32ms */
3124 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3125 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3126
3127 I915_WRITE(GEN6_RP_CONTROL,
3128 GEN6_RP_MEDIA_TURBO |
3129 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3130 GEN6_RP_MEDIA_IS_GFX |
3131 GEN6_RP_ENABLE |
3132 GEN6_RP_UP_BUSY_AVG |
3133 GEN6_RP_DOWN_IDLE_AVG);
3134 break;
3135
3136 case BETWEEN:
3137 /* Upclock if more than 90% busy over 13ms */
3138 I915_WRITE(GEN6_RP_UP_EI, 10250);
3139 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3140
3141 /* Downclock if less than 75% busy over 32ms */
3142 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3143 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3144
3145 I915_WRITE(GEN6_RP_CONTROL,
3146 GEN6_RP_MEDIA_TURBO |
3147 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3148 GEN6_RP_MEDIA_IS_GFX |
3149 GEN6_RP_ENABLE |
3150 GEN6_RP_UP_BUSY_AVG |
3151 GEN6_RP_DOWN_IDLE_AVG);
3152 break;
3153
3154 case HIGH_POWER:
3155 /* Upclock if more than 85% busy over 10ms */
3156 I915_WRITE(GEN6_RP_UP_EI, 8000);
3157 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3158
3159 /* Downclock if less than 60% busy over 32ms */
3160 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3161 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3162
3163 I915_WRITE(GEN6_RP_CONTROL,
3164 GEN6_RP_MEDIA_TURBO |
3165 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3166 GEN6_RP_MEDIA_IS_GFX |
3167 GEN6_RP_ENABLE |
3168 GEN6_RP_UP_BUSY_AVG |
3169 GEN6_RP_DOWN_IDLE_AVG);
3170 break;
3171 }
3172
3173 dev_priv->rps.power = new_power;
3174 dev_priv->rps.last_adj = 0;
3175}
3176
2876ce73
CW		 3177static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3178{
3179 u32 mask = 0;
3180
3181 if (val > dev_priv->rps.min_freq_softlimit)
3182 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3183 if (val < dev_priv->rps.max_freq_softlimit)
3184 mask |= GEN6_PM_RP_UP_THRESHOLD;
3185
3186 /* IVB and SNB hard hangs on looping batchbuffer
3187 * if GEN6_PM_UP_EI_EXPIRED is masked.
3188 */
3189 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3190 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3191
baccd458
D		 3192 if (IS_GEN8(dev_priv->dev))
3193 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3194
2876ce73
CW		 3195 return ~mask;
3196}
3197
b8a5ff8d
JM		 3198/* gen6_set_rps is called to update the frequency request, but should also be
3199 * called when the range (min_delay and max_delay) is modified so that we can
3200 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
20b46e59
DV		 3201void gen6_set_rps(struct drm_device *dev, u8 val)
3202{
3203 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3204
4fc688ce 3205 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3206 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3207 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
004777cb 3208
eb64cad1
CW		 3209 /* min/max delay may still have been modified so be sure to
3210 * write the limits value.
3211 */
3212 if (val != dev_priv->rps.cur_freq) {
3213 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3214
50e6a2a7 3215 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3216 I915_WRITE(GEN6_RPNSWREQ,
3217 HSW_FREQUENCY(val));
3218 else
3219 I915_WRITE(GEN6_RPNSWREQ,
3220 GEN6_FREQUENCY(val) |
3221 GEN6_OFFSET(0) |
3222 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3223 }
7b9e0ae6 3224
7b9e0ae6
CW		 3225 /* Make sure we continue to get interrupts
3226 * until we hit the minimum or maximum frequencies.
3227 */
eb64cad1 3228 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
2876ce73 3229 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3230
d5570a72
BW		 3231 POSTING_READ(GEN6_RPNSWREQ);
3232
b39fb297 3233 dev_priv->rps.cur_freq = val;
be2cde9a 3234 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3235}
3236
76c3552f
D		 3237/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3238 *
3239 * * If Gfx is Idle, then
3240 * 1. Mask Turbo interrupts
3241 * 2. Bring up Gfx clock
3242 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3243 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3244 * 5. Unmask Turbo interrupts
3245*/
3246static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3247{
5549d25f
D		 3248 struct drm_device *dev = dev_priv->dev;
3249
3250 /* Latest VLV doesn't need to force the gfx clock */
3251 if (dev->pdev->revision >= 0xd) {
3252 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3253 return;
3254 }
3255
76c3552f
D		 3256 /*
3257 * When we are idle. Drop to min voltage state.
3258 */
3259
b39fb297 3260 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
76c3552f
D		 3261 return;
3262
3263 /* Mask turbo interrupt so that they will not come in between */
3264 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3265
650ad970 3266 vlv_force_gfx_clock(dev_priv, true);
76c3552f 3267
b39fb297 3268 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
76c3552f
D		 3269
3270 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
b39fb297 3271 dev_priv->rps.min_freq_softlimit);
76c3552f
D		 3272
3273 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3274 & GENFREQSTATUS) == 0, 5))
3275 DRM_ERROR("timed out waiting for Punit\n");
3276
650ad970 3277 vlv_force_gfx_clock(dev_priv, false);
76c3552f 3278
31685c25
D		 3279 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
3280 I915_WRITE(GEN6_PMINTRMSK, ~dev_priv->pm_rps_events);
3281 else
3282 I915_WRITE(GEN6_PMINTRMSK,
3283 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
76c3552f
D		 3284}
3285
b29c19b6
CW		 3286void gen6_rps_idle(struct drm_i915_private *dev_priv)
3287{
691bb717
DL		 3288 struct drm_device *dev = dev_priv->dev;
3289
b29c19b6 3290 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3291 if (dev_priv->rps.enabled) {
691bb717 3292 if (IS_VALLEYVIEW(dev))
76c3552f 3293 vlv_set_rps_idle(dev_priv);
c0951f0c 3294 else
b39fb297 3295 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
c0951f0c
CW		 3296 dev_priv->rps.last_adj = 0;
3297 }
b29c19b6
CW		 3298 mutex_unlock(&dev_priv->rps.hw_lock);
3299}
3300
3301void gen6_rps_boost(struct drm_i915_private *dev_priv)
3302{
691bb717
DL		 3303 struct drm_device *dev = dev_priv->dev;
3304
b29c19b6 3305 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3306 if (dev_priv->rps.enabled) {
691bb717 3307 if (IS_VALLEYVIEW(dev))
b39fb297 3308 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c 3309 else
b39fb297 3310 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c
CW		 3311 dev_priv->rps.last_adj = 0;
3312 }
b29c19b6
CW		 3313 mutex_unlock(&dev_priv->rps.hw_lock);
3314}
3315
0a073b84
JB		 3316void valleyview_set_rps(struct drm_device *dev, u8 val)
3317{
3318 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3319
0a073b84 3320 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3321 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3322 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
0a073b84 3323
73008b98 3324 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
b39fb297
BW		 3325 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3326 dev_priv->rps.cur_freq,
2ec3815f 3327 vlv_gpu_freq(dev_priv, val), val);
0a073b84 3328
2876ce73
CW		 3329 if (val != dev_priv->rps.cur_freq)
3330 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3331
09c87db8 3332 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
0a073b84 3333
b39fb297 3334 dev_priv->rps.cur_freq = val;
2ec3815f 3335 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3336}
3337
0961021a
BW		 3338static void gen8_disable_rps_interrupts(struct drm_device *dev)
3339{
3340 struct drm_i915_private *dev_priv = dev->dev_private;
3341
992f191f 3342 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
0961021a
BW		 3343 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3344 ~dev_priv->pm_rps_events);
3345 /* Complete PM interrupt masking here doesn't race with the rps work
3346 * item again unmasking PM interrupts because that is using a different
3347 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3348 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3349 * gen8_enable_rps will clean up. */
3350
3351 spin_lock_irq(&dev_priv->irq_lock);
3352 dev_priv->rps.pm_iir = 0;
3353 spin_unlock_irq(&dev_priv->irq_lock);
3354
3355 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3356}
3357
44fc7d5c 3358static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3359{
3360 struct drm_i915_private *dev_priv = dev->dev_private;
3361
2b4e57bd 3362 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
a6706b45
D		 3363 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3364 ~dev_priv->pm_rps_events);
2b4e57bd
ED		 3365 /* Complete PM interrupt masking here doesn't race with the rps work
3366 * item again unmasking PM interrupts because that is using a different
3367 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3368 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3369
59cdb63d 3370 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3371 dev_priv->rps.pm_iir = 0;
59cdb63d 3372 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3373
a6706b45 3374 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
2b4e57bd
ED		 3375}
3376
44fc7d5c 3377static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3378{
3379 struct drm_i915_private *dev_priv = dev->dev_private;
3380
3381 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3382 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3383
0961021a
BW		 3384 if (IS_BROADWELL(dev))
3385 gen8_disable_rps_interrupts(dev);
3386 else
3387 gen6_disable_rps_interrupts(dev);
44fc7d5c
DV		 3388}
3389
38807746
D		 3390static void cherryview_disable_rps(struct drm_device *dev)
3391{
3392 struct drm_i915_private *dev_priv = dev->dev_private;
3393
3394 I915_WRITE(GEN6_RC_CONTROL, 0);
3395}
3396
44fc7d5c
DV		 3397static void valleyview_disable_rps(struct drm_device *dev)
3398{
3399 struct drm_i915_private *dev_priv = dev->dev_private;
3400
3401 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3402
44fc7d5c 3403 gen6_disable_rps_interrupts(dev);
d20d4f0c
JB		 3404}
3405
dc39fff7
BW		 3406static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3407{
91ca689a
ID		 3408 if (IS_VALLEYVIEW(dev)) {
3409 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3410 mode = GEN6_RC_CTL_RC6_ENABLE;
3411 else
3412 mode = 0;
3413 }
dc39fff7 3414 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
1c79b42f
BW		 3415 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3416 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3417 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
dc39fff7
BW		 3418}
3419
e6069ca8 3420static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 3421{
eb4926e4
DL		 3422 /* No RC6 before Ironlake */
3423 if (INTEL_INFO(dev)->gen < 5)
3424 return 0;
3425
e6069ca8
ID		 3426 /* RC6 is only on Ironlake mobile not on desktop */
3427 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3428 return 0;
3429
456470eb 3430 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 3431 if (enable_rc6 >= 0) {
3432 int mask;
3433
3434 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3435 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3436 INTEL_RC6pp_ENABLE;
3437 else
3438 mask = INTEL_RC6_ENABLE;
3439
3440 if ((enable_rc6 & mask) != enable_rc6)
3441 DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
8fd9c1a9 3442 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 3443
3444 return enable_rc6 & mask;
3445 }
2b4e57bd 3446
6567d748
CW		 3447 /* Disable RC6 on Ironlake */
3448 if (INTEL_INFO(dev)->gen == 5)
3449 return 0;
2b4e57bd 3450
8bade1ad 3451 if (IS_IVYBRIDGE(dev))
cca84a1f 3452 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 3453
3454 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 3455}
3456
e6069ca8
ID		 3457int intel_enable_rc6(const struct drm_device *dev)
3458{
3459 return i915.enable_rc6;
3460}
3461
0961021a
BW		 3462static void gen8_enable_rps_interrupts(struct drm_device *dev)
3463{
3464 struct drm_i915_private *dev_priv = dev->dev_private;
3465
3466 spin_lock_irq(&dev_priv->irq_lock);
3467 WARN_ON(dev_priv->rps.pm_iir);
3468 bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3469 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3470 spin_unlock_irq(&dev_priv->irq_lock);
3471}
3472
44fc7d5c
DV		 3473static void gen6_enable_rps_interrupts(struct drm_device *dev)
3474{
3475 struct drm_i915_private *dev_priv = dev->dev_private;
3476
3477 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3478 WARN_ON(dev_priv->rps.pm_iir);
a6706b45
D		 3479 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3480 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
44fc7d5c 3481 spin_unlock_irq(&dev_priv->irq_lock);
44fc7d5c
DV		 3482}
3483
3280e8b0
BW		 3484static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3485{
3486 /* All of these values are in units of 50MHz */
3487 dev_priv->rps.cur_freq = 0;
3488 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3489 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3490 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3491 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3492 /* XXX: only BYT has a special efficient freq */
3493 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3494 /* hw_max = RP0 until we check for overclocking */
3495 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3496
3497 /* Preserve min/max settings in case of re-init */
3498 if (dev_priv->rps.max_freq_softlimit == 0)
3499 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3500
3501 if (dev_priv->rps.min_freq_softlimit == 0)
3502 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3503}
3504
6edee7f3
BW		 3505static void gen8_enable_rps(struct drm_device *dev)
3506{
3507 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3508 struct intel_engine_cs *ring;
6edee7f3
BW		 3509 uint32_t rc6_mask = 0, rp_state_cap;
3510 int unused;
3511
3512 /* 1a: Software RC state - RC0 */
3513 I915_WRITE(GEN6_RC_STATE, 0);
3514
3515 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3516 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3517 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3518
3519 /* 2a: Disable RC states. */
3520 I915_WRITE(GEN6_RC_CONTROL, 0);
3521
3522 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0 3523 parse_rp_state_cap(dev_priv, rp_state_cap);
6edee7f3
BW		 3524
3525 /* 2b: Program RC6 thresholds.*/
3526 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3527 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3528 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3529 for_each_ring(ring, dev_priv, unused)
3530 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3531 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 3532 if (IS_BROADWELL(dev))
3533 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3534 else
3535 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 3536
3537 /* 3: Enable RC6 */
3538 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3539 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 3540 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 3541 if (IS_BROADWELL(dev))
3542 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3543 GEN7_RC_CTL_TO_MODE |
3544 rc6_mask);
3545 else
3546 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3547 GEN6_RC_CTL_EI_MODE(1) |
3548 rc6_mask);
6edee7f3
BW		 3549
3550 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 3551 I915_WRITE(GEN6_RPNSWREQ,
3552 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3553 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3554 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
6edee7f3
BW		 3555 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3556 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3557
3558 /* Docs recommend 900MHz, and 300 MHz respectively */
3559 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
b39fb297
BW		 3560 dev_priv->rps.max_freq_softlimit << 24 |
3561 dev_priv->rps.min_freq_softlimit << 16);
6edee7f3
BW		 3562
3563 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3564 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3565 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3566 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3567
3568 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3569
3570 /* 5: Enable RPS */
3571 I915_WRITE(GEN6_RP_CONTROL,
3572 GEN6_RP_MEDIA_TURBO |
3573 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7405f42c 3574 GEN6_RP_MEDIA_IS_GFX |
6edee7f3
BW		 3575 GEN6_RP_ENABLE |
3576 GEN6_RP_UP_BUSY_AVG |
3577 GEN6_RP_DOWN_IDLE_AVG);
3578
3579 /* 6: Ring frequency + overclocking (our driver does this later */
3580
3581 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3582
0961021a 3583 gen8_enable_rps_interrupts(dev);
6edee7f3 3584
c8d9a590 3585 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3586}
3587
79f5b2c7 3588static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3589{
79f5b2c7 3590 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3591 struct intel_engine_cs *ring;
2a5913a8 3592 u32 rp_state_cap;
7b9e0ae6 3593 u32 gt_perf_status;
d060c169 3594 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 3595 u32 gtfifodbg;
2b4e57bd 3596 int rc6_mode;
42c0526c 3597 int i, ret;
2b4e57bd 3598
4fc688ce 3599 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3600
2b4e57bd
ED		 3601 /* Here begins a magic sequence of register writes to enable
3602 * auto-downclocking.
3603 *
3604 * Perhaps there might be some value in exposing these to
3605 * userspace...
3606 */
3607 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3608
3609 /* Clear the DBG now so we don't confuse earlier errors */
3610 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3611 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3612 I915_WRITE(GTFIFODBG, gtfifodbg);
3613 }
3614
c8d9a590 3615 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3616
7b9e0ae6
CW		 3617 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3618 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3619
3280e8b0 3620 parse_rp_state_cap(dev_priv, rp_state_cap);
dd0a1aa1 3621
2b4e57bd
ED		 3622 /* disable the counters and set deterministic thresholds */
3623 I915_WRITE(GEN6_RC_CONTROL, 0);
3624
3625 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3626 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3627 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3628 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3629 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3630
b4519513
CW		 3631 for_each_ring(ring, dev_priv, i)
3632 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3633
3634 I915_WRITE(GEN6_RC_SLEEP, 0);
3635 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3636 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3637 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3638 else
3639 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3640 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3641 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3642
5a7dc92a 3643 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3644 rc6_mode = intel_enable_rc6(dev_priv->dev);
3645 if (rc6_mode & INTEL_RC6_ENABLE)
3646 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3647
5a7dc92a
ED		 3648 /* We don't use those on Haswell */
3649 if (!IS_HASWELL(dev)) {
3650 if (rc6_mode & INTEL_RC6p_ENABLE)
3651 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3652
5a7dc92a
ED		 3653 if (rc6_mode & INTEL_RC6pp_ENABLE)
3654 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3655 }
2b4e57bd 3656
dc39fff7 3657 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3658
3659 I915_WRITE(GEN6_RC_CONTROL,
3660 rc6_mask |
3661 GEN6_RC_CTL_EI_MODE(1) |
3662 GEN6_RC_CTL_HW_ENABLE);
3663
dd75fdc8
CW		 3664 /* Power down if completely idle for over 50ms */
3665 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3666 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3667
42c0526c 3668 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 3669 if (ret)
42c0526c 3670 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 3671
3672 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3673 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3674 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 3675 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 3676 (pcu_mbox & 0xff) * 50);
b39fb297 3677 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 3678 }
3679
dd75fdc8 3680 dev_priv->rps.power = HIGH_POWER; /* force a reset */
b39fb297 3681 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
2b4e57bd 3682
44fc7d5c 3683 gen6_enable_rps_interrupts(dev);
2b4e57bd 3684
31643d54
BW		 3685 rc6vids = 0;
3686 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3687 if (IS_GEN6(dev) && ret) {
3688 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3689 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3690 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3691 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3692 rc6vids &= 0xffff00;
3693 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3694 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3695 if (ret)
3696 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3697 }
3698
c8d9a590 3699 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 3700}
3701
c2bc2fc5 3702static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3703{
79f5b2c7 3704 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3705 int min_freq = 15;
3ebecd07
CW		 3706 unsigned int gpu_freq;
3707 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3708 int scaling_factor = 180;
eda79642 3709 struct cpufreq_policy *policy;
2b4e57bd 3710
4fc688ce 3711 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3712
eda79642
BW		 3713 policy = cpufreq_cpu_get(0);
3714 if (policy) {
3715 max_ia_freq = policy->cpuinfo.max_freq;
3716 cpufreq_cpu_put(policy);
3717 } else {
3718 /*
3719 * Default to measured freq if none found, PCU will ensure we
3720 * don't go over
3721 */
2b4e57bd 3722 max_ia_freq = tsc_khz;
eda79642 3723 }
2b4e57bd
ED		 3724
3725 /* Convert from kHz to MHz */
3726 max_ia_freq /= 1000;
3727
153b4b95 3728 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3729 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3730 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3731
2b4e57bd
ED		 3732 /*
3733 * For each potential GPU frequency, load a ring frequency we'd like
3734 * to use for memory access. We do this by specifying the IA frequency
3735 * the PCU should use as a reference to determine the ring frequency.
3736 */
b39fb297 3737 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
2b4e57bd 3738 gpu_freq--) {
b39fb297 3739 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3ebecd07
CW		 3740 unsigned int ia_freq = 0, ring_freq = 0;
3741
46c764d4
BW		 3742 if (INTEL_INFO(dev)->gen >= 8) {
3743 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3744 ring_freq = max(min_ring_freq, gpu_freq);
3745 } else if (IS_HASWELL(dev)) {
f6aca45c 3746 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3747 ring_freq = max(min_ring_freq, ring_freq);
3748 /* leave ia_freq as the default, chosen by cpufreq */
3749 } else {
3750 /* On older processors, there is no separate ring
3751 * clock domain, so in order to boost the bandwidth
3752 * of the ring, we need to upclock the CPU (ia_freq).
3753 *
3754 * For GPU frequencies less than 750MHz,
3755 * just use the lowest ring freq.
3756 */
3757 if (gpu_freq < min_freq)
3758 ia_freq = 800;
3759 else
3760 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3761 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3762 }
2b4e57bd 3763
42c0526c
BW		 3764 sandybridge_pcode_write(dev_priv,
3765 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3766 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3767 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3768 gpu_freq);
2b4e57bd 3769 }
2b4e57bd
ED		 3770}
3771
c2bc2fc5
ID		 3772void gen6_update_ring_freq(struct drm_device *dev)
3773{
3774 struct drm_i915_private *dev_priv = dev->dev_private;
3775
3776 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3777 return;
3778
3779 mutex_lock(&dev_priv->rps.hw_lock);
3780 __gen6_update_ring_freq(dev);
3781 mutex_unlock(&dev_priv->rps.hw_lock);
3782}
3783
2b6b3a09
D		 3784int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
3785{
3786 u32 val, rp0;
3787
3788 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3789 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3790
3791 return rp0;
3792}
3793
3794static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3795{
3796 u32 val, rpe;
3797
3798 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
3799 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
3800
3801 return rpe;
3802}
3803
3804int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
3805{
3806 u32 val, rpn;
3807
3808 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3809 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
3810 return rpn;
3811}
3812
0a073b84
JB		 3813int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3814{
3815 u32 val, rp0;
3816
64936258 3817 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3818
3819 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3820 /* Clamp to max */
3821 rp0 = min_t(u32, rp0, 0xea);
3822
3823 return rp0;
3824}
3825
3826static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3827{
3828 u32 val, rpe;
3829
64936258 3830 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3831 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3832 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3833 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3834
3835 return rpe;
3836}
3837
3838int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3839{
64936258 3840 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3841}
3842
ae48434c
ID		 3843/* Check that the pctx buffer wasn't move under us. */
3844static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3845{
3846 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3847
3848 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3849 dev_priv->vlv_pctx->stolen->start);
3850}
3851
38807746
D		 3852
3853/* Check that the pcbr address is not empty. */
3854static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
3855{
3856 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3857
3858 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
3859}
3860
3861static void cherryview_setup_pctx(struct drm_device *dev)
3862{
3863 struct drm_i915_private *dev_priv = dev->dev_private;
3864 unsigned long pctx_paddr, paddr;
3865 struct i915_gtt *gtt = &dev_priv->gtt;
3866 u32 pcbr;
3867 int pctx_size = 32*1024;
3868
3869 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3870
3871 pcbr = I915_READ(VLV_PCBR);
3872 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
3873 paddr = (dev_priv->mm.stolen_base +
3874 (gtt->stolen_size - pctx_size));
3875
3876 pctx_paddr = (paddr & (~4095));
3877 I915_WRITE(VLV_PCBR, pctx_paddr);
3878 }
3879}
3880
c9cddffc
JB		 3881static void valleyview_setup_pctx(struct drm_device *dev)
3882{
3883 struct drm_i915_private *dev_priv = dev->dev_private;
3884 struct drm_i915_gem_object *pctx;
3885 unsigned long pctx_paddr;
3886 u32 pcbr;
3887 int pctx_size = 24*1024;
3888
17b0c1f7
ID		 3889 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3890
c9cddffc
JB		 3891 pcbr = I915_READ(VLV_PCBR);
3892 if (pcbr) {
3893 /* BIOS set it up already, grab the pre-alloc'd space */
3894 int pcbr_offset;
3895
3896 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3897 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3898 pcbr_offset,
190d6cd5 3899 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3900 pctx_size);
3901 goto out;
3902 }
3903
3904 /*
3905 * From the Gunit register HAS:
3906 * The Gfx driver is expected to program this register and ensure
3907 * proper allocation within Gfx stolen memory. For example, this
3908 * register should be programmed such than the PCBR range does not
3909 * overlap with other ranges, such as the frame buffer, protected
3910 * memory, or any other relevant ranges.
3911 */
3912 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3913 if (!pctx) {
3914 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3915 return;
3916 }
3917
3918 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3919 I915_WRITE(VLV_PCBR, pctx_paddr);
3920
3921out:
3922 dev_priv->vlv_pctx = pctx;
3923}
3924
ae48434c
ID		 3925static void valleyview_cleanup_pctx(struct drm_device *dev)
3926{
3927 struct drm_i915_private *dev_priv = dev->dev_private;
3928
3929 if (WARN_ON(!dev_priv->vlv_pctx))
3930 return;
3931
3932 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3933 dev_priv->vlv_pctx = NULL;
3934}
3935
4e80519e
ID		 3936static void valleyview_init_gt_powersave(struct drm_device *dev)
3937{
3938 struct drm_i915_private *dev_priv = dev->dev_private;
3939
3940 valleyview_setup_pctx(dev);
3941
3942 mutex_lock(&dev_priv->rps.hw_lock);
3943
3944 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3945 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3946 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3947 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3948 dev_priv->rps.max_freq);
3949
3950 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3951 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3952 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3953 dev_priv->rps.efficient_freq);
3954
3955 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3956 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3957 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3958 dev_priv->rps.min_freq);
3959
3960 /* Preserve min/max settings in case of re-init */
3961 if (dev_priv->rps.max_freq_softlimit == 0)
3962 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3963
3964 if (dev_priv->rps.min_freq_softlimit == 0)
3965 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3966
3967 mutex_unlock(&dev_priv->rps.hw_lock);
3968}
3969
38807746
D		 3970static void cherryview_init_gt_powersave(struct drm_device *dev)
3971{
2b6b3a09
D		 3972 struct drm_i915_private *dev_priv = dev->dev_private;
3973
38807746 3974 cherryview_setup_pctx(dev);
2b6b3a09
D		 3975
3976 mutex_lock(&dev_priv->rps.hw_lock);
3977
3978 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
3979 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3980 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3981 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3982 dev_priv->rps.max_freq);
3983
3984 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
3985 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3986 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3987 dev_priv->rps.efficient_freq);
3988
3989 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
3990 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3991 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3992 dev_priv->rps.min_freq);
3993
3994 /* Preserve min/max settings in case of re-init */
3995 if (dev_priv->rps.max_freq_softlimit == 0)
3996 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3997
3998 if (dev_priv->rps.min_freq_softlimit == 0)
3999 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4000
4001 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 4002}
4003
4e80519e
ID		 4004static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4005{
4006 valleyview_cleanup_pctx(dev);
4007}
4008
38807746
D		 4009static void cherryview_enable_rps(struct drm_device *dev)
4010{
4011 struct drm_i915_private *dev_priv = dev->dev_private;
4012 struct intel_engine_cs *ring;
2b6b3a09 4013 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 4014 int i;
4015
4016 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4017
4018 gtfifodbg = I915_READ(GTFIFODBG);
4019 if (gtfifodbg) {
4020 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4021 gtfifodbg);
4022 I915_WRITE(GTFIFODBG, gtfifodbg);
4023 }
4024
4025 cherryview_check_pctx(dev_priv);
4026
4027 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4028 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4029 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4030
4031 /* 2a: Program RC6 thresholds.*/
4032 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4033 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4034 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4035
4036 for_each_ring(ring, dev_priv, i)
4037 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4038 I915_WRITE(GEN6_RC_SLEEP, 0);
4039
4040 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4041
4042 /* allows RC6 residency counter to work */
4043 I915_WRITE(VLV_COUNTER_CONTROL,
4044 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4045 VLV_MEDIA_RC6_COUNT_EN |
4046 VLV_RENDER_RC6_COUNT_EN));
4047
4048 /* For now we assume BIOS is allocating and populating the PCBR */
4049 pcbr = I915_READ(VLV_PCBR);
4050
4051 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4052
4053 /* 3: Enable RC6 */
4054 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4055 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4056 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4057
4058 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4059
2b6b3a09
D		 4060 /* 4 Program defaults and thresholds for RPS*/
4061 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4062 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4063 I915_WRITE(GEN6_RP_UP_EI, 66000);
4064 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4065
4066 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4067
7405f42c
TR		 4068 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4069 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4070 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4071
2b6b3a09
D		 4072 /* 5: Enable RPS */
4073 I915_WRITE(GEN6_RP_CONTROL,
4074 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7405f42c 4075 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
2b6b3a09
D		 4076 GEN6_RP_ENABLE |
4077 GEN6_RP_UP_BUSY_AVG |
4078 GEN6_RP_DOWN_IDLE_AVG);
4079
4080 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4081
4082 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4083 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4084
4085 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4086 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4087 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4088 dev_priv->rps.cur_freq);
4089
4090 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4091 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4092 dev_priv->rps.efficient_freq);
4093
4094 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4095
38807746
D		 4096 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4097}
4098
0a073b84
JB		 4099static void valleyview_enable_rps(struct drm_device *dev)
4100{
4101 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4102 struct intel_engine_cs *ring;
2a5913a8 4103 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 4104 int i;
4105
4106 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4107
ae48434c
ID		 4108 valleyview_check_pctx(dev_priv);
4109
0a073b84 4110 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 4111 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4112 gtfifodbg);
0a073b84
JB		 4113 I915_WRITE(GTFIFODBG, gtfifodbg);
4114 }
4115
c8d9a590
D		 4116 /* If VLV, Forcewake all wells, else re-direct to regular path */
4117 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4118
4119 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4120 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4121 I915_WRITE(GEN6_RP_UP_EI, 66000);
4122 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4123
4124 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
31685c25 4125 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
0a073b84
JB		 4126
4127 I915_WRITE(GEN6_RP_CONTROL,
4128 GEN6_RP_MEDIA_TURBO |
4129 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4130 GEN6_RP_MEDIA_IS_GFX |
4131 GEN6_RP_ENABLE |
4132 GEN6_RP_UP_BUSY_AVG |
4133 GEN6_RP_DOWN_IDLE_CONT);
4134
4135 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4136 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4137 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4138
4139 for_each_ring(ring, dev_priv, i)
4140 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4141
2f0aa304 4142 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 4143
4144 /* allows RC6 residency counter to work */
49798eb2 4145 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 4146 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4147 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 4148 VLV_MEDIA_RC6_COUNT_EN |
4149 VLV_RENDER_RC6_COUNT_EN));
31685c25 4150
a2b23fe0 4151 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 4152 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 4153
4154 intel_print_rc6_info(dev, rc6_mode);
4155
a2b23fe0 4156 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 4157
64936258 4158 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 4159
4160 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4161 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4162
b39fb297 4163 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 4164 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
b39fb297
BW		 4165 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4166 dev_priv->rps.cur_freq);
0a073b84 4167
73008b98 4168 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
b39fb297
BW		 4169 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4170 dev_priv->rps.efficient_freq);
0a073b84 4171
b39fb297 4172 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 4173
44fc7d5c 4174 gen6_enable_rps_interrupts(dev);
0a073b84 4175
c8d9a590 4176 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4177}
4178
930ebb46 4179void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 4180{
4181 struct drm_i915_private *dev_priv = dev->dev_private;
4182
3e373948 4183 if (dev_priv->ips.renderctx) {
d7f46fc4 4184 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3e373948
DV		 4185 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4186 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 4187 }
4188
3e373948 4189 if (dev_priv->ips.pwrctx) {
d7f46fc4 4190 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3e373948
DV		 4191 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4192 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 4193 }
4194}
4195
930ebb46 4196static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4197{
4198 struct drm_i915_private *dev_priv = dev->dev_private;
4199
4200 if (I915_READ(PWRCTXA)) {
4201 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4202 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4203 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4204 50);
4205
4206 I915_WRITE(PWRCTXA, 0);
4207 POSTING_READ(PWRCTXA);
4208
4209 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4210 POSTING_READ(RSTDBYCTL);
4211 }
2b4e57bd
ED		 4212}
4213
4214static int ironlake_setup_rc6(struct drm_device *dev)
4215{
4216 struct drm_i915_private *dev_priv = dev->dev_private;
4217
3e373948
DV		 4218 if (dev_priv->ips.renderctx == NULL)
4219 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4220 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 4221 return -ENOMEM;
4222
3e373948
DV		 4223 if (dev_priv->ips.pwrctx == NULL)
4224 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4225 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 4226 ironlake_teardown_rc6(dev);
4227 return -ENOMEM;
4228 }
4229
4230 return 0;
4231}
4232
930ebb46 4233static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4234{
4235 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4236 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e960501 4237 bool was_interruptible;
2b4e57bd
ED		 4238 int ret;
4239
4240 /* rc6 disabled by default due to repeated reports of hanging during
4241 * boot and resume.
4242 */
4243 if (!intel_enable_rc6(dev))
4244 return;
4245
79f5b2c7
DV		 4246 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4247
2b4e57bd 4248 ret = ironlake_setup_rc6(dev);
79f5b2c7 4249 if (ret)
2b4e57bd 4250 return;
2b4e57bd 4251
3e960501
CW		 4252 was_interruptible = dev_priv->mm.interruptible;
4253 dev_priv->mm.interruptible = false;
4254
2b4e57bd
ED		 4255 /*
4256 * GPU can automatically power down the render unit if given a page
4257 * to save state.
4258 */
6d90c952 4259 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 4260 if (ret) {
4261 ironlake_teardown_rc6(dev);
3e960501 4262 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 4263 return;
4264 }
4265
6d90c952
DV		 4266 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4267 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 4268 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 4269 MI_MM_SPACE_GTT |
4270 MI_SAVE_EXT_STATE_EN |
4271 MI_RESTORE_EXT_STATE_EN |
4272 MI_RESTORE_INHIBIT);
4273 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4274 intel_ring_emit(ring, MI_NOOP);
4275 intel_ring_emit(ring, MI_FLUSH);
4276 intel_ring_advance(ring);
2b4e57bd
ED		 4277
4278 /*
4279 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4280 * does an implicit flush, combined with MI_FLUSH above, it should be
4281 * safe to assume that renderctx is valid
4282 */
3e960501
CW		 4283 ret = intel_ring_idle(ring);
4284 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 4285 if (ret) {
def27a58 4286 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4287 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4288 return;
4289 }
4290
f343c5f6 4291 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4292 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7 4293
91ca689a 4294 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
2b4e57bd
ED		 4295}
4296
dde18883
ED		 4297static unsigned long intel_pxfreq(u32 vidfreq)
4298{
4299 unsigned long freq;
4300 int div = (vidfreq & 0x3f0000) >> 16;
4301 int post = (vidfreq & 0x3000) >> 12;
4302 int pre = (vidfreq & 0x7);
4303
4304 if (!pre)
4305 return 0;
4306
4307 freq = ((div * 133333) / ((1<<post) * pre));
4308
4309 return freq;
4310}
4311
eb48eb00
DV		 4312static const struct cparams {
4313 u16 i;
4314 u16 t;
4315 u16 m;
4316 u16 c;
4317} cparams[] = {
4318 { 1, 1333, 301, 28664 },
4319 { 1, 1066, 294, 24460 },
4320 { 1, 800, 294, 25192 },
4321 { 0, 1333, 276, 27605 },
4322 { 0, 1066, 276, 27605 },
4323 { 0, 800, 231, 23784 },
4324};
4325
f531dcb2 4326static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4327{
4328 u64 total_count, diff, ret;
4329 u32 count1, count2, count3, m = 0, c = 0;
4330 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4331 int i;
4332
02d71956
DV		 4333 assert_spin_locked(&mchdev_lock);
4334
20e4d407 4335 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4336
4337 /* Prevent division-by-zero if we are asking too fast.
4338 * Also, we don't get interesting results if we are polling
4339 * faster than once in 10ms, so just return the saved value
4340 * in such cases.
4341 */
4342 if (diff1 <= 10)
20e4d407 4343 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4344
4345 count1 = I915_READ(DMIEC);
4346 count2 = I915_READ(DDREC);
4347 count3 = I915_READ(CSIEC);
4348
4349 total_count = count1 + count2 + count3;
4350
4351 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4352 if (total_count < dev_priv->ips.last_count1) {
4353 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4354 diff += total_count;
4355 } else {
20e4d407 4356 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4357 }
4358
4359 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4360 if (cparams[i].i == dev_priv->ips.c_m &&
4361 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4362 m = cparams[i].m;
4363 c = cparams[i].c;
4364 break;
4365 }
4366 }
4367
4368 diff = div_u64(diff, diff1);
4369 ret = ((m * diff) + c);
4370 ret = div_u64(ret, 10);
4371
20e4d407
DV		 4372 dev_priv->ips.last_count1 = total_count;
4373 dev_priv->ips.last_time1 = now;
eb48eb00 4374
20e4d407 4375 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4376
4377 return ret;
4378}
4379
f531dcb2
CW		 4380unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4381{
3d13ef2e 4382 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4383 unsigned long val;
4384
3d13ef2e 4385 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4386 return 0;
4387
4388 spin_lock_irq(&mchdev_lock);
4389
4390 val = __i915_chipset_val(dev_priv);
4391
4392 spin_unlock_irq(&mchdev_lock);
4393
4394 return val;
4395}
4396
eb48eb00
DV		 4397unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4398{
4399 unsigned long m, x, b;
4400 u32 tsfs;
4401
4402 tsfs = I915_READ(TSFS);
4403
4404 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4405 x = I915_READ8(TR1);
4406
4407 b = tsfs & TSFS_INTR_MASK;
4408
4409 return ((m * x) / 127) - b;
4410}
4411
4412static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4413{
3d13ef2e 4414 struct drm_device *dev = dev_priv->dev;
eb48eb00
DV		 4415 static const struct v_table {
4416 u16 vd; /* in .1 mil */
4417 u16 vm; /* in .1 mil */
4418 } v_table[] = {
4419 { 0, 0, },
4420 { 375, 0, },
4421 { 500, 0, },
4422 { 625, 0, },
4423 { 750, 0, },
4424 { 875, 0, },
4425 { 1000, 0, },
4426 { 1125, 0, },
4427 { 4125, 3000, },
4428 { 4125, 3000, },
4429 { 4125, 3000, },
4430 { 4125, 3000, },
4431 { 4125, 3000, },
4432 { 4125, 3000, },
4433 { 4125, 3000, },
4434 { 4125, 3000, },
4435 { 4125, 3000, },
4436 { 4125, 3000, },
4437 { 4125, 3000, },
4438 { 4125, 3000, },
4439 { 4125, 3000, },
4440 { 4125, 3000, },
4441 { 4125, 3000, },
4442 { 4125, 3000, },
4443 { 4125, 3000, },
4444 { 4125, 3000, },
4445 { 4125, 3000, },
4446 { 4125, 3000, },
4447 { 4125, 3000, },
4448 { 4125, 3000, },
4449 { 4125, 3000, },
4450 { 4125, 3000, },
4451 { 4250, 3125, },
4452 { 4375, 3250, },
4453 { 4500, 3375, },
4454 { 4625, 3500, },
4455 { 4750, 3625, },
4456 { 4875, 3750, },
4457 { 5000, 3875, },
4458 { 5125, 4000, },
4459 { 5250, 4125, },
4460 { 5375, 4250, },
4461 { 5500, 4375, },
4462 { 5625, 4500, },
4463 { 5750, 4625, },
4464 { 5875, 4750, },
4465 { 6000, 4875, },
4466 { 6125, 5000, },
4467 { 6250, 5125, },
4468 { 6375, 5250, },
4469 { 6500, 5375, },
4470 { 6625, 5500, },
4471 { 6750, 5625, },
4472 { 6875, 5750, },
4473 { 7000, 5875, },
4474 { 7125, 6000, },
4475 { 7250, 6125, },
4476 { 7375, 6250, },
4477 { 7500, 6375, },
4478 { 7625, 6500, },
4479 { 7750, 6625, },
4480 { 7875, 6750, },
4481 { 8000, 6875, },
4482 { 8125, 7000, },
4483 { 8250, 7125, },
4484 { 8375, 7250, },
4485 { 8500, 7375, },
4486 { 8625, 7500, },
4487 { 8750, 7625, },
4488 { 8875, 7750, },
4489 { 9000, 7875, },
4490 { 9125, 8000, },
4491 { 9250, 8125, },
4492 { 9375, 8250, },
4493 { 9500, 8375, },
4494 { 9625, 8500, },
4495 { 9750, 8625, },
4496 { 9875, 8750, },
4497 { 10000, 8875, },
4498 { 10125, 9000, },
4499 { 10250, 9125, },
4500 { 10375, 9250, },
4501 { 10500, 9375, },
4502 { 10625, 9500, },
4503 { 10750, 9625, },
4504 { 10875, 9750, },
4505 { 11000, 9875, },
4506 { 11125, 10000, },
4507 { 11250, 10125, },
4508 { 11375, 10250, },
4509 { 11500, 10375, },
4510 { 11625, 10500, },
4511 { 11750, 10625, },
4512 { 11875, 10750, },
4513 { 12000, 10875, },
4514 { 12125, 11000, },
4515 { 12250, 11125, },
4516 { 12375, 11250, },
4517 { 12500, 11375, },
4518 { 12625, 11500, },
4519 { 12750, 11625, },
4520 { 12875, 11750, },
4521 { 13000, 11875, },
4522 { 13125, 12000, },
4523 { 13250, 12125, },
4524 { 13375, 12250, },
4525 { 13500, 12375, },
4526 { 13625, 12500, },
4527 { 13750, 12625, },
4528 { 13875, 12750, },
4529 { 14000, 12875, },
4530 { 14125, 13000, },
4531 { 14250, 13125, },
4532 { 14375, 13250, },
4533 { 14500, 13375, },
4534 { 14625, 13500, },
4535 { 14750, 13625, },
4536 { 14875, 13750, },
4537 { 15000, 13875, },
4538 { 15125, 14000, },
4539 { 15250, 14125, },
4540 { 15375, 14250, },
4541 { 15500, 14375, },
4542 { 15625, 14500, },
4543 { 15750, 14625, },
4544 { 15875, 14750, },
4545 { 16000, 14875, },
4546 { 16125, 15000, },
4547 };
3d13ef2e 4548 if (INTEL_INFO(dev)->is_mobile)
eb48eb00
DV		 4549 return v_table[pxvid].vm;
4550 else
4551 return v_table[pxvid].vd;
4552}
4553
02d71956 4554static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4555{
4556 struct timespec now, diff1;
4557 u64 diff;
4558 unsigned long diffms;
4559 u32 count;
4560
02d71956 4561 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4562
4563 getrawmonotonic(&now);
20e4d407 4564 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4565
4566 /* Don't divide by 0 */
4567 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4568 if (!diffms)
4569 return;
4570
4571 count = I915_READ(GFXEC);
4572
20e4d407
DV		 4573 if (count < dev_priv->ips.last_count2) {
4574 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4575 diff += count;
4576 } else {
20e4d407 4577 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4578 }
4579
20e4d407
DV		 4580 dev_priv->ips.last_count2 = count;
4581 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4582
4583 /* More magic constants... */
4584 diff = diff * 1181;
4585 diff = div_u64(diff, diffms * 10);
20e4d407 4586 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4587}
4588
02d71956
DV		 4589void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4590{
3d13ef2e
DL		 4591 struct drm_device *dev = dev_priv->dev;
4592
4593 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 4594 return;
4595
9270388e 4596 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4597
4598 __i915_update_gfx_val(dev_priv);
4599
9270388e 4600 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4601}
4602
f531dcb2 4603static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4604{
4605 unsigned long t, corr, state1, corr2, state2;
4606 u32 pxvid, ext_v;
4607
02d71956
DV		 4608 assert_spin_locked(&mchdev_lock);
4609
b39fb297 4610 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 4611 pxvid = (pxvid >> 24) & 0x7f;
4612 ext_v = pvid_to_extvid(dev_priv, pxvid);
4613
4614 state1 = ext_v;
4615
4616 t = i915_mch_val(dev_priv);
4617
4618 /* Revel in the empirically derived constants */
4619
4620 /* Correction factor in 1/100000 units */
4621 if (t > 80)
4622 corr = ((t * 2349) + 135940);
4623 else if (t >= 50)
4624 corr = ((t * 964) + 29317);
4625 else /* < 50 */
4626 corr = ((t * 301) + 1004);
4627
4628 corr = corr * ((150142 * state1) / 10000 - 78642);
4629 corr /= 100000;
20e4d407 4630 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4631
4632 state2 = (corr2 * state1) / 10000;
4633 state2 /= 100; /* convert to mW */
4634
02d71956 4635 __i915_update_gfx_val(dev_priv);
eb48eb00 4636
20e4d407 4637 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4638}
4639
f531dcb2
CW		 4640unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4641{
3d13ef2e 4642 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4643 unsigned long val;
4644
3d13ef2e 4645 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4646 return 0;
4647
4648 spin_lock_irq(&mchdev_lock);
4649
4650 val = __i915_gfx_val(dev_priv);
4651
4652 spin_unlock_irq(&mchdev_lock);
4653
4654 return val;
4655}
4656
eb48eb00
DV		 4657/**
4658 * i915_read_mch_val - return value for IPS use
4659 *
4660 * Calculate and return a value for the IPS driver to use when deciding whether
4661 * we have thermal and power headroom to increase CPU or GPU power budget.
4662 */
4663unsigned long i915_read_mch_val(void)
4664{
4665 struct drm_i915_private *dev_priv;
4666 unsigned long chipset_val, graphics_val, ret = 0;
4667
9270388e 4668 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4669 if (!i915_mch_dev)
4670 goto out_unlock;
4671 dev_priv = i915_mch_dev;
4672
f531dcb2
CW		 4673 chipset_val = __i915_chipset_val(dev_priv);
4674 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4675
4676 ret = chipset_val + graphics_val;
4677
4678out_unlock:
9270388e 4679 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4680
4681 return ret;
4682}
4683EXPORT_SYMBOL_GPL(i915_read_mch_val);
4684
4685/**
4686 * i915_gpu_raise - raise GPU frequency limit
4687 *
4688 * Raise the limit; IPS indicates we have thermal headroom.
4689 */
4690bool i915_gpu_raise(void)
4691{
4692 struct drm_i915_private *dev_priv;
4693 bool ret = true;
4694
9270388e 4695 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4696 if (!i915_mch_dev) {
4697 ret = false;
4698 goto out_unlock;
4699 }
4700 dev_priv = i915_mch_dev;
4701
20e4d407
DV		 4702 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4703 dev_priv->ips.max_delay--;
eb48eb00
DV		 4704
4705out_unlock:
9270388e 4706 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4707
4708 return ret;
4709}
4710EXPORT_SYMBOL_GPL(i915_gpu_raise);
4711
4712/**
4713 * i915_gpu_lower - lower GPU frequency limit
4714 *
4715 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4716 * frequency maximum.
4717 */
4718bool i915_gpu_lower(void)
4719{
4720 struct drm_i915_private *dev_priv;
4721 bool ret = true;
4722
9270388e 4723 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4724 if (!i915_mch_dev) {
4725 ret = false;
4726 goto out_unlock;
4727 }
4728 dev_priv = i915_mch_dev;
4729
20e4d407
DV		 4730 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4731 dev_priv->ips.max_delay++;
eb48eb00
DV		 4732
4733out_unlock:
9270388e 4734 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4735
4736 return ret;
4737}
4738EXPORT_SYMBOL_GPL(i915_gpu_lower);
4739
4740/**
4741 * i915_gpu_busy - indicate GPU business to IPS
4742 *
4743 * Tell the IPS driver whether or not the GPU is busy.
4744 */
4745bool i915_gpu_busy(void)
4746{
4747 struct drm_i915_private *dev_priv;
a4872ba6 4748 struct intel_engine_cs *ring;
eb48eb00 4749 bool ret = false;
f047e395 4750 int i;
eb48eb00 4751
9270388e 4752 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4753 if (!i915_mch_dev)
4754 goto out_unlock;
4755 dev_priv = i915_mch_dev;
4756
f047e395
CW		 4757 for_each_ring(ring, dev_priv, i)
4758 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4759
4760out_unlock:
9270388e 4761 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4762
4763 return ret;
4764}
4765EXPORT_SYMBOL_GPL(i915_gpu_busy);
4766
4767/**
4768 * i915_gpu_turbo_disable - disable graphics turbo
4769 *
4770 * Disable graphics turbo by resetting the max frequency and setting the
4771 * current frequency to the default.
4772 */
4773bool i915_gpu_turbo_disable(void)
4774{
4775 struct drm_i915_private *dev_priv;
4776 bool ret = true;
4777
9270388e 4778 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4779 if (!i915_mch_dev) {
4780 ret = false;
4781 goto out_unlock;
4782 }
4783 dev_priv = i915_mch_dev;
4784
20e4d407 4785 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4786
20e4d407 4787 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4788 ret = false;
4789
4790out_unlock:
9270388e 4791 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4792
4793 return ret;
4794}
4795EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4796
4797/**
4798 * Tells the intel_ips driver that the i915 driver is now loaded, if
4799 * IPS got loaded first.
4800 *
4801 * This awkward dance is so that neither module has to depend on the
4802 * other in order for IPS to do the appropriate communication of
4803 * GPU turbo limits to i915.
4804 */
4805static void
4806ips_ping_for_i915_load(void)
4807{
4808 void (*link)(void);
4809
4810 link = symbol_get(ips_link_to_i915_driver);
4811 if (link) {
4812 link();
4813 symbol_put(ips_link_to_i915_driver);
4814 }
4815}
4816
4817void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4818{
02d71956
DV		 4819 /* We only register the i915 ips part with intel-ips once everything is
4820 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4821 spin_lock_irq(&mchdev_lock);
eb48eb00 4822 i915_mch_dev = dev_priv;
9270388e 4823 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4824
4825 ips_ping_for_i915_load();
4826}
4827
4828void intel_gpu_ips_teardown(void)
4829{
9270388e 4830 spin_lock_irq(&mchdev_lock);
eb48eb00 4831 i915_mch_dev = NULL;
9270388e 4832 spin_unlock_irq(&mchdev_lock);
eb48eb00 4833}
76c3552f 4834
8090c6b9 4835static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4836{
4837 struct drm_i915_private *dev_priv = dev->dev_private;
4838 u32 lcfuse;
4839 u8 pxw[16];
4840 int i;
4841
4842 /* Disable to program */
4843 I915_WRITE(ECR, 0);
4844 POSTING_READ(ECR);
4845
4846 /* Program energy weights for various events */
4847 I915_WRITE(SDEW, 0x15040d00);
4848 I915_WRITE(CSIEW0, 0x007f0000);
4849 I915_WRITE(CSIEW1, 0x1e220004);
4850 I915_WRITE(CSIEW2, 0x04000004);
4851
4852 for (i = 0; i < 5; i++)
4853 I915_WRITE(PEW + (i * 4), 0);
4854 for (i = 0; i < 3; i++)
4855 I915_WRITE(DEW + (i * 4), 0);
4856
4857 /* Program P-state weights to account for frequency power adjustment */
4858 for (i = 0; i < 16; i++) {
4859 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4860 unsigned long freq = intel_pxfreq(pxvidfreq);
4861 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4862 PXVFREQ_PX_SHIFT;
4863 unsigned long val;
4864
4865 val = vid * vid;
4866 val *= (freq / 1000);
4867 val *= 255;
4868 val /= (127*127*900);
4869 if (val > 0xff)
4870 DRM_ERROR("bad pxval: %ld\n", val);
4871 pxw[i] = val;
4872 }
4873 /* Render standby states get 0 weight */
4874 pxw[14] = 0;
4875 pxw[15] = 0;
4876
4877 for (i = 0; i < 4; i++) {
4878 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4879 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4880 I915_WRITE(PXW + (i * 4), val);
4881 }
4882
4883 /* Adjust magic regs to magic values (more experimental results) */
4884 I915_WRITE(OGW0, 0);
4885 I915_WRITE(OGW1, 0);
4886 I915_WRITE(EG0, 0x00007f00);
4887 I915_WRITE(EG1, 0x0000000e);
4888 I915_WRITE(EG2, 0x000e0000);
4889 I915_WRITE(EG3, 0x68000300);
4890 I915_WRITE(EG4, 0x42000000);
4891 I915_WRITE(EG5, 0x00140031);
4892 I915_WRITE(EG6, 0);
4893 I915_WRITE(EG7, 0);
4894
4895 for (i = 0; i < 8; i++)
4896 I915_WRITE(PXWL + (i * 4), 0);
4897
4898 /* Enable PMON + select events */
4899 I915_WRITE(ECR, 0x80000019);
4900
4901 lcfuse = I915_READ(LCFUSE02);
4902
20e4d407 4903 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4904}
4905
ae48434c
ID		 4906void intel_init_gt_powersave(struct drm_device *dev)
4907{
e6069ca8
ID		 4908 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4909
38807746
D		 4910 if (IS_CHERRYVIEW(dev))
4911 cherryview_init_gt_powersave(dev);
4912 else if (IS_VALLEYVIEW(dev))
4e80519e 4913 valleyview_init_gt_powersave(dev);
ae48434c
ID		 4914}
4915
4916void intel_cleanup_gt_powersave(struct drm_device *dev)
4917{
38807746
D		 4918 if (IS_CHERRYVIEW(dev))
4919 return;
4920 else if (IS_VALLEYVIEW(dev))
4e80519e 4921 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 4922}
4923
156c7ca0
JB		 4924/**
4925 * intel_suspend_gt_powersave - suspend PM work and helper threads
4926 * @dev: drm device
4927 *
4928 * We don't want to disable RC6 or other features here, we just want
4929 * to make sure any work we've queued has finished and won't bother
4930 * us while we're suspended.
4931 */
4932void intel_suspend_gt_powersave(struct drm_device *dev)
4933{
4934 struct drm_i915_private *dev_priv = dev->dev_private;
4935
4936 /* Interrupts should be disabled already to avoid re-arming. */
e11aa362 4937 WARN_ON(dev->irq_enabled && !dev_priv->pm.irqs_disabled);
156c7ca0
JB		 4938
4939 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4940
4941 cancel_work_sync(&dev_priv->rps.work);
4942}
4943
8090c6b9
DV		 4944void intel_disable_gt_powersave(struct drm_device *dev)
4945{
1a01ab3b
JB		 4946 struct drm_i915_private *dev_priv = dev->dev_private;
4947
fd0c0642 4948 /* Interrupts should be disabled already to avoid re-arming. */
e11aa362 4949 WARN_ON(dev->irq_enabled && !dev_priv->pm.irqs_disabled);
fd0c0642 4950
930ebb46 4951 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4952 ironlake_disable_drps(dev);
930ebb46 4953 ironlake_disable_rc6(dev);
38807746 4954 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 4955 intel_suspend_gt_powersave(dev);
e494837a 4956
4fc688ce 4957 mutex_lock(&dev_priv->rps.hw_lock);
38807746
D		 4958 if (IS_CHERRYVIEW(dev))
4959 cherryview_disable_rps(dev);
4960 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 4961 valleyview_disable_rps(dev);
4962 else
4963 gen6_disable_rps(dev);
c0951f0c 4964 dev_priv->rps.enabled = false;
4fc688ce 4965 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4966 }
8090c6b9
DV		 4967}
4968
1a01ab3b
JB		 4969static void intel_gen6_powersave_work(struct work_struct *work)
4970{
4971 struct drm_i915_private *dev_priv =
4972 container_of(work, struct drm_i915_private,
4973 rps.delayed_resume_work.work);
4974 struct drm_device *dev = dev_priv->dev;
4975
4fc688ce 4976 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 4977
38807746
D		 4978 if (IS_CHERRYVIEW(dev)) {
4979 cherryview_enable_rps(dev);
4980 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 4981 valleyview_enable_rps(dev);
6edee7f3
BW		 4982 } else if (IS_BROADWELL(dev)) {
4983 gen8_enable_rps(dev);
c2bc2fc5 4984 __gen6_update_ring_freq(dev);
0a073b84
JB		 4985 } else {
4986 gen6_enable_rps(dev);
c2bc2fc5 4987 __gen6_update_ring_freq(dev);
0a073b84 4988 }
c0951f0c 4989 dev_priv->rps.enabled = true;
4fc688ce 4990 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 4991
4992 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 4993}
4994
8090c6b9
DV		 4995void intel_enable_gt_powersave(struct drm_device *dev)
4996{
1a01ab3b
JB		 4997 struct drm_i915_private *dev_priv = dev->dev_private;
4998
8090c6b9 4999 if (IS_IRONLAKE_M(dev)) {
dc1d0136 5000 mutex_lock(&dev->struct_mutex);
8090c6b9
DV		 5001 ironlake_enable_drps(dev);
5002 ironlake_enable_rc6(dev);
5003 intel_init_emon(dev);
dc1d0136 5004 mutex_unlock(&dev->struct_mutex);
38807746 5005 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 5006 /*
5007 * PCU communication is slow and this doesn't need to be
5008 * done at any specific time, so do this out of our fast path
5009 * to make resume and init faster.
c6df39b5
ID		 5010 *
5011 * We depend on the HW RC6 power context save/restore
5012 * mechanism when entering D3 through runtime PM suspend. So
5013 * disable RPM until RPS/RC6 is properly setup. We can only
5014 * get here via the driver load/system resume/runtime resume
5015 * paths, so the _noresume version is enough (and in case of
5016 * runtime resume it's necessary).
1a01ab3b 5017 */
c6df39b5
ID		 5018 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5019 round_jiffies_up_relative(HZ)))
5020 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 5021 }
5022}
5023
c6df39b5
ID		 5024void intel_reset_gt_powersave(struct drm_device *dev)
5025{
5026 struct drm_i915_private *dev_priv = dev->dev_private;
5027
5028 dev_priv->rps.enabled = false;
5029 intel_enable_gt_powersave(dev);
5030}
5031
3107bd48
DV		 5032static void ibx_init_clock_gating(struct drm_device *dev)
5033{
5034 struct drm_i915_private *dev_priv = dev->dev_private;
5035
5036 /*
5037 * On Ibex Peak and Cougar Point, we need to disable clock
5038 * gating for the panel power sequencer or it will fail to
5039 * start up when no ports are active.
5040 */
5041 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5042}
5043
0e088b8f
VS		 5044static void g4x_disable_trickle_feed(struct drm_device *dev)
5045{
5046 struct drm_i915_private *dev_priv = dev->dev_private;
5047 int pipe;
5048
5049 for_each_pipe(pipe) {
5050 I915_WRITE(DSPCNTR(pipe),
5051 I915_READ(DSPCNTR(pipe)) |
5052 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 5053 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 5054 }
5055}
5056
017636cc
VS		 5057static void ilk_init_lp_watermarks(struct drm_device *dev)
5058{
5059 struct drm_i915_private *dev_priv = dev->dev_private;
5060
5061 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5062 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5063 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5064
5065 /*
5066 * Don't touch WM1S_LP_EN here.
5067 * Doing so could cause underruns.
5068 */
5069}
5070
1fa61106 5071static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5072{
5073 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5074 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5075
f1e8fa56
DL		 5076 /*
5077 * Required for FBC
5078 * WaFbcDisableDpfcClockGating:ilk
5079 */
4d47e4f5
DL		 5080 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5081 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5082 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5083
5084 I915_WRITE(PCH_3DCGDIS0,
5085 MARIUNIT_CLOCK_GATE_DISABLE |
5086 SVSMUNIT_CLOCK_GATE_DISABLE);
5087 I915_WRITE(PCH_3DCGDIS1,
5088 VFMUNIT_CLOCK_GATE_DISABLE);
5089
6f1d69b0
ED		 5090 /*
5091 * According to the spec the following bits should be set in
5092 * order to enable memory self-refresh
5093 * The bit 22/21 of 0x42004
5094 * The bit 5 of 0x42020
5095 * The bit 15 of 0x45000
5096 */
5097 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5098 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5099 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5100 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5101 I915_WRITE(DISP_ARB_CTL,
5102 (I915_READ(DISP_ARB_CTL) |
5103 DISP_FBC_WM_DIS));
017636cc
VS		 5104
5105 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 5106
5107 /*
5108 * Based on the document from hardware guys the following bits
5109 * should be set unconditionally in order to enable FBC.
5110 * The bit 22 of 0x42000
5111 * The bit 22 of 0x42004
5112 * The bit 7,8,9 of 0x42020.
5113 */
5114 if (IS_IRONLAKE_M(dev)) {
4bb35334 5115 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5116 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5117 I915_READ(ILK_DISPLAY_CHICKEN1) |
5118 ILK_FBCQ_DIS);
5119 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5120 I915_READ(ILK_DISPLAY_CHICKEN2) |
5121 ILK_DPARB_GATE);
6f1d69b0
ED		 5122 }
5123
4d47e4f5
DL		 5124 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5125
6f1d69b0
ED		 5126 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5127 I915_READ(ILK_DISPLAY_CHICKEN2) |
5128 ILK_ELPIN_409_SELECT);
5129 I915_WRITE(_3D_CHICKEN2,
5130 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5131 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5132
ecdb4eb7 5133 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5134 I915_WRITE(CACHE_MODE_0,
5135 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5136
4e04632e
AG		 5137 /* WaDisable_RenderCache_OperationalFlush:ilk */
5138 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5139
0e088b8f 5140 g4x_disable_trickle_feed(dev);
bdad2b2f 5141
3107bd48
DV		 5142 ibx_init_clock_gating(dev);
5143}
5144
5145static void cpt_init_clock_gating(struct drm_device *dev)
5146{
5147 struct drm_i915_private *dev_priv = dev->dev_private;
5148 int pipe;
3f704fa2 5149 uint32_t val;
3107bd48
DV		 5150
5151 /*
5152 * On Ibex Peak and Cougar Point, we need to disable clock
5153 * gating for the panel power sequencer or it will fail to
5154 * start up when no ports are active.
5155 */
cd664078
JB		 5156 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5157 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5158 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5159 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5160 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5161 /* The below fixes the weird display corruption, a few pixels shifted
5162 * downward, on (only) LVDS of some HP laptops with IVY.
5163 */
3f704fa2 5164 for_each_pipe(pipe) {
dc4bd2d1
PZ		 5165 val = I915_READ(TRANS_CHICKEN2(pipe));
5166 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5167 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5168 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5169 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5170 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5171 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5172 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5173 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5174 }
3107bd48
DV		 5175 /* WADP0ClockGatingDisable */
5176 for_each_pipe(pipe) {
5177 I915_WRITE(TRANS_CHICKEN1(pipe),
5178 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5179 }
6f1d69b0
ED		 5180}
5181
1d7aaa0c
DV		 5182static void gen6_check_mch_setup(struct drm_device *dev)
5183{
5184 struct drm_i915_private *dev_priv = dev->dev_private;
5185 uint32_t tmp;
5186
5187 tmp = I915_READ(MCH_SSKPD);
5188 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5189 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5190 DRM_INFO("This can cause pipe underruns and display issues.\n");
5191 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5192 }
5193}
5194
1fa61106 5195static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5196{
5197 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5198 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5199
231e54f6 5200 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5201
5202 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5203 I915_READ(ILK_DISPLAY_CHICKEN2) |
5204 ILK_ELPIN_409_SELECT);
5205
ecdb4eb7 5206 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5207 I915_WRITE(_3D_CHICKEN,
5208 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5209
ecdb4eb7 5210 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 5211 if (IS_SNB_GT1(dev))
5212 I915_WRITE(GEN6_GT_MODE,
5213 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5214
4e04632e
AG		 5215 /* WaDisable_RenderCache_OperationalFlush:snb */
5216 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5217
8d85d272
VS		 5218 /*
5219 * BSpec recoomends 8x4 when MSAA is used,
5220 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5221 *
5222 * Note that PS/WM thread counts depend on the WIZ hashing
5223 * disable bit, which we don't touch here, but it's good
5224 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 5225 */
5226 I915_WRITE(GEN6_GT_MODE,
5227 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5228
017636cc 5229 ilk_init_lp_watermarks(dev);
6f1d69b0 5230
6f1d69b0 5231 I915_WRITE(CACHE_MODE_0,
50743298 5232 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5233
5234 I915_WRITE(GEN6_UCGCTL1,
5235 I915_READ(GEN6_UCGCTL1) |
5236 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5237 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5238
5239 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5240 * gating disable must be set. Failure to set it results in
5241 * flickering pixels due to Z write ordering failures after
5242 * some amount of runtime in the Mesa "fire" demo, and Unigine
5243 * Sanctuary and Tropics, and apparently anything else with
5244 * alpha test or pixel discard.
5245 *
5246 * According to the spec, bit 11 (RCCUNIT) must also be set,
5247 * but we didn't debug actual testcases to find it out.
0f846f81 5248 *
ef59318c
VS		 5249 * WaDisableRCCUnitClockGating:snb
5250 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 5251 */
5252 I915_WRITE(GEN6_UCGCTL2,
5253 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5254 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5255
5eb146dd 5256 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 5257 I915_WRITE(_3D_CHICKEN3,
5258 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 5259
e927ecde
VS		 5260 /*
5261 * Bspec says:
5262 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5263 * 3DSTATE_SF number of SF output attributes is more than 16."
5264 */
5265 I915_WRITE(_3D_CHICKEN3,
5266 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5267
6f1d69b0
ED		 5268 /*
5269 * According to the spec the following bits should be
5270 * set in order to enable memory self-refresh and fbc:
5271 * The bit21 and bit22 of 0x42000
5272 * The bit21 and bit22 of 0x42004
5273 * The bit5 and bit7 of 0x42020
5274 * The bit14 of 0x70180
5275 * The bit14 of 0x71180
4bb35334
DL		 5276 *
5277 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 5278 */
5279 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5280 I915_READ(ILK_DISPLAY_CHICKEN1) |
5281 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5282 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5283 I915_READ(ILK_DISPLAY_CHICKEN2) |
5284 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 5285 I915_WRITE(ILK_DSPCLK_GATE_D,
5286 I915_READ(ILK_DSPCLK_GATE_D) |
5287 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5288 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 5289
0e088b8f 5290 g4x_disable_trickle_feed(dev);
f8f2ac9a 5291
3107bd48 5292 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5293
5294 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5295}
5296
5297static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5298{
5299 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5300
3aad9059 5301 /*
46680e0a 5302 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 5303 *
5304 * This actually overrides the dispatch
5305 * mode for all thread types.
5306 */
6f1d69b0
ED		 5307 reg &= ~GEN7_FF_SCHED_MASK;
5308 reg |= GEN7_FF_TS_SCHED_HW;
5309 reg |= GEN7_FF_VS_SCHED_HW;
5310 reg |= GEN7_FF_DS_SCHED_HW;
5311
5312 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5313}
5314
17a303ec
PZ		 5315static void lpt_init_clock_gating(struct drm_device *dev)
5316{
5317 struct drm_i915_private *dev_priv = dev->dev_private;
5318
5319 /*
5320 * TODO: this bit should only be enabled when really needed, then
5321 * disabled when not needed anymore in order to save power.
5322 */
5323 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5324 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5325 I915_READ(SOUTH_DSPCLK_GATE_D) |
5326 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 5327
5328 /* WADPOClockGatingDisable:hsw */
5329 I915_WRITE(_TRANSA_CHICKEN1,
5330 I915_READ(_TRANSA_CHICKEN1) |
5331 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 5332}
5333
7d708ee4
ID		 5334static void lpt_suspend_hw(struct drm_device *dev)
5335{
5336 struct drm_i915_private *dev_priv = dev->dev_private;
5337
5338 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5339 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5340
5341 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5342 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5343 }
5344}
5345
1020a5c2
BW		 5346static void gen8_init_clock_gating(struct drm_device *dev)
5347{
5348 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 5349 enum pipe pipe;
1020a5c2
BW		 5350
5351 I915_WRITE(WM3_LP_ILK, 0);
5352 I915_WRITE(WM2_LP_ILK, 0);
5353 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 5354
5355 /* FIXME(BDW): Check all the w/a, some might only apply to
5356 * pre-production hw. */
5357
c8966e10
KG		 5358 /* WaDisablePartialInstShootdown:bdw */
5359 I915_WRITE(GEN8_ROW_CHICKEN,
5360 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5361
1411e6a5
KG		 5362 /* WaDisableThreadStallDopClockGating:bdw */
5363 /* FIXME: Unclear whether we really need this on production bdw. */
5364 I915_WRITE(GEN8_ROW_CHICKEN,
5365 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5366
4167e32c
DL		 5367 /*
5368 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5369 * pre-production hardware
5370 */
fd392b60
BW		 5371 I915_WRITE(HALF_SLICE_CHICKEN3,
5372 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 5373 I915_WRITE(HALF_SLICE_CHICKEN3,
5374 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 5375 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5376
7f88da0c 5377 I915_WRITE(_3D_CHICKEN3,
b3f9ad93 5378 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
7f88da0c 5379
a75f3628
BW		 5380 I915_WRITE(COMMON_SLICE_CHICKEN2,
5381 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5382
4c2e7a5f
BW		 5383 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5384 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5385
242a4018
BW		 5386 /* WaDisableDopClockGating:bdw May not be needed for production */
5387 I915_WRITE(GEN7_ROW_CHICKEN2,
5388 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5389
ab57fff1 5390 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 5391 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 5392
ab57fff1 5393 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 5394 I915_WRITE(CHICKEN_PAR1_1,
5395 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5396
ab57fff1 5397 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
07d27e20
DL		 5398 for_each_pipe(pipe) {
5399 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 5400 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 5401 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 5402 }
63801f21
BW		 5403
5404 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5405 * workaround for for a possible hang in the unlikely event a TLB
5406 * invalidation occurs during a PSD flush.
5407 */
5408 I915_WRITE(HDC_CHICKEN0,
5409 I915_READ(HDC_CHICKEN0) |
5410 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
ab57fff1
BW		 5411
5412 /* WaVSRefCountFullforceMissDisable:bdw */
5413 /* WaDSRefCountFullforceMissDisable:bdw */
5414 I915_WRITE(GEN7_FF_THREAD_MODE,
5415 I915_READ(GEN7_FF_THREAD_MODE) &
5416 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c
VS		 5417
5418 /*
5419 * BSpec recommends 8x4 when MSAA is used,
5420 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5421 *
5422 * Note that PS/WM thread counts depend on the WIZ hashing
5423 * disable bit, which we don't touch here, but it's good
5424 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
36075a4c
VS		 5425 */
5426 I915_WRITE(GEN7_GT_MODE,
5427 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
295e8bb7
VS		 5428
5429 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5430 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 5431
5432 /* WaDisableSDEUnitClockGating:bdw */
5433 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5434 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680
DL		 5435
5436 /* Wa4x4STCOptimizationDisable:bdw */
5437 I915_WRITE(CACHE_MODE_1,
5438 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
1020a5c2
BW		 5439}
5440
cad2a2d7
ED		 5441static void haswell_init_clock_gating(struct drm_device *dev)
5442{
5443 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 5444
017636cc 5445 ilk_init_lp_watermarks(dev);
cad2a2d7 5446
f3fc4884
FJ		 5447 /* L3 caching of data atomics doesn't work -- disable it. */
5448 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5449 I915_WRITE(HSW_ROW_CHICKEN3,
5450 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5451
ecdb4eb7 5452 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5453 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5454 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5455 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5456
e36ea7ff
VS		 5457 /* WaVSRefCountFullforceMissDisable:hsw */
5458 I915_WRITE(GEN7_FF_THREAD_MODE,
5459 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 5460
4e04632e
AG		 5461 /* WaDisable_RenderCache_OperationalFlush:hsw */
5462 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5463
fe27c606
CW		 5464 /* enable HiZ Raw Stall Optimization */
5465 I915_WRITE(CACHE_MODE_0_GEN7,
5466 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5467
ecdb4eb7 5468 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5469 I915_WRITE(CACHE_MODE_1,
5470 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5471
a12c4967
VS		 5472 /*
5473 * BSpec recommends 8x4 when MSAA is used,
5474 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5475 *
5476 * Note that PS/WM thread counts depend on the WIZ hashing
5477 * disable bit, which we don't touch here, but it's good
5478 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 5479 */
5480 I915_WRITE(GEN7_GT_MODE,
5481 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5482
ecdb4eb7 5483 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5484 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5485
90a88643
PZ		 5486 /* WaRsPkgCStateDisplayPMReq:hsw */
5487 I915_WRITE(CHICKEN_PAR1_1,
5488 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5489
17a303ec 5490 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5491}
5492
1fa61106 5493static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5494{
5495 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5496 uint32_t snpcr;
6f1d69b0 5497
017636cc 5498 ilk_init_lp_watermarks(dev);
6f1d69b0 5499
231e54f6 5500 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5501
ecdb4eb7 5502 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5503 I915_WRITE(_3D_CHICKEN3,
5504 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5505
ecdb4eb7 5506 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5507 I915_WRITE(IVB_CHICKEN3,
5508 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5509 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5510
ecdb4eb7 5511 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5512 if (IS_IVB_GT1(dev))
5513 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5514 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5515
4e04632e
AG		 5516 /* WaDisable_RenderCache_OperationalFlush:ivb */
5517 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5518
ecdb4eb7 5519 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5520 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5521 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5522
ecdb4eb7 5523 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5524 I915_WRITE(GEN7_L3CNTLREG1,
5525 GEN7_WA_FOR_GEN7_L3_CONTROL);
5526 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5527 GEN7_WA_L3_CHICKEN_MODE);
5528 if (IS_IVB_GT1(dev))
5529 I915_WRITE(GEN7_ROW_CHICKEN2,
5530 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 5531 else {
5532 /* must write both registers */
5533 I915_WRITE(GEN7_ROW_CHICKEN2,
5534 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 5535 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5536 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 5537 }
6f1d69b0 5538
ecdb4eb7 5539 /* WaForceL3Serialization:ivb */
61939d97
JB		 5540 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5541 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5542
1b80a19a 5543 /*
0f846f81 5544 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5545 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5546 */
5547 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 5548 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5549
ecdb4eb7 5550 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5551 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5552 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5553 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5554
0e088b8f 5555 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5556
5557 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5558
22721343
CW		 5559 if (0) { /* causes HiZ corruption on ivb:gt1 */
5560 /* enable HiZ Raw Stall Optimization */
5561 I915_WRITE(CACHE_MODE_0_GEN7,
5562 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5563 }
116f2b6d 5564
ecdb4eb7 5565 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5566 I915_WRITE(CACHE_MODE_1,
5567 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 5568
a607c1a4
VS		 5569 /*
5570 * BSpec recommends 8x4 when MSAA is used,
5571 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5572 *
5573 * Note that PS/WM thread counts depend on the WIZ hashing
5574 * disable bit, which we don't touch here, but it's good
5575 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 5576 */
5577 I915_WRITE(GEN7_GT_MODE,
5578 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5579
20848223
BW		 5580 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5581 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5582 snpcr |= GEN6_MBC_SNPCR_MED;
5583 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5584
ab5c608b
BW		 5585 if (!HAS_PCH_NOP(dev))
5586 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5587
5588 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5589}
5590
1fa61106 5591static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5592{
5593 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 5594 u32 val;
5595
5596 mutex_lock(&dev_priv->rps.hw_lock);
5597 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5598 mutex_unlock(&dev_priv->rps.hw_lock);
5599 switch ((val >> 6) & 3) {
5600 case 0:
f64a28a7 5601 case 1:
f6d51948 5602 dev_priv->mem_freq = 800;
85b1d7b3 5603 break;
f64a28a7 5604 case 2:
f6d51948 5605 dev_priv->mem_freq = 1066;
85b1d7b3 5606 break;
f64a28a7 5607 case 3:
2325991e 5608 dev_priv->mem_freq = 1333;
f64a28a7 5609 break;
85b1d7b3
JB		 5610 }
5611 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 5612
d7fe0cc0 5613 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5614
ecdb4eb7 5615 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5616 I915_WRITE(_3D_CHICKEN3,
5617 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5618
ecdb4eb7 5619 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5620 I915_WRITE(IVB_CHICKEN3,
5621 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5622 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5623
fad7d36e 5624 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 5625 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5626 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5627 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5628 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5629
4e04632e
AG		 5630 /* WaDisable_RenderCache_OperationalFlush:vlv */
5631 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5632
ecdb4eb7 5633 /* WaForceL3Serialization:vlv */
61939d97
JB		 5634 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5635 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5636
ecdb4eb7 5637 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5638 I915_WRITE(GEN7_ROW_CHICKEN2,
5639 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5640
ecdb4eb7 5641 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5642 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5643 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5644 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5645
46680e0a
VS		 5646 gen7_setup_fixed_func_scheduler(dev_priv);
5647
3c0edaeb 5648 /*
0f846f81 5649 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5650 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 5651 */
5652 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 5653 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5654
c98f5062
AG		 5655 /* WaDisableL3Bank2xClockGate:vlv
5656 * Disabling L3 clock gating- MMIO 940c[25] = 1
5657 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5658 I915_WRITE(GEN7_UCGCTL4,
5659 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 5660
e0d8d59b 5661 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5662
afd58e79
VS		 5663 /*
5664 * BSpec says this must be set, even though
5665 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5666 */
6b26c86d
DV		 5667 I915_WRITE(CACHE_MODE_1,
5668 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5669
031994ee
VS		 5670 /*
5671 * WaIncreaseL3CreditsForVLVB0:vlv
5672 * This is the hardware default actually.
5673 */
5674 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5675
2d809570 5676 /*
ecdb4eb7 5677 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5678 * Disable clock gating on th GCFG unit to prevent a delay
5679 * in the reporting of vblank events.
5680 */
7a0d1eed 5681 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 5682}
5683
a4565da8
VS		 5684static void cherryview_init_clock_gating(struct drm_device *dev)
5685{
5686 struct drm_i915_private *dev_priv = dev->dev_private;
5687
5688 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5689
5690 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
dd811e70
VS		 5691
5692 /* WaDisablePartialInstShootdown:chv */
5693 I915_WRITE(GEN8_ROW_CHICKEN,
5694 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
a7068025
VS		 5695
5696 /* WaDisableThreadStallDopClockGating:chv */
5697 I915_WRITE(GEN8_ROW_CHICKEN,
5698 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
232ce337
VS		 5699
5700 /* WaVSRefCountFullforceMissDisable:chv */
5701 /* WaDSRefCountFullforceMissDisable:chv */
5702 I915_WRITE(GEN7_FF_THREAD_MODE,
5703 I915_READ(GEN7_FF_THREAD_MODE) &
5704 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 5705
5706 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5707 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5708 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 5709
5710 /* WaDisableCSUnitClockGating:chv */
5711 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5712 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 5713
5714 /* WaDisableSDEUnitClockGating:chv */
5715 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5716 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
e0d34ce7
RB		 5717
5718 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5719 I915_WRITE(HALF_SLICE_CHICKEN3,
5720 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
e4443e45
VS		 5721
5722 /* WaDisableGunitClockGating:chv (pre-production hw) */
5723 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5724 GINT_DIS);
5725
5726 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5727 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5728 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5729
5730 /* WaDisableDopClockGating:chv (pre-production hw) */
5731 I915_WRITE(GEN7_ROW_CHICKEN2,
5732 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5733 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5734 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS		 5735}
5736
1fa61106 5737static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5738{
5739 struct drm_i915_private *dev_priv = dev->dev_private;
5740 uint32_t dspclk_gate;
5741
5742 I915_WRITE(RENCLK_GATE_D1, 0);
5743 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5744 GS_UNIT_CLOCK_GATE_DISABLE |
5745 CL_UNIT_CLOCK_GATE_DISABLE);
5746 I915_WRITE(RAMCLK_GATE_D, 0);
5747 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5748 OVRUNIT_CLOCK_GATE_DISABLE |
5749 OVCUNIT_CLOCK_GATE_DISABLE;
5750 if (IS_GM45(dev))
5751 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5752 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5753
5754 /* WaDisableRenderCachePipelinedFlush */
5755 I915_WRITE(CACHE_MODE_0,
5756 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5757
4e04632e
AG		 5758 /* WaDisable_RenderCache_OperationalFlush:g4x */
5759 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5760
0e088b8f 5761 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5762}
5763
1fa61106 5764static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5765{
5766 struct drm_i915_private *dev_priv = dev->dev_private;
5767
5768 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5769 I915_WRITE(RENCLK_GATE_D2, 0);
5770 I915_WRITE(DSPCLK_GATE_D, 0);
5771 I915_WRITE(RAMCLK_GATE_D, 0);
5772 I915_WRITE16(DEUC, 0);
20f94967
VS		 5773 I915_WRITE(MI_ARB_STATE,
5774 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5775
5776 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5777 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5778}
5779
1fa61106 5780static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5781{
5782 struct drm_i915_private *dev_priv = dev->dev_private;
5783
5784 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5785 I965_RCC_CLOCK_GATE_DISABLE |
5786 I965_RCPB_CLOCK_GATE_DISABLE |
5787 I965_ISC_CLOCK_GATE_DISABLE |
5788 I965_FBC_CLOCK_GATE_DISABLE);
5789 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5790 I915_WRITE(MI_ARB_STATE,
5791 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5792
5793 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5794 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5795}
5796
1fa61106 5797static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5798{
5799 struct drm_i915_private *dev_priv = dev->dev_private;
5800 u32 dstate = I915_READ(D_STATE);
5801
5802 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5803 DSTATE_DOT_CLOCK_GATING;
5804 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5805
5806 if (IS_PINEVIEW(dev))
5807 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5808
5809 /* IIR "flip pending" means done if this bit is set */
5810 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 5811
5812 /* interrupts should cause a wake up from C3 */
3299254f 5813 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 5814
5815 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5816 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6f1d69b0
ED		 5817}
5818
1fa61106 5819static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5820{
5821 struct drm_i915_private *dev_priv = dev->dev_private;
5822
5823 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 5824
5825 /* interrupts should cause a wake up from C3 */
5826 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
5827 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6f1d69b0
ED		 5828}
5829
1fa61106 5830static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5831{
5832 struct drm_i915_private *dev_priv = dev->dev_private;
5833
5834 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5835}
5836
6f1d69b0
ED		 5837void intel_init_clock_gating(struct drm_device *dev)
5838{
5839 struct drm_i915_private *dev_priv = dev->dev_private;
5840
5841 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5842}
5843
7d708ee4
ID		 5844void intel_suspend_hw(struct drm_device *dev)
5845{
5846 if (HAS_PCH_LPT(dev))
5847 lpt_suspend_hw(dev);
5848}
5849
c1ca727f
ID		 5850#define for_each_power_well(i, power_well, domain_mask, power_domains) \
5851 for (i = 0; \
5852 i < (power_domains)->power_well_count && \
5853 ((power_well) = &(power_domains)->power_wells[i]); \
5854 i++) \
5855 if ((power_well)->domains & (domain_mask))
5856
5857#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5858 for (i = (power_domains)->power_well_count - 1; \
5859 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5860 i--) \
5861 if ((power_well)->domains & (domain_mask))
5862
15d199ea
PZ		 5863/**
5864 * We should only use the power well if we explicitly asked the hardware to
5865 * enable it, so check if it's enabled and also check if we've requested it to
5866 * be enabled.
5867 */
da7e29bd 5868static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
c1ca727f
ID		 5869 struct i915_power_well *power_well)
5870{
c1ca727f
ID		 5871 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5872 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5873}
5874
bfafe93a
ID		 5875bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
5876 enum intel_display_power_domain domain)
ddf9c536 5877{
ddf9c536 5878 struct i915_power_domains *power_domains;
b8c000d9
ID		 5879 struct i915_power_well *power_well;
5880 bool is_enabled;
5881 int i;
5882
5883 if (dev_priv->pm.suspended)
5884 return false;
ddf9c536
ID		 5885
5886 power_domains = &dev_priv->power_domains;
bfafe93a 5887
b8c000d9 5888 is_enabled = true;
bfafe93a 5889
b8c000d9
ID		 5890 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5891 if (power_well->always_on)
5892 continue;
ddf9c536 5893
bfafe93a 5894 if (!power_well->hw_enabled) {
b8c000d9
ID		 5895 is_enabled = false;
5896 break;
5897 }
5898 }
bfafe93a 5899
b8c000d9 5900 return is_enabled;
ddf9c536
ID		 5901}
5902
da7e29bd 5903bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
b97186f0 5904 enum intel_display_power_domain domain)
15d199ea 5905{
c1ca727f 5906 struct i915_power_domains *power_domains;
bfafe93a 5907 bool ret;
882244a3 5908
c1ca727f
ID		 5909 power_domains = &dev_priv->power_domains;
5910
c1ca727f 5911 mutex_lock(&power_domains->lock);
bfafe93a 5912 ret = intel_display_power_enabled_unlocked(dev_priv, domain);
c1ca727f
ID		 5913 mutex_unlock(&power_domains->lock);
5914
bfafe93a 5915 return ret;
15d199ea
PZ		 5916}
5917
93c73e8c
ID		 5918/*
5919 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5920 * when not needed anymore. We have 4 registers that can request the power well
5921 * to be enabled, and it will only be disabled if none of the registers is
5922 * requesting it to be enabled.
5923 */
d5e8fdc8
PZ		 5924static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5925{
5926 struct drm_device *dev = dev_priv->dev;
5927 unsigned long irqflags;
5928
f9dcb0df
PZ		 5929 /*
5930 * After we re-enable the power well, if we touch VGA register 0x3d5
5931 * we'll get unclaimed register interrupts. This stops after we write
5932 * anything to the VGA MSR register. The vgacon module uses this
5933 * register all the time, so if we unbind our driver and, as a
5934 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5935 * console_unlock(). So make here we touch the VGA MSR register, making
5936 * sure vgacon can keep working normally without triggering interrupts
5937 * and error messages.
5938 */
5939 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5940 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5941 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5942
d5e8fdc8
PZ		 5943 if (IS_BROADWELL(dev)) {
5944 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5945 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5946 dev_priv->de_irq_mask[PIPE_B]);
5947 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5948 ~dev_priv->de_irq_mask[PIPE_B] |
5949 GEN8_PIPE_VBLANK);
5950 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5951 dev_priv->de_irq_mask[PIPE_C]);
5952 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5953 ~dev_priv->de_irq_mask[PIPE_C] |
5954 GEN8_PIPE_VBLANK);
5955 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5956 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5957 }
5958}
5959
da7e29bd 5960static void hsw_set_power_well(struct drm_i915_private *dev_priv,
c1ca727f 5961 struct i915_power_well *power_well, bool enable)
d0d3e513 5962{
fa42e23c
PZ		 5963 bool is_enabled, enable_requested;
5964 uint32_t tmp;
d0d3e513 5965
fa42e23c 5966 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5967 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5968 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5969
fa42e23c
PZ		 5970 if (enable) {
5971 if (!enable_requested)
6aedd1f5
PZ		 5972 I915_WRITE(HSW_PWR_WELL_DRIVER,
5973 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5974
fa42e23c
PZ		 5975 if (!is_enabled) {
5976 DRM_DEBUG_KMS("Enabling power well\n");
5977 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5978 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5979 DRM_ERROR("Timeout enabling power well\n");
5980 }
596cc11e 5981
d5e8fdc8 5982 hsw_power_well_post_enable(dev_priv);
fa42e23c
PZ		 5983 } else {
5984 if (enable_requested) {
5985 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5986 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5987 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 5988 }
5989 }
fa42e23c 5990}
d0d3e513 5991
c6cb582e
ID		 5992static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5993 struct i915_power_well *power_well)
5994{
5995 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5996
5997 /*
5998 * We're taking over the BIOS, so clear any requests made by it since
5999 * the driver is in charge now.
6000 */
6001 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6002 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6003}
6004
6005static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
6006 struct i915_power_well *power_well)
6007{
c6cb582e
ID		 6008 hsw_set_power_well(dev_priv, power_well, true);
6009}
6010
6011static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
6012 struct i915_power_well *power_well)
6013{
6014 hsw_set_power_well(dev_priv, power_well, false);
c6cb582e
ID		 6015}
6016
a45f4466
ID		 6017static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
6018 struct i915_power_well *power_well)
6019{
6020}
6021
6022static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
6023 struct i915_power_well *power_well)
6024{
6025 return true;
6026}
6027
d2011dc8
VS		 6028static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6029 struct i915_power_well *power_well, bool enable)
77961eb9 6030{
d2011dc8 6031 enum punit_power_well power_well_id = power_well->data;
77961eb9
ID		 6032 u32 mask;
6033 u32 state;
6034 u32 ctrl;
6035
6036 mask = PUNIT_PWRGT_MASK(power_well_id);
6037 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6038 PUNIT_PWRGT_PWR_GATE(power_well_id);
6039
6040 mutex_lock(&dev_priv->rps.hw_lock);
6041
6042#define COND \
6043 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6044
6045 if (COND)
6046 goto out;
6047
6048 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6049 ctrl &= ~mask;
6050 ctrl |= state;
6051 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6052
6053 if (wait_for(COND, 100))
6054 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6055 state,
6056 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6057
6058#undef COND
6059
6060out:
6061 mutex_unlock(&dev_priv->rps.hw_lock);
6062}
6063
6064static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6065 struct i915_power_well *power_well)
6066{
6067 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6068}
6069
6070static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6071 struct i915_power_well *power_well)
6072{
6073 vlv_set_power_well(dev_priv, power_well, true);
6074}
6075
6076static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6077 struct i915_power_well *power_well)
6078{
6079 vlv_set_power_well(dev_priv, power_well, false);
6080}
6081
6082static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6083 struct i915_power_well *power_well)
6084{
6085 int power_well_id = power_well->data;
6086 bool enabled = false;
6087 u32 mask;
6088 u32 state;
6089 u32 ctrl;
6090
6091 mask = PUNIT_PWRGT_MASK(power_well_id);
6092 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6093
6094 mutex_lock(&dev_priv->rps.hw_lock);
6095
6096 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6097 /*
6098 * We only ever set the power-on and power-gate states, anything
6099 * else is unexpected.
6100 */
6101 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6102 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6103 if (state == ctrl)
6104 enabled = true;
6105
6106 /*
6107 * A transient state at this point would mean some unexpected party
6108 * is poking at the power controls too.
6109 */
6110 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6111 WARN_ON(ctrl != state);
6112
6113 mutex_unlock(&dev_priv->rps.hw_lock);
6114
6115 return enabled;
6116}
6117
6118static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6119 struct i915_power_well *power_well)
6120{
6121 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6122
6123 vlv_set_power_well(dev_priv, power_well, true);
6124
6125 spin_lock_irq(&dev_priv->irq_lock);
6126 valleyview_enable_display_irqs(dev_priv);
6127 spin_unlock_irq(&dev_priv->irq_lock);
6128
6129 /*
0d116a29
ID		 6130 * During driver initialization/resume we can avoid restoring the
6131 * part of the HW/SW state that will be inited anyway explicitly.
77961eb9 6132 */
0d116a29
ID		 6133 if (dev_priv->power_domains.initializing)
6134 return;
6135
6136 intel_hpd_init(dev_priv->dev);
77961eb9
ID		 6137
6138 i915_redisable_vga_power_on(dev_priv->dev);
6139}
6140
6141static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6142 struct i915_power_well *power_well)
6143{
77961eb9
ID		 6144 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6145
6146 spin_lock_irq(&dev_priv->irq_lock);
77961eb9
ID		 6147 valleyview_disable_display_irqs(dev_priv);
6148 spin_unlock_irq(&dev_priv->irq_lock);
6149
77961eb9
ID		 6150 vlv_set_power_well(dev_priv, power_well, false);
6151}
6152
aa519f23
VS		 6153static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6154 struct i915_power_well *power_well)
6155{
6156 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6157
6158 /*
6159 * Enable the CRI clock source so we can get at the
6160 * display and the reference clock for VGA
6161 * hotplug / manual detection.
6162 */
6163 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6164 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6165 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6166
6167 vlv_set_power_well(dev_priv, power_well, true);
6168
6169 /*
6170 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6171 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6172 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6173 * b. The other bits such as sfr settings / modesel may all
6174 * be set to 0.
6175 *
6176 * This should only be done on init and resume from S3 with
6177 * both PLLs disabled, or we risk losing DPIO and PLL
6178 * synchronization.
6179 */
6180 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
6181}
6182
6183static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6184 struct i915_power_well *power_well)
6185{
6186 struct drm_device *dev = dev_priv->dev;
6187 enum pipe pipe;
6188
6189 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6190
6191 for_each_pipe(pipe)
6192 assert_pll_disabled(dev_priv, pipe);
6193
6194 /* Assert common reset */
6195 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
6196
6197 vlv_set_power_well(dev_priv, power_well, false);
6198}
6199
25eaa003
ID		 6200static void check_power_well_state(struct drm_i915_private *dev_priv,
6201 struct i915_power_well *power_well)
6202{
6203 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6204
6205 if (power_well->always_on || !i915.disable_power_well) {
6206 if (!enabled)
6207 goto mismatch;
6208
6209 return;
6210 }
6211
6212 if (enabled != (power_well->count > 0))
6213 goto mismatch;
6214
6215 return;
6216
6217mismatch:
6218 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6219 power_well->name, power_well->always_on, enabled,
6220 power_well->count, i915.disable_power_well);
6221}
6222
da7e29bd 6223void intel_display_power_get(struct drm_i915_private *dev_priv,
6765625e
VS		 6224 enum intel_display_power_domain domain)
6225{
83c00f55 6226 struct i915_power_domains *power_domains;
c1ca727f
ID		 6227 struct i915_power_well *power_well;
6228 int i;
6765625e 6229
9e6ea71a
PZ		 6230 intel_runtime_pm_get(dev_priv);
6231
83c00f55
ID		 6232 power_domains = &dev_priv->power_domains;
6233
6234 mutex_lock(&power_domains->lock);
1da51581 6235
25eaa003
ID		 6236 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6237 if (!power_well->count++) {
6238 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
c6cb582e 6239 power_well->ops->enable(dev_priv, power_well);
bfafe93a 6240 power_well->hw_enabled = true;
25eaa003
ID		 6241 }
6242
6243 check_power_well_state(dev_priv, power_well);
6244 }
1da51581 6245
ddf9c536
ID		 6246 power_domains->domain_use_count[domain]++;
6247
83c00f55 6248 mutex_unlock(&power_domains->lock);
6765625e
VS		 6249}
6250
da7e29bd 6251void intel_display_power_put(struct drm_i915_private *dev_priv,
6765625e
VS		 6252 enum intel_display_power_domain domain)
6253{
83c00f55 6254 struct i915_power_domains *power_domains;
c1ca727f
ID		 6255 struct i915_power_well *power_well;
6256 int i;
6765625e 6257
83c00f55
ID		 6258 power_domains = &dev_priv->power_domains;
6259
6260 mutex_lock(&power_domains->lock);
1da51581 6261
1da51581
ID		 6262 WARN_ON(!power_domains->domain_use_count[domain]);
6263 power_domains->domain_use_count[domain]--;
ddf9c536 6264
70bf407c
ID		 6265 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6266 WARN_ON(!power_well->count);
6267
25eaa003
ID		 6268 if (!--power_well->count && i915.disable_power_well) {
6269 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
bfafe93a 6270 power_well->hw_enabled = false;
c6cb582e 6271 power_well->ops->disable(dev_priv, power_well);
25eaa003
ID		 6272 }
6273
6274 check_power_well_state(dev_priv, power_well);
70bf407c 6275 }
1da51581 6276
83c00f55 6277 mutex_unlock(&power_domains->lock);
9e6ea71a
PZ		 6278
6279 intel_runtime_pm_put(dev_priv);
6765625e
VS		 6280}
6281
83c00f55 6282static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 6283
6284/* Display audio driver power well request */
74b0c2d7 6285int i915_request_power_well(void)
a38911a3 6286{
b4ed4484
ID		 6287 struct drm_i915_private *dev_priv;
6288
74b0c2d7
TI		 6289 if (!hsw_pwr)
6290 return -ENODEV;
a38911a3 6291
b4ed4484
ID		 6292 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6293 power_domains);
da7e29bd 6294 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
74b0c2d7 6295 return 0;
a38911a3
WX		 6296}
6297EXPORT_SYMBOL_GPL(i915_request_power_well);
6298
6299/* Display audio driver power well release */
74b0c2d7 6300int i915_release_power_well(void)
a38911a3 6301{
b4ed4484
ID		 6302 struct drm_i915_private *dev_priv;
6303
74b0c2d7
TI		 6304 if (!hsw_pwr)
6305 return -ENODEV;
a38911a3 6306
b4ed4484
ID		 6307 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6308 power_domains);
da7e29bd 6309 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
74b0c2d7 6310 return 0;
a38911a3
WX		 6311}
6312EXPORT_SYMBOL_GPL(i915_release_power_well);
6313
c149dcb5
JN		 6314/*
6315 * Private interface for the audio driver to get CDCLK in kHz.
6316 *
6317 * Caller must request power well using i915_request_power_well() prior to
6318 * making the call.
6319 */
6320int i915_get_cdclk_freq(void)
6321{
6322 struct drm_i915_private *dev_priv;
6323
6324 if (!hsw_pwr)
6325 return -ENODEV;
6326
6327 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6328 power_domains);
6329
6330 return intel_ddi_get_cdclk_freq(dev_priv);
6331}
6332EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6333
6334
efcad917
ID		 6335#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6336
6337#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6338 BIT(POWER_DOMAIN_PIPE_A) | \
f5938f36 6339 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
319be8ae
ID		 6340 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6341 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6342 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6343 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6344 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6345 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6346 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6347 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6348 BIT(POWER_DOMAIN_PORT_CRT) | \
f5938f36 6349 BIT(POWER_DOMAIN_INIT))
efcad917
ID		 6350#define HSW_DISPLAY_POWER_DOMAINS ( \
6351 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6352 BIT(POWER_DOMAIN_INIT))
6353
6354#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6355 HSW_ALWAYS_ON_POWER_DOMAINS | \
6356 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6357#define BDW_DISPLAY_POWER_DOMAINS ( \
6358 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6359 BIT(POWER_DOMAIN_INIT))
6360
77961eb9
ID		 6361#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6362#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6363
6364#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6365 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6366 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6367 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6368 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6369 BIT(POWER_DOMAIN_PORT_CRT) | \
6370 BIT(POWER_DOMAIN_INIT))
6371
6372#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6373 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6374 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6375 BIT(POWER_DOMAIN_INIT))
6376
6377#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6378 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6379 BIT(POWER_DOMAIN_INIT))
6380
6381#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6382 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6383 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6384 BIT(POWER_DOMAIN_INIT))
6385
6386#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6387 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6388 BIT(POWER_DOMAIN_INIT))
6389
a45f4466
ID		 6390static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6391 .sync_hw = i9xx_always_on_power_well_noop,
6392 .enable = i9xx_always_on_power_well_noop,
6393 .disable = i9xx_always_on_power_well_noop,
6394 .is_enabled = i9xx_always_on_power_well_enabled,
6395};
c6cb582e 6396
1c2256df
ID		 6397static struct i915_power_well i9xx_always_on_power_well[] = {
6398 {
6399 .name = "always-on",
6400 .always_on = 1,
6401 .domains = POWER_DOMAIN_MASK,
c6cb582e 6402 .ops = &i9xx_always_on_power_well_ops,
1c2256df
ID		 6403 },
6404};
6405
c6cb582e
ID		 6406static const struct i915_power_well_ops hsw_power_well_ops = {
6407 .sync_hw = hsw_power_well_sync_hw,
6408 .enable = hsw_power_well_enable,
6409 .disable = hsw_power_well_disable,
6410 .is_enabled = hsw_power_well_enabled,
6411};
6412
c1ca727f 6413static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 6414 {
6415 .name = "always-on",
6416 .always_on = 1,
6417 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 6418 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 6419 },
c1ca727f
ID		 6420 {
6421 .name = "display",
efcad917 6422 .domains = HSW_DISPLAY_POWER_DOMAINS,
c6cb582e 6423 .ops = &hsw_power_well_ops,
c1ca727f
ID		 6424 },
6425};
6426
6427static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 6428 {
6429 .name = "always-on",
6430 .always_on = 1,
6431 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 6432 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 6433 },
c1ca727f
ID		 6434 {
6435 .name = "display",
efcad917 6436 .domains = BDW_DISPLAY_POWER_DOMAINS,
c6cb582e 6437 .ops = &hsw_power_well_ops,
c1ca727f
ID		 6438 },
6439};
6440
77961eb9
ID		 6441static const struct i915_power_well_ops vlv_display_power_well_ops = {
6442 .sync_hw = vlv_power_well_sync_hw,
6443 .enable = vlv_display_power_well_enable,
6444 .disable = vlv_display_power_well_disable,
6445 .is_enabled = vlv_power_well_enabled,
6446};
6447
aa519f23
VS		 6448static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
6449 .sync_hw = vlv_power_well_sync_hw,
6450 .enable = vlv_dpio_cmn_power_well_enable,
6451 .disable = vlv_dpio_cmn_power_well_disable,
6452 .is_enabled = vlv_power_well_enabled,
6453};
6454
77961eb9
ID		 6455static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6456 .sync_hw = vlv_power_well_sync_hw,
6457 .enable = vlv_power_well_enable,
6458 .disable = vlv_power_well_disable,
6459 .is_enabled = vlv_power_well_enabled,
6460};
6461
6462static struct i915_power_well vlv_power_wells[] = {
6463 {
6464 .name = "always-on",
6465 .always_on = 1,
6466 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6467 .ops = &i9xx_always_on_power_well_ops,
6468 },
6469 {
6470 .name = "display",
6471 .domains = VLV_DISPLAY_POWER_DOMAINS,
6472 .data = PUNIT_POWER_WELL_DISP2D,
6473 .ops = &vlv_display_power_well_ops,
6474 },
77961eb9
ID		 6475 {
6476 .name = "dpio-tx-b-01",
6477 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6478 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6479 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6480 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6481 .ops = &vlv_dpio_power_well_ops,
6482 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6483 },
6484 {
6485 .name = "dpio-tx-b-23",
6486 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6487 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6488 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6489 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6490 .ops = &vlv_dpio_power_well_ops,
6491 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6492 },
6493 {
6494 .name = "dpio-tx-c-01",
6495 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6496 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6497 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6498 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6499 .ops = &vlv_dpio_power_well_ops,
6500 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6501 },
6502 {
6503 .name = "dpio-tx-c-23",
6504 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6505 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6506 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6507 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6508 .ops = &vlv_dpio_power_well_ops,
6509 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6510 },
f099a3c6
JB		 6511 {
6512 .name = "dpio-common",
6513 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6514 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
aa519f23 6515 .ops = &vlv_dpio_cmn_power_well_ops,
f099a3c6 6516 },
77961eb9
ID		 6517};
6518
d2011dc8
VS		 6519static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
6520 enum punit_power_well power_well_id)
6521{
6522 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6523 struct i915_power_well *power_well;
6524 int i;
6525
6526 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
6527 if (power_well->data == power_well_id)
6528 return power_well;
6529 }
6530
6531 return NULL;
6532}
6533
c1ca727f
ID		 6534#define set_power_wells(power_domains, __power_wells) ({ \
6535 (power_domains)->power_wells = (__power_wells); \
6536 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6537})
6538
da7e29bd 6539int intel_power_domains_init(struct drm_i915_private *dev_priv)
a38911a3 6540{
83c00f55 6541 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 6542
83c00f55 6543 mutex_init(&power_domains->lock);
a38911a3 6544
c1ca727f
ID		 6545 /*
6546 * The enabling order will be from lower to higher indexed wells,
6547 * the disabling order is reversed.
6548 */
da7e29bd 6549 if (IS_HASWELL(dev_priv->dev)) {
c1ca727f
ID		 6550 set_power_wells(power_domains, hsw_power_wells);
6551 hsw_pwr = power_domains;
da7e29bd 6552 } else if (IS_BROADWELL(dev_priv->dev)) {
c1ca727f
ID		 6553 set_power_wells(power_domains, bdw_power_wells);
6554 hsw_pwr = power_domains;
77961eb9
ID		 6555 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6556 set_power_wells(power_domains, vlv_power_wells);
c1ca727f 6557 } else {
1c2256df 6558 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 6559 }
a38911a3
WX		 6560
6561 return 0;
6562}
6563
da7e29bd 6564void intel_power_domains_remove(struct drm_i915_private *dev_priv)
a38911a3
WX		 6565{
6566 hsw_pwr = NULL;
6567}
6568
da7e29bd 6569static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
9cdb826c 6570{
83c00f55
ID		 6571 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6572 struct i915_power_well *power_well;
c1ca727f 6573 int i;
9cdb826c 6574
83c00f55 6575 mutex_lock(&power_domains->lock);
bfafe93a 6576 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
a45f4466 6577 power_well->ops->sync_hw(dev_priv, power_well);
bfafe93a
ID		 6578 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
6579 power_well);
6580 }
83c00f55 6581 mutex_unlock(&power_domains->lock);
a38911a3
WX		 6582}
6583
d2011dc8
VS		 6584static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
6585{
6586 struct i915_power_well *cmn =
6587 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
6588 struct i915_power_well *disp2d =
6589 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
6590
6591 /* nothing to do if common lane is already off */
6592 if (!cmn->ops->is_enabled(dev_priv, cmn))
6593 return;
6594
6595 /* If the display might be already active skip this */
6596 if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
6597 I915_READ(DPIO_CTL) & DPIO_CMNRST)
6598 return;
6599
6600 DRM_DEBUG_KMS("toggling display PHY side reset\n");
6601
6602 /* cmnlane needs DPLL registers */
6603 disp2d->ops->enable(dev_priv, disp2d);
6604
6605 /*
6606 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
6607 * Need to assert and de-assert PHY SB reset by gating the
6608 * common lane power, then un-gating it.
6609 * Simply ungating isn't enough to reset the PHY enough to get
6610 * ports and lanes running.
6611 */
6612 cmn->ops->disable(dev_priv, cmn);
6613}
6614
da7e29bd 6615void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
d0d3e513 6616{
d2011dc8 6617 struct drm_device *dev = dev_priv->dev;
0d116a29
ID		 6618 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6619
6620 power_domains->initializing = true;
d2011dc8
VS		 6621
6622 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
6623 mutex_lock(&power_domains->lock);
6624 vlv_cmnlane_wa(dev_priv);
6625 mutex_unlock(&power_domains->lock);
6626 }
6627
fa42e23c 6628 /* For now, we need the power well to be always enabled. */
da7e29bd
ID		 6629 intel_display_set_init_power(dev_priv, true);
6630 intel_power_domains_resume(dev_priv);
0d116a29 6631 power_domains->initializing = false;
d0d3e513
ED		 6632}
6633
c67a470b
PZ		 6634void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6635{
d361ae26 6636 intel_runtime_pm_get(dev_priv);
c67a470b
PZ		 6637}
6638
6639void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6640{
d361ae26 6641 intel_runtime_pm_put(dev_priv);
c67a470b
PZ		 6642}
6643
8a187455
PZ		 6644void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6645{
6646 struct drm_device *dev = dev_priv->dev;
6647 struct device *device = &dev->pdev->dev;
6648
6649 if (!HAS_RUNTIME_PM(dev))
6650 return;
6651
6652 pm_runtime_get_sync(device);
6653 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6654}
6655
c6df39b5
ID		 6656void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
6657{
6658 struct drm_device *dev = dev_priv->dev;
6659 struct device *device = &dev->pdev->dev;
6660
6661 if (!HAS_RUNTIME_PM(dev))
6662 return;
6663
6664 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
6665 pm_runtime_get_noresume(device);
6666}
6667
8a187455
PZ		 6668void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6669{
6670 struct drm_device *dev = dev_priv->dev;
6671 struct device *device = &dev->pdev->dev;
6672
6673 if (!HAS_RUNTIME_PM(dev))
6674 return;
6675
6676 pm_runtime_mark_last_busy(device);
6677 pm_runtime_put_autosuspend(device);
6678}
6679
6680void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6681{
6682 struct drm_device *dev = dev_priv->dev;
6683 struct device *device = &dev->pdev->dev;
6684
8a187455
PZ		 6685 if (!HAS_RUNTIME_PM(dev))
6686 return;
6687
6688 pm_runtime_set_active(device);
6689
aeab0b5a
ID		 6690 /*
6691 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6692 * requirement.
6693 */
6694 if (!intel_enable_rc6(dev)) {
6695 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6696 return;
6697 }
6698
8a187455
PZ		 6699 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6700 pm_runtime_mark_last_busy(device);
6701 pm_runtime_use_autosuspend(device);
ba0239e0
PZ		 6702
6703 pm_runtime_put_autosuspend(device);
8a187455
PZ		 6704}
6705
6706void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6707{
6708 struct drm_device *dev = dev_priv->dev;
6709 struct device *device = &dev->pdev->dev;
6710
6711 if (!HAS_RUNTIME_PM(dev))
6712 return;
6713
aeab0b5a
ID		 6714 if (!intel_enable_rc6(dev))
6715 return;
6716
8a187455
PZ		 6717 /* Make sure we're not suspended first. */
6718 pm_runtime_get_sync(device);
6719 pm_runtime_disable(device);
6720}
6721
1fa61106
ED		 6722/* Set up chip specific power management-related functions */
6723void intel_init_pm(struct drm_device *dev)
6724{
6725 struct drm_i915_private *dev_priv = dev->dev_private;
6726
3a77c4c4 6727 if (HAS_FBC(dev)) {
40045465 6728 if (INTEL_INFO(dev)->gen >= 7) {
1fa61106 6729 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
40045465
VS		 6730 dev_priv->display.enable_fbc = gen7_enable_fbc;
6731 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6732 } else if (INTEL_INFO(dev)->gen >= 5) {
6733 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6734 dev_priv->display.enable_fbc = ironlake_enable_fbc;
1fa61106
ED		 6735 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6736 } else if (IS_GM45(dev)) {
6737 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6738 dev_priv->display.enable_fbc = g4x_enable_fbc;
6739 dev_priv->display.disable_fbc = g4x_disable_fbc;
40045465 6740 } else {
1fa61106
ED		 6741 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6742 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6743 dev_priv->display.disable_fbc = i8xx_disable_fbc;
993495ae
VS		 6744
6745 /* This value was pulled out of someone's hat */
6746 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1fa61106 6747 }
1fa61106
ED		 6748 }
6749
c921aba8
DV		 6750 /* For cxsr */
6751 if (IS_PINEVIEW(dev))
6752 i915_pineview_get_mem_freq(dev);
6753 else if (IS_GEN5(dev))
6754 i915_ironlake_get_mem_freq(dev);
6755
1fa61106
ED		 6756 /* For FIFO watermark updates */
6757 if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6758 ilk_setup_wm_latency(dev);
53615a5e 6759
bd602544
VS		 6760 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6761 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6762 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6763 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6764 dev_priv->display.update_wm = ilk_update_wm;
6765 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6766 } else {
6767 DRM_DEBUG_KMS("Failed to read display plane latency. "
6768 "Disable CxSR\n");
6769 }
6770
6771 if (IS_GEN5(dev))
1fa61106 6772 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6773 else if (IS_GEN6(dev))
1fa61106 6774 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6775 else if (IS_IVYBRIDGE(dev))
1fa61106 6776 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6777 else if (IS_HASWELL(dev))
cad2a2d7 6778 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6779 else if (INTEL_INFO(dev)->gen == 8)
1020a5c2 6780 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
a4565da8
VS		 6781 } else if (IS_CHERRYVIEW(dev)) {
6782 dev_priv->display.update_wm = valleyview_update_wm;
6783 dev_priv->display.init_clock_gating =
6784 cherryview_init_clock_gating;
1fa61106
ED		 6785 } else if (IS_VALLEYVIEW(dev)) {
6786 dev_priv->display.update_wm = valleyview_update_wm;
6787 dev_priv->display.init_clock_gating =
6788 valleyview_init_clock_gating;
1fa61106
ED		 6789 } else if (IS_PINEVIEW(dev)) {
6790 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6791 dev_priv->is_ddr3,
6792 dev_priv->fsb_freq,
6793 dev_priv->mem_freq)) {
6794 DRM_INFO("failed to find known CxSR latency "
6795 "(found ddr%s fsb freq %d, mem freq %d), "
6796 "disabling CxSR\n",
6797 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6798 dev_priv->fsb_freq, dev_priv->mem_freq);
6799 /* Disable CxSR and never update its watermark again */
5209b1f4 6800 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 6801 dev_priv->display.update_wm = NULL;
6802 } else
6803 dev_priv->display.update_wm = pineview_update_wm;
6804 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6805 } else if (IS_G4X(dev)) {
6806 dev_priv->display.update_wm = g4x_update_wm;
6807 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6808 } else if (IS_GEN4(dev)) {
6809 dev_priv->display.update_wm = i965_update_wm;
6810 if (IS_CRESTLINE(dev))
6811 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6812 else if (IS_BROADWATER(dev))
6813 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6814 } else if (IS_GEN3(dev)) {
6815 dev_priv->display.update_wm = i9xx_update_wm;
6816 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6817 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 6818 } else if (IS_GEN2(dev)) {
6819 if (INTEL_INFO(dev)->num_pipes == 1) {
6820 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6821 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 6822 } else {
6823 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6824 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 6825 }
6826
6827 if (IS_I85X(dev) || IS_I865G(dev))
6828 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6829 else
6830 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6831 } else {
6832 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 6833 }
6834}
6835
42c0526c
BW		 6836int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6837{
4fc688ce 6838 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6839
6840 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6841 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6842 return -EAGAIN;
6843 }
6844
6845 I915_WRITE(GEN6_PCODE_DATA, *val);
6846 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6847
6848 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6849 500)) {
6850 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6851 return -ETIMEDOUT;
6852 }
6853
6854 *val = I915_READ(GEN6_PCODE_DATA);
6855 I915_WRITE(GEN6_PCODE_DATA, 0);
6856
6857 return 0;
6858}
6859
6860int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6861{
4fc688ce 6862 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6863
6864 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6865 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6866 return -EAGAIN;
6867 }
6868
6869 I915_WRITE(GEN6_PCODE_DATA, val);
6870 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6871
6872 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6873 500)) {
6874 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6875 return -ETIMEDOUT;
6876 }
6877
6878 I915_WRITE(GEN6_PCODE_DATA, 0);
6879
6880 return 0;
6881}
a0e4e199 6882
2ec3815f 6883int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 6884{
07ab118b 6885 int div;
855ba3be 6886
07ab118b 6887 /* 4 x czclk */
2ec3815f 6888 switch (dev_priv->mem_freq) {
855ba3be 6889 case 800:
07ab118b 6890 div = 10;
855ba3be
JB		 6891 break;
6892 case 1066:
07ab118b 6893 div = 12;
855ba3be
JB		 6894 break;
6895 case 1333:
07ab118b 6896 div = 16;
855ba3be
JB		 6897 break;
6898 default:
6899 return -1;
6900 }
6901
2ec3815f 6902 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 6903}
6904
2ec3815f 6905int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6906{
07ab118b 6907 int mul;
855ba3be 6908
07ab118b 6909 /* 4 x czclk */
2ec3815f 6910 switch (dev_priv->mem_freq) {
855ba3be 6911 case 800:
07ab118b 6912 mul = 10;
855ba3be
JB		 6913 break;
6914 case 1066:
07ab118b 6915 mul = 12;
855ba3be
JB		 6916 break;
6917 case 1333:
07ab118b 6918 mul = 16;
855ba3be
JB		 6919 break;
6920 default:
6921 return -1;
6922 }
6923
2ec3815f 6924 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 6925}
6926
f742a552 6927void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 6928{
6929 struct drm_i915_private *dev_priv = dev->dev_private;
6930
f742a552
DV		 6931 mutex_init(&dev_priv->rps.hw_lock);
6932
907b28c5
CW		 6933 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6934 intel_gen6_powersave_work);
5d584b2e 6935
33688d95 6936 dev_priv->pm.suspended = false;
5d584b2e 6937 dev_priv->pm.irqs_disabled = false;
907b28c5 6938}
Linux kernel - Deliverables
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