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drm/i915/skl: Reduce the number of holes in struct skl_wm_level
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
f6750b3c
ED		 55/* FBC, or Frame Buffer Compression, is a technique employed to compress the
56 * framebuffer contents in-memory, aiming at reducing the required bandwidth
57 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 58 *
f6750b3c
ED		 59 * The benefits of FBC are mostly visible with solid backgrounds and
60 * variation-less patterns.
85208be0 61 *
f6750b3c
ED		 62 * FBC-related functionality can be enabled by the means of the
63 * i915.i915_enable_fbc parameter
85208be0
ED		 64 */
65
da2078cd
DL		 66static void gen9_init_clock_gating(struct drm_device *dev)
67{
acd5c346
DL		 68 struct drm_i915_private *dev_priv = dev->dev_private;
69
70 /*
71 * WaDisableSDEUnitClockGating:skl
72 * This seems to be a pre-production w/a.
73 */
74 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
75 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
91e41d16 76
3ca5da43
DL		 77 /*
78 * WaDisableDgMirrorFixInHalfSliceChicken5:skl
79 * This is a pre-production w/a.
80 */
81 I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
82 I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
83 ~GEN9_DG_MIRROR_FIX_ENABLE);
84
91e41d16
DL		 85 /* Wa4x4STCOptimizationDisable:skl */
86 I915_WRITE(CACHE_MODE_1,
87 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
da2078cd
DL		 88}
89
1fa61106 90static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 91{
92 struct drm_i915_private *dev_priv = dev->dev_private;
93 u32 fbc_ctl;
94
9adccc60
PZ		 95 dev_priv->fbc.enabled = false;
96
85208be0
ED		 97 /* Disable compression */
98 fbc_ctl = I915_READ(FBC_CONTROL);
99 if ((fbc_ctl & FBC_CTL_EN) == 0)
100 return;
101
102 fbc_ctl &= ~FBC_CTL_EN;
103 I915_WRITE(FBC_CONTROL, fbc_ctl);
104
105 /* Wait for compressing bit to clear */
106 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
107 DRM_DEBUG_KMS("FBC idle timed out\n");
108 return;
109 }
110
111 DRM_DEBUG_KMS("disabled FBC\n");
112}
113
993495ae 114static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 115{
116 struct drm_device *dev = crtc->dev;
117 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 118 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 119 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0
ED		 120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
121 int cfb_pitch;
7f2cf220 122 int i;
159f9875 123 u32 fbc_ctl;
85208be0 124
9adccc60
PZ		 125 dev_priv->fbc.enabled = true;
126
5c3fe8b0 127 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 128 if (fb->pitches[0] < cfb_pitch)
129 cfb_pitch = fb->pitches[0];
130
42a430f5
VS		 131 /* FBC_CTL wants 32B or 64B units */
132 if (IS_GEN2(dev))
133 cfb_pitch = (cfb_pitch / 32) - 1;
134 else
135 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 136
137 /* Clear old tags */
138 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
139 I915_WRITE(FBC_TAG + (i * 4), 0);
140
159f9875
VS		 141 if (IS_GEN4(dev)) {
142 u32 fbc_ctl2;
143
144 /* Set it up... */
145 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
7f2cf220 146 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
159f9875
VS		 147 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
148 I915_WRITE(FBC_FENCE_OFF, crtc->y);
149 }
85208be0
ED		 150
151 /* enable it... */
993495ae
VS		 152 fbc_ctl = I915_READ(FBC_CONTROL);
153 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
154 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 155 if (IS_I945GM(dev))
156 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
157 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 158 fbc_ctl |= obj->fence_reg;
159 I915_WRITE(FBC_CONTROL, fbc_ctl);
160
5cd5410e 161 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
84f44ce7 162 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 163}
164
1fa61106 165static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 166{
167 struct drm_i915_private *dev_priv = dev->dev_private;
168
169 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
170}
171
993495ae 172static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 173{
174 struct drm_device *dev = crtc->dev;
175 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 176 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 177 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0 178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 179 u32 dpfc_ctl;
180
9adccc60
PZ		 181 dev_priv->fbc.enabled = true;
182
3fa2e0ee
VS		 183 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
184 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
185 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
186 else
187 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
85208be0 188 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
85208be0 189
85208be0
ED		 190 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
191
192 /* enable it... */
fe74c1a5 193 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
85208be0 194
84f44ce7 195 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 196}
197
1fa61106 198static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 199{
200 struct drm_i915_private *dev_priv = dev->dev_private;
201 u32 dpfc_ctl;
202
9adccc60
PZ		 203 dev_priv->fbc.enabled = false;
204
85208be0
ED		 205 /* Disable compression */
206 dpfc_ctl = I915_READ(DPFC_CONTROL);
207 if (dpfc_ctl & DPFC_CTL_EN) {
208 dpfc_ctl &= ~DPFC_CTL_EN;
209 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
210
211 DRM_DEBUG_KMS("disabled FBC\n");
212 }
213}
214
1fa61106 215static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 216{
217 struct drm_i915_private *dev_priv = dev->dev_private;
218
219 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
220}
221
222static void sandybridge_blit_fbc_update(struct drm_device *dev)
223{
224 struct drm_i915_private *dev_priv = dev->dev_private;
225 u32 blt_ecoskpd;
226
227 /* Make sure blitter notifies FBC of writes */
940aece4
D		 228
229 /* Blitter is part of Media powerwell on VLV. No impact of
230 * his param in other platforms for now */
231 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 232
85208be0
ED		 233 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
234 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
235 GEN6_BLITTER_LOCK_SHIFT;
236 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
237 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
238 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
239 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
240 GEN6_BLITTER_LOCK_SHIFT);
241 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
242 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 243
940aece4 244 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 245}
246
993495ae 247static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 248{
249 struct drm_device *dev = crtc->dev;
250 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 251 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 252 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0 253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 254 u32 dpfc_ctl;
255
9adccc60
PZ		 256 dev_priv->fbc.enabled = true;
257
46f3dab9 258 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
3fa2e0ee 259 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
5e59f717
BW		 260 dev_priv->fbc.threshold++;
261
262 switch (dev_priv->fbc.threshold) {
263 case 4:
264 case 3:
265 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
266 break;
267 case 2:
3fa2e0ee 268 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
5e59f717
BW		 269 break;
270 case 1:
3fa2e0ee 271 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
5e59f717
BW		 272 break;
273 }
d629336b
VS		 274 dpfc_ctl |= DPFC_CTL_FENCE_EN;
275 if (IS_GEN5(dev))
276 dpfc_ctl |= obj->fence_reg;
85208be0 277
85208be0 278 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 279 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 280 /* enable it... */
281 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
282
283 if (IS_GEN6(dev)) {
284 I915_WRITE(SNB_DPFC_CTL_SA,
285 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
286 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
287 sandybridge_blit_fbc_update(dev);
288 }
289
84f44ce7 290 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 291}
292
1fa61106 293static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 294{
295 struct drm_i915_private *dev_priv = dev->dev_private;
296 u32 dpfc_ctl;
297
9adccc60
PZ		 298 dev_priv->fbc.enabled = false;
299
85208be0
ED		 300 /* Disable compression */
301 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
302 if (dpfc_ctl & DPFC_CTL_EN) {
303 dpfc_ctl &= ~DPFC_CTL_EN;
304 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
305
306 DRM_DEBUG_KMS("disabled FBC\n");
307 }
308}
309
1fa61106 310static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 311{
312 struct drm_i915_private *dev_priv = dev->dev_private;
313
314 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
315}
316
993495ae 317static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 318{
319 struct drm_device *dev = crtc->dev;
320 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 321 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 322 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
abe959c7 323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3fa2e0ee 324 u32 dpfc_ctl;
abe959c7 325
9adccc60
PZ		 326 dev_priv->fbc.enabled = true;
327
3fa2e0ee
VS		 328 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
329 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
5e59f717
BW		 330 dev_priv->fbc.threshold++;
331
332 switch (dev_priv->fbc.threshold) {
333 case 4:
334 case 3:
335 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
336 break;
337 case 2:
3fa2e0ee 338 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
5e59f717
BW		 339 break;
340 case 1:
3fa2e0ee 341 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
5e59f717
BW		 342 break;
343 }
344
3fa2e0ee
VS		 345 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
346
da46f936
RV		 347 if (dev_priv->fbc.false_color)
348 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
349
3fa2e0ee 350 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
abe959c7 351
891348b2 352 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 353 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
2adb6db8
VS		 354 I915_WRITE(ILK_DISPLAY_CHICKEN1,
355 I915_READ(ILK_DISPLAY_CHICKEN1) |
356 ILK_FBCQ_DIS);
28554164 357 } else {
2adb6db8 358 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
8f670bb1
VS		 359 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
360 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
361 HSW_FBCQ_DIS);
891348b2 362 }
b74ea102 363
abe959c7
RV		 364 I915_WRITE(SNB_DPFC_CTL_SA,
365 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
366 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
367
368 sandybridge_blit_fbc_update(dev);
369
b19870ee 370 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 371}
372
85208be0
ED		 373bool intel_fbc_enabled(struct drm_device *dev)
374{
375 struct drm_i915_private *dev_priv = dev->dev_private;
376
9adccc60 377 return dev_priv->fbc.enabled;
85208be0
ED		 378}
379
1d73c2a8 380void bdw_fbc_sw_flush(struct drm_device *dev, u32 value)
c5ad011d
RV		 381{
382 struct drm_i915_private *dev_priv = dev->dev_private;
383
384 if (!IS_GEN8(dev))
385 return;
386
01d06e9f
RV		 387 if (!intel_fbc_enabled(dev))
388 return;
389
c5ad011d
RV		 390 I915_WRITE(MSG_FBC_REND_STATE, value);
391}
392
85208be0
ED		 393static void intel_fbc_work_fn(struct work_struct *__work)
394{
395 struct intel_fbc_work *work =
396 container_of(to_delayed_work(__work),
397 struct intel_fbc_work, work);
398 struct drm_device *dev = work->crtc->dev;
399 struct drm_i915_private *dev_priv = dev->dev_private;
400
401 mutex_lock(&dev->struct_mutex);
5c3fe8b0 402 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 403 /* Double check that we haven't switched fb without cancelling
404 * the prior work.
405 */
f4510a27 406 if (work->crtc->primary->fb == work->fb) {
993495ae 407 dev_priv->display.enable_fbc(work->crtc);
85208be0 408
5c3fe8b0 409 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
f4510a27 410 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
5c3fe8b0 411 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 412 }
413
5c3fe8b0 414 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 415 }
416 mutex_unlock(&dev->struct_mutex);
417
418 kfree(work);
419}
420
421static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
422{
5c3fe8b0 423 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 424 return;
425
426 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
427
428 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 429 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 430 * entirely asynchronously.
431 */
5c3fe8b0 432 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 433 /* tasklet was killed before being run, clean up */
5c3fe8b0 434 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 435
436 /* Mark the work as no longer wanted so that if it does
437 * wake-up (because the work was already running and waiting
438 * for our mutex), it will discover that is no longer
439 * necessary to run.
440 */
5c3fe8b0 441 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 442}
443
993495ae 444static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 445{
446 struct intel_fbc_work *work;
447 struct drm_device *dev = crtc->dev;
448 struct drm_i915_private *dev_priv = dev->dev_private;
449
450 if (!dev_priv->display.enable_fbc)
451 return;
452
453 intel_cancel_fbc_work(dev_priv);
454
b14c5679 455 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 456 if (work == NULL) {
6cdcb5e7 457 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 458 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 459 return;
460 }
461
462 work->crtc = crtc;
f4510a27 463 work->fb = crtc->primary->fb;
85208be0
ED		 464 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
465
5c3fe8b0 466 dev_priv->fbc.fbc_work = work;
85208be0 467
85208be0
ED		 468 /* Delay the actual enabling to let pageflipping cease and the
469 * display to settle before starting the compression. Note that
470 * this delay also serves a second purpose: it allows for a
471 * vblank to pass after disabling the FBC before we attempt
472 * to modify the control registers.
473 *
474 * A more complicated solution would involve tracking vblanks
475 * following the termination of the page-flipping sequence
476 * and indeed performing the enable as a co-routine and not
477 * waiting synchronously upon the vblank.
7457d617
DL		 478 *
479 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 480 */
481 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
482}
483
484void intel_disable_fbc(struct drm_device *dev)
485{
486 struct drm_i915_private *dev_priv = dev->dev_private;
487
488 intel_cancel_fbc_work(dev_priv);
489
490 if (!dev_priv->display.disable_fbc)
491 return;
492
493 dev_priv->display.disable_fbc(dev);
5c3fe8b0 494 dev_priv->fbc.plane = -1;
85208be0
ED		 495}
496
29ebf90f
CW		 497static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
498 enum no_fbc_reason reason)
499{
500 if (dev_priv->fbc.no_fbc_reason == reason)
501 return false;
502
503 dev_priv->fbc.no_fbc_reason = reason;
504 return true;
505}
506
85208be0
ED		 507/**
508 * intel_update_fbc - enable/disable FBC as needed
509 * @dev: the drm_device
510 *
511 * Set up the framebuffer compression hardware at mode set time. We
512 * enable it if possible:
513 * - plane A only (on pre-965)
514 * - no pixel mulitply/line duplication
515 * - no alpha buffer discard
516 * - no dual wide
f85da868 517 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 518 *
519 * We can't assume that any compression will take place (worst case),
520 * so the compressed buffer has to be the same size as the uncompressed
521 * one. It also must reside (along with the line length buffer) in
522 * stolen memory.
523 *
524 * We need to enable/disable FBC on a global basis.
525 */
526void intel_update_fbc(struct drm_device *dev)
527{
528 struct drm_i915_private *dev_priv = dev->dev_private;
529 struct drm_crtc *crtc = NULL, *tmp_crtc;
530 struct intel_crtc *intel_crtc;
531 struct drm_framebuffer *fb;
85208be0 532 struct drm_i915_gem_object *obj;
ef644fda 533 const struct drm_display_mode *adjusted_mode;
37327abd 534 unsigned int max_width, max_height;
85208be0 535
3a77c4c4 536 if (!HAS_FBC(dev)) {
29ebf90f 537 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 538 return;
29ebf90f 539 }
85208be0 540
d330a953 541 if (!i915.powersave) {
29ebf90f
CW		 542 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
543 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 544 return;
29ebf90f 545 }
85208be0
ED		 546
547 /*
548 * If FBC is already on, we just have to verify that we can
549 * keep it that way...
550 * Need to disable if:
551 * - more than one pipe is active
552 * - changing FBC params (stride, fence, mode)
553 * - new fb is too large to fit in compressed buffer
554 * - going to an unsupported config (interlace, pixel multiply, etc.)
555 */
70e1e0ec 556 for_each_crtc(dev, tmp_crtc) {
3490ea5d 557 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 558 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 559 if (crtc) {
29ebf90f
CW		 560 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
561 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 562 goto out_disable;
563 }
564 crtc = tmp_crtc;
565 }
566 }
567
f4510a27 568 if (!crtc || crtc->primary->fb == NULL) {
29ebf90f
CW		 569 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
570 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 571 goto out_disable;
572 }
573
574 intel_crtc = to_intel_crtc(crtc);
f4510a27 575 fb = crtc->primary->fb;
2ff8fde1 576 obj = intel_fb_obj(fb);
ef644fda 577 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 578
0368920e 579 if (i915.enable_fbc < 0) {
29ebf90f
CW		 580 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
581 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 582 goto out_disable;
85208be0 583 }
d330a953 584 if (!i915.enable_fbc) {
29ebf90f
CW		 585 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
586 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 587 goto out_disable;
588 }
ef644fda
VS		 589 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
590 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 591 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
592 DRM_DEBUG_KMS("mode incompatible with compression, "
593 "disabling\n");
85208be0
ED		 594 goto out_disable;
595 }
f85da868 596
032843a5
DS		 597 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
598 max_width = 4096;
599 max_height = 4096;
600 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 601 max_width = 4096;
602 max_height = 2048;
f85da868 603 } else {
37327abd
VS		 604 max_width = 2048;
605 max_height = 1536;
f85da868 606 }
37327abd
VS		 607 if (intel_crtc->config.pipe_src_w > max_width ||
608 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 609 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
610 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 611 goto out_disable;
612 }
8f94d24b 613 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
c5a44aa0 614 intel_crtc->plane != PLANE_A) {
29ebf90f 615 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 616 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 617 goto out_disable;
618 }
619
620 /* The use of a CPU fence is mandatory in order to detect writes
621 * by the CPU to the scanout and trigger updates to the FBC.
622 */
623 if (obj->tiling_mode != I915_TILING_X ||
624 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 625 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
626 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 627 goto out_disable;
628 }
48404c1e
SJ		 629 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
630 to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
631 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
632 DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
633 goto out_disable;
634 }
85208be0
ED		 635
636 /* If the kernel debugger is active, always disable compression */
637 if (in_dbg_master())
638 goto out_disable;
639
2ff8fde1 640 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
5e59f717 641 drm_format_plane_cpp(fb->pixel_format, 0))) {
29ebf90f
CW		 642 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
643 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 644 goto out_disable;
645 }
646
85208be0
ED		 647 /* If the scanout has not changed, don't modify the FBC settings.
648 * Note that we make the fundamental assumption that the fb->obj
649 * cannot be unpinned (and have its GTT offset and fence revoked)
650 * without first being decoupled from the scanout and FBC disabled.
651 */
5c3fe8b0
BW		 652 if (dev_priv->fbc.plane == intel_crtc->plane &&
653 dev_priv->fbc.fb_id == fb->base.id &&
654 dev_priv->fbc.y == crtc->y)
85208be0
ED		 655 return;
656
657 if (intel_fbc_enabled(dev)) {
658 /* We update FBC along two paths, after changing fb/crtc
659 * configuration (modeswitching) and after page-flipping
660 * finishes. For the latter, we know that not only did
661 * we disable the FBC at the start of the page-flip
662 * sequence, but also more than one vblank has passed.
663 *
664 * For the former case of modeswitching, it is possible
665 * to switch between two FBC valid configurations
666 * instantaneously so we do need to disable the FBC
667 * before we can modify its control registers. We also
668 * have to wait for the next vblank for that to take
669 * effect. However, since we delay enabling FBC we can
670 * assume that a vblank has passed since disabling and
671 * that we can safely alter the registers in the deferred
672 * callback.
673 *
674 * In the scenario that we go from a valid to invalid
675 * and then back to valid FBC configuration we have
676 * no strict enforcement that a vblank occurred since
677 * disabling the FBC. However, along all current pipe
678 * disabling paths we do need to wait for a vblank at
679 * some point. And we wait before enabling FBC anyway.
680 */
681 DRM_DEBUG_KMS("disabling active FBC for update\n");
682 intel_disable_fbc(dev);
683 }
684
993495ae 685 intel_enable_fbc(crtc);
29ebf90f 686 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 687 return;
688
689out_disable:
690 /* Multiple disables should be harmless */
691 if (intel_fbc_enabled(dev)) {
692 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
693 intel_disable_fbc(dev);
694 }
11be49eb 695 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 696}
697
c921aba8
DV		 698static void i915_pineview_get_mem_freq(struct drm_device *dev)
699{
50227e1c 700 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 701 u32 tmp;
702
703 tmp = I915_READ(CLKCFG);
704
705 switch (tmp & CLKCFG_FSB_MASK) {
706 case CLKCFG_FSB_533:
707 dev_priv->fsb_freq = 533; /* 133*4 */
708 break;
709 case CLKCFG_FSB_800:
710 dev_priv->fsb_freq = 800; /* 200*4 */
711 break;
712 case CLKCFG_FSB_667:
713 dev_priv->fsb_freq = 667; /* 167*4 */
714 break;
715 case CLKCFG_FSB_400:
716 dev_priv->fsb_freq = 400; /* 100*4 */
717 break;
718 }
719
720 switch (tmp & CLKCFG_MEM_MASK) {
721 case CLKCFG_MEM_533:
722 dev_priv->mem_freq = 533;
723 break;
724 case CLKCFG_MEM_667:
725 dev_priv->mem_freq = 667;
726 break;
727 case CLKCFG_MEM_800:
728 dev_priv->mem_freq = 800;
729 break;
730 }
731
732 /* detect pineview DDR3 setting */
733 tmp = I915_READ(CSHRDDR3CTL);
734 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
735}
736
737static void i915_ironlake_get_mem_freq(struct drm_device *dev)
738{
50227e1c 739 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 740 u16 ddrpll, csipll;
741
742 ddrpll = I915_READ16(DDRMPLL1);
743 csipll = I915_READ16(CSIPLL0);
744
745 switch (ddrpll & 0xff) {
746 case 0xc:
747 dev_priv->mem_freq = 800;
748 break;
749 case 0x10:
750 dev_priv->mem_freq = 1066;
751 break;
752 case 0x14:
753 dev_priv->mem_freq = 1333;
754 break;
755 case 0x18:
756 dev_priv->mem_freq = 1600;
757 break;
758 default:
759 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
760 ddrpll & 0xff);
761 dev_priv->mem_freq = 0;
762 break;
763 }
764
20e4d407 765 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 766
767 switch (csipll & 0x3ff) {
768 case 0x00c:
769 dev_priv->fsb_freq = 3200;
770 break;
771 case 0x00e:
772 dev_priv->fsb_freq = 3733;
773 break;
774 case 0x010:
775 dev_priv->fsb_freq = 4266;
776 break;
777 case 0x012:
778 dev_priv->fsb_freq = 4800;
779 break;
780 case 0x014:
781 dev_priv->fsb_freq = 5333;
782 break;
783 case 0x016:
784 dev_priv->fsb_freq = 5866;
785 break;
786 case 0x018:
787 dev_priv->fsb_freq = 6400;
788 break;
789 default:
790 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
791 csipll & 0x3ff);
792 dev_priv->fsb_freq = 0;
793 break;
794 }
795
796 if (dev_priv->fsb_freq == 3200) {
20e4d407 797 dev_priv->ips.c_m = 0;
c921aba8 798 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 799 dev_priv->ips.c_m = 1;
c921aba8 800 } else {
20e4d407 801 dev_priv->ips.c_m = 2;
c921aba8
DV		 802 }
803}
804
b445e3b0
ED		 805static const struct cxsr_latency cxsr_latency_table[] = {
806 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
807 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
808 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
809 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
810 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
811
812 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
813 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
814 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
815 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
816 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
817
818 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
819 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
820 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
821 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
822 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
823
824 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
825 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
826 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
827 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
828 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
829
830 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
831 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
832 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
833 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
834 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
835
836 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
837 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
838 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
839 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
840 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
841};
842
63c62275 843static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 844 int is_ddr3,
845 int fsb,
846 int mem)
847{
848 const struct cxsr_latency *latency;
849 int i;
850
851 if (fsb == 0 || mem == 0)
852 return NULL;
853
854 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
855 latency = &cxsr_latency_table[i];
856 if (is_desktop == latency->is_desktop &&
857 is_ddr3 == latency->is_ddr3 &&
858 fsb == latency->fsb_freq && mem == latency->mem_freq)
859 return latency;
860 }
861
862 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
863
864 return NULL;
865}
866
5209b1f4 867void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 868{
5209b1f4
ID		 869 struct drm_device *dev = dev_priv->dev;
870 u32 val;
b445e3b0 871
5209b1f4
ID		 872 if (IS_VALLEYVIEW(dev)) {
873 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
874 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
875 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
876 } else if (IS_PINEVIEW(dev)) {
877 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
878 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
879 I915_WRITE(DSPFW3, val);
880 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
881 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
882 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
883 I915_WRITE(FW_BLC_SELF, val);
884 } else if (IS_I915GM(dev)) {
885 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
886 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
887 I915_WRITE(INSTPM, val);
888 } else {
889 return;
890 }
b445e3b0 891
5209b1f4
ID		 892 DRM_DEBUG_KMS("memory self-refresh is %s\n",
893 enable ? "enabled" : "disabled");
b445e3b0
ED		 894}
895
896/*
897 * Latency for FIFO fetches is dependent on several factors:
898 * - memory configuration (speed, channels)
899 * - chipset
900 * - current MCH state
901 * It can be fairly high in some situations, so here we assume a fairly
902 * pessimal value. It's a tradeoff between extra memory fetches (if we
903 * set this value too high, the FIFO will fetch frequently to stay full)
904 * and power consumption (set it too low to save power and we might see
905 * FIFO underruns and display "flicker").
906 *
907 * A value of 5us seems to be a good balance; safe for very low end
908 * platforms but not overly aggressive on lower latency configs.
909 */
5aef6003 910static const int pessimal_latency_ns = 5000;
b445e3b0 911
1fa61106 912static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 913{
914 struct drm_i915_private *dev_priv = dev->dev_private;
915 uint32_t dsparb = I915_READ(DSPARB);
916 int size;
917
918 size = dsparb & 0x7f;
919 if (plane)
920 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
921
922 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
923 plane ? "B" : "A", size);
924
925 return size;
926}
927
feb56b93 928static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 929{
930 struct drm_i915_private *dev_priv = dev->dev_private;
931 uint32_t dsparb = I915_READ(DSPARB);
932 int size;
933
934 size = dsparb & 0x1ff;
935 if (plane)
936 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
937 size >>= 1; /* Convert to cachelines */
938
939 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
940 plane ? "B" : "A", size);
941
942 return size;
943}
944
1fa61106 945static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 946{
947 struct drm_i915_private *dev_priv = dev->dev_private;
948 uint32_t dsparb = I915_READ(DSPARB);
949 int size;
950
951 size = dsparb & 0x7f;
952 size >>= 2; /* Convert to cachelines */
953
954 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
955 plane ? "B" : "A",
956 size);
957
958 return size;
959}
960
b445e3b0
ED		 961/* Pineview has different values for various configs */
962static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 963 .fifo_size = PINEVIEW_DISPLAY_FIFO,
964 .max_wm = PINEVIEW_MAX_WM,
965 .default_wm = PINEVIEW_DFT_WM,
966 .guard_size = PINEVIEW_GUARD_WM,
967 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 968};
969static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 970 .fifo_size = PINEVIEW_DISPLAY_FIFO,
971 .max_wm = PINEVIEW_MAX_WM,
972 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
973 .guard_size = PINEVIEW_GUARD_WM,
974 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 975};
976static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 977 .fifo_size = PINEVIEW_CURSOR_FIFO,
978 .max_wm = PINEVIEW_CURSOR_MAX_WM,
979 .default_wm = PINEVIEW_CURSOR_DFT_WM,
980 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
981 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 982};
983static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 984 .fifo_size = PINEVIEW_CURSOR_FIFO,
985 .max_wm = PINEVIEW_CURSOR_MAX_WM,
986 .default_wm = PINEVIEW_CURSOR_DFT_WM,
987 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
988 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 989};
990static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 991 .fifo_size = G4X_FIFO_SIZE,
992 .max_wm = G4X_MAX_WM,
993 .default_wm = G4X_MAX_WM,
994 .guard_size = 2,
995 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 996};
997static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 998 .fifo_size = I965_CURSOR_FIFO,
999 .max_wm = I965_CURSOR_MAX_WM,
1000 .default_wm = I965_CURSOR_DFT_WM,
1001 .guard_size = 2,
1002 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 1003};
1004static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 1005 .fifo_size = VALLEYVIEW_FIFO_SIZE,
1006 .max_wm = VALLEYVIEW_MAX_WM,
1007 .default_wm = VALLEYVIEW_MAX_WM,
1008 .guard_size = 2,
1009 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 1010};
1011static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 1012 .fifo_size = I965_CURSOR_FIFO,
1013 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
1014 .default_wm = I965_CURSOR_DFT_WM,
1015 .guard_size = 2,
1016 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 1017};
1018static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 1019 .fifo_size = I965_CURSOR_FIFO,
1020 .max_wm = I965_CURSOR_MAX_WM,
1021 .default_wm = I965_CURSOR_DFT_WM,
1022 .guard_size = 2,
1023 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 1024};
1025static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 1026 .fifo_size = I945_FIFO_SIZE,
1027 .max_wm = I915_MAX_WM,
1028 .default_wm = 1,
1029 .guard_size = 2,
1030 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 1031};
1032static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 1033 .fifo_size = I915_FIFO_SIZE,
1034 .max_wm = I915_MAX_WM,
1035 .default_wm = 1,
1036 .guard_size = 2,
1037 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 1038};
9d539105 1039static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 1040 .fifo_size = I855GM_FIFO_SIZE,
1041 .max_wm = I915_MAX_WM,
1042 .default_wm = 1,
1043 .guard_size = 2,
1044 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 1045};
9d539105
VS		 1046static const struct intel_watermark_params i830_bc_wm_info = {
1047 .fifo_size = I855GM_FIFO_SIZE,
1048 .max_wm = I915_MAX_WM/2,
1049 .default_wm = 1,
1050 .guard_size = 2,
1051 .cacheline_size = I830_FIFO_LINE_SIZE,
1052};
feb56b93 1053static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 1054 .fifo_size = I830_FIFO_SIZE,
1055 .max_wm = I915_MAX_WM,
1056 .default_wm = 1,
1057 .guard_size = 2,
1058 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 1059};
1060
b445e3b0
ED		 1061/**
1062 * intel_calculate_wm - calculate watermark level
1063 * @clock_in_khz: pixel clock
1064 * @wm: chip FIFO params
1065 * @pixel_size: display pixel size
1066 * @latency_ns: memory latency for the platform
1067 *
1068 * Calculate the watermark level (the level at which the display plane will
1069 * start fetching from memory again). Each chip has a different display
1070 * FIFO size and allocation, so the caller needs to figure that out and pass
1071 * in the correct intel_watermark_params structure.
1072 *
1073 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1074 * on the pixel size. When it reaches the watermark level, it'll start
1075 * fetching FIFO line sized based chunks from memory until the FIFO fills
1076 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1077 * will occur, and a display engine hang could result.
1078 */
1079static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1080 const struct intel_watermark_params *wm,
1081 int fifo_size,
1082 int pixel_size,
1083 unsigned long latency_ns)
1084{
1085 long entries_required, wm_size;
1086
1087 /*
1088 * Note: we need to make sure we don't overflow for various clock &
1089 * latency values.
1090 * clocks go from a few thousand to several hundred thousand.
1091 * latency is usually a few thousand
1092 */
1093 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1094 1000;
1095 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1096
1097 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1098
1099 wm_size = fifo_size - (entries_required + wm->guard_size);
1100
1101 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1102
1103 /* Don't promote wm_size to unsigned... */
1104 if (wm_size > (long)wm->max_wm)
1105 wm_size = wm->max_wm;
1106 if (wm_size <= 0)
1107 wm_size = wm->default_wm;
d6feb196
VS		 1108
1109 /*
1110 * Bspec seems to indicate that the value shouldn't be lower than
1111 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
1112 * Lets go for 8 which is the burst size since certain platforms
1113 * already use a hardcoded 8 (which is what the spec says should be
1114 * done).
1115 */
1116 if (wm_size <= 8)
1117 wm_size = 8;
1118
b445e3b0
ED		 1119 return wm_size;
1120}
1121
1122static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1123{
1124 struct drm_crtc *crtc, *enabled = NULL;
1125
70e1e0ec 1126 for_each_crtc(dev, crtc) {
3490ea5d 1127 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1128 if (enabled)
1129 return NULL;
1130 enabled = crtc;
1131 }
1132 }
1133
1134 return enabled;
1135}
1136
46ba614c 1137static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1138{
46ba614c 1139 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1140 struct drm_i915_private *dev_priv = dev->dev_private;
1141 struct drm_crtc *crtc;
1142 const struct cxsr_latency *latency;
1143 u32 reg;
1144 unsigned long wm;
1145
1146 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1147 dev_priv->fsb_freq, dev_priv->mem_freq);
1148 if (!latency) {
1149 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 1150 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1151 return;
1152 }
1153
1154 crtc = single_enabled_crtc(dev);
1155 if (crtc) {
241bfc38 1156 const struct drm_display_mode *adjusted_mode;
f4510a27 1157 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
241bfc38
DL		 1158 int clock;
1159
1160 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1161 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1162
1163 /* Display SR */
1164 wm = intel_calculate_wm(clock, &pineview_display_wm,
1165 pineview_display_wm.fifo_size,
1166 pixel_size, latency->display_sr);
1167 reg = I915_READ(DSPFW1);
1168 reg &= ~DSPFW_SR_MASK;
1169 reg |= wm << DSPFW_SR_SHIFT;
1170 I915_WRITE(DSPFW1, reg);
1171 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1172
1173 /* cursor SR */
1174 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1175 pineview_display_wm.fifo_size,
1176 pixel_size, latency->cursor_sr);
1177 reg = I915_READ(DSPFW3);
1178 reg &= ~DSPFW_CURSOR_SR_MASK;
1179 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1180 I915_WRITE(DSPFW3, reg);
1181
1182 /* Display HPLL off SR */
1183 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1184 pineview_display_hplloff_wm.fifo_size,
1185 pixel_size, latency->display_hpll_disable);
1186 reg = I915_READ(DSPFW3);
1187 reg &= ~DSPFW_HPLL_SR_MASK;
1188 reg |= wm & DSPFW_HPLL_SR_MASK;
1189 I915_WRITE(DSPFW3, reg);
1190
1191 /* cursor HPLL off SR */
1192 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1193 pineview_display_hplloff_wm.fifo_size,
1194 pixel_size, latency->cursor_hpll_disable);
1195 reg = I915_READ(DSPFW3);
1196 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1197 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1198 I915_WRITE(DSPFW3, reg);
1199 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1200
5209b1f4 1201 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 1202 } else {
5209b1f4 1203 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1204 }
1205}
1206
1207static bool g4x_compute_wm0(struct drm_device *dev,
1208 int plane,
1209 const struct intel_watermark_params *display,
1210 int display_latency_ns,
1211 const struct intel_watermark_params *cursor,
1212 int cursor_latency_ns,
1213 int *plane_wm,
1214 int *cursor_wm)
1215{
1216 struct drm_crtc *crtc;
4fe8590a 1217 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1218 int htotal, hdisplay, clock, pixel_size;
1219 int line_time_us, line_count;
1220 int entries, tlb_miss;
1221
1222 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1223 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1224 *cursor_wm = cursor->guard_size;
1225 *plane_wm = display->guard_size;
1226 return false;
1227 }
1228
4fe8590a 1229 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1230 clock = adjusted_mode->crtc_clock;
fec8cba3 1231 htotal = adjusted_mode->crtc_htotal;
37327abd 1232 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1233 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1234
1235 /* Use the small buffer method to calculate plane watermark */
1236 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1237 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1238 if (tlb_miss > 0)
1239 entries += tlb_miss;
1240 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1241 *plane_wm = entries + display->guard_size;
1242 if (*plane_wm > (int)display->max_wm)
1243 *plane_wm = display->max_wm;
1244
1245 /* Use the large buffer method to calculate cursor watermark */
922044c9 1246 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 1247 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
7bb836dd 1248 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
b445e3b0
ED		 1249 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1250 if (tlb_miss > 0)
1251 entries += tlb_miss;
1252 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1253 *cursor_wm = entries + cursor->guard_size;
1254 if (*cursor_wm > (int)cursor->max_wm)
1255 *cursor_wm = (int)cursor->max_wm;
1256
1257 return true;
1258}
1259
1260/*
1261 * Check the wm result.
1262 *
1263 * If any calculated watermark values is larger than the maximum value that
1264 * can be programmed into the associated watermark register, that watermark
1265 * must be disabled.
1266 */
1267static bool g4x_check_srwm(struct drm_device *dev,
1268 int display_wm, int cursor_wm,
1269 const struct intel_watermark_params *display,
1270 const struct intel_watermark_params *cursor)
1271{
1272 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1273 display_wm, cursor_wm);
1274
1275 if (display_wm > display->max_wm) {
1276 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1277 display_wm, display->max_wm);
1278 return false;
1279 }
1280
1281 if (cursor_wm > cursor->max_wm) {
1282 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1283 cursor_wm, cursor->max_wm);
1284 return false;
1285 }
1286
1287 if (!(display_wm || cursor_wm)) {
1288 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1289 return false;
1290 }
1291
1292 return true;
1293}
1294
1295static bool g4x_compute_srwm(struct drm_device *dev,
1296 int plane,
1297 int latency_ns,
1298 const struct intel_watermark_params *display,
1299 const struct intel_watermark_params *cursor,
1300 int *display_wm, int *cursor_wm)
1301{
1302 struct drm_crtc *crtc;
4fe8590a 1303 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1304 int hdisplay, htotal, pixel_size, clock;
1305 unsigned long line_time_us;
1306 int line_count, line_size;
1307 int small, large;
1308 int entries;
1309
1310 if (!latency_ns) {
1311 *display_wm = *cursor_wm = 0;
1312 return false;
1313 }
1314
1315 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1316 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1317 clock = adjusted_mode->crtc_clock;
fec8cba3 1318 htotal = adjusted_mode->crtc_htotal;
37327abd 1319 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1320 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0 1321
922044c9 1322 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1323 line_count = (latency_ns / line_time_us + 1000) / 1000;
1324 line_size = hdisplay * pixel_size;
1325
1326 /* Use the minimum of the small and large buffer method for primary */
1327 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1328 large = line_count * line_size;
1329
1330 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1331 *display_wm = entries + display->guard_size;
1332
1333 /* calculate the self-refresh watermark for display cursor */
7bb836dd 1334 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1335 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1336 *cursor_wm = entries + cursor->guard_size;
1337
1338 return g4x_check_srwm(dev,
1339 *display_wm, *cursor_wm,
1340 display, cursor);
1341}
1342
0948c265
GB		 1343static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
1344 int pixel_size,
1345 int *prec_mult,
1346 int *drain_latency)
b445e3b0 1347{
5e56ba45 1348 struct drm_device *dev = crtc->dev;
b445e3b0 1349 int entries;
0948c265 1350 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0 1351
0948c265 1352 if (WARN(clock == 0, "Pixel clock is zero!\n"))
b445e3b0
ED		 1353 return false;
1354
0948c265
GB		 1355 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
1356 return false;
b445e3b0 1357
a398e9c7 1358 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
5e56ba45
RV		 1359 if (IS_CHERRYVIEW(dev))
1360 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_32 :
1361 DRAIN_LATENCY_PRECISION_16;
1362 else
1363 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
1364 DRAIN_LATENCY_PRECISION_32;
0948c265 1365 *drain_latency = (64 * (*prec_mult) * 4) / entries;
b445e3b0 1366
a398e9c7
GB		 1367 if (*drain_latency > DRAIN_LATENCY_MASK)
1368 *drain_latency = DRAIN_LATENCY_MASK;
b445e3b0
ED		 1369
1370 return true;
1371}
1372
1373/*
1374 * Update drain latency registers of memory arbiter
1375 *
1376 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1377 * to be programmed. Each plane has a drain latency multiplier and a drain
1378 * latency value.
1379 */
1380
41aad816 1381static void vlv_update_drain_latency(struct drm_crtc *crtc)
b445e3b0 1382{
5e56ba45
RV		 1383 struct drm_device *dev = crtc->dev;
1384 struct drm_i915_private *dev_priv = dev->dev_private;
0948c265
GB		 1385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1386 int pixel_size;
1387 int drain_latency;
1388 enum pipe pipe = intel_crtc->pipe;
1389 int plane_prec, prec_mult, plane_dl;
5e56ba45
RV		 1390 const int high_precision = IS_CHERRYVIEW(dev) ?
1391 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
b445e3b0 1392
5e56ba45
RV		 1393 plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH |
1394 DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH |
0948c265
GB		 1395 (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
1396
1397 if (!intel_crtc_active(crtc)) {
1398 I915_WRITE(VLV_DDL(pipe), plane_dl);
1399 return;
1400 }
b445e3b0 1401
0948c265
GB		 1402 /* Primary plane Drain Latency */
1403 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1404 if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
5e56ba45
RV		 1405 plane_prec = (prec_mult == high_precision) ?
1406 DDL_PLANE_PRECISION_HIGH :
1407 DDL_PLANE_PRECISION_LOW;
0948c265 1408 plane_dl |= plane_prec | drain_latency;
b445e3b0
ED		 1409 }
1410
0948c265
GB		 1411 /* Cursor Drain Latency
1412 * BPP is always 4 for cursor
1413 */
1414 pixel_size = 4;
b445e3b0 1415
0948c265
GB		 1416 /* Program cursor DL only if it is enabled */
1417 if (intel_crtc->cursor_base &&
1418 vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
5e56ba45
RV		 1419 plane_prec = (prec_mult == high_precision) ?
1420 DDL_CURSOR_PRECISION_HIGH :
1421 DDL_CURSOR_PRECISION_LOW;
0948c265 1422 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
b445e3b0 1423 }
0948c265
GB		 1424
1425 I915_WRITE(VLV_DDL(pipe), plane_dl);
b445e3b0
ED		 1426}
1427
1428#define single_plane_enabled(mask) is_power_of_2(mask)
1429
46ba614c 1430static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1431{
46ba614c 1432 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1433 static const int sr_latency_ns = 12000;
1434 struct drm_i915_private *dev_priv = dev->dev_private;
1435 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1436 int plane_sr, cursor_sr;
af6c4575 1437 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0 1438 unsigned int enabled = 0;
9858425c 1439 bool cxsr_enabled;
b445e3b0 1440
41aad816 1441 vlv_update_drain_latency(crtc);
b445e3b0 1442
51cea1f4 1443 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1444 &valleyview_wm_info, pessimal_latency_ns,
1445 &valleyview_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1446 &planea_wm, &cursora_wm))
51cea1f4 1447 enabled |= 1 << PIPE_A;
b445e3b0 1448
51cea1f4 1449 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1450 &valleyview_wm_info, pessimal_latency_ns,
1451 &valleyview_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1452 &planeb_wm, &cursorb_wm))
51cea1f4 1453 enabled |= 1 << PIPE_B;
b445e3b0 1454
b445e3b0
ED		 1455 if (single_plane_enabled(enabled) &&
1456 g4x_compute_srwm(dev, ffs(enabled) - 1,
1457 sr_latency_ns,
1458 &valleyview_wm_info,
1459 &valleyview_cursor_wm_info,
af6c4575
CW		 1460 &plane_sr, &ignore_cursor_sr) &&
1461 g4x_compute_srwm(dev, ffs(enabled) - 1,
1462 2*sr_latency_ns,
1463 &valleyview_wm_info,
1464 &valleyview_cursor_wm_info,
52bd02d8 1465 &ignore_plane_sr, &cursor_sr)) {
9858425c 1466 cxsr_enabled = true;
52bd02d8 1467 } else {
9858425c 1468 cxsr_enabled = false;
5209b1f4 1469 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1470 plane_sr = cursor_sr = 0;
1471 }
b445e3b0 1472
a5043453
VS		 1473 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1474 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1475 planea_wm, cursora_wm,
1476 planeb_wm, cursorb_wm,
1477 plane_sr, cursor_sr);
1478
1479 I915_WRITE(DSPFW1,
1480 (plane_sr << DSPFW_SR_SHIFT) |
1481 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1482 (planeb_wm << DSPFW_PLANEB_SHIFT) |
0a560674 1483 (planea_wm << DSPFW_PLANEA_SHIFT));
b445e3b0 1484 I915_WRITE(DSPFW2,
8c919b28 1485 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1486 (cursora_wm << DSPFW_CURSORA_SHIFT));
1487 I915_WRITE(DSPFW3,
8c919b28
CW		 1488 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1489 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1490
1491 if (cxsr_enabled)
1492 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1493}
1494
3c2777fd
VS		 1495static void cherryview_update_wm(struct drm_crtc *crtc)
1496{
1497 struct drm_device *dev = crtc->dev;
1498 static const int sr_latency_ns = 12000;
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500 int planea_wm, planeb_wm, planec_wm;
1501 int cursora_wm, cursorb_wm, cursorc_wm;
1502 int plane_sr, cursor_sr;
1503 int ignore_plane_sr, ignore_cursor_sr;
1504 unsigned int enabled = 0;
1505 bool cxsr_enabled;
1506
1507 vlv_update_drain_latency(crtc);
1508
1509 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1510 &valleyview_wm_info, pessimal_latency_ns,
1511 &valleyview_cursor_wm_info, pessimal_latency_ns,
3c2777fd
VS		 1512 &planea_wm, &cursora_wm))
1513 enabled |= 1 << PIPE_A;
1514
1515 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1516 &valleyview_wm_info, pessimal_latency_ns,
1517 &valleyview_cursor_wm_info, pessimal_latency_ns,
3c2777fd
VS		 1518 &planeb_wm, &cursorb_wm))
1519 enabled |= 1 << PIPE_B;
1520
1521 if (g4x_compute_wm0(dev, PIPE_C,
5aef6003
CW		 1522 &valleyview_wm_info, pessimal_latency_ns,
1523 &valleyview_cursor_wm_info, pessimal_latency_ns,
3c2777fd
VS		 1524 &planec_wm, &cursorc_wm))
1525 enabled |= 1 << PIPE_C;
1526
1527 if (single_plane_enabled(enabled) &&
1528 g4x_compute_srwm(dev, ffs(enabled) - 1,
1529 sr_latency_ns,
1530 &valleyview_wm_info,
1531 &valleyview_cursor_wm_info,
1532 &plane_sr, &ignore_cursor_sr) &&
1533 g4x_compute_srwm(dev, ffs(enabled) - 1,
1534 2*sr_latency_ns,
1535 &valleyview_wm_info,
1536 &valleyview_cursor_wm_info,
1537 &ignore_plane_sr, &cursor_sr)) {
1538 cxsr_enabled = true;
1539 } else {
1540 cxsr_enabled = false;
1541 intel_set_memory_cxsr(dev_priv, false);
1542 plane_sr = cursor_sr = 0;
1543 }
1544
1545 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1546 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1547 "SR: plane=%d, cursor=%d\n",
1548 planea_wm, cursora_wm,
1549 planeb_wm, cursorb_wm,
1550 planec_wm, cursorc_wm,
1551 plane_sr, cursor_sr);
1552
1553 I915_WRITE(DSPFW1,
1554 (plane_sr << DSPFW_SR_SHIFT) |
1555 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1556 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1557 (planea_wm << DSPFW_PLANEA_SHIFT));
1558 I915_WRITE(DSPFW2,
1559 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1560 (cursora_wm << DSPFW_CURSORA_SHIFT));
1561 I915_WRITE(DSPFW3,
1562 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1563 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1564 I915_WRITE(DSPFW9_CHV,
1565 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
1566 DSPFW_CURSORC_MASK)) |
1567 (planec_wm << DSPFW_PLANEC_SHIFT) |
1568 (cursorc_wm << DSPFW_CURSORC_SHIFT));
1569
1570 if (cxsr_enabled)
1571 intel_set_memory_cxsr(dev_priv, true);
1572}
1573
01e184cc
GB		 1574static void valleyview_update_sprite_wm(struct drm_plane *plane,
1575 struct drm_crtc *crtc,
1576 uint32_t sprite_width,
1577 uint32_t sprite_height,
1578 int pixel_size,
1579 bool enabled, bool scaled)
1580{
1581 struct drm_device *dev = crtc->dev;
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583 int pipe = to_intel_plane(plane)->pipe;
1584 int sprite = to_intel_plane(plane)->plane;
1585 int drain_latency;
1586 int plane_prec;
1587 int sprite_dl;
1588 int prec_mult;
5e56ba45
RV		 1589 const int high_precision = IS_CHERRYVIEW(dev) ?
1590 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
01e184cc 1591
5e56ba45 1592 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_HIGH(sprite) |
01e184cc
GB		 1593 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
1594
1595 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
1596 &drain_latency)) {
5e56ba45
RV		 1597 plane_prec = (prec_mult == high_precision) ?
1598 DDL_SPRITE_PRECISION_HIGH(sprite) :
1599 DDL_SPRITE_PRECISION_LOW(sprite);
01e184cc
GB		 1600 sprite_dl |= plane_prec |
1601 (drain_latency << DDL_SPRITE_SHIFT(sprite));
1602 }
1603
1604 I915_WRITE(VLV_DDL(pipe), sprite_dl);
1605}
1606
46ba614c 1607static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1608{
46ba614c 1609 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1610 static const int sr_latency_ns = 12000;
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1613 int plane_sr, cursor_sr;
1614 unsigned int enabled = 0;
9858425c 1615 bool cxsr_enabled;
b445e3b0 1616
51cea1f4 1617 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1618 &g4x_wm_info, pessimal_latency_ns,
1619 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1620 &planea_wm, &cursora_wm))
51cea1f4 1621 enabled |= 1 << PIPE_A;
b445e3b0 1622
51cea1f4 1623 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1624 &g4x_wm_info, pessimal_latency_ns,
1625 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1626 &planeb_wm, &cursorb_wm))
51cea1f4 1627 enabled |= 1 << PIPE_B;
b445e3b0 1628
b445e3b0
ED		 1629 if (single_plane_enabled(enabled) &&
1630 g4x_compute_srwm(dev, ffs(enabled) - 1,
1631 sr_latency_ns,
1632 &g4x_wm_info,
1633 &g4x_cursor_wm_info,
52bd02d8 1634 &plane_sr, &cursor_sr)) {
9858425c 1635 cxsr_enabled = true;
52bd02d8 1636 } else {
9858425c 1637 cxsr_enabled = false;
5209b1f4 1638 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1639 plane_sr = cursor_sr = 0;
1640 }
b445e3b0 1641
a5043453
VS		 1642 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1643 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1644 planea_wm, cursora_wm,
1645 planeb_wm, cursorb_wm,
1646 plane_sr, cursor_sr);
1647
1648 I915_WRITE(DSPFW1,
1649 (plane_sr << DSPFW_SR_SHIFT) |
1650 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1651 (planeb_wm << DSPFW_PLANEB_SHIFT) |
0a560674 1652 (planea_wm << DSPFW_PLANEA_SHIFT));
b445e3b0 1653 I915_WRITE(DSPFW2,
8c919b28 1654 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1655 (cursora_wm << DSPFW_CURSORA_SHIFT));
1656 /* HPLL off in SR has some issues on G4x... disable it */
1657 I915_WRITE(DSPFW3,
8c919b28 1658 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0 1659 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1660
1661 if (cxsr_enabled)
1662 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1663}
1664
46ba614c 1665static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1666{
46ba614c 1667 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 struct drm_crtc *crtc;
1670 int srwm = 1;
1671 int cursor_sr = 16;
9858425c 1672 bool cxsr_enabled;
b445e3b0
ED		 1673
1674 /* Calc sr entries for one plane configs */
1675 crtc = single_enabled_crtc(dev);
1676 if (crtc) {
1677 /* self-refresh has much higher latency */
1678 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1679 const struct drm_display_mode *adjusted_mode =
1680 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1681 int clock = adjusted_mode->crtc_clock;
fec8cba3 1682 int htotal = adjusted_mode->crtc_htotal;
37327abd 1683 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1684 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1685 unsigned long line_time_us;
1686 int entries;
1687
922044c9 1688 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1689
1690 /* Use ns/us then divide to preserve precision */
1691 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1692 pixel_size * hdisplay;
1693 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1694 srwm = I965_FIFO_SIZE - entries;
1695 if (srwm < 0)
1696 srwm = 1;
1697 srwm &= 0x1ff;
1698 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1699 entries, srwm);
1700
1701 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
7bb836dd 1702 pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1703 entries = DIV_ROUND_UP(entries,
1704 i965_cursor_wm_info.cacheline_size);
1705 cursor_sr = i965_cursor_wm_info.fifo_size -
1706 (entries + i965_cursor_wm_info.guard_size);
1707
1708 if (cursor_sr > i965_cursor_wm_info.max_wm)
1709 cursor_sr = i965_cursor_wm_info.max_wm;
1710
1711 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1712 "cursor %d\n", srwm, cursor_sr);
1713
9858425c 1714 cxsr_enabled = true;
b445e3b0 1715 } else {
9858425c 1716 cxsr_enabled = false;
b445e3b0 1717 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1718 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1719 }
1720
1721 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1722 srwm);
1723
1724 /* 965 has limitations... */
1725 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
0a560674
VS		 1726 (8 << DSPFW_CURSORB_SHIFT) |
1727 (8 << DSPFW_PLANEB_SHIFT) |
1728 (8 << DSPFW_PLANEA_SHIFT));
1729 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1730 (8 << DSPFW_PLANEC_SHIFT_OLD));
b445e3b0
ED		 1731 /* update cursor SR watermark */
1732 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1733
1734 if (cxsr_enabled)
1735 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1736}
1737
46ba614c 1738static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1739{
46ba614c 1740 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1741 struct drm_i915_private *dev_priv = dev->dev_private;
1742 const struct intel_watermark_params *wm_info;
1743 uint32_t fwater_lo;
1744 uint32_t fwater_hi;
1745 int cwm, srwm = 1;
1746 int fifo_size;
1747 int planea_wm, planeb_wm;
1748 struct drm_crtc *crtc, *enabled = NULL;
1749
1750 if (IS_I945GM(dev))
1751 wm_info = &i945_wm_info;
1752 else if (!IS_GEN2(dev))
1753 wm_info = &i915_wm_info;
1754 else
9d539105 1755 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1756
1757 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1758 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1759 if (intel_crtc_active(crtc)) {
241bfc38 1760 const struct drm_display_mode *adjusted_mode;
f4510a27 1761 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1762 if (IS_GEN2(dev))
1763 cpp = 4;
1764
241bfc38
DL		 1765 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1766 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1767 wm_info, fifo_size, cpp,
5aef6003 1768 pessimal_latency_ns);
b445e3b0 1769 enabled = crtc;
9d539105 1770 } else {
b445e3b0 1771 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1772 if (planea_wm > (long)wm_info->max_wm)
1773 planea_wm = wm_info->max_wm;
1774 }
1775
1776 if (IS_GEN2(dev))
1777 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1778
1779 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1780 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1781 if (intel_crtc_active(crtc)) {
241bfc38 1782 const struct drm_display_mode *adjusted_mode;
f4510a27 1783 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1784 if (IS_GEN2(dev))
1785 cpp = 4;
1786
241bfc38
DL		 1787 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1788 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1789 wm_info, fifo_size, cpp,
5aef6003 1790 pessimal_latency_ns);
b445e3b0
ED		 1791 if (enabled == NULL)
1792 enabled = crtc;
1793 else
1794 enabled = NULL;
9d539105 1795 } else {
b445e3b0 1796 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1797 if (planeb_wm > (long)wm_info->max_wm)
1798 planeb_wm = wm_info->max_wm;
1799 }
b445e3b0
ED		 1800
1801 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1802
2ab1bc9d 1803 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1804 struct drm_i915_gem_object *obj;
2ab1bc9d 1805
2ff8fde1 1806 obj = intel_fb_obj(enabled->primary->fb);
2ab1bc9d
DV		 1807
1808 /* self-refresh seems busted with untiled */
2ff8fde1 1809 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1810 enabled = NULL;
1811 }
1812
b445e3b0
ED		 1813 /*
1814 * Overlay gets an aggressive default since video jitter is bad.
1815 */
1816 cwm = 2;
1817
1818 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1819 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1820
1821 /* Calc sr entries for one plane configs */
1822 if (HAS_FW_BLC(dev) && enabled) {
1823 /* self-refresh has much higher latency */
1824 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1825 const struct drm_display_mode *adjusted_mode =
1826 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1827 int clock = adjusted_mode->crtc_clock;
fec8cba3 1828 int htotal = adjusted_mode->crtc_htotal;
f727b490 1829 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
f4510a27 1830 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1831 unsigned long line_time_us;
1832 int entries;
1833
922044c9 1834 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1835
1836 /* Use ns/us then divide to preserve precision */
1837 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1838 pixel_size * hdisplay;
1839 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1840 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1841 srwm = wm_info->fifo_size - entries;
1842 if (srwm < 0)
1843 srwm = 1;
1844
1845 if (IS_I945G(dev) || IS_I945GM(dev))
1846 I915_WRITE(FW_BLC_SELF,
1847 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1848 else if (IS_I915GM(dev))
1849 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1850 }
1851
1852 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1853 planea_wm, planeb_wm, cwm, srwm);
1854
1855 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1856 fwater_hi = (cwm & 0x1f);
1857
1858 /* Set request length to 8 cachelines per fetch */
1859 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1860 fwater_hi = fwater_hi | (1 << 8);
1861
1862 I915_WRITE(FW_BLC, fwater_lo);
1863 I915_WRITE(FW_BLC2, fwater_hi);
1864
5209b1f4
ID		 1865 if (enabled)
1866 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1867}
1868
feb56b93 1869static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1870{
46ba614c 1871 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1872 struct drm_i915_private *dev_priv = dev->dev_private;
1873 struct drm_crtc *crtc;
241bfc38 1874 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1875 uint32_t fwater_lo;
1876 int planea_wm;
1877
1878 crtc = single_enabled_crtc(dev);
1879 if (crtc == NULL)
1880 return;
1881
241bfc38
DL		 1882 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1883 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1884 &i845_wm_info,
b445e3b0 1885 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1886 4, pessimal_latency_ns);
b445e3b0
ED		 1887 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1888 fwater_lo |= (3<<8) | planea_wm;
1889
1890 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1891
1892 I915_WRITE(FW_BLC, fwater_lo);
1893}
1894
3658729a
VS		 1895static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1896 struct drm_crtc *crtc)
801bcfff
PZ		 1897{
1898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1899 uint32_t pixel_rate;
801bcfff 1900
241bfc38 1901 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 1902
1903 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1904 * adjust the pixel_rate here. */
1905
fd4daa9c 1906 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1907 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1908 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1909
37327abd
VS		 1910 pipe_w = intel_crtc->config.pipe_src_w;
1911 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 1912 pfit_w = (pfit_size >> 16) & 0xFFFF;
1913 pfit_h = pfit_size & 0xFFFF;
1914 if (pipe_w < pfit_w)
1915 pipe_w = pfit_w;
1916 if (pipe_h < pfit_h)
1917 pipe_h = pfit_h;
1918
1919 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1920 pfit_w * pfit_h);
1921 }
1922
1923 return pixel_rate;
1924}
1925
37126462 1926/* latency must be in 0.1us units. */
23297044 1927static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1928 uint32_t latency)
1929{
1930 uint64_t ret;
1931
3312ba65
VS		 1932 if (WARN(latency == 0, "Latency value missing\n"))
1933 return UINT_MAX;
1934
801bcfff
PZ		 1935 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1936 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1937
1938 return ret;
1939}
1940
37126462 1941/* latency must be in 0.1us units. */
23297044 1942static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1943 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1944 uint32_t latency)
1945{
1946 uint32_t ret;
1947
3312ba65
VS		 1948 if (WARN(latency == 0, "Latency value missing\n"))
1949 return UINT_MAX;
1950
801bcfff
PZ		 1951 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1952 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1953 ret = DIV_ROUND_UP(ret, 64) + 2;
1954 return ret;
1955}
1956
23297044 1957static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1958 uint8_t bytes_per_pixel)
1959{
1960 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1961}
1962
2ac96d2a
PB		 1963struct skl_pipe_wm_parameters {
1964 bool active;
1965 uint32_t pipe_htotal;
1966 uint32_t pixel_rate; /* in KHz */
1967 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1968 struct intel_plane_wm_parameters cursor;
1969};
1970
820c1980 1971struct ilk_pipe_wm_parameters {
801bcfff 1972 bool active;
801bcfff
PZ		 1973 uint32_t pipe_htotal;
1974 uint32_t pixel_rate;
c35426d2
VS		 1975 struct intel_plane_wm_parameters pri;
1976 struct intel_plane_wm_parameters spr;
1977 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1978};
1979
820c1980 1980struct ilk_wm_maximums {
cca32e9a
PZ		 1981 uint16_t pri;
1982 uint16_t spr;
1983 uint16_t cur;
1984 uint16_t fbc;
1985};
1986
240264f4
VS		 1987/* used in computing the new watermarks state */
1988struct intel_wm_config {
1989 unsigned int num_pipes_active;
1990 bool sprites_enabled;
1991 bool sprites_scaled;
240264f4
VS		 1992};
1993
37126462
VS		 1994/*
1995 * For both WM_PIPE and WM_LP.
1996 * mem_value must be in 0.1us units.
1997 */
820c1980 1998static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1999 uint32_t mem_value,
2000 bool is_lp)
801bcfff 2001{
cca32e9a
PZ		 2002 uint32_t method1, method2;
2003
c35426d2 2004 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 2005 return 0;
2006
23297044 2007 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2008 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2009 mem_value);
2010
2011 if (!is_lp)
2012 return method1;
2013
23297044 2014 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 2015 params->pipe_htotal,
c35426d2
VS		 2016 params->pri.horiz_pixels,
2017 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2018 mem_value);
2019
2020 return min(method1, method2);
801bcfff
PZ		 2021}
2022
37126462
VS		 2023/*
2024 * For both WM_PIPE and WM_LP.
2025 * mem_value must be in 0.1us units.
2026 */
820c1980 2027static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 2028 uint32_t mem_value)
2029{
2030 uint32_t method1, method2;
2031
c35426d2 2032 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 2033 return 0;
2034
23297044 2035 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2036 params->spr.bytes_per_pixel,
801bcfff 2037 mem_value);
23297044 2038 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 2039 params->pipe_htotal,
c35426d2
VS		 2040 params->spr.horiz_pixels,
2041 params->spr.bytes_per_pixel,
801bcfff
PZ		 2042 mem_value);
2043 return min(method1, method2);
2044}
2045
37126462
VS		 2046/*
2047 * For both WM_PIPE and WM_LP.
2048 * mem_value must be in 0.1us units.
2049 */
820c1980 2050static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 2051 uint32_t mem_value)
2052{
c35426d2 2053 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 2054 return 0;
2055
23297044 2056 return ilk_wm_method2(params->pixel_rate,
801bcfff 2057 params->pipe_htotal,
c35426d2
VS		 2058 params->cur.horiz_pixels,
2059 params->cur.bytes_per_pixel,
801bcfff
PZ		 2060 mem_value);
2061}
2062
cca32e9a 2063/* Only for WM_LP. */
820c1980 2064static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 2065 uint32_t pri_val)
cca32e9a 2066{
c35426d2 2067 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 2068 return 0;
2069
23297044 2070 return ilk_wm_fbc(pri_val,
c35426d2
VS		 2071 params->pri.horiz_pixels,
2072 params->pri.bytes_per_pixel);
cca32e9a
PZ		 2073}
2074
158ae64f
VS		 2075static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2076{
416f4727
VS		 2077 if (INTEL_INFO(dev)->gen >= 8)
2078 return 3072;
2079 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 2080 return 768;
2081 else
2082 return 512;
2083}
2084
4e975081
VS		 2085static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
2086 int level, bool is_sprite)
2087{
2088 if (INTEL_INFO(dev)->gen >= 8)
2089 /* BDW primary/sprite plane watermarks */
2090 return level == 0 ? 255 : 2047;
2091 else if (INTEL_INFO(dev)->gen >= 7)
2092 /* IVB/HSW primary/sprite plane watermarks */
2093 return level == 0 ? 127 : 1023;
2094 else if (!is_sprite)
2095 /* ILK/SNB primary plane watermarks */
2096 return level == 0 ? 127 : 511;
2097 else
2098 /* ILK/SNB sprite plane watermarks */
2099 return level == 0 ? 63 : 255;
2100}
2101
2102static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
2103 int level)
2104{
2105 if (INTEL_INFO(dev)->gen >= 7)
2106 return level == 0 ? 63 : 255;
2107 else
2108 return level == 0 ? 31 : 63;
2109}
2110
2111static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
2112{
2113 if (INTEL_INFO(dev)->gen >= 8)
2114 return 31;
2115 else
2116 return 15;
2117}
2118
158ae64f
VS		 2119/* Calculate the maximum primary/sprite plane watermark */
2120static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2121 int level,
240264f4 2122 const struct intel_wm_config *config,
158ae64f
VS		 2123 enum intel_ddb_partitioning ddb_partitioning,
2124 bool is_sprite)
2125{
2126 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 2127
2128 /* if sprites aren't enabled, sprites get nothing */
240264f4 2129 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 2130 return 0;
2131
2132 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 2133 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 2134 fifo_size /= INTEL_INFO(dev)->num_pipes;
2135
2136 /*
2137 * For some reason the non self refresh
2138 * FIFO size is only half of the self
2139 * refresh FIFO size on ILK/SNB.
2140 */
2141 if (INTEL_INFO(dev)->gen <= 6)
2142 fifo_size /= 2;
2143 }
2144
240264f4 2145 if (config->sprites_enabled) {
158ae64f
VS		 2146 /* level 0 is always calculated with 1:1 split */
2147 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2148 if (is_sprite)
2149 fifo_size *= 5;
2150 fifo_size /= 6;
2151 } else {
2152 fifo_size /= 2;
2153 }
2154 }
2155
2156 /* clamp to max that the registers can hold */
4e975081 2157 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 2158}
2159
2160/* Calculate the maximum cursor plane watermark */
2161static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 2162 int level,
2163 const struct intel_wm_config *config)
158ae64f
VS		 2164{
2165 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 2166 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 2167 return 64;
2168
2169 /* otherwise just report max that registers can hold */
4e975081 2170 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 2171}
2172
d34ff9c6 2173static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 2174 int level,
2175 const struct intel_wm_config *config,
2176 enum intel_ddb_partitioning ddb_partitioning,
820c1980 2177 struct ilk_wm_maximums *max)
158ae64f 2178{
240264f4
VS		 2179 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2180 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2181 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 2182 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 2183}
2184
a3cb4048
VS		 2185static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2186 int level,
2187 struct ilk_wm_maximums *max)
2188{
2189 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2190 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2191 max->cur = ilk_cursor_wm_reg_max(dev, level);
2192 max->fbc = ilk_fbc_wm_reg_max(dev);
2193}
2194
d9395655 2195static bool ilk_validate_wm_level(int level,
820c1980 2196 const struct ilk_wm_maximums *max,
d9395655 2197 struct intel_wm_level *result)
a9786a11
VS		 2198{
2199 bool ret;
2200
2201 /* already determined to be invalid? */
2202 if (!result->enable)
2203 return false;
2204
2205 result->enable = result->pri_val <= max->pri &&
2206 result->spr_val <= max->spr &&
2207 result->cur_val <= max->cur;
2208
2209 ret = result->enable;
2210
2211 /*
2212 * HACK until we can pre-compute everything,
2213 * and thus fail gracefully if LP0 watermarks
2214 * are exceeded...
2215 */
2216 if (level == 0 && !result->enable) {
2217 if (result->pri_val > max->pri)
2218 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2219 level, result->pri_val, max->pri);
2220 if (result->spr_val > max->spr)
2221 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2222 level, result->spr_val, max->spr);
2223 if (result->cur_val > max->cur)
2224 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2225 level, result->cur_val, max->cur);
2226
2227 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2228 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2229 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2230 result->enable = true;
2231 }
2232
a9786a11
VS		 2233 return ret;
2234}
2235
d34ff9c6 2236static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 2237 int level,
820c1980 2238 const struct ilk_pipe_wm_parameters *p,
1fd527cc 2239 struct intel_wm_level *result)
6f5ddd17
VS		 2240{
2241 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2242 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2243 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2244
2245 /* WM1+ latency values stored in 0.5us units */
2246 if (level > 0) {
2247 pri_latency *= 5;
2248 spr_latency *= 5;
2249 cur_latency *= 5;
2250 }
2251
2252 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2253 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2254 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2255 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2256 result->enable = true;
2257}
2258
801bcfff
PZ		 2259static uint32_t
2260hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2261{
2262 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2264 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2265 u32 linetime, ips_linetime;
1f8eeabf 2266
801bcfff
PZ		 2267 if (!intel_crtc_active(crtc))
2268 return 0;
1011d8c4 2269
1f8eeabf
ED		 2270 /* The WM are computed with base on how long it takes to fill a single
2271 * row at the given clock rate, multiplied by 8.
2272 * */
fec8cba3
JB		 2273 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2274 mode->crtc_clock);
2275 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 2276 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2277
801bcfff
PZ		 2278 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2279 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2280}
2281
2af30a5c 2282static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2283{
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285
2af30a5c
PB		 2286 if (IS_GEN9(dev)) {
2287 uint32_t val;
4f947386 2288 int ret, i;
367294be 2289 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2290
2291 /* read the first set of memory latencies[0:3] */
2292 val = 0; /* data0 to be programmed to 0 for first set */
2293 mutex_lock(&dev_priv->rps.hw_lock);
2294 ret = sandybridge_pcode_read(dev_priv,
2295 GEN9_PCODE_READ_MEM_LATENCY,
2296 &val);
2297 mutex_unlock(&dev_priv->rps.hw_lock);
2298
2299 if (ret) {
2300 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2301 return;
2302 }
2303
2304 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2305 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2306 GEN9_MEM_LATENCY_LEVEL_MASK;
2307 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2308 GEN9_MEM_LATENCY_LEVEL_MASK;
2309 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2310 GEN9_MEM_LATENCY_LEVEL_MASK;
2311
2312 /* read the second set of memory latencies[4:7] */
2313 val = 1; /* data0 to be programmed to 1 for second set */
2314 mutex_lock(&dev_priv->rps.hw_lock);
2315 ret = sandybridge_pcode_read(dev_priv,
2316 GEN9_PCODE_READ_MEM_LATENCY,
2317 &val);
2318 mutex_unlock(&dev_priv->rps.hw_lock);
2319 if (ret) {
2320 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2321 return;
2322 }
2323
2324 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2325 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2326 GEN9_MEM_LATENCY_LEVEL_MASK;
2327 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2328 GEN9_MEM_LATENCY_LEVEL_MASK;
2329 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2330 GEN9_MEM_LATENCY_LEVEL_MASK;
2331
367294be
VK		 2332 /*
2333 * punit doesn't take into account the read latency so we need
2334 * to add 2us to the various latency levels we retrieve from
2335 * the punit.
2336 * - W0 is a bit special in that it's the only level that
2337 * can't be disabled if we want to have display working, so
2338 * we always add 2us there.
2339 * - For levels >=1, punit returns 0us latency when they are
2340 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2341 *
2342 * Additionally, if a level n (n > 1) has a 0us latency, all
2343 * levels m (m >= n) need to be disabled. We make sure to
2344 * sanitize the values out of the punit to satisfy this
2345 * requirement.
367294be
VK		 2346 */
2347 wm[0] += 2;
2348 for (level = 1; level <= max_level; level++)
2349 if (wm[level] != 0)
2350 wm[level] += 2;
4f947386
VK		 2351 else {
2352 for (i = level + 1; i <= max_level; i++)
2353 wm[i] = 0;
367294be 2354
4f947386
VK		 2355 break;
2356 }
2af30a5c 2357 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2358 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2359
2360 wm[0] = (sskpd >> 56) & 0xFF;
2361 if (wm[0] == 0)
2362 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2363 wm[1] = (sskpd >> 4) & 0xFF;
2364 wm[2] = (sskpd >> 12) & 0xFF;
2365 wm[3] = (sskpd >> 20) & 0x1FF;
2366 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2367 } else if (INTEL_INFO(dev)->gen >= 6) {
2368 uint32_t sskpd = I915_READ(MCH_SSKPD);
2369
2370 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2371 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2372 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2373 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2374 } else if (INTEL_INFO(dev)->gen >= 5) {
2375 uint32_t mltr = I915_READ(MLTR_ILK);
2376
2377 /* ILK primary LP0 latency is 700 ns */
2378 wm[0] = 7;
2379 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2380 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2381 }
2382}
2383
53615a5e
VS		 2384static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2385{
2386 /* ILK sprite LP0 latency is 1300 ns */
2387 if (INTEL_INFO(dev)->gen == 5)
2388 wm[0] = 13;
2389}
2390
2391static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2392{
2393 /* ILK cursor LP0 latency is 1300 ns */
2394 if (INTEL_INFO(dev)->gen == 5)
2395 wm[0] = 13;
2396
2397 /* WaDoubleCursorLP3Latency:ivb */
2398 if (IS_IVYBRIDGE(dev))
2399 wm[3] *= 2;
2400}
2401
546c81fd 2402int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2403{
26ec971e 2404 /* how many WM levels are we expecting */
2af30a5c
PB		 2405 if (IS_GEN9(dev))
2406 return 7;
2407 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2408 return 4;
26ec971e 2409 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2410 return 3;
26ec971e 2411 else
ad0d6dc4
VS		 2412 return 2;
2413}
7526ed79 2414
ad0d6dc4
VS		 2415static void intel_print_wm_latency(struct drm_device *dev,
2416 const char *name,
2af30a5c 2417 const uint16_t wm[8])
ad0d6dc4
VS		 2418{
2419 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2420
2421 for (level = 0; level <= max_level; level++) {
2422 unsigned int latency = wm[level];
2423
2424 if (latency == 0) {
2425 DRM_ERROR("%s WM%d latency not provided\n",
2426 name, level);
2427 continue;
2428 }
2429
2af30a5c
PB		 2430 /*
2431 * - latencies are in us on gen9.
2432 * - before then, WM1+ latency values are in 0.5us units
2433 */
2434 if (IS_GEN9(dev))
2435 latency *= 10;
2436 else if (level > 0)
26ec971e
VS		 2437 latency *= 5;
2438
2439 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2440 name, level, wm[level],
2441 latency / 10, latency % 10);
2442 }
2443}
2444
e95a2f75
VS		 2445static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2446 uint16_t wm[5], uint16_t min)
2447{
2448 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2449
2450 if (wm[0] >= min)
2451 return false;
2452
2453 wm[0] = max(wm[0], min);
2454 for (level = 1; level <= max_level; level++)
2455 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2456
2457 return true;
2458}
2459
2460static void snb_wm_latency_quirk(struct drm_device *dev)
2461{
2462 struct drm_i915_private *dev_priv = dev->dev_private;
2463 bool changed;
2464
2465 /*
2466 * The BIOS provided WM memory latency values are often
2467 * inadequate for high resolution displays. Adjust them.
2468 */
2469 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2470 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2471 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2472
2473 if (!changed)
2474 return;
2475
2476 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2477 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2478 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2479 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2480}
2481
fa50ad61 2482static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2483{
2484 struct drm_i915_private *dev_priv = dev->dev_private;
2485
2486 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2487
2488 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2489 sizeof(dev_priv->wm.pri_latency));
2490 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2491 sizeof(dev_priv->wm.pri_latency));
2492
2493 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2494 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2495
2496 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2497 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2498 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2499
2500 if (IS_GEN6(dev))
2501 snb_wm_latency_quirk(dev);
53615a5e
VS		 2502}
2503
2af30a5c
PB		 2504static void skl_setup_wm_latency(struct drm_device *dev)
2505{
2506 struct drm_i915_private *dev_priv = dev->dev_private;
2507
2508 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2509 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2510}
2511
820c1980 2512static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2513 struct ilk_pipe_wm_parameters *p)
1011d8c4 2514{
7c4a395f
VS		 2515 struct drm_device *dev = crtc->dev;
2516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2517 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2518 struct drm_plane *plane;
1011d8c4 2519
2a44b76b
VS		 2520 if (!intel_crtc_active(crtc))
2521 return;
801bcfff 2522
2a44b76b
VS		 2523 p->active = true;
2524 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2525 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2526 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2527 p->cur.bytes_per_pixel = 4;
2528 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2529 p->cur.horiz_pixels = intel_crtc->cursor_width;
2530 /* TODO: for now, assume primary and cursor planes are always enabled. */
2531 p->pri.enabled = true;
2532 p->cur.enabled = true;
7c4a395f 2533
af2b653b 2534 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2535 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2536
2a44b76b 2537 if (intel_plane->pipe == pipe) {
7c4a395f 2538 p->spr = intel_plane->wm;
2a44b76b
VS		 2539 break;
2540 }
2541 }
2542}
2543
2544static void ilk_compute_wm_config(struct drm_device *dev,
2545 struct intel_wm_config *config)
2546{
2547 struct intel_crtc *intel_crtc;
2548
2549 /* Compute the currently _active_ config */
d3fcc808 2550 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2551 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2552
2a44b76b
VS		 2553 if (!wm->pipe_enabled)
2554 continue;
cca32e9a 2555
2a44b76b
VS		 2556 config->sprites_enabled |= wm->sprites_enabled;
2557 config->sprites_scaled |= wm->sprites_scaled;
2558 config->num_pipes_active++;
cca32e9a 2559 }
801bcfff
PZ		 2560}
2561
0b2ae6d7
VS		 2562/* Compute new watermarks for the pipe */
2563static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2564 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2565 struct intel_pipe_wm *pipe_wm)
2566{
2567 struct drm_device *dev = crtc->dev;
d34ff9c6 2568 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2569 int level, max_level = ilk_wm_max_level(dev);
2570 /* LP0 watermark maximums depend on this pipe alone */
2571 struct intel_wm_config config = {
2572 .num_pipes_active = 1,
2573 .sprites_enabled = params->spr.enabled,
2574 .sprites_scaled = params->spr.scaled,
2575 };
820c1980 2576 struct ilk_wm_maximums max;
0b2ae6d7 2577
2a44b76b
VS		 2578 pipe_wm->pipe_enabled = params->active;
2579 pipe_wm->sprites_enabled = params->spr.enabled;
2580 pipe_wm->sprites_scaled = params->spr.scaled;
2581
7b39a0b7
VS		 2582 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2583 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2584 max_level = 1;
2585
2586 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2587 if (params->spr.scaled)
2588 max_level = 0;
2589
a3cb4048 2590 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2591
a42a5719 2592 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2593 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2594
a3cb4048
VS		 2595 /* LP0 watermarks always use 1/2 DDB partitioning */
2596 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2597
0b2ae6d7 2598 /* At least LP0 must be valid */
a3cb4048
VS		 2599 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2600 return false;
2601
2602 ilk_compute_wm_reg_maximums(dev, 1, &max);
2603
2604 for (level = 1; level <= max_level; level++) {
2605 struct intel_wm_level wm = {};
2606
2607 ilk_compute_wm_level(dev_priv, level, params, &wm);
2608
2609 /*
2610 * Disable any watermark level that exceeds the
2611 * register maximums since such watermarks are
2612 * always invalid.
2613 */
2614 if (!ilk_validate_wm_level(level, &max, &wm))
2615 break;
2616
2617 pipe_wm->wm[level] = wm;
2618 }
2619
2620 return true;
0b2ae6d7
VS		 2621}
2622
2623/*
2624 * Merge the watermarks from all active pipes for a specific level.
2625 */
2626static void ilk_merge_wm_level(struct drm_device *dev,
2627 int level,
2628 struct intel_wm_level *ret_wm)
2629{
2630 const struct intel_crtc *intel_crtc;
2631
d52fea5b
VS		 2632 ret_wm->enable = true;
2633
d3fcc808 2634 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2635 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2636 const struct intel_wm_level *wm = &active->wm[level];
2637
2638 if (!active->pipe_enabled)
2639 continue;
0b2ae6d7 2640
d52fea5b
VS		 2641 /*
2642 * The watermark values may have been used in the past,
2643 * so we must maintain them in the registers for some
2644 * time even if the level is now disabled.
2645 */
0b2ae6d7 2646 if (!wm->enable)
d52fea5b 2647 ret_wm->enable = false;
0b2ae6d7
VS		 2648
2649 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2650 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2651 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2652 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2653 }
0b2ae6d7
VS		 2654}
2655
2656/*
2657 * Merge all low power watermarks for all active pipes.
2658 */
2659static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2660 const struct intel_wm_config *config,
820c1980 2661 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2662 struct intel_pipe_wm *merged)
2663{
2664 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2665 int last_enabled_level = max_level;
0b2ae6d7 2666
0ba22e26
VS		 2667 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2668 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2669 config->num_pipes_active > 1)
2670 return;
2671
6c8b6c28
VS		 2672 /* ILK: FBC WM must be disabled always */
2673 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2674
2675 /* merge each WM1+ level */
2676 for (level = 1; level <= max_level; level++) {
2677 struct intel_wm_level *wm = &merged->wm[level];
2678
2679 ilk_merge_wm_level(dev, level, wm);
2680
d52fea5b
VS		 2681 if (level > last_enabled_level)
2682 wm->enable = false;
2683 else if (!ilk_validate_wm_level(level, max, wm))
2684 /* make sure all following levels get disabled */
2685 last_enabled_level = level - 1;
0b2ae6d7
VS		 2686
2687 /*
2688 * The spec says it is preferred to disable
2689 * FBC WMs instead of disabling a WM level.
2690 */
2691 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2692 if (wm->enable)
2693 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2694 wm->fbc_val = 0;
2695 }
2696 }
6c8b6c28
VS		 2697
2698 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2699 /*
2700 * FIXME this is racy. FBC might get enabled later.
2701 * What we should check here is whether FBC can be
2702 * enabled sometime later.
2703 */
2704 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2705 for (level = 2; level <= max_level; level++) {
2706 struct intel_wm_level *wm = &merged->wm[level];
2707
2708 wm->enable = false;
2709 }
2710 }
0b2ae6d7
VS		 2711}
2712
b380ca3c
VS		 2713static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2714{
2715 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2716 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2717}
2718
a68d68ee
VS		 2719/* The value we need to program into the WM_LPx latency field */
2720static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2721{
2722 struct drm_i915_private *dev_priv = dev->dev_private;
2723
a42a5719 2724 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2725 return 2 * level;
2726 else
2727 return dev_priv->wm.pri_latency[level];
2728}
2729
820c1980 2730static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2731 const struct intel_pipe_wm *merged,
609cedef 2732 enum intel_ddb_partitioning partitioning,
820c1980 2733 struct ilk_wm_values *results)
801bcfff 2734{
0b2ae6d7
VS		 2735 struct intel_crtc *intel_crtc;
2736 int level, wm_lp;
cca32e9a 2737
0362c781 2738 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2739 results->partitioning = partitioning;
cca32e9a 2740
0b2ae6d7 2741 /* LP1+ register values */
cca32e9a 2742 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2743 const struct intel_wm_level *r;
801bcfff 2744
b380ca3c 2745 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2746
0362c781 2747 r = &merged->wm[level];
cca32e9a 2748
d52fea5b
VS		 2749 /*
2750 * Maintain the watermark values even if the level is
2751 * disabled. Doing otherwise could cause underruns.
2752 */
2753 results->wm_lp[wm_lp - 1] =
a68d68ee 2754 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2755 (r->pri_val << WM1_LP_SR_SHIFT) |
2756 r->cur_val;
2757
d52fea5b
VS		 2758 if (r->enable)
2759 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2760
416f4727
VS		 2761 if (INTEL_INFO(dev)->gen >= 8)
2762 results->wm_lp[wm_lp - 1] |=
2763 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2764 else
2765 results->wm_lp[wm_lp - 1] |=
2766 r->fbc_val << WM1_LP_FBC_SHIFT;
2767
d52fea5b
VS		 2768 /*
2769 * Always set WM1S_LP_EN when spr_val != 0, even if the
2770 * level is disabled. Doing otherwise could cause underruns.
2771 */
6cef2b8a
VS		 2772 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2773 WARN_ON(wm_lp != 1);
2774 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2775 } else
2776 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2777 }
801bcfff 2778
0b2ae6d7 2779 /* LP0 register values */
d3fcc808 2780 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2781 enum pipe pipe = intel_crtc->pipe;
2782 const struct intel_wm_level *r =
2783 &intel_crtc->wm.active.wm[0];
2784
2785 if (WARN_ON(!r->enable))
2786 continue;
2787
2788 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2789
0b2ae6d7
VS		 2790 results->wm_pipe[pipe] =
2791 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2792 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2793 r->cur_val;
801bcfff
PZ		 2794 }
2795}
2796
861f3389
PZ		 2797/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2798 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2799static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2800 struct intel_pipe_wm *r1,
2801 struct intel_pipe_wm *r2)
861f3389 2802{
198a1e9b
VS		 2803 int level, max_level = ilk_wm_max_level(dev);
2804 int level1 = 0, level2 = 0;
861f3389 2805
198a1e9b
VS		 2806 for (level = 1; level <= max_level; level++) {
2807 if (r1->wm[level].enable)
2808 level1 = level;
2809 if (r2->wm[level].enable)
2810 level2 = level;
861f3389
PZ		 2811 }
2812
198a1e9b
VS		 2813 if (level1 == level2) {
2814 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2815 return r2;
2816 else
2817 return r1;
198a1e9b 2818 } else if (level1 > level2) {
861f3389
PZ		 2819 return r1;
2820 } else {
2821 return r2;
2822 }
2823}
2824
49a687c4
VS		 2825/* dirty bits used to track which watermarks need changes */
2826#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2827#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2828#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2829#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2830#define WM_DIRTY_FBC (1 << 24)
2831#define WM_DIRTY_DDB (1 << 25)
2832
055e393f 2833static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2834 const struct ilk_wm_values *old,
2835 const struct ilk_wm_values *new)
49a687c4
VS		 2836{
2837 unsigned int dirty = 0;
2838 enum pipe pipe;
2839 int wm_lp;
2840
055e393f 2841 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2842 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2843 dirty |= WM_DIRTY_LINETIME(pipe);
2844 /* Must disable LP1+ watermarks too */
2845 dirty |= WM_DIRTY_LP_ALL;
2846 }
2847
2848 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2849 dirty |= WM_DIRTY_PIPE(pipe);
2850 /* Must disable LP1+ watermarks too */
2851 dirty |= WM_DIRTY_LP_ALL;
2852 }
2853 }
2854
2855 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2856 dirty |= WM_DIRTY_FBC;
2857 /* Must disable LP1+ watermarks too */
2858 dirty |= WM_DIRTY_LP_ALL;
2859 }
2860
2861 if (old->partitioning != new->partitioning) {
2862 dirty |= WM_DIRTY_DDB;
2863 /* Must disable LP1+ watermarks too */
2864 dirty |= WM_DIRTY_LP_ALL;
2865 }
2866
2867 /* LP1+ watermarks already deemed dirty, no need to continue */
2868 if (dirty & WM_DIRTY_LP_ALL)
2869 return dirty;
2870
2871 /* Find the lowest numbered LP1+ watermark in need of an update... */
2872 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2873 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2874 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2875 break;
2876 }
2877
2878 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2879 for (; wm_lp <= 3; wm_lp++)
2880 dirty |= WM_DIRTY_LP(wm_lp);
2881
2882 return dirty;
2883}
2884
8553c18e
VS		 2885static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2886 unsigned int dirty)
801bcfff 2887{
820c1980 2888 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2889 bool changed = false;
801bcfff 2890
facd619b
VS		 2891 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2892 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2893 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2894 changed = true;
facd619b
VS		 2895 }
2896 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2897 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2898 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2899 changed = true;
facd619b
VS		 2900 }
2901 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2902 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2903 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2904 changed = true;
facd619b 2905 }
801bcfff 2906
facd619b
VS		 2907 /*
2908 * Don't touch WM1S_LP_EN here.
2909 * Doing so could cause underruns.
2910 */
6cef2b8a 2911
8553c18e
VS		 2912 return changed;
2913}
2914
2915/*
2916 * The spec says we shouldn't write when we don't need, because every write
2917 * causes WMs to be re-evaluated, expending some power.
2918 */
820c1980
ID		 2919static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2920 struct ilk_wm_values *results)
8553c18e
VS		 2921{
2922 struct drm_device *dev = dev_priv->dev;
820c1980 2923 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2924 unsigned int dirty;
2925 uint32_t val;
2926
055e393f 2927 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2928 if (!dirty)
2929 return;
2930
2931 _ilk_disable_lp_wm(dev_priv, dirty);
2932
49a687c4 2933 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2934 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2935 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2936 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2937 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2938 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2939
49a687c4 2940 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2941 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2942 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2943 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2944 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2945 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2946
49a687c4 2947 if (dirty & WM_DIRTY_DDB) {
a42a5719 2948 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2949 val = I915_READ(WM_MISC);
2950 if (results->partitioning == INTEL_DDB_PART_1_2)
2951 val &= ~WM_MISC_DATA_PARTITION_5_6;
2952 else
2953 val |= WM_MISC_DATA_PARTITION_5_6;
2954 I915_WRITE(WM_MISC, val);
2955 } else {
2956 val = I915_READ(DISP_ARB_CTL2);
2957 if (results->partitioning == INTEL_DDB_PART_1_2)
2958 val &= ~DISP_DATA_PARTITION_5_6;
2959 else
2960 val |= DISP_DATA_PARTITION_5_6;
2961 I915_WRITE(DISP_ARB_CTL2, val);
2962 }
1011d8c4
PZ		 2963 }
2964
49a687c4 2965 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2966 val = I915_READ(DISP_ARB_CTL);
2967 if (results->enable_fbc_wm)
2968 val &= ~DISP_FBC_WM_DIS;
2969 else
2970 val |= DISP_FBC_WM_DIS;
2971 I915_WRITE(DISP_ARB_CTL, val);
2972 }
2973
954911eb
ID		 2974 if (dirty & WM_DIRTY_LP(1) &&
2975 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2976 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2977
2978 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2979 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2980 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2981 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2982 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2983 }
801bcfff 2984
facd619b 2985 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2986 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2987 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2988 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2989 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2990 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2991
2992 dev_priv->wm.hw = *results;
801bcfff
PZ		 2993}
2994
8553c18e
VS		 2995static bool ilk_disable_lp_wm(struct drm_device *dev)
2996{
2997 struct drm_i915_private *dev_priv = dev->dev_private;
2998
2999 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
3000}
3001
b9cec075
DL		 3002/*
3003 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
3004 * different active planes.
3005 */
3006
3007#define SKL_DDB_SIZE 896 /* in blocks */
3008
3009static void
3010skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3011 struct drm_crtc *for_crtc,
3012 const struct intel_wm_config *config,
3013 const struct skl_pipe_wm_parameters *params,
3014 struct skl_ddb_entry *alloc /* out */)
3015{
3016 struct drm_crtc *crtc;
3017 unsigned int pipe_size, ddb_size;
3018 int nth_active_pipe;
3019
3020 if (!params->active) {
3021 alloc->start = 0;
3022 alloc->end = 0;
3023 return;
3024 }
3025
3026 ddb_size = SKL_DDB_SIZE;
3027
3028 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3029
3030 nth_active_pipe = 0;
3031 for_each_crtc(dev, crtc) {
3032 if (!intel_crtc_active(crtc))
3033 continue;
3034
3035 if (crtc == for_crtc)
3036 break;
3037
3038 nth_active_pipe++;
3039 }
3040
3041 pipe_size = ddb_size / config->num_pipes_active;
3042 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 3043 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3044}
3045
3046static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
3047{
3048 if (config->num_pipes_active == 1)
3049 return 32;
3050
3051 return 8;
3052}
3053
a269c583
DL		 3054static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3055{
3056 entry->start = reg & 0x3ff;
3057 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3058 if (entry->end)
3059 entry->end += 1;
a269c583
DL		 3060}
3061
08db6652
DL		 3062void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3063 struct skl_ddb_allocation *ddb /* out */)
a269c583
DL		 3064{
3065 struct drm_device *dev = dev_priv->dev;
3066 enum pipe pipe;
3067 int plane;
3068 u32 val;
3069
3070 for_each_pipe(dev_priv, pipe) {
3071 for_each_plane(pipe, plane) {
3072 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3073 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3074 val);
3075 }
3076
3077 val = I915_READ(CUR_BUF_CFG(pipe));
3078 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
3079 }
3080}
3081
b9cec075
DL		 3082static unsigned int
3083skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p)
3084{
3085 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
3086}
3087
3088/*
3089 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3090 * a 8192x4096@32bpp framebuffer:
3091 * 3 * 4096 * 8192 * 4 < 2^32
3092 */
3093static unsigned int
3094skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
3095 const struct skl_pipe_wm_parameters *params)
3096{
3097 unsigned int total_data_rate = 0;
3098 int plane;
3099
3100 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3101 const struct intel_plane_wm_parameters *p;
3102
3103 p = &params->plane[plane];
3104 if (!p->enabled)
3105 continue;
3106
3107 total_data_rate += skl_plane_relative_data_rate(p);
3108 }
3109
3110 return total_data_rate;
3111}
3112
3113static void
3114skl_allocate_pipe_ddb(struct drm_crtc *crtc,
3115 const struct intel_wm_config *config,
3116 const struct skl_pipe_wm_parameters *params,
3117 struct skl_ddb_allocation *ddb /* out */)
3118{
3119 struct drm_device *dev = crtc->dev;
3120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3121 enum pipe pipe = intel_crtc->pipe;
3122 struct skl_ddb_entry alloc;
3123 uint16_t alloc_size, start, cursor_blocks;
3124 unsigned int total_data_rate;
3125 int plane;
3126
3127 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, &alloc);
3128 alloc_size = skl_ddb_entry_size(&alloc);
3129 if (alloc_size == 0) {
3130 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3131 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
3132 return;
3133 }
3134
3135 cursor_blocks = skl_cursor_allocation(config);
16160e3d 3136 ddb->cursor[pipe].start = alloc.end - cursor_blocks;
b9cec075
DL		 3137 ddb->cursor[pipe].end = alloc.end;
3138
3139 alloc_size -= cursor_blocks;
3140 alloc.end -= cursor_blocks;
3141
3142 /*
3143 * Each active plane get a portion of the remaining space, in
3144 * proportion to the amount of data they need to fetch from memory.
3145 *
3146 * FIXME: we may not allocate every single block here.
3147 */
3148 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
3149
3150 start = alloc.start;
3151 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3152 const struct intel_plane_wm_parameters *p;
3153 unsigned int data_rate;
3154 uint16_t plane_blocks;
3155
3156 p = &params->plane[plane];
3157 if (!p->enabled)
3158 continue;
3159
3160 data_rate = skl_plane_relative_data_rate(p);
3161
3162 /*
3163 * promote the expression to 64 bits to avoid overflowing, the
3164 * result is < available as data_rate / total_data_rate < 1
3165 */
3166 plane_blocks = div_u64((uint64_t)alloc_size * data_rate,
3167 total_data_rate);
3168
3169 ddb->plane[pipe][plane].start = start;
16160e3d 3170 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL		 3171
3172 start += plane_blocks;
3173 }
3174
3175}
3176
2d41c0b5
PB		 3177static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_config *config)
3178{
3179 /* TODO: Take into account the scalers once we support them */
3180 return config->adjusted_mode.crtc_clock;
3181}
3182
3183/*
3184 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3185 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3186 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3187 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3188*/
3189static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3190 uint32_t latency)
3191{
3192 uint32_t wm_intermediate_val, ret;
3193
3194 if (latency == 0)
3195 return UINT_MAX;
3196
3197 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel;
3198 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3199
3200 return ret;
3201}
3202
3203static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3204 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3205 uint32_t latency)
3206{
3207 uint32_t ret, plane_bytes_per_line, wm_intermediate_val;
3208
3209 if (latency == 0)
3210 return UINT_MAX;
3211
3212 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3213 wm_intermediate_val = latency * pixel_rate;
3214 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3215 plane_bytes_per_line;
3216
3217 return ret;
3218}
3219
3220static void skl_compute_transition_wm(struct drm_crtc *crtc,
3221 struct skl_pipe_wm_parameters *params,
3222 struct skl_pipe_wm *pipe_wm)
3223{
3224 /*
3225 * For now it is suggested to use the LP0 wm val of corresponding
3226 * plane as transition wm val. This is done while computing results.
3227 */
3228 if (!params->active)
3229 return;
3230}
3231
3232static uint32_t
3233skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3234{
3235 if (!intel_crtc_active(crtc))
3236 return 0;
3237
3238 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3239
3240}
3241
3242static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3243 const struct intel_crtc *intel_crtc)
3244{
3245 struct drm_device *dev = intel_crtc->base.dev;
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3248 enum pipe pipe = intel_crtc->pipe;
3249
3250 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3251 sizeof(new_ddb->plane[pipe])))
3252 return true;
3253
3254 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
3255 sizeof(new_ddb->cursor[pipe])))
3256 return true;
3257
3258 return false;
3259}
3260
3261static void skl_compute_wm_global_parameters(struct drm_device *dev,
3262 struct intel_wm_config *config)
3263{
3264 struct drm_crtc *crtc;
3265 struct drm_plane *plane;
3266
3267 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3268 config->num_pipes_active += intel_crtc_active(crtc);
3269
3270 /* FIXME: I don't think we need those two global parameters on SKL */
3271 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3272 struct intel_plane *intel_plane = to_intel_plane(plane);
3273
3274 config->sprites_enabled |= intel_plane->wm.enabled;
3275 config->sprites_scaled |= intel_plane->wm.scaled;
3276 }
3277}
3278
3279static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3280 struct skl_pipe_wm_parameters *p)
3281{
3282 struct drm_device *dev = crtc->dev;
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284 enum pipe pipe = intel_crtc->pipe;
3285 struct drm_plane *plane;
3286 int i = 1; /* Index for sprite planes start */
3287
3288 p->active = intel_crtc_active(crtc);
3289 if (p->active) {
3290 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
3291 p->pixel_rate = skl_pipe_pixel_rate(&intel_crtc->config);
3292
3293 /*
3294 * For now, assume primary and cursor planes are always enabled.
3295 */
3296 p->plane[0].enabled = true;
3297 p->plane[0].bytes_per_pixel =
3298 crtc->primary->fb->bits_per_pixel / 8;
3299 p->plane[0].horiz_pixels = intel_crtc->config.pipe_src_w;
3300 p->plane[0].vert_pixels = intel_crtc->config.pipe_src_h;
3301
3302 p->cursor.enabled = true;
3303 p->cursor.bytes_per_pixel = 4;
3304 p->cursor.horiz_pixels = intel_crtc->cursor_width ?
3305 intel_crtc->cursor_width : 64;
3306 }
3307
3308 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3309 struct intel_plane *intel_plane = to_intel_plane(plane);
3310
3311 if (intel_plane->pipe == pipe)
3312 p->plane[i++] = intel_plane->wm;
3313 }
3314}
3315
3316static bool skl_compute_plane_wm(struct skl_pipe_wm_parameters *p,
3317 struct intel_plane_wm_parameters *p_params,
21fca258 3318 uint16_t ddb_allocation,
2d41c0b5 3319 uint32_t mem_value,
e6d66171
DL		 3320 uint16_t *out_blocks, /* out */
3321 uint8_t *out_lines /* out */)
2d41c0b5 3322{
e6d66171 3323 uint32_t method1, method2, plane_bytes_per_line, res_blocks, res_lines;
2d41c0b5
PB		 3324 uint32_t result_bytes;
3325
4f947386 3326 if (mem_value == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB		 3327 return false;
3328
3329 method1 = skl_wm_method1(p->pixel_rate,
3330 p_params->bytes_per_pixel,
3331 mem_value);
3332 method2 = skl_wm_method2(p->pixel_rate,
3333 p->pipe_htotal,
3334 p_params->horiz_pixels,
3335 p_params->bytes_per_pixel,
3336 mem_value);
3337
3338 plane_bytes_per_line = p_params->horiz_pixels *
3339 p_params->bytes_per_pixel;
3340
3341 /* For now xtile and linear */
21fca258 3342 if (((ddb_allocation * 512) / plane_bytes_per_line) >= 1)
2d41c0b5
PB		 3343 result_bytes = min(method1, method2);
3344 else
3345 result_bytes = method1;
3346
e6d66171
DL		 3347 res_blocks = DIV_ROUND_UP(result_bytes, 512) + 1;
3348 res_lines = DIV_ROUND_UP(result_bytes, plane_bytes_per_line);
3349
3350 if (res_blocks > ddb_allocation || res_lines > 31)
3351 return false;
3352
3353 *out_blocks = res_blocks;
3354 *out_lines = res_lines;
2d41c0b5
PB		 3355
3356 return true;
3357}
3358
3359static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3360 struct skl_ddb_allocation *ddb,
3361 struct skl_pipe_wm_parameters *p,
3362 enum pipe pipe,
3363 int level,
3364 int num_planes,
3365 struct skl_wm_level *result)
3366{
3367 uint16_t latency = dev_priv->wm.skl_latency[level];
3368 uint16_t ddb_blocks;
3369 int i;
3370
3371 for (i = 0; i < num_planes; i++) {
3372 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3373
3374 result->plane_en[i] = skl_compute_plane_wm(p, &p->plane[i],
3375 ddb_blocks,
3376 latency,
3377 &result->plane_res_b[i],
3378 &result->plane_res_l[i]);
3379 }
3380
3381 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
3382 result->cursor_en = skl_compute_plane_wm(p, &p->cursor, ddb_blocks,
3383 latency, &result->cursor_res_b,
3384 &result->cursor_res_l);
3385}
3386
3387static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3388 struct skl_ddb_allocation *ddb,
3389 struct skl_pipe_wm_parameters *params,
3390 struct skl_pipe_wm *pipe_wm)
3391{
3392 struct drm_device *dev = crtc->dev;
3393 const struct drm_i915_private *dev_priv = dev->dev_private;
3394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3395 int level, max_level = ilk_wm_max_level(dev);
3396
3397 for (level = 0; level <= max_level; level++) {
3398 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3399 level, intel_num_planes(intel_crtc),
3400 &pipe_wm->wm[level]);
3401 }
3402 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3403
3404 skl_compute_transition_wm(crtc, params, pipe_wm);
3405}
3406
3407static void skl_compute_wm_results(struct drm_device *dev,
3408 struct skl_pipe_wm_parameters *p,
3409 struct skl_pipe_wm *p_wm,
3410 struct skl_wm_values *r,
3411 struct intel_crtc *intel_crtc)
3412{
3413 int level, max_level = ilk_wm_max_level(dev);
3414 enum pipe pipe = intel_crtc->pipe;
3415
3416 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3417 uint32_t temp;
3418 int i;
3419
3420 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3421 temp = 0;
2d41c0b5
PB		 3422
3423 temp |= p_wm->wm[level].plane_res_l[i] <<
3424 PLANE_WM_LINES_SHIFT;
3425 temp |= p_wm->wm[level].plane_res_b[i];
3426 if (p_wm->wm[level].plane_en[i])
3427 temp |= PLANE_WM_EN;
3428
3429 r->plane[pipe][i][level] = temp;
3430 /* Use the LP0 WM value for transition WM for now. */
3431 if (level == 0)
3432 r->plane_trans[pipe][i] = temp;
3433 }
3434
3435 temp = 0;
2d41c0b5
PB		 3436
3437 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3438 temp |= p_wm->wm[level].cursor_res_b;
3439
3440 if (p_wm->wm[level].cursor_en)
3441 temp |= PLANE_WM_EN;
3442
3443 r->cursor[pipe][level] = temp;
3444 /* Use the LP0 WM value for transition WM for now. */
3445 if (level == 0)
3446 r->cursor_trans[pipe] = temp;
3447
3448 }
3449
3450 r->wm_linetime[pipe] = p_wm->linetime;
3451}
3452
16160e3d
DL		 3453static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3454 const struct skl_ddb_entry *entry)
3455{
3456 if (entry->end)
3457 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3458 else
3459 I915_WRITE(reg, 0);
3460}
3461
2d41c0b5
PB		 3462static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3463 const struct skl_wm_values *new)
3464{
3465 struct drm_device *dev = dev_priv->dev;
3466 struct intel_crtc *crtc;
3467
3468 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3469 int i, level, max_level = ilk_wm_max_level(dev);
3470 enum pipe pipe = crtc->pipe;
3471
3472 if (new->dirty[pipe]) {
3473 I915_WRITE(PIPE_WM_LINETIME(pipe),
3474 new->wm_linetime[pipe]);
3475
3476 for (level = 0; level <= max_level; level++) {
3477 for (i = 0; i < intel_num_planes(crtc); i++)
3478 I915_WRITE(PLANE_WM(pipe, i, level),
3479 new->plane[pipe][i][level]);
3480 I915_WRITE(CUR_WM(pipe, level),
3481 new->cursor[pipe][level]);
3482 }
3483 for (i = 0; i < intel_num_planes(crtc); i++)
3484 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3485 new->plane_trans[pipe][i]);
3486 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
8211bd5b
DL		 3487
3488 for (i = 0; i < intel_num_planes(crtc); i++)
16160e3d
DL		 3489 skl_ddb_entry_write(dev_priv,
3490 PLANE_BUF_CFG(pipe, i),
3491 &new->ddb.plane[pipe][i]);
8211bd5b 3492
16160e3d
DL		 3493 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3494 &new->ddb.cursor[pipe]);
2d41c0b5
PB		 3495 }
3496 }
2d41c0b5
PB		 3497}
3498
3499static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3500 struct skl_pipe_wm_parameters *params,
3501 struct intel_wm_config *config,
3502 struct skl_ddb_allocation *ddb, /* out */
3503 struct skl_pipe_wm *pipe_wm /* out */)
3504{
3505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3506
3507 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3508 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB		 3509 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3510
3511 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3512 return false;
3513
3514 intel_crtc->wm.skl_active = *pipe_wm;
3515 return true;
3516}
3517
3518static void skl_update_other_pipe_wm(struct drm_device *dev,
3519 struct drm_crtc *crtc,
3520 struct intel_wm_config *config,
3521 struct skl_wm_values *r)
3522{
3523 struct intel_crtc *intel_crtc;
3524 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3525
3526 /*
3527 * If the WM update hasn't changed the allocation for this_crtc (the
3528 * crtc we are currently computing the new WM values for), other
3529 * enabled crtcs will keep the same allocation and we don't need to
3530 * recompute anything for them.
3531 */
3532 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3533 return;
3534
3535 /*
3536 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3537 * other active pipes need new DDB allocation and WM values.
3538 */
3539 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3540 base.head) {
3541 struct skl_pipe_wm_parameters params = {};
3542 struct skl_pipe_wm pipe_wm = {};
3543 bool wm_changed;
3544
3545 if (this_crtc->pipe == intel_crtc->pipe)
3546 continue;
3547
3548 if (!intel_crtc->active)
3549 continue;
3550
3551 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3552 &params, config,
3553 &r->ddb, &pipe_wm);
3554
3555 /*
3556 * If we end up re-computing the other pipe WM values, it's
3557 * because it was really needed, so we expect the WM values to
3558 * be different.
3559 */
3560 WARN_ON(!wm_changed);
3561
3562 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3563 r->dirty[intel_crtc->pipe] = true;
3564 }
3565}
3566
3567static void skl_update_wm(struct drm_crtc *crtc)
3568{
3569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3570 struct drm_device *dev = crtc->dev;
3571 struct drm_i915_private *dev_priv = dev->dev_private;
3572 struct skl_pipe_wm_parameters params = {};
3573 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3574 struct skl_pipe_wm pipe_wm = {};
3575 struct intel_wm_config config = {};
3576
3577 memset(results, 0, sizeof(*results));
3578
3579 skl_compute_wm_global_parameters(dev, &config);
3580
3581 if (!skl_update_pipe_wm(crtc, &params, &config,
3582 &results->ddb, &pipe_wm))
3583 return;
3584
3585 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3586 results->dirty[intel_crtc->pipe] = true;
3587
3588 skl_update_other_pipe_wm(dev, crtc, &config, results);
3589 skl_write_wm_values(dev_priv, results);
53b0deb4
DL		 3590
3591 /* store the new configuration */
3592 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3593}
3594
3595static void
3596skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3597 uint32_t sprite_width, uint32_t sprite_height,
3598 int pixel_size, bool enabled, bool scaled)
3599{
3600 struct intel_plane *intel_plane = to_intel_plane(plane);
3601
3602 intel_plane->wm.enabled = enabled;
3603 intel_plane->wm.scaled = scaled;
3604 intel_plane->wm.horiz_pixels = sprite_width;
3605 intel_plane->wm.vert_pixels = sprite_height;
3606 intel_plane->wm.bytes_per_pixel = pixel_size;
3607
3608 skl_update_wm(crtc);
3609}
3610
820c1980 3611static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3612{
7c4a395f 3613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3614 struct drm_device *dev = crtc->dev;
801bcfff 3615 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 3616 struct ilk_wm_maximums max;
3617 struct ilk_pipe_wm_parameters params = {};
3618 struct ilk_wm_values results = {};
77c122bc 3619 enum intel_ddb_partitioning partitioning;
7c4a395f 3620 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3621 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3622 struct intel_wm_config config = {};
7c4a395f 3623
2a44b76b 3624 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 3625
3626 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3627
3628 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3629 return;
861f3389 3630
7c4a395f 3631 intel_crtc->wm.active = pipe_wm;
861f3389 3632
2a44b76b
VS		 3633 ilk_compute_wm_config(dev, &config);
3634
34982fe1 3635 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3636 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3637
3638 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 3639 if (INTEL_INFO(dev)->gen >= 7 &&
3640 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3641 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3642 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3643
820c1980 3644 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3645 } else {
198a1e9b 3646 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3647 }
3648
198a1e9b 3649 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3650 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3651
820c1980 3652 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3653
820c1980 3654 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3655}
3656
ed57cb8a
DL		 3657static void
3658ilk_update_sprite_wm(struct drm_plane *plane,
3659 struct drm_crtc *crtc,
3660 uint32_t sprite_width, uint32_t sprite_height,
3661 int pixel_size, bool enabled, bool scaled)
526682e9 3662{
8553c18e 3663 struct drm_device *dev = plane->dev;
adf3d35e 3664 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3665
adf3d35e
VS		 3666 intel_plane->wm.enabled = enabled;
3667 intel_plane->wm.scaled = scaled;
3668 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3669 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3670 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3671
8553c18e
VS		 3672 /*
3673 * IVB workaround: must disable low power watermarks for at least
3674 * one frame before enabling scaling. LP watermarks can be re-enabled
3675 * when scaling is disabled.
3676 *
3677 * WaCxSRDisabledForSpriteScaling:ivb
3678 */
3679 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3680 intel_wait_for_vblank(dev, intel_plane->pipe);
3681
820c1980 3682 ilk_update_wm(crtc);
526682e9
PZ		 3683}
3684
3078999f
PB		 3685static void skl_pipe_wm_active_state(uint32_t val,
3686 struct skl_pipe_wm *active,
3687 bool is_transwm,
3688 bool is_cursor,
3689 int i,
3690 int level)
3691{
3692 bool is_enabled = (val & PLANE_WM_EN) != 0;
3693
3694 if (!is_transwm) {
3695 if (!is_cursor) {
3696 active->wm[level].plane_en[i] = is_enabled;
3697 active->wm[level].plane_res_b[i] =
3698 val & PLANE_WM_BLOCKS_MASK;
3699 active->wm[level].plane_res_l[i] =
3700 (val >> PLANE_WM_LINES_SHIFT) &
3701 PLANE_WM_LINES_MASK;
3702 } else {
3703 active->wm[level].cursor_en = is_enabled;
3704 active->wm[level].cursor_res_b =
3705 val & PLANE_WM_BLOCKS_MASK;
3706 active->wm[level].cursor_res_l =
3707 (val >> PLANE_WM_LINES_SHIFT) &
3708 PLANE_WM_LINES_MASK;
3709 }
3710 } else {
3711 if (!is_cursor) {
3712 active->trans_wm.plane_en[i] = is_enabled;
3713 active->trans_wm.plane_res_b[i] =
3714 val & PLANE_WM_BLOCKS_MASK;
3715 active->trans_wm.plane_res_l[i] =
3716 (val >> PLANE_WM_LINES_SHIFT) &
3717 PLANE_WM_LINES_MASK;
3718 } else {
3719 active->trans_wm.cursor_en = is_enabled;
3720 active->trans_wm.cursor_res_b =
3721 val & PLANE_WM_BLOCKS_MASK;
3722 active->trans_wm.cursor_res_l =
3723 (val >> PLANE_WM_LINES_SHIFT) &
3724 PLANE_WM_LINES_MASK;
3725 }
3726 }
3727}
3728
3729static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3730{
3731 struct drm_device *dev = crtc->dev;
3732 struct drm_i915_private *dev_priv = dev->dev_private;
3733 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3735 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3736 enum pipe pipe = intel_crtc->pipe;
3737 int level, i, max_level;
3738 uint32_t temp;
3739
3740 max_level = ilk_wm_max_level(dev);
3741
3742 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3743
3744 for (level = 0; level <= max_level; level++) {
3745 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3746 hw->plane[pipe][i][level] =
3747 I915_READ(PLANE_WM(pipe, i, level));
3748 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3749 }
3750
3751 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3752 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3753 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3754
3755 if (!intel_crtc_active(crtc))
3756 return;
3757
3758 hw->dirty[pipe] = true;
3759
3760 active->linetime = hw->wm_linetime[pipe];
3761
3762 for (level = 0; level <= max_level; level++) {
3763 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3764 temp = hw->plane[pipe][i][level];
3765 skl_pipe_wm_active_state(temp, active, false,
3766 false, i, level);
3767 }
3768 temp = hw->cursor[pipe][level];
3769 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3770 }
3771
3772 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3773 temp = hw->plane_trans[pipe][i];
3774 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3775 }
3776
3777 temp = hw->cursor_trans[pipe];
3778 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3779}
3780
3781void skl_wm_get_hw_state(struct drm_device *dev)
3782{
a269c583
DL		 3783 struct drm_i915_private *dev_priv = dev->dev_private;
3784 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3785 struct drm_crtc *crtc;
3786
a269c583 3787 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3788 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3789 skl_pipe_wm_get_hw_state(crtc);
3790}
3791
243e6a44
VS		 3792static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3793{
3794 struct drm_device *dev = crtc->dev;
3795 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3796 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3798 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3799 enum pipe pipe = intel_crtc->pipe;
3800 static const unsigned int wm0_pipe_reg[] = {
3801 [PIPE_A] = WM0_PIPEA_ILK,
3802 [PIPE_B] = WM0_PIPEB_ILK,
3803 [PIPE_C] = WM0_PIPEC_IVB,
3804 };
3805
3806 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3807 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3808 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3809
2a44b76b
VS		 3810 active->pipe_enabled = intel_crtc_active(crtc);
3811
3812 if (active->pipe_enabled) {
243e6a44
VS		 3813 u32 tmp = hw->wm_pipe[pipe];
3814
3815 /*
3816 * For active pipes LP0 watermark is marked as
3817 * enabled, and LP1+ watermaks as disabled since
3818 * we can't really reverse compute them in case
3819 * multiple pipes are active.
3820 */
3821 active->wm[0].enable = true;
3822 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3823 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3824 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3825 active->linetime = hw->wm_linetime[pipe];
3826 } else {
3827 int level, max_level = ilk_wm_max_level(dev);
3828
3829 /*
3830 * For inactive pipes, all watermark levels
3831 * should be marked as enabled but zeroed,
3832 * which is what we'd compute them to.
3833 */
3834 for (level = 0; level <= max_level; level++)
3835 active->wm[level].enable = true;
3836 }
3837}
3838
3839void ilk_wm_get_hw_state(struct drm_device *dev)
3840{
3841 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3842 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3843 struct drm_crtc *crtc;
3844
70e1e0ec 3845 for_each_crtc(dev, crtc)
243e6a44
VS		 3846 ilk_pipe_wm_get_hw_state(crtc);
3847
3848 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3849 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3850 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3851
3852 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 3853 if (INTEL_INFO(dev)->gen >= 7) {
3854 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3855 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3856 }
243e6a44 3857
a42a5719 3858 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 3859 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3860 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3861 else if (IS_IVYBRIDGE(dev))
3862 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3863 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 3864
3865 hw->enable_fbc_wm =
3866 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3867}
3868
b445e3b0
ED		 3869/**
3870 * intel_update_watermarks - update FIFO watermark values based on current modes
3871 *
3872 * Calculate watermark values for the various WM regs based on current mode
3873 * and plane configuration.
3874 *
3875 * There are several cases to deal with here:
3876 * - normal (i.e. non-self-refresh)
3877 * - self-refresh (SR) mode
3878 * - lines are large relative to FIFO size (buffer can hold up to 2)
3879 * - lines are small relative to FIFO size (buffer can hold more than 2
3880 * lines), so need to account for TLB latency
3881 *
3882 * The normal calculation is:
3883 * watermark = dotclock * bytes per pixel * latency
3884 * where latency is platform & configuration dependent (we assume pessimal
3885 * values here).
3886 *
3887 * The SR calculation is:
3888 * watermark = (trunc(latency/line time)+1) * surface width *
3889 * bytes per pixel
3890 * where
3891 * line time = htotal / dotclock
3892 * surface width = hdisplay for normal plane and 64 for cursor
3893 * and latency is assumed to be high, as above.
3894 *
3895 * The final value programmed to the register should always be rounded up,
3896 * and include an extra 2 entries to account for clock crossings.
3897 *
3898 * We don't use the sprite, so we can ignore that. And on Crestline we have
3899 * to set the non-SR watermarks to 8.
3900 */
46ba614c 3901void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3902{
46ba614c 3903 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3904
3905 if (dev_priv->display.update_wm)
46ba614c 3906 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3907}
3908
adf3d35e
VS		 3909void intel_update_sprite_watermarks(struct drm_plane *plane,
3910 struct drm_crtc *crtc,
ed57cb8a
DL		 3911 uint32_t sprite_width,
3912 uint32_t sprite_height,
3913 int pixel_size,
39db4a4d 3914 bool enabled, bool scaled)
b445e3b0 3915{
adf3d35e 3916 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3917
3918 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 3919 dev_priv->display.update_sprite_wm(plane, crtc,
3920 sprite_width, sprite_height,
39db4a4d 3921 pixel_size, enabled, scaled);
b445e3b0
ED		 3922}
3923
2b4e57bd
ED		 3924static struct drm_i915_gem_object *
3925intel_alloc_context_page(struct drm_device *dev)
3926{
3927 struct drm_i915_gem_object *ctx;
3928 int ret;
3929
3930 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3931
3932 ctx = i915_gem_alloc_object(dev, 4096);
3933 if (!ctx) {
3934 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3935 return NULL;
3936 }
3937
c69766f2 3938 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2b4e57bd
ED		 3939 if (ret) {
3940 DRM_ERROR("failed to pin power context: %d\n", ret);
3941 goto err_unref;
3942 }
3943
3944 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3945 if (ret) {
3946 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3947 goto err_unpin;
3948 }
3949
3950 return ctx;
3951
3952err_unpin:
d7f46fc4 3953 i915_gem_object_ggtt_unpin(ctx);
2b4e57bd
ED		 3954err_unref:
3955 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 3956 return NULL;
3957}
3958
9270388e
DV		 3959/**
3960 * Lock protecting IPS related data structures
9270388e
DV		 3961 */
3962DEFINE_SPINLOCK(mchdev_lock);
3963
3964/* Global for IPS driver to get at the current i915 device. Protected by
3965 * mchdev_lock. */
3966static struct drm_i915_private *i915_mch_dev;
3967
2b4e57bd
ED		 3968bool ironlake_set_drps(struct drm_device *dev, u8 val)
3969{
3970 struct drm_i915_private *dev_priv = dev->dev_private;
3971 u16 rgvswctl;
3972
9270388e
DV		 3973 assert_spin_locked(&mchdev_lock);
3974
2b4e57bd
ED		 3975 rgvswctl = I915_READ16(MEMSWCTL);
3976 if (rgvswctl & MEMCTL_CMD_STS) {
3977 DRM_DEBUG("gpu busy, RCS change rejected\n");
3978 return false; /* still busy with another command */
3979 }
3980
3981 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3982 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3983 I915_WRITE16(MEMSWCTL, rgvswctl);
3984 POSTING_READ16(MEMSWCTL);
3985
3986 rgvswctl |= MEMCTL_CMD_STS;
3987 I915_WRITE16(MEMSWCTL, rgvswctl);
3988
3989 return true;
3990}
3991
8090c6b9 3992static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3993{
3994 struct drm_i915_private *dev_priv = dev->dev_private;
3995 u32 rgvmodectl = I915_READ(MEMMODECTL);
3996 u8 fmax, fmin, fstart, vstart;
3997
9270388e
DV		 3998 spin_lock_irq(&mchdev_lock);
3999
2b4e57bd
ED		 4000 /* Enable temp reporting */
4001 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4002 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4003
4004 /* 100ms RC evaluation intervals */
4005 I915_WRITE(RCUPEI, 100000);
4006 I915_WRITE(RCDNEI, 100000);
4007
4008 /* Set max/min thresholds to 90ms and 80ms respectively */
4009 I915_WRITE(RCBMAXAVG, 90000);
4010 I915_WRITE(RCBMINAVG, 80000);
4011
4012 I915_WRITE(MEMIHYST, 1);
4013
4014 /* Set up min, max, and cur for interrupt handling */
4015 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4016 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4017 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4018 MEMMODE_FSTART_SHIFT;
4019
4020 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4021 PXVFREQ_PX_SHIFT;
4022
20e4d407
DV		 4023 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4024 dev_priv->ips.fstart = fstart;
2b4e57bd 4025
20e4d407
DV		 4026 dev_priv->ips.max_delay = fstart;
4027 dev_priv->ips.min_delay = fmin;
4028 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4029
4030 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4031 fmax, fmin, fstart);
4032
4033 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4034
4035 /*
4036 * Interrupts will be enabled in ironlake_irq_postinstall
4037 */
4038
4039 I915_WRITE(VIDSTART, vstart);
4040 POSTING_READ(VIDSTART);
4041
4042 rgvmodectl |= MEMMODE_SWMODE_EN;
4043 I915_WRITE(MEMMODECTL, rgvmodectl);
4044
9270388e 4045 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4046 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 4047 mdelay(1);
2b4e57bd
ED		 4048
4049 ironlake_set_drps(dev, fstart);
4050
20e4d407 4051 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 4052 I915_READ(0x112e0);
20e4d407
DV		 4053 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4054 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 4055 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4056
4057 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4058}
4059
8090c6b9 4060static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4061{
4062 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4063 u16 rgvswctl;
4064
4065 spin_lock_irq(&mchdev_lock);
4066
4067 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4068
4069 /* Ack interrupts, disable EFC interrupt */
4070 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4071 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4072 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4073 I915_WRITE(DEIIR, DE_PCU_EVENT);
4074 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4075
4076 /* Go back to the starting frequency */
20e4d407 4077 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 4078 mdelay(1);
2b4e57bd
ED		 4079 rgvswctl |= MEMCTL_CMD_STS;
4080 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 4081 mdelay(1);
2b4e57bd 4082
9270388e 4083 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4084}
4085
acbe9475
DV		 4086/* There's a funny hw issue where the hw returns all 0 when reading from
4087 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4088 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4089 * all limits and the gpu stuck at whatever frequency it is at atm).
4090 */
6917c7b9 4091static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4092{
7b9e0ae6 4093 u32 limits;
2b4e57bd 4094
20b46e59
DV		 4095 /* Only set the down limit when we've reached the lowest level to avoid
4096 * getting more interrupts, otherwise leave this clear. This prevents a
4097 * race in the hw when coming out of rc6: There's a tiny window where
4098 * the hw runs at the minimal clock before selecting the desired
4099 * frequency, if the down threshold expires in that window we will not
4100 * receive a down interrupt. */
b39fb297
BW		 4101 limits = dev_priv->rps.max_freq_softlimit << 24;
4102 if (val <= dev_priv->rps.min_freq_softlimit)
4103 limits |= dev_priv->rps.min_freq_softlimit << 16;
20b46e59
DV		 4104
4105 return limits;
4106}
4107
dd75fdc8
CW		 4108static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4109{
4110 int new_power;
4111
4112 new_power = dev_priv->rps.power;
4113 switch (dev_priv->rps.power) {
4114 case LOW_POWER:
b39fb297 4115 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4116 new_power = BETWEEN;
4117 break;
4118
4119 case BETWEEN:
b39fb297 4120 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4121 new_power = LOW_POWER;
b39fb297 4122 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4123 new_power = HIGH_POWER;
4124 break;
4125
4126 case HIGH_POWER:
b39fb297 4127 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4128 new_power = BETWEEN;
4129 break;
4130 }
4131 /* Max/min bins are special */
b39fb297 4132 if (val == dev_priv->rps.min_freq_softlimit)
dd75fdc8 4133 new_power = LOW_POWER;
b39fb297 4134 if (val == dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4135 new_power = HIGH_POWER;
4136 if (new_power == dev_priv->rps.power)
4137 return;
4138
4139 /* Note the units here are not exactly 1us, but 1280ns. */
4140 switch (new_power) {
4141 case LOW_POWER:
4142 /* Upclock if more than 95% busy over 16ms */
4143 I915_WRITE(GEN6_RP_UP_EI, 12500);
4144 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
4145
4146 /* Downclock if less than 85% busy over 32ms */
4147 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
4148 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
4149
4150 I915_WRITE(GEN6_RP_CONTROL,
4151 GEN6_RP_MEDIA_TURBO |
4152 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4153 GEN6_RP_MEDIA_IS_GFX |
4154 GEN6_RP_ENABLE |
4155 GEN6_RP_UP_BUSY_AVG |
4156 GEN6_RP_DOWN_IDLE_AVG);
4157 break;
4158
4159 case BETWEEN:
4160 /* Upclock if more than 90% busy over 13ms */
4161 I915_WRITE(GEN6_RP_UP_EI, 10250);
4162 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
4163
4164 /* Downclock if less than 75% busy over 32ms */
4165 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
4166 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
4167
4168 I915_WRITE(GEN6_RP_CONTROL,
4169 GEN6_RP_MEDIA_TURBO |
4170 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4171 GEN6_RP_MEDIA_IS_GFX |
4172 GEN6_RP_ENABLE |
4173 GEN6_RP_UP_BUSY_AVG |
4174 GEN6_RP_DOWN_IDLE_AVG);
4175 break;
4176
4177 case HIGH_POWER:
4178 /* Upclock if more than 85% busy over 10ms */
4179 I915_WRITE(GEN6_RP_UP_EI, 8000);
4180 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
4181
4182 /* Downclock if less than 60% busy over 32ms */
4183 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
4184 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
4185
4186 I915_WRITE(GEN6_RP_CONTROL,
4187 GEN6_RP_MEDIA_TURBO |
4188 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4189 GEN6_RP_MEDIA_IS_GFX |
4190 GEN6_RP_ENABLE |
4191 GEN6_RP_UP_BUSY_AVG |
4192 GEN6_RP_DOWN_IDLE_AVG);
4193 break;
4194 }
4195
4196 dev_priv->rps.power = new_power;
4197 dev_priv->rps.last_adj = 0;
4198}
4199
2876ce73
CW		 4200static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4201{
4202 u32 mask = 0;
4203
4204 if (val > dev_priv->rps.min_freq_softlimit)
4205 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4206 if (val < dev_priv->rps.max_freq_softlimit)
4207 mask |= GEN6_PM_RP_UP_THRESHOLD;
4208
7b3c29f6
CW		 4209 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
4210 mask &= dev_priv->pm_rps_events;
4211
2876ce73
CW		 4212 /* IVB and SNB hard hangs on looping batchbuffer
4213 * if GEN6_PM_UP_EI_EXPIRED is masked.
4214 */
4215 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
4216 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
4217
baccd458
D		 4218 if (IS_GEN8(dev_priv->dev))
4219 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
4220
2876ce73
CW		 4221 return ~mask;
4222}
4223
b8a5ff8d
JM		 4224/* gen6_set_rps is called to update the frequency request, but should also be
4225 * called when the range (min_delay and max_delay) is modified so that we can
4226 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
20b46e59
DV		 4227void gen6_set_rps(struct drm_device *dev, u8 val)
4228{
4229 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4230
4fc688ce 4231 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 4232 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
4233 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
004777cb 4234
eb64cad1
CW		 4235 /* min/max delay may still have been modified so be sure to
4236 * write the limits value.
4237 */
4238 if (val != dev_priv->rps.cur_freq) {
4239 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4240
50e6a2a7 4241 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4242 I915_WRITE(GEN6_RPNSWREQ,
4243 HSW_FREQUENCY(val));
4244 else
4245 I915_WRITE(GEN6_RPNSWREQ,
4246 GEN6_FREQUENCY(val) |
4247 GEN6_OFFSET(0) |
4248 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4249 }
7b9e0ae6 4250
7b9e0ae6
CW		 4251 /* Make sure we continue to get interrupts
4252 * until we hit the minimum or maximum frequencies.
4253 */
eb64cad1 4254 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
2876ce73 4255 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4256
d5570a72
BW		 4257 POSTING_READ(GEN6_RPNSWREQ);
4258
b39fb297 4259 dev_priv->rps.cur_freq = val;
be2cde9a 4260 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 4261}
4262
76c3552f
D		 4263/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
4264 *
4265 * * If Gfx is Idle, then
4266 * 1. Mask Turbo interrupts
4267 * 2. Bring up Gfx clock
4268 * 3. Change the freq to Rpn and wait till P-Unit updates freq
4269 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
4270 * 5. Unmask Turbo interrupts
4271*/
4272static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4273{
5549d25f
D		 4274 struct drm_device *dev = dev_priv->dev;
4275
4276 /* Latest VLV doesn't need to force the gfx clock */
4277 if (dev->pdev->revision >= 0xd) {
4278 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4279 return;
4280 }
4281
76c3552f
D		 4282 /*
4283 * When we are idle. Drop to min voltage state.
4284 */
4285
b39fb297 4286 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
76c3552f
D		 4287 return;
4288
4289 /* Mask turbo interrupt so that they will not come in between */
4290 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4291
650ad970 4292 vlv_force_gfx_clock(dev_priv, true);
76c3552f 4293
b39fb297 4294 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
76c3552f
D		 4295
4296 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
b39fb297 4297 dev_priv->rps.min_freq_softlimit);
76c3552f
D		 4298
4299 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
4300 & GENFREQSTATUS) == 0, 5))
4301 DRM_ERROR("timed out waiting for Punit\n");
4302
650ad970 4303 vlv_force_gfx_clock(dev_priv, false);
76c3552f 4304
2876ce73
CW		 4305 I915_WRITE(GEN6_PMINTRMSK,
4306 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
76c3552f
D		 4307}
4308
b29c19b6
CW		 4309void gen6_rps_idle(struct drm_i915_private *dev_priv)
4310{
691bb717
DL		 4311 struct drm_device *dev = dev_priv->dev;
4312
b29c19b6 4313 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4314 if (dev_priv->rps.enabled) {
34638118
D		 4315 if (IS_CHERRYVIEW(dev))
4316 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4317 else if (IS_VALLEYVIEW(dev))
76c3552f 4318 vlv_set_rps_idle(dev_priv);
7526ed79 4319 else
b39fb297 4320 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
c0951f0c
CW		 4321 dev_priv->rps.last_adj = 0;
4322 }
b29c19b6
CW		 4323 mutex_unlock(&dev_priv->rps.hw_lock);
4324}
4325
4326void gen6_rps_boost(struct drm_i915_private *dev_priv)
4327{
691bb717
DL		 4328 struct drm_device *dev = dev_priv->dev;
4329
b29c19b6 4330 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4331 if (dev_priv->rps.enabled) {
691bb717 4332 if (IS_VALLEYVIEW(dev))
b39fb297 4333 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
7526ed79 4334 else
b39fb297 4335 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c
CW		 4336 dev_priv->rps.last_adj = 0;
4337 }
b29c19b6
CW		 4338 mutex_unlock(&dev_priv->rps.hw_lock);
4339}
4340
0a073b84
JB		 4341void valleyview_set_rps(struct drm_device *dev, u8 val)
4342{
4343 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 4344
0a073b84 4345 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 4346 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
4347 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
0a073b84 4348
1c14762d
VS		 4349 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4350 "Odd GPU freq value\n"))
4351 val &= ~1;
4352
67956867
VS		 4353 if (val != dev_priv->rps.cur_freq) {
4354 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
4355 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4356 dev_priv->rps.cur_freq,
4357 vlv_gpu_freq(dev_priv, val), val);
4358
2876ce73 4359 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
67956867 4360 }
0a073b84 4361
09c87db8 4362 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
0a073b84 4363
b39fb297 4364 dev_priv->rps.cur_freq = val;
2ec3815f 4365 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 4366}
4367
0961021a
BW		 4368static void gen8_disable_rps_interrupts(struct drm_device *dev)
4369{
4370 struct drm_i915_private *dev_priv = dev->dev_private;
7526ed79
DV		 4371
4372 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
4373 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
4374 ~dev_priv->pm_rps_events);
4375 /* Complete PM interrupt masking here doesn't race with the rps work
4376 * item again unmasking PM interrupts because that is using a different
4377 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
4378 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
4379 * gen8_enable_rps will clean up. */
4380
4381 spin_lock_irq(&dev_priv->irq_lock);
4382 dev_priv->rps.pm_iir = 0;
4383 spin_unlock_irq(&dev_priv->irq_lock);
4384
4385 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
0961021a
BW		 4386}
4387
44fc7d5c 4388static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 4389{
4390 struct drm_i915_private *dev_priv = dev->dev_private;
4391
2b4e57bd 4392 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
a6706b45
D		 4393 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
4394 ~dev_priv->pm_rps_events);
2b4e57bd
ED		 4395 /* Complete PM interrupt masking here doesn't race with the rps work
4396 * item again unmasking PM interrupts because that is using a different
4397 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
4398 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
4399
59cdb63d 4400 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 4401 dev_priv->rps.pm_iir = 0;
59cdb63d 4402 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 4403
a6706b45 4404 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
2b4e57bd
ED		 4405}
4406
44fc7d5c 4407static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4408{
4409 struct drm_i915_private *dev_priv = dev->dev_private;
4410
4411 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4412 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 4413
0961021a
BW		 4414 if (IS_BROADWELL(dev))
4415 gen8_disable_rps_interrupts(dev);
4416 else
4417 gen6_disable_rps_interrupts(dev);
44fc7d5c
DV		 4418}
4419
38807746
D		 4420static void cherryview_disable_rps(struct drm_device *dev)
4421{
4422 struct drm_i915_private *dev_priv = dev->dev_private;
4423
4424 I915_WRITE(GEN6_RC_CONTROL, 0);
3497a562
D		 4425
4426 gen8_disable_rps_interrupts(dev);
38807746
D		 4427}
4428
44fc7d5c
DV		 4429static void valleyview_disable_rps(struct drm_device *dev)
4430{
4431 struct drm_i915_private *dev_priv = dev->dev_private;
4432
98a2e5f9
D		 4433 /* we're doing forcewake before Disabling RC6,
4434 * This what the BIOS expects when going into suspend */
4435 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4436
44fc7d5c 4437 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4438
98a2e5f9
D		 4439 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4440
44fc7d5c 4441 gen6_disable_rps_interrupts(dev);
d20d4f0c
JB		 4442}
4443
dc39fff7
BW		 4444static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4445{
91ca689a
ID		 4446 if (IS_VALLEYVIEW(dev)) {
4447 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4448 mode = GEN6_RC_CTL_RC6_ENABLE;
4449 else
4450 mode = 0;
4451 }
58abf1da
RV		 4452 if (HAS_RC6p(dev))
4453 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4454 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4455 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4456 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4457
4458 else
4459 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4460 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4461}
4462
e6069ca8 4463static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4464{
eb4926e4
DL		 4465 /* No RC6 before Ironlake */
4466 if (INTEL_INFO(dev)->gen < 5)
4467 return 0;
4468
e6069ca8
ID		 4469 /* RC6 is only on Ironlake mobile not on desktop */
4470 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
4471 return 0;
4472
456470eb 4473 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4474 if (enable_rc6 >= 0) {
4475 int mask;
4476
58abf1da 4477 if (HAS_RC6p(dev))
e6069ca8
ID		 4478 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4479 INTEL_RC6pp_ENABLE;
4480 else
4481 mask = INTEL_RC6_ENABLE;
4482
4483 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4484 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4485 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4486
4487 return enable_rc6 & mask;
4488 }
2b4e57bd 4489
6567d748
CW		 4490 /* Disable RC6 on Ironlake */
4491 if (INTEL_INFO(dev)->gen == 5)
4492 return 0;
2b4e57bd 4493
8bade1ad 4494 if (IS_IVYBRIDGE(dev))
cca84a1f 4495 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4496
4497 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4498}
4499
e6069ca8
ID		 4500int intel_enable_rc6(const struct drm_device *dev)
4501{
4502 return i915.enable_rc6;
4503}
4504
0961021a
BW		 4505static void gen8_enable_rps_interrupts(struct drm_device *dev)
4506{
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4508
4509 spin_lock_irq(&dev_priv->irq_lock);
4510 WARN_ON(dev_priv->rps.pm_iir);
480c8033 4511 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
0961021a
BW		 4512 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
4513 spin_unlock_irq(&dev_priv->irq_lock);
4514}
4515
44fc7d5c
DV		 4516static void gen6_enable_rps_interrupts(struct drm_device *dev)
4517{
4518 struct drm_i915_private *dev_priv = dev->dev_private;
4519
4520 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 4521 WARN_ON(dev_priv->rps.pm_iir);
480c8033 4522 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
a6706b45 4523 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
44fc7d5c 4524 spin_unlock_irq(&dev_priv->irq_lock);
44fc7d5c
DV		 4525}
4526
3280e8b0
BW		 4527static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
4528{
4529 /* All of these values are in units of 50MHz */
4530 dev_priv->rps.cur_freq = 0;
4531 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
4532 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4533 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4534 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4535 /* XXX: only BYT has a special efficient freq */
4536 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4537 /* hw_max = RP0 until we check for overclocking */
4538 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4539
4540 /* Preserve min/max settings in case of re-init */
4541 if (dev_priv->rps.max_freq_softlimit == 0)
4542 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4543
4544 if (dev_priv->rps.min_freq_softlimit == 0)
4545 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4546}
4547
6edee7f3
BW		 4548static void gen8_enable_rps(struct drm_device *dev)
4549{
4550 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4551 struct intel_engine_cs *ring;
6edee7f3
BW		 4552 uint32_t rc6_mask = 0, rp_state_cap;
4553 int unused;
4554
4555 /* 1a: Software RC state - RC0 */
4556 I915_WRITE(GEN6_RC_STATE, 0);
4557
4558 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4559 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 4560 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4561
4562 /* 2a: Disable RC states. */
4563 I915_WRITE(GEN6_RC_CONTROL, 0);
4564
4565 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0 4566 parse_rp_state_cap(dev_priv, rp_state_cap);
6edee7f3
BW		 4567
4568 /* 2b: Program RC6 thresholds.*/
4569 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4570 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4571 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4572 for_each_ring(ring, dev_priv, unused)
4573 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4574 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4575 if (IS_BROADWELL(dev))
4576 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4577 else
4578 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4579
4580 /* 3: Enable RC6 */
4581 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4582 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4583 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4584 if (IS_BROADWELL(dev))
4585 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4586 GEN7_RC_CTL_TO_MODE |
4587 rc6_mask);
4588 else
4589 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4590 GEN6_RC_CTL_EI_MODE(1) |
4591 rc6_mask);
6edee7f3
BW		 4592
4593 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4594 I915_WRITE(GEN6_RPNSWREQ,
4595 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4596 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4597 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4598 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4599 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4600
4601 /* Docs recommend 900MHz, and 300 MHz respectively */
4602 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4603 dev_priv->rps.max_freq_softlimit << 24 |
4604 dev_priv->rps.min_freq_softlimit << 16);
4605
4606 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4607 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4608 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4609 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4610
4611 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4612
4613 /* 5: Enable RPS */
7526ed79
DV		 4614 I915_WRITE(GEN6_RP_CONTROL,
4615 GEN6_RP_MEDIA_TURBO |
4616 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4617 GEN6_RP_MEDIA_IS_GFX |
4618 GEN6_RP_ENABLE |
4619 GEN6_RP_UP_BUSY_AVG |
4620 GEN6_RP_DOWN_IDLE_AVG);
4621
4622 /* 6: Ring frequency + overclocking (our driver does this later */
4623
6edee7f3 4624 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
7526ed79
DV		 4625
4626 gen8_enable_rps_interrupts(dev);
6edee7f3 4627
c8d9a590 4628 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4629}
4630
79f5b2c7 4631static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4632{
79f5b2c7 4633 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4634 struct intel_engine_cs *ring;
2a5913a8 4635 u32 rp_state_cap;
d060c169 4636 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4637 u32 gtfifodbg;
2b4e57bd 4638 int rc6_mode;
42c0526c 4639 int i, ret;
2b4e57bd 4640
4fc688ce 4641 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4642
2b4e57bd
ED		 4643 /* Here begins a magic sequence of register writes to enable
4644 * auto-downclocking.
4645 *
4646 * Perhaps there might be some value in exposing these to
4647 * userspace...
4648 */
4649 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4650
4651 /* Clear the DBG now so we don't confuse earlier errors */
4652 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4653 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4654 I915_WRITE(GTFIFODBG, gtfifodbg);
4655 }
4656
c8d9a590 4657 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4658
7b9e0ae6 4659 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7b9e0ae6 4660
3280e8b0 4661 parse_rp_state_cap(dev_priv, rp_state_cap);
dd0a1aa1 4662
2b4e57bd
ED		 4663 /* disable the counters and set deterministic thresholds */
4664 I915_WRITE(GEN6_RC_CONTROL, 0);
4665
4666 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4667 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4668 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4669 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4670 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4671
b4519513
CW		 4672 for_each_ring(ring, dev_priv, i)
4673 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4674
4675 I915_WRITE(GEN6_RC_SLEEP, 0);
4676 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4677 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4678 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4679 else
4680 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4681 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4682 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4683
5a7dc92a 4684 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4685 rc6_mode = intel_enable_rc6(dev_priv->dev);
4686 if (rc6_mode & INTEL_RC6_ENABLE)
4687 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4688
5a7dc92a
ED		 4689 /* We don't use those on Haswell */
4690 if (!IS_HASWELL(dev)) {
4691 if (rc6_mode & INTEL_RC6p_ENABLE)
4692 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4693
5a7dc92a
ED		 4694 if (rc6_mode & INTEL_RC6pp_ENABLE)
4695 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4696 }
2b4e57bd 4697
dc39fff7 4698 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4699
4700 I915_WRITE(GEN6_RC_CONTROL,
4701 rc6_mask |
4702 GEN6_RC_CTL_EI_MODE(1) |
4703 GEN6_RC_CTL_HW_ENABLE);
4704
dd75fdc8
CW		 4705 /* Power down if completely idle for over 50ms */
4706 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4707 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4708
42c0526c 4709 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4710 if (ret)
42c0526c 4711 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4712
4713 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4714 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4715 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4716 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4717 (pcu_mbox & 0xff) * 50);
b39fb297 4718 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4719 }
4720
dd75fdc8 4721 dev_priv->rps.power = HIGH_POWER; /* force a reset */
b39fb297 4722 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
2b4e57bd 4723
44fc7d5c 4724 gen6_enable_rps_interrupts(dev);
2b4e57bd 4725
31643d54
BW		 4726 rc6vids = 0;
4727 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4728 if (IS_GEN6(dev) && ret) {
4729 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4730 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4731 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4732 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4733 rc6vids &= 0xffff00;
4734 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4735 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4736 if (ret)
4737 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4738 }
4739
c8d9a590 4740 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4741}
4742
c2bc2fc5 4743static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4744{
79f5b2c7 4745 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4746 int min_freq = 15;
3ebecd07
CW		 4747 unsigned int gpu_freq;
4748 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 4749 int scaling_factor = 180;
eda79642 4750 struct cpufreq_policy *policy;
2b4e57bd 4751
4fc688ce 4752 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4753
eda79642
BW		 4754 policy = cpufreq_cpu_get(0);
4755 if (policy) {
4756 max_ia_freq = policy->cpuinfo.max_freq;
4757 cpufreq_cpu_put(policy);
4758 } else {
4759 /*
4760 * Default to measured freq if none found, PCU will ensure we
4761 * don't go over
4762 */
2b4e57bd 4763 max_ia_freq = tsc_khz;
eda79642 4764 }
2b4e57bd
ED		 4765
4766 /* Convert from kHz to MHz */
4767 max_ia_freq /= 1000;
4768
153b4b95 4769 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4770 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4771 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4772
2b4e57bd
ED		 4773 /*
4774 * For each potential GPU frequency, load a ring frequency we'd like
4775 * to use for memory access. We do this by specifying the IA frequency
4776 * the PCU should use as a reference to determine the ring frequency.
4777 */
b39fb297 4778 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
2b4e57bd 4779 gpu_freq--) {
b39fb297 4780 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3ebecd07
CW		 4781 unsigned int ia_freq = 0, ring_freq = 0;
4782
46c764d4
BW		 4783 if (INTEL_INFO(dev)->gen >= 8) {
4784 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4785 ring_freq = max(min_ring_freq, gpu_freq);
4786 } else if (IS_HASWELL(dev)) {
f6aca45c 4787 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 4788 ring_freq = max(min_ring_freq, ring_freq);
4789 /* leave ia_freq as the default, chosen by cpufreq */
4790 } else {
4791 /* On older processors, there is no separate ring
4792 * clock domain, so in order to boost the bandwidth
4793 * of the ring, we need to upclock the CPU (ia_freq).
4794 *
4795 * For GPU frequencies less than 750MHz,
4796 * just use the lowest ring freq.
4797 */
4798 if (gpu_freq < min_freq)
4799 ia_freq = 800;
4800 else
4801 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4802 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4803 }
2b4e57bd 4804
42c0526c
BW		 4805 sandybridge_pcode_write(dev_priv,
4806 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 4807 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4808 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4809 gpu_freq);
2b4e57bd 4810 }
2b4e57bd
ED		 4811}
4812
c2bc2fc5
ID		 4813void gen6_update_ring_freq(struct drm_device *dev)
4814{
4815 struct drm_i915_private *dev_priv = dev->dev_private;
4816
4817 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4818 return;
4819
4820 mutex_lock(&dev_priv->rps.hw_lock);
4821 __gen6_update_ring_freq(dev);
4822 mutex_unlock(&dev_priv->rps.hw_lock);
4823}
4824
03af2045 4825static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 4826{
4827 u32 val, rp0;
4828
4829 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4830 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4831
4832 return rp0;
4833}
4834
4835static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4836{
4837 u32 val, rpe;
4838
4839 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4840 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4841
4842 return rpe;
4843}
4844
7707df4a
D		 4845static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4846{
4847 u32 val, rp1;
4848
4849 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4850 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4851
4852 return rp1;
4853}
4854
03af2045 4855static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 4856{
4857 u32 val, rpn;
4858
4859 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4860 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
4861 return rpn;
4862}
4863
f8f2b001
D		 4864static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4865{
4866 u32 val, rp1;
4867
4868 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4869
4870 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4871
4872 return rp1;
4873}
4874
03af2045 4875static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 4876{
4877 u32 val, rp0;
4878
64936258 4879 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 4880
4881 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4882 /* Clamp to max */
4883 rp0 = min_t(u32, rp0, 0xea);
4884
4885 return rp0;
4886}
4887
4888static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4889{
4890 u32 val, rpe;
4891
64936258 4892 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 4893 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 4894 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 4895 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4896
4897 return rpe;
4898}
4899
03af2045 4900static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 4901{
64936258 4902 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 4903}
4904
ae48434c
ID		 4905/* Check that the pctx buffer wasn't move under us. */
4906static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4907{
4908 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4909
4910 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4911 dev_priv->vlv_pctx->stolen->start);
4912}
4913
38807746
D		 4914
4915/* Check that the pcbr address is not empty. */
4916static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4917{
4918 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4919
4920 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4921}
4922
4923static void cherryview_setup_pctx(struct drm_device *dev)
4924{
4925 struct drm_i915_private *dev_priv = dev->dev_private;
4926 unsigned long pctx_paddr, paddr;
4927 struct i915_gtt *gtt = &dev_priv->gtt;
4928 u32 pcbr;
4929 int pctx_size = 32*1024;
4930
4931 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4932
4933 pcbr = I915_READ(VLV_PCBR);
4934 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4935 paddr = (dev_priv->mm.stolen_base +
4936 (gtt->stolen_size - pctx_size));
4937
4938 pctx_paddr = (paddr & (~4095));
4939 I915_WRITE(VLV_PCBR, pctx_paddr);
4940 }
4941}
4942
c9cddffc
JB		 4943static void valleyview_setup_pctx(struct drm_device *dev)
4944{
4945 struct drm_i915_private *dev_priv = dev->dev_private;
4946 struct drm_i915_gem_object *pctx;
4947 unsigned long pctx_paddr;
4948 u32 pcbr;
4949 int pctx_size = 24*1024;
4950
17b0c1f7
ID		 4951 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4952
c9cddffc
JB		 4953 pcbr = I915_READ(VLV_PCBR);
4954 if (pcbr) {
4955 /* BIOS set it up already, grab the pre-alloc'd space */
4956 int pcbr_offset;
4957
4958 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4959 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4960 pcbr_offset,
190d6cd5 4961 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 4962 pctx_size);
4963 goto out;
4964 }
4965
4966 /*
4967 * From the Gunit register HAS:
4968 * The Gfx driver is expected to program this register and ensure
4969 * proper allocation within Gfx stolen memory. For example, this
4970 * register should be programmed such than the PCBR range does not
4971 * overlap with other ranges, such as the frame buffer, protected
4972 * memory, or any other relevant ranges.
4973 */
4974 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4975 if (!pctx) {
4976 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4977 return;
4978 }
4979
4980 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4981 I915_WRITE(VLV_PCBR, pctx_paddr);
4982
4983out:
4984 dev_priv->vlv_pctx = pctx;
4985}
4986
ae48434c
ID		 4987static void valleyview_cleanup_pctx(struct drm_device *dev)
4988{
4989 struct drm_i915_private *dev_priv = dev->dev_private;
4990
4991 if (WARN_ON(!dev_priv->vlv_pctx))
4992 return;
4993
4994 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4995 dev_priv->vlv_pctx = NULL;
4996}
4997
4e80519e
ID		 4998static void valleyview_init_gt_powersave(struct drm_device *dev)
4999{
5000 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5001 u32 val;
4e80519e
ID		 5002
5003 valleyview_setup_pctx(dev);
5004
5005 mutex_lock(&dev_priv->rps.hw_lock);
5006
2bb25c17
VS		 5007 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5008 switch ((val >> 6) & 3) {
5009 case 0:
5010 case 1:
5011 dev_priv->mem_freq = 800;
5012 break;
5013 case 2:
5014 dev_priv->mem_freq = 1066;
5015 break;
5016 case 3:
5017 dev_priv->mem_freq = 1333;
5018 break;
5019 }
5020 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5021
4e80519e
ID		 5022 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5023 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5024 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5025 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5026 dev_priv->rps.max_freq);
5027
5028 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5029 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5030 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5031 dev_priv->rps.efficient_freq);
5032
f8f2b001
D		 5033 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5034 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5035 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5036 dev_priv->rps.rp1_freq);
5037
4e80519e
ID		 5038 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5039 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5040 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5041 dev_priv->rps.min_freq);
5042
5043 /* Preserve min/max settings in case of re-init */
5044 if (dev_priv->rps.max_freq_softlimit == 0)
5045 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5046
5047 if (dev_priv->rps.min_freq_softlimit == 0)
5048 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5049
5050 mutex_unlock(&dev_priv->rps.hw_lock);
5051}
5052
38807746
D		 5053static void cherryview_init_gt_powersave(struct drm_device *dev)
5054{
2b6b3a09 5055 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5056 u32 val;
2b6b3a09 5057
38807746 5058 cherryview_setup_pctx(dev);
2b6b3a09
D		 5059
5060 mutex_lock(&dev_priv->rps.hw_lock);
5061
2bb25c17
VS		 5062 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
5063 switch ((val >> 2) & 0x7) {
5064 case 0:
5065 case 1:
5066 dev_priv->rps.cz_freq = 200;
5067 dev_priv->mem_freq = 1600;
5068 break;
5069 case 2:
5070 dev_priv->rps.cz_freq = 267;
5071 dev_priv->mem_freq = 1600;
5072 break;
5073 case 3:
5074 dev_priv->rps.cz_freq = 333;
5075 dev_priv->mem_freq = 2000;
5076 break;
5077 case 4:
5078 dev_priv->rps.cz_freq = 320;
5079 dev_priv->mem_freq = 1600;
5080 break;
5081 case 5:
5082 dev_priv->rps.cz_freq = 400;
5083 dev_priv->mem_freq = 1600;
5084 break;
5085 }
5086 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5087
2b6b3a09
D		 5088 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5089 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5090 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5091 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5092 dev_priv->rps.max_freq);
5093
5094 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5095 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5096 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5097 dev_priv->rps.efficient_freq);
5098
7707df4a
D		 5099 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5100 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5101 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5102 dev_priv->rps.rp1_freq);
5103
2b6b3a09
D		 5104 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
5105 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5106 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5107 dev_priv->rps.min_freq);
5108
1c14762d
VS		 5109 WARN_ONCE((dev_priv->rps.max_freq |
5110 dev_priv->rps.efficient_freq |
5111 dev_priv->rps.rp1_freq |
5112 dev_priv->rps.min_freq) & 1,
5113 "Odd GPU freq values\n");
5114
2b6b3a09
D		 5115 /* Preserve min/max settings in case of re-init */
5116 if (dev_priv->rps.max_freq_softlimit == 0)
5117 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5118
5119 if (dev_priv->rps.min_freq_softlimit == 0)
5120 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5121
5122 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5123}
5124
4e80519e
ID		 5125static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5126{
5127 valleyview_cleanup_pctx(dev);
5128}
5129
38807746
D		 5130static void cherryview_enable_rps(struct drm_device *dev)
5131{
5132 struct drm_i915_private *dev_priv = dev->dev_private;
5133 struct intel_engine_cs *ring;
2b6b3a09 5134 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5135 int i;
5136
5137 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5138
5139 gtfifodbg = I915_READ(GTFIFODBG);
5140 if (gtfifodbg) {
5141 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5142 gtfifodbg);
5143 I915_WRITE(GTFIFODBG, gtfifodbg);
5144 }
5145
5146 cherryview_check_pctx(dev_priv);
5147
5148 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5149 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5150 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
5151
5152 /* 2a: Program RC6 thresholds.*/
5153 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5154 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5155 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5156
5157 for_each_ring(ring, dev_priv, i)
5158 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5159 I915_WRITE(GEN6_RC_SLEEP, 0);
5160
5161 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5162
5163 /* allows RC6 residency counter to work */
5164 I915_WRITE(VLV_COUNTER_CONTROL,
5165 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5166 VLV_MEDIA_RC6_COUNT_EN |
5167 VLV_RENDER_RC6_COUNT_EN));
5168
5169 /* For now we assume BIOS is allocating and populating the PCBR */
5170 pcbr = I915_READ(VLV_PCBR);
5171
5172 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
5173
5174 /* 3: Enable RC6 */
5175 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5176 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5177 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
5178
5179 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5180
2b6b3a09
D		 5181 /* 4 Program defaults and thresholds for RPS*/
5182 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5183 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5184 I915_WRITE(GEN6_RP_UP_EI, 66000);
5185 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5186
5187 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5188
7405f42c
TR		 5189 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
5190 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
5191 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
5192
2b6b3a09
D		 5193 /* 5: Enable RPS */
5194 I915_WRITE(GEN6_RP_CONTROL,
5195 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7405f42c 5196 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
2b6b3a09
D		 5197 GEN6_RP_ENABLE |
5198 GEN6_RP_UP_BUSY_AVG |
5199 GEN6_RP_DOWN_IDLE_AVG);
5200
5201 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5202
5203 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
5204 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5205
5206 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5207 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5208 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5209 dev_priv->rps.cur_freq);
5210
5211 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5212 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5213 dev_priv->rps.efficient_freq);
5214
5215 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5216
3497a562
D		 5217 gen8_enable_rps_interrupts(dev);
5218
38807746
D		 5219 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
5220}
5221
0a073b84
JB		 5222static void valleyview_enable_rps(struct drm_device *dev)
5223{
5224 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5225 struct intel_engine_cs *ring;
2a5913a8 5226 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5227 int i;
5228
5229 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5230
ae48434c
ID		 5231 valleyview_check_pctx(dev_priv);
5232
0a073b84 5233 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5234 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5235 gtfifodbg);
0a073b84
JB		 5236 I915_WRITE(GTFIFODBG, gtfifodbg);
5237 }
5238
c8d9a590
D		 5239 /* If VLV, Forcewake all wells, else re-direct to regular path */
5240 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5241
5242 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5243 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5244 I915_WRITE(GEN6_RP_UP_EI, 66000);
5245 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5246
5247 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
31685c25 5248 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
0a073b84
JB		 5249
5250 I915_WRITE(GEN6_RP_CONTROL,
5251 GEN6_RP_MEDIA_TURBO |
5252 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5253 GEN6_RP_MEDIA_IS_GFX |
5254 GEN6_RP_ENABLE |
5255 GEN6_RP_UP_BUSY_AVG |
5256 GEN6_RP_DOWN_IDLE_CONT);
5257
5258 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5259 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5260 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5261
5262 for_each_ring(ring, dev_priv, i)
5263 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5264
2f0aa304 5265 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5266
5267 /* allows RC6 residency counter to work */
49798eb2 5268 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5269 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5270 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5271 VLV_MEDIA_RC6_COUNT_EN |
5272 VLV_RENDER_RC6_COUNT_EN));
31685c25 5273
a2b23fe0 5274 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5275 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5276
5277 intel_print_rc6_info(dev, rc6_mode);
5278
a2b23fe0 5279 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5280
64936258 5281 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 5282
5283 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
5284 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5285
b39fb297 5286 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5287 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
b39fb297
BW		 5288 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5289 dev_priv->rps.cur_freq);
0a073b84 5290
73008b98 5291 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
b39fb297
BW		 5292 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5293 dev_priv->rps.efficient_freq);
0a073b84 5294
b39fb297 5295 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5296
44fc7d5c 5297 gen6_enable_rps_interrupts(dev);
0a073b84 5298
c8d9a590 5299 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5300}
5301
930ebb46 5302void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 5303{
5304 struct drm_i915_private *dev_priv = dev->dev_private;
5305
3e373948 5306 if (dev_priv->ips.renderctx) {
d7f46fc4 5307 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3e373948
DV		 5308 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
5309 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 5310 }
5311
3e373948 5312 if (dev_priv->ips.pwrctx) {
d7f46fc4 5313 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3e373948
DV		 5314 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
5315 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 5316 }
5317}
5318
930ebb46 5319static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 5320{
5321 struct drm_i915_private *dev_priv = dev->dev_private;
5322
5323 if (I915_READ(PWRCTXA)) {
5324 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
5325 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
5326 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
5327 50);
5328
5329 I915_WRITE(PWRCTXA, 0);
5330 POSTING_READ(PWRCTXA);
5331
5332 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
5333 POSTING_READ(RSTDBYCTL);
5334 }
2b4e57bd
ED		 5335}
5336
5337static int ironlake_setup_rc6(struct drm_device *dev)
5338{
5339 struct drm_i915_private *dev_priv = dev->dev_private;
5340
3e373948
DV		 5341 if (dev_priv->ips.renderctx == NULL)
5342 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
5343 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 5344 return -ENOMEM;
5345
3e373948
DV		 5346 if (dev_priv->ips.pwrctx == NULL)
5347 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
5348 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 5349 ironlake_teardown_rc6(dev);
5350 return -ENOMEM;
5351 }
5352
5353 return 0;
5354}
5355
930ebb46 5356static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 5357{
5358 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5359 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e960501 5360 bool was_interruptible;
2b4e57bd
ED		 5361 int ret;
5362
5363 /* rc6 disabled by default due to repeated reports of hanging during
5364 * boot and resume.
5365 */
5366 if (!intel_enable_rc6(dev))
5367 return;
5368
79f5b2c7
DV		 5369 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5370
2b4e57bd 5371 ret = ironlake_setup_rc6(dev);
79f5b2c7 5372 if (ret)
2b4e57bd 5373 return;
2b4e57bd 5374
3e960501
CW		 5375 was_interruptible = dev_priv->mm.interruptible;
5376 dev_priv->mm.interruptible = false;
5377
2b4e57bd
ED		 5378 /*
5379 * GPU can automatically power down the render unit if given a page
5380 * to save state.
5381 */
6d90c952 5382 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 5383 if (ret) {
5384 ironlake_teardown_rc6(dev);
3e960501 5385 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 5386 return;
5387 }
5388
6d90c952
DV		 5389 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
5390 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 5391 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 5392 MI_MM_SPACE_GTT |
5393 MI_SAVE_EXT_STATE_EN |
5394 MI_RESTORE_EXT_STATE_EN |
5395 MI_RESTORE_INHIBIT);
5396 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
5397 intel_ring_emit(ring, MI_NOOP);
5398 intel_ring_emit(ring, MI_FLUSH);
5399 intel_ring_advance(ring);
2b4e57bd
ED		 5400
5401 /*
5402 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
5403 * does an implicit flush, combined with MI_FLUSH above, it should be
5404 * safe to assume that renderctx is valid
5405 */
3e960501
CW		 5406 ret = intel_ring_idle(ring);
5407 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 5408 if (ret) {
def27a58 5409 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 5410 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 5411 return;
5412 }
5413
f343c5f6 5414 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 5415 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7 5416
91ca689a 5417 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
2b4e57bd
ED		 5418}
5419
dde18883
ED		 5420static unsigned long intel_pxfreq(u32 vidfreq)
5421{
5422 unsigned long freq;
5423 int div = (vidfreq & 0x3f0000) >> 16;
5424 int post = (vidfreq & 0x3000) >> 12;
5425 int pre = (vidfreq & 0x7);
5426
5427 if (!pre)
5428 return 0;
5429
5430 freq = ((div * 133333) / ((1<<post) * pre));
5431
5432 return freq;
5433}
5434
eb48eb00
DV		 5435static const struct cparams {
5436 u16 i;
5437 u16 t;
5438 u16 m;
5439 u16 c;
5440} cparams[] = {
5441 { 1, 1333, 301, 28664 },
5442 { 1, 1066, 294, 24460 },
5443 { 1, 800, 294, 25192 },
5444 { 0, 1333, 276, 27605 },
5445 { 0, 1066, 276, 27605 },
5446 { 0, 800, 231, 23784 },
5447};
5448
f531dcb2 5449static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5450{
5451 u64 total_count, diff, ret;
5452 u32 count1, count2, count3, m = 0, c = 0;
5453 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5454 int i;
5455
02d71956
DV		 5456 assert_spin_locked(&mchdev_lock);
5457
20e4d407 5458 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5459
5460 /* Prevent division-by-zero if we are asking too fast.
5461 * Also, we don't get interesting results if we are polling
5462 * faster than once in 10ms, so just return the saved value
5463 * in such cases.
5464 */
5465 if (diff1 <= 10)
20e4d407 5466 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5467
5468 count1 = I915_READ(DMIEC);
5469 count2 = I915_READ(DDREC);
5470 count3 = I915_READ(CSIEC);
5471
5472 total_count = count1 + count2 + count3;
5473
5474 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5475 if (total_count < dev_priv->ips.last_count1) {
5476 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5477 diff += total_count;
5478 } else {
20e4d407 5479 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5480 }
5481
5482 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5483 if (cparams[i].i == dev_priv->ips.c_m &&
5484 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5485 m = cparams[i].m;
5486 c = cparams[i].c;
5487 break;
5488 }
5489 }
5490
5491 diff = div_u64(diff, diff1);
5492 ret = ((m * diff) + c);
5493 ret = div_u64(ret, 10);
5494
20e4d407
DV		 5495 dev_priv->ips.last_count1 = total_count;
5496 dev_priv->ips.last_time1 = now;
eb48eb00 5497
20e4d407 5498 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5499
5500 return ret;
5501}
5502
f531dcb2
CW		 5503unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5504{
3d13ef2e 5505 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5506 unsigned long val;
5507
3d13ef2e 5508 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5509 return 0;
5510
5511 spin_lock_irq(&mchdev_lock);
5512
5513 val = __i915_chipset_val(dev_priv);
5514
5515 spin_unlock_irq(&mchdev_lock);
5516
5517 return val;
5518}
5519
eb48eb00
DV		 5520unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5521{
5522 unsigned long m, x, b;
5523 u32 tsfs;
5524
5525 tsfs = I915_READ(TSFS);
5526
5527 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5528 x = I915_READ8(TR1);
5529
5530 b = tsfs & TSFS_INTR_MASK;
5531
5532 return ((m * x) / 127) - b;
5533}
5534
5535static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5536{
3d13ef2e 5537 struct drm_device *dev = dev_priv->dev;
eb48eb00
DV		 5538 static const struct v_table {
5539 u16 vd; /* in .1 mil */
5540 u16 vm; /* in .1 mil */
5541 } v_table[] = {
5542 { 0, 0, },
5543 { 375, 0, },
5544 { 500, 0, },
5545 { 625, 0, },
5546 { 750, 0, },
5547 { 875, 0, },
5548 { 1000, 0, },
5549 { 1125, 0, },
5550 { 4125, 3000, },
5551 { 4125, 3000, },
5552 { 4125, 3000, },
5553 { 4125, 3000, },
5554 { 4125, 3000, },
5555 { 4125, 3000, },
5556 { 4125, 3000, },
5557 { 4125, 3000, },
5558 { 4125, 3000, },
5559 { 4125, 3000, },
5560 { 4125, 3000, },
5561 { 4125, 3000, },
5562 { 4125, 3000, },
5563 { 4125, 3000, },
5564 { 4125, 3000, },
5565 { 4125, 3000, },
5566 { 4125, 3000, },
5567 { 4125, 3000, },
5568 { 4125, 3000, },
5569 { 4125, 3000, },
5570 { 4125, 3000, },
5571 { 4125, 3000, },
5572 { 4125, 3000, },
5573 { 4125, 3000, },
5574 { 4250, 3125, },
5575 { 4375, 3250, },
5576 { 4500, 3375, },
5577 { 4625, 3500, },
5578 { 4750, 3625, },
5579 { 4875, 3750, },
5580 { 5000, 3875, },
5581 { 5125, 4000, },
5582 { 5250, 4125, },
5583 { 5375, 4250, },
5584 { 5500, 4375, },
5585 { 5625, 4500, },
5586 { 5750, 4625, },
5587 { 5875, 4750, },
5588 { 6000, 4875, },
5589 { 6125, 5000, },
5590 { 6250, 5125, },
5591 { 6375, 5250, },
5592 { 6500, 5375, },
5593 { 6625, 5500, },
5594 { 6750, 5625, },
5595 { 6875, 5750, },
5596 { 7000, 5875, },
5597 { 7125, 6000, },
5598 { 7250, 6125, },
5599 { 7375, 6250, },
5600 { 7500, 6375, },
5601 { 7625, 6500, },
5602 { 7750, 6625, },
5603 { 7875, 6750, },
5604 { 8000, 6875, },
5605 { 8125, 7000, },
5606 { 8250, 7125, },
5607 { 8375, 7250, },
5608 { 8500, 7375, },
5609 { 8625, 7500, },
5610 { 8750, 7625, },
5611 { 8875, 7750, },
5612 { 9000, 7875, },
5613 { 9125, 8000, },
5614 { 9250, 8125, },
5615 { 9375, 8250, },
5616 { 9500, 8375, },
5617 { 9625, 8500, },
5618 { 9750, 8625, },
5619 { 9875, 8750, },
5620 { 10000, 8875, },
5621 { 10125, 9000, },
5622 { 10250, 9125, },
5623 { 10375, 9250, },
5624 { 10500, 9375, },
5625 { 10625, 9500, },
5626 { 10750, 9625, },
5627 { 10875, 9750, },
5628 { 11000, 9875, },
5629 { 11125, 10000, },
5630 { 11250, 10125, },
5631 { 11375, 10250, },
5632 { 11500, 10375, },
5633 { 11625, 10500, },
5634 { 11750, 10625, },
5635 { 11875, 10750, },
5636 { 12000, 10875, },
5637 { 12125, 11000, },
5638 { 12250, 11125, },
5639 { 12375, 11250, },
5640 { 12500, 11375, },
5641 { 12625, 11500, },
5642 { 12750, 11625, },
5643 { 12875, 11750, },
5644 { 13000, 11875, },
5645 { 13125, 12000, },
5646 { 13250, 12125, },
5647 { 13375, 12250, },
5648 { 13500, 12375, },
5649 { 13625, 12500, },
5650 { 13750, 12625, },
5651 { 13875, 12750, },
5652 { 14000, 12875, },
5653 { 14125, 13000, },
5654 { 14250, 13125, },
5655 { 14375, 13250, },
5656 { 14500, 13375, },
5657 { 14625, 13500, },
5658 { 14750, 13625, },
5659 { 14875, 13750, },
5660 { 15000, 13875, },
5661 { 15125, 14000, },
5662 { 15250, 14125, },
5663 { 15375, 14250, },
5664 { 15500, 14375, },
5665 { 15625, 14500, },
5666 { 15750, 14625, },
5667 { 15875, 14750, },
5668 { 16000, 14875, },
5669 { 16125, 15000, },
5670 };
3d13ef2e 5671 if (INTEL_INFO(dev)->is_mobile)
eb48eb00
DV		 5672 return v_table[pxvid].vm;
5673 else
5674 return v_table[pxvid].vd;
5675}
5676
02d71956 5677static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5678{
5ed0bdf2 5679 u64 now, diff, diffms;
eb48eb00
DV		 5680 u32 count;
5681
02d71956 5682 assert_spin_locked(&mchdev_lock);
eb48eb00 5683
5ed0bdf2
TG		 5684 now = ktime_get_raw_ns();
5685 diffms = now - dev_priv->ips.last_time2;
5686 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5687
5688 /* Don't divide by 0 */
eb48eb00
DV		 5689 if (!diffms)
5690 return;
5691
5692 count = I915_READ(GFXEC);
5693
20e4d407
DV		 5694 if (count < dev_priv->ips.last_count2) {
5695 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5696 diff += count;
5697 } else {
20e4d407 5698 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5699 }
5700
20e4d407
DV		 5701 dev_priv->ips.last_count2 = count;
5702 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5703
5704 /* More magic constants... */
5705 diff = diff * 1181;
5706 diff = div_u64(diff, diffms * 10);
20e4d407 5707 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5708}
5709
02d71956
DV		 5710void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5711{
3d13ef2e
DL		 5712 struct drm_device *dev = dev_priv->dev;
5713
5714 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5715 return;
5716
9270388e 5717 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5718
5719 __i915_update_gfx_val(dev_priv);
5720
9270388e 5721 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5722}
5723
f531dcb2 5724static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5725{
5726 unsigned long t, corr, state1, corr2, state2;
5727 u32 pxvid, ext_v;
5728
02d71956
DV		 5729 assert_spin_locked(&mchdev_lock);
5730
b39fb297 5731 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 5732 pxvid = (pxvid >> 24) & 0x7f;
5733 ext_v = pvid_to_extvid(dev_priv, pxvid);
5734
5735 state1 = ext_v;
5736
5737 t = i915_mch_val(dev_priv);
5738
5739 /* Revel in the empirically derived constants */
5740
5741 /* Correction factor in 1/100000 units */
5742 if (t > 80)
5743 corr = ((t * 2349) + 135940);
5744 else if (t >= 50)
5745 corr = ((t * 964) + 29317);
5746 else /* < 50 */
5747 corr = ((t * 301) + 1004);
5748
5749 corr = corr * ((150142 * state1) / 10000 - 78642);
5750 corr /= 100000;
20e4d407 5751 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5752
5753 state2 = (corr2 * state1) / 10000;
5754 state2 /= 100; /* convert to mW */
5755
02d71956 5756 __i915_update_gfx_val(dev_priv);
eb48eb00 5757
20e4d407 5758 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5759}
5760
f531dcb2
CW		 5761unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5762{
3d13ef2e 5763 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5764 unsigned long val;
5765
3d13ef2e 5766 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5767 return 0;
5768
5769 spin_lock_irq(&mchdev_lock);
5770
5771 val = __i915_gfx_val(dev_priv);
5772
5773 spin_unlock_irq(&mchdev_lock);
5774
5775 return val;
5776}
5777
eb48eb00
DV		 5778/**
5779 * i915_read_mch_val - return value for IPS use
5780 *
5781 * Calculate and return a value for the IPS driver to use when deciding whether
5782 * we have thermal and power headroom to increase CPU or GPU power budget.
5783 */
5784unsigned long i915_read_mch_val(void)
5785{
5786 struct drm_i915_private *dev_priv;
5787 unsigned long chipset_val, graphics_val, ret = 0;
5788
9270388e 5789 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5790 if (!i915_mch_dev)
5791 goto out_unlock;
5792 dev_priv = i915_mch_dev;
5793
f531dcb2
CW		 5794 chipset_val = __i915_chipset_val(dev_priv);
5795 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5796
5797 ret = chipset_val + graphics_val;
5798
5799out_unlock:
9270388e 5800 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5801
5802 return ret;
5803}
5804EXPORT_SYMBOL_GPL(i915_read_mch_val);
5805
5806/**
5807 * i915_gpu_raise - raise GPU frequency limit
5808 *
5809 * Raise the limit; IPS indicates we have thermal headroom.
5810 */
5811bool i915_gpu_raise(void)
5812{
5813 struct drm_i915_private *dev_priv;
5814 bool ret = true;
5815
9270388e 5816 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5817 if (!i915_mch_dev) {
5818 ret = false;
5819 goto out_unlock;
5820 }
5821 dev_priv = i915_mch_dev;
5822
20e4d407
DV		 5823 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5824 dev_priv->ips.max_delay--;
eb48eb00
DV		 5825
5826out_unlock:
9270388e 5827 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5828
5829 return ret;
5830}
5831EXPORT_SYMBOL_GPL(i915_gpu_raise);
5832
5833/**
5834 * i915_gpu_lower - lower GPU frequency limit
5835 *
5836 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5837 * frequency maximum.
5838 */
5839bool i915_gpu_lower(void)
5840{
5841 struct drm_i915_private *dev_priv;
5842 bool ret = true;
5843
9270388e 5844 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5845 if (!i915_mch_dev) {
5846 ret = false;
5847 goto out_unlock;
5848 }
5849 dev_priv = i915_mch_dev;
5850
20e4d407
DV		 5851 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5852 dev_priv->ips.max_delay++;
eb48eb00
DV		 5853
5854out_unlock:
9270388e 5855 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5856
5857 return ret;
5858}
5859EXPORT_SYMBOL_GPL(i915_gpu_lower);
5860
5861/**
5862 * i915_gpu_busy - indicate GPU business to IPS
5863 *
5864 * Tell the IPS driver whether or not the GPU is busy.
5865 */
5866bool i915_gpu_busy(void)
5867{
5868 struct drm_i915_private *dev_priv;
a4872ba6 5869 struct intel_engine_cs *ring;
eb48eb00 5870 bool ret = false;
f047e395 5871 int i;
eb48eb00 5872
9270388e 5873 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5874 if (!i915_mch_dev)
5875 goto out_unlock;
5876 dev_priv = i915_mch_dev;
5877
f047e395
CW		 5878 for_each_ring(ring, dev_priv, i)
5879 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5880
5881out_unlock:
9270388e 5882 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5883
5884 return ret;
5885}
5886EXPORT_SYMBOL_GPL(i915_gpu_busy);
5887
5888/**
5889 * i915_gpu_turbo_disable - disable graphics turbo
5890 *
5891 * Disable graphics turbo by resetting the max frequency and setting the
5892 * current frequency to the default.
5893 */
5894bool i915_gpu_turbo_disable(void)
5895{
5896 struct drm_i915_private *dev_priv;
5897 bool ret = true;
5898
9270388e 5899 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5900 if (!i915_mch_dev) {
5901 ret = false;
5902 goto out_unlock;
5903 }
5904 dev_priv = i915_mch_dev;
5905
20e4d407 5906 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5907
20e4d407 5908 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5909 ret = false;
5910
5911out_unlock:
9270388e 5912 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5913
5914 return ret;
5915}
5916EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5917
5918/**
5919 * Tells the intel_ips driver that the i915 driver is now loaded, if
5920 * IPS got loaded first.
5921 *
5922 * This awkward dance is so that neither module has to depend on the
5923 * other in order for IPS to do the appropriate communication of
5924 * GPU turbo limits to i915.
5925 */
5926static void
5927ips_ping_for_i915_load(void)
5928{
5929 void (*link)(void);
5930
5931 link = symbol_get(ips_link_to_i915_driver);
5932 if (link) {
5933 link();
5934 symbol_put(ips_link_to_i915_driver);
5935 }
5936}
5937
5938void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5939{
02d71956
DV		 5940 /* We only register the i915 ips part with intel-ips once everything is
5941 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5942 spin_lock_irq(&mchdev_lock);
eb48eb00 5943 i915_mch_dev = dev_priv;
9270388e 5944 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5945
5946 ips_ping_for_i915_load();
5947}
5948
5949void intel_gpu_ips_teardown(void)
5950{
9270388e 5951 spin_lock_irq(&mchdev_lock);
eb48eb00 5952 i915_mch_dev = NULL;
9270388e 5953 spin_unlock_irq(&mchdev_lock);
eb48eb00 5954}
76c3552f 5955
8090c6b9 5956static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5957{
5958 struct drm_i915_private *dev_priv = dev->dev_private;
5959 u32 lcfuse;
5960 u8 pxw[16];
5961 int i;
5962
5963 /* Disable to program */
5964 I915_WRITE(ECR, 0);
5965 POSTING_READ(ECR);
5966
5967 /* Program energy weights for various events */
5968 I915_WRITE(SDEW, 0x15040d00);
5969 I915_WRITE(CSIEW0, 0x007f0000);
5970 I915_WRITE(CSIEW1, 0x1e220004);
5971 I915_WRITE(CSIEW2, 0x04000004);
5972
5973 for (i = 0; i < 5; i++)
5974 I915_WRITE(PEW + (i * 4), 0);
5975 for (i = 0; i < 3; i++)
5976 I915_WRITE(DEW + (i * 4), 0);
5977
5978 /* Program P-state weights to account for frequency power adjustment */
5979 for (i = 0; i < 16; i++) {
5980 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5981 unsigned long freq = intel_pxfreq(pxvidfreq);
5982 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5983 PXVFREQ_PX_SHIFT;
5984 unsigned long val;
5985
5986 val = vid * vid;
5987 val *= (freq / 1000);
5988 val *= 255;
5989 val /= (127*127*900);
5990 if (val > 0xff)
5991 DRM_ERROR("bad pxval: %ld\n", val);
5992 pxw[i] = val;
5993 }
5994 /* Render standby states get 0 weight */
5995 pxw[14] = 0;
5996 pxw[15] = 0;
5997
5998 for (i = 0; i < 4; i++) {
5999 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6000 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6001 I915_WRITE(PXW + (i * 4), val);
6002 }
6003
6004 /* Adjust magic regs to magic values (more experimental results) */
6005 I915_WRITE(OGW0, 0);
6006 I915_WRITE(OGW1, 0);
6007 I915_WRITE(EG0, 0x00007f00);
6008 I915_WRITE(EG1, 0x0000000e);
6009 I915_WRITE(EG2, 0x000e0000);
6010 I915_WRITE(EG3, 0x68000300);
6011 I915_WRITE(EG4, 0x42000000);
6012 I915_WRITE(EG5, 0x00140031);
6013 I915_WRITE(EG6, 0);
6014 I915_WRITE(EG7, 0);
6015
6016 for (i = 0; i < 8; i++)
6017 I915_WRITE(PXWL + (i * 4), 0);
6018
6019 /* Enable PMON + select events */
6020 I915_WRITE(ECR, 0x80000019);
6021
6022 lcfuse = I915_READ(LCFUSE02);
6023
20e4d407 6024 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6025}
6026
ae48434c
ID		 6027void intel_init_gt_powersave(struct drm_device *dev)
6028{
e6069ca8
ID		 6029 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6030
38807746
D		 6031 if (IS_CHERRYVIEW(dev))
6032 cherryview_init_gt_powersave(dev);
6033 else if (IS_VALLEYVIEW(dev))
4e80519e 6034 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6035}
6036
6037void intel_cleanup_gt_powersave(struct drm_device *dev)
6038{
38807746
D		 6039 if (IS_CHERRYVIEW(dev))
6040 return;
6041 else if (IS_VALLEYVIEW(dev))
4e80519e 6042 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 6043}
6044
156c7ca0
JB		 6045/**
6046 * intel_suspend_gt_powersave - suspend PM work and helper threads
6047 * @dev: drm device
6048 *
6049 * We don't want to disable RC6 or other features here, we just want
6050 * to make sure any work we've queued has finished and won't bother
6051 * us while we're suspended.
6052 */
6053void intel_suspend_gt_powersave(struct drm_device *dev)
6054{
6055 struct drm_i915_private *dev_priv = dev->dev_private;
6056
6057 /* Interrupts should be disabled already to avoid re-arming. */
9df7575f 6058 WARN_ON(intel_irqs_enabled(dev_priv));
156c7ca0
JB		 6059
6060 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6061
6062 cancel_work_sync(&dev_priv->rps.work);
b47adc17
D		 6063
6064 /* Force GPU to min freq during suspend */
6065 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6066}
6067
8090c6b9
DV		 6068void intel_disable_gt_powersave(struct drm_device *dev)
6069{
1a01ab3b
JB		 6070 struct drm_i915_private *dev_priv = dev->dev_private;
6071
fd0c0642 6072 /* Interrupts should be disabled already to avoid re-arming. */
9df7575f 6073 WARN_ON(intel_irqs_enabled(dev_priv));
fd0c0642 6074
930ebb46 6075 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6076 ironlake_disable_drps(dev);
930ebb46 6077 ironlake_disable_rc6(dev);
38807746 6078 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6079 intel_suspend_gt_powersave(dev);
e494837a 6080
4fc688ce 6081 mutex_lock(&dev_priv->rps.hw_lock);
38807746
D		 6082 if (IS_CHERRYVIEW(dev))
6083 cherryview_disable_rps(dev);
6084 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6085 valleyview_disable_rps(dev);
6086 else
6087 gen6_disable_rps(dev);
c0951f0c 6088 dev_priv->rps.enabled = false;
4fc688ce 6089 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6090 }
8090c6b9
DV		 6091}
6092
1a01ab3b
JB		 6093static void intel_gen6_powersave_work(struct work_struct *work)
6094{
6095 struct drm_i915_private *dev_priv =
6096 container_of(work, struct drm_i915_private,
6097 rps.delayed_resume_work.work);
6098 struct drm_device *dev = dev_priv->dev;
6099
4fc688ce 6100 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6101
38807746
D		 6102 if (IS_CHERRYVIEW(dev)) {
6103 cherryview_enable_rps(dev);
6104 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6105 valleyview_enable_rps(dev);
6edee7f3
BW		 6106 } else if (IS_BROADWELL(dev)) {
6107 gen8_enable_rps(dev);
c2bc2fc5 6108 __gen6_update_ring_freq(dev);
0a073b84
JB		 6109 } else {
6110 gen6_enable_rps(dev);
c2bc2fc5 6111 __gen6_update_ring_freq(dev);
0a073b84 6112 }
c0951f0c 6113 dev_priv->rps.enabled = true;
4fc688ce 6114 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6115
6116 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6117}
6118
8090c6b9
DV		 6119void intel_enable_gt_powersave(struct drm_device *dev)
6120{
1a01ab3b
JB		 6121 struct drm_i915_private *dev_priv = dev->dev_private;
6122
8090c6b9 6123 if (IS_IRONLAKE_M(dev)) {
dc1d0136 6124 mutex_lock(&dev->struct_mutex);
8090c6b9
DV		 6125 ironlake_enable_drps(dev);
6126 ironlake_enable_rc6(dev);
6127 intel_init_emon(dev);
dc1d0136 6128 mutex_unlock(&dev->struct_mutex);
38807746 6129 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6130 /*
6131 * PCU communication is slow and this doesn't need to be
6132 * done at any specific time, so do this out of our fast path
6133 * to make resume and init faster.
c6df39b5
ID		 6134 *
6135 * We depend on the HW RC6 power context save/restore
6136 * mechanism when entering D3 through runtime PM suspend. So
6137 * disable RPM until RPS/RC6 is properly setup. We can only
6138 * get here via the driver load/system resume/runtime resume
6139 * paths, so the _noresume version is enough (and in case of
6140 * runtime resume it's necessary).
1a01ab3b 6141 */
c6df39b5
ID		 6142 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6143 round_jiffies_up_relative(HZ)))
6144 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6145 }
6146}
6147
c6df39b5
ID		 6148void intel_reset_gt_powersave(struct drm_device *dev)
6149{
6150 struct drm_i915_private *dev_priv = dev->dev_private;
6151
6152 dev_priv->rps.enabled = false;
6153 intel_enable_gt_powersave(dev);
6154}
6155
3107bd48
DV		 6156static void ibx_init_clock_gating(struct drm_device *dev)
6157{
6158 struct drm_i915_private *dev_priv = dev->dev_private;
6159
6160 /*
6161 * On Ibex Peak and Cougar Point, we need to disable clock
6162 * gating for the panel power sequencer or it will fail to
6163 * start up when no ports are active.
6164 */
6165 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6166}
6167
0e088b8f
VS		 6168static void g4x_disable_trickle_feed(struct drm_device *dev)
6169{
6170 struct drm_i915_private *dev_priv = dev->dev_private;
6171 int pipe;
6172
055e393f 6173 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6174 I915_WRITE(DSPCNTR(pipe),
6175 I915_READ(DSPCNTR(pipe)) |
6176 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 6177 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 6178 }
6179}
6180
017636cc
VS		 6181static void ilk_init_lp_watermarks(struct drm_device *dev)
6182{
6183 struct drm_i915_private *dev_priv = dev->dev_private;
6184
6185 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6186 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6187 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6188
6189 /*
6190 * Don't touch WM1S_LP_EN here.
6191 * Doing so could cause underruns.
6192 */
6193}
6194
1fa61106 6195static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6196{
6197 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6198 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6199
f1e8fa56
DL		 6200 /*
6201 * Required for FBC
6202 * WaFbcDisableDpfcClockGating:ilk
6203 */
4d47e4f5
DL		 6204 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6205 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6206 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6207
6208 I915_WRITE(PCH_3DCGDIS0,
6209 MARIUNIT_CLOCK_GATE_DISABLE |
6210 SVSMUNIT_CLOCK_GATE_DISABLE);
6211 I915_WRITE(PCH_3DCGDIS1,
6212 VFMUNIT_CLOCK_GATE_DISABLE);
6213
6f1d69b0
ED		 6214 /*
6215 * According to the spec the following bits should be set in
6216 * order to enable memory self-refresh
6217 * The bit 22/21 of 0x42004
6218 * The bit 5 of 0x42020
6219 * The bit 15 of 0x45000
6220 */
6221 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6222 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6223 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6224 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6225 I915_WRITE(DISP_ARB_CTL,
6226 (I915_READ(DISP_ARB_CTL) |
6227 DISP_FBC_WM_DIS));
017636cc
VS		 6228
6229 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6230
6231 /*
6232 * Based on the document from hardware guys the following bits
6233 * should be set unconditionally in order to enable FBC.
6234 * The bit 22 of 0x42000
6235 * The bit 22 of 0x42004
6236 * The bit 7,8,9 of 0x42020.
6237 */
6238 if (IS_IRONLAKE_M(dev)) {
4bb35334 6239 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6240 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6241 I915_READ(ILK_DISPLAY_CHICKEN1) |
6242 ILK_FBCQ_DIS);
6243 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6244 I915_READ(ILK_DISPLAY_CHICKEN2) |
6245 ILK_DPARB_GATE);
6f1d69b0
ED		 6246 }
6247
4d47e4f5
DL		 6248 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6249
6f1d69b0
ED		 6250 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6251 I915_READ(ILK_DISPLAY_CHICKEN2) |
6252 ILK_ELPIN_409_SELECT);
6253 I915_WRITE(_3D_CHICKEN2,
6254 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6255 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6256
ecdb4eb7 6257 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6258 I915_WRITE(CACHE_MODE_0,
6259 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6260
4e04632e
AG		 6261 /* WaDisable_RenderCache_OperationalFlush:ilk */
6262 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6263
0e088b8f 6264 g4x_disable_trickle_feed(dev);
bdad2b2f 6265
3107bd48
DV		 6266 ibx_init_clock_gating(dev);
6267}
6268
6269static void cpt_init_clock_gating(struct drm_device *dev)
6270{
6271 struct drm_i915_private *dev_priv = dev->dev_private;
6272 int pipe;
3f704fa2 6273 uint32_t val;
3107bd48
DV		 6274
6275 /*
6276 * On Ibex Peak and Cougar Point, we need to disable clock
6277 * gating for the panel power sequencer or it will fail to
6278 * start up when no ports are active.
6279 */
cd664078
JB		 6280 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6281 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6282 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6283 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6284 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6285 /* The below fixes the weird display corruption, a few pixels shifted
6286 * downward, on (only) LVDS of some HP laptops with IVY.
6287 */
055e393f 6288 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6289 val = I915_READ(TRANS_CHICKEN2(pipe));
6290 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6291 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6292 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6293 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6294 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6295 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6296 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6297 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6298 }
3107bd48 6299 /* WADP0ClockGatingDisable */
055e393f 6300 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6301 I915_WRITE(TRANS_CHICKEN1(pipe),
6302 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6303 }
6f1d69b0
ED		 6304}
6305
1d7aaa0c
DV		 6306static void gen6_check_mch_setup(struct drm_device *dev)
6307{
6308 struct drm_i915_private *dev_priv = dev->dev_private;
6309 uint32_t tmp;
6310
6311 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6312 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6313 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6314 tmp);
1d7aaa0c
DV		 6315}
6316
1fa61106 6317static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6318{
6319 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6320 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6321
231e54f6 6322 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6323
6324 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6325 I915_READ(ILK_DISPLAY_CHICKEN2) |
6326 ILK_ELPIN_409_SELECT);
6327
ecdb4eb7 6328 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6329 I915_WRITE(_3D_CHICKEN,
6330 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6331
ecdb4eb7 6332 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 6333 if (IS_SNB_GT1(dev))
6334 I915_WRITE(GEN6_GT_MODE,
6335 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
6336
4e04632e
AG		 6337 /* WaDisable_RenderCache_OperationalFlush:snb */
6338 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6339
8d85d272
VS		 6340 /*
6341 * BSpec recoomends 8x4 when MSAA is used,
6342 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6343 *
6344 * Note that PS/WM thread counts depend on the WIZ hashing
6345 * disable bit, which we don't touch here, but it's good
6346 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6347 */
6348 I915_WRITE(GEN6_GT_MODE,
6349 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
6350
017636cc 6351 ilk_init_lp_watermarks(dev);
6f1d69b0 6352
6f1d69b0 6353 I915_WRITE(CACHE_MODE_0,
50743298 6354 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6355
6356 I915_WRITE(GEN6_UCGCTL1,
6357 I915_READ(GEN6_UCGCTL1) |
6358 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6359 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6360
6361 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6362 * gating disable must be set. Failure to set it results in
6363 * flickering pixels due to Z write ordering failures after
6364 * some amount of runtime in the Mesa "fire" demo, and Unigine
6365 * Sanctuary and Tropics, and apparently anything else with
6366 * alpha test or pixel discard.
6367 *
6368 * According to the spec, bit 11 (RCCUNIT) must also be set,
6369 * but we didn't debug actual testcases to find it out.
0f846f81 6370 *
ef59318c
VS		 6371 * WaDisableRCCUnitClockGating:snb
6372 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6373 */
6374 I915_WRITE(GEN6_UCGCTL2,
6375 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6376 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6377
5eb146dd 6378 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6379 I915_WRITE(_3D_CHICKEN3,
6380 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6381
e927ecde
VS		 6382 /*
6383 * Bspec says:
6384 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6385 * 3DSTATE_SF number of SF output attributes is more than 16."
6386 */
6387 I915_WRITE(_3D_CHICKEN3,
6388 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6389
6f1d69b0
ED		 6390 /*
6391 * According to the spec the following bits should be
6392 * set in order to enable memory self-refresh and fbc:
6393 * The bit21 and bit22 of 0x42000
6394 * The bit21 and bit22 of 0x42004
6395 * The bit5 and bit7 of 0x42020
6396 * The bit14 of 0x70180
6397 * The bit14 of 0x71180
4bb35334
DL		 6398 *
6399 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6400 */
6401 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6402 I915_READ(ILK_DISPLAY_CHICKEN1) |
6403 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6404 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6405 I915_READ(ILK_DISPLAY_CHICKEN2) |
6406 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6407 I915_WRITE(ILK_DSPCLK_GATE_D,
6408 I915_READ(ILK_DSPCLK_GATE_D) |
6409 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6410 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6411
0e088b8f 6412 g4x_disable_trickle_feed(dev);
f8f2ac9a 6413
3107bd48 6414 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6415
6416 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6417}
6418
6419static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6420{
6421 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6422
3aad9059 6423 /*
46680e0a 6424 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6425 *
6426 * This actually overrides the dispatch
6427 * mode for all thread types.
6428 */
6f1d69b0
ED		 6429 reg &= ~GEN7_FF_SCHED_MASK;
6430 reg |= GEN7_FF_TS_SCHED_HW;
6431 reg |= GEN7_FF_VS_SCHED_HW;
6432 reg |= GEN7_FF_DS_SCHED_HW;
6433
6434 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6435}
6436
17a303ec
PZ		 6437static void lpt_init_clock_gating(struct drm_device *dev)
6438{
6439 struct drm_i915_private *dev_priv = dev->dev_private;
6440
6441 /*
6442 * TODO: this bit should only be enabled when really needed, then
6443 * disabled when not needed anymore in order to save power.
6444 */
6445 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6446 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6447 I915_READ(SOUTH_DSPCLK_GATE_D) |
6448 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6449
6450 /* WADPOClockGatingDisable:hsw */
6451 I915_WRITE(_TRANSA_CHICKEN1,
6452 I915_READ(_TRANSA_CHICKEN1) |
6453 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6454}
6455
7d708ee4
ID		 6456static void lpt_suspend_hw(struct drm_device *dev)
6457{
6458 struct drm_i915_private *dev_priv = dev->dev_private;
6459
6460 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6461 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6462
6463 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6464 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6465 }
6466}
6467
47c2bd97 6468static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6469{
6470 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6471 enum pipe pipe;
1020a5c2
BW		 6472
6473 I915_WRITE(WM3_LP_ILK, 0);
6474 I915_WRITE(WM2_LP_ILK, 0);
6475 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd 6476
ab57fff1 6477 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6478 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6479
ab57fff1 6480 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6481 I915_WRITE(CHICKEN_PAR1_1,
6482 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6483
ab57fff1 6484 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6485 for_each_pipe(dev_priv, pipe) {
07d27e20 6486 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6487 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6488 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6489 }
63801f21 6490
ab57fff1
BW		 6491 /* WaVSRefCountFullforceMissDisable:bdw */
6492 /* WaDSRefCountFullforceMissDisable:bdw */
6493 I915_WRITE(GEN7_FF_THREAD_MODE,
6494 I915_READ(GEN7_FF_THREAD_MODE) &
6495 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6496
295e8bb7
VS		 6497 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6498 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6499
6500 /* WaDisableSDEUnitClockGating:bdw */
6501 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6502 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6503
89d6b2b8 6504 lpt_init_clock_gating(dev);
1020a5c2
BW		 6505}
6506
cad2a2d7
ED		 6507static void haswell_init_clock_gating(struct drm_device *dev)
6508{
6509 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6510
017636cc 6511 ilk_init_lp_watermarks(dev);
cad2a2d7 6512
f3fc4884
FJ		 6513 /* L3 caching of data atomics doesn't work -- disable it. */
6514 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6515 I915_WRITE(HSW_ROW_CHICKEN3,
6516 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6517
ecdb4eb7 6518 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6519 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6520 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6521 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6522
e36ea7ff
VS		 6523 /* WaVSRefCountFullforceMissDisable:hsw */
6524 I915_WRITE(GEN7_FF_THREAD_MODE,
6525 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6526
4e04632e
AG		 6527 /* WaDisable_RenderCache_OperationalFlush:hsw */
6528 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6529
fe27c606
CW		 6530 /* enable HiZ Raw Stall Optimization */
6531 I915_WRITE(CACHE_MODE_0_GEN7,
6532 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6533
ecdb4eb7 6534 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6535 I915_WRITE(CACHE_MODE_1,
6536 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6537
a12c4967
VS		 6538 /*
6539 * BSpec recommends 8x4 when MSAA is used,
6540 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6541 *
6542 * Note that PS/WM thread counts depend on the WIZ hashing
6543 * disable bit, which we don't touch here, but it's good
6544 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6545 */
6546 I915_WRITE(GEN7_GT_MODE,
6547 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
6548
ecdb4eb7 6549 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6550 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6551
90a88643
PZ		 6552 /* WaRsPkgCStateDisplayPMReq:hsw */
6553 I915_WRITE(CHICKEN_PAR1_1,
6554 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6555
17a303ec 6556 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6557}
6558
1fa61106 6559static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6560{
6561 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6562 uint32_t snpcr;
6f1d69b0 6563
017636cc 6564 ilk_init_lp_watermarks(dev);
6f1d69b0 6565
231e54f6 6566 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6567
ecdb4eb7 6568 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6569 I915_WRITE(_3D_CHICKEN3,
6570 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6571
ecdb4eb7 6572 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6573 I915_WRITE(IVB_CHICKEN3,
6574 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6575 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6576
ecdb4eb7 6577 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6578 if (IS_IVB_GT1(dev))
6579 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6580 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6581
4e04632e
AG		 6582 /* WaDisable_RenderCache_OperationalFlush:ivb */
6583 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6584
ecdb4eb7 6585 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6586 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6587 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6588
ecdb4eb7 6589 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6590 I915_WRITE(GEN7_L3CNTLREG1,
6591 GEN7_WA_FOR_GEN7_L3_CONTROL);
6592 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6593 GEN7_WA_L3_CHICKEN_MODE);
6594 if (IS_IVB_GT1(dev))
6595 I915_WRITE(GEN7_ROW_CHICKEN2,
6596 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6597 else {
6598 /* must write both registers */
6599 I915_WRITE(GEN7_ROW_CHICKEN2,
6600 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6601 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6602 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6603 }
6f1d69b0 6604
ecdb4eb7 6605 /* WaForceL3Serialization:ivb */
61939d97
JB		 6606 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6607 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6608
1b80a19a 6609 /*
0f846f81 6610 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6611 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6612 */
6613 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6614 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6615
ecdb4eb7 6616 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6617 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6618 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6619 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6620
0e088b8f 6621 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6622
6623 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6624
22721343
CW		 6625 if (0) { /* causes HiZ corruption on ivb:gt1 */
6626 /* enable HiZ Raw Stall Optimization */
6627 I915_WRITE(CACHE_MODE_0_GEN7,
6628 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6629 }
116f2b6d 6630
ecdb4eb7 6631 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6632 I915_WRITE(CACHE_MODE_1,
6633 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6634
a607c1a4
VS		 6635 /*
6636 * BSpec recommends 8x4 when MSAA is used,
6637 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6638 *
6639 * Note that PS/WM thread counts depend on the WIZ hashing
6640 * disable bit, which we don't touch here, but it's good
6641 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6642 */
6643 I915_WRITE(GEN7_GT_MODE,
6644 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
6645
20848223
BW		 6646 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6647 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6648 snpcr |= GEN6_MBC_SNPCR_MED;
6649 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6650
ab5c608b
BW		 6651 if (!HAS_PCH_NOP(dev))
6652 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6653
6654 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6655}
6656
1fa61106 6657static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6658{
6659 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6660
d7fe0cc0 6661 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6662
ecdb4eb7 6663 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6664 I915_WRITE(_3D_CHICKEN3,
6665 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6666
ecdb4eb7 6667 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6668 I915_WRITE(IVB_CHICKEN3,
6669 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6670 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6671
fad7d36e 6672 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6673 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6674 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6675 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6676 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6677
4e04632e
AG		 6678 /* WaDisable_RenderCache_OperationalFlush:vlv */
6679 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6680
ecdb4eb7 6681 /* WaForceL3Serialization:vlv */
61939d97
JB		 6682 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6683 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6684
ecdb4eb7 6685 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6686 I915_WRITE(GEN7_ROW_CHICKEN2,
6687 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6688
ecdb4eb7 6689 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6690 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6691 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6692 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6693
46680e0a
VS		 6694 gen7_setup_fixed_func_scheduler(dev_priv);
6695
3c0edaeb 6696 /*
0f846f81 6697 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6698 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6699 */
6700 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6701 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6702
c98f5062
AG		 6703 /* WaDisableL3Bank2xClockGate:vlv
6704 * Disabling L3 clock gating- MMIO 940c[25] = 1
6705 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6706 I915_WRITE(GEN7_UCGCTL4,
6707 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6708
e0d8d59b 6709 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 6710
afd58e79
VS		 6711 /*
6712 * BSpec says this must be set, even though
6713 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6714 */
6b26c86d
DV		 6715 I915_WRITE(CACHE_MODE_1,
6716 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6717
031994ee
VS		 6718 /*
6719 * WaIncreaseL3CreditsForVLVB0:vlv
6720 * This is the hardware default actually.
6721 */
6722 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6723
2d809570 6724 /*
ecdb4eb7 6725 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6726 * Disable clock gating on th GCFG unit to prevent a delay
6727 * in the reporting of vblank events.
6728 */
7a0d1eed 6729 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6730}
6731
a4565da8
VS		 6732static void cherryview_init_clock_gating(struct drm_device *dev)
6733{
6734 struct drm_i915_private *dev_priv = dev->dev_private;
6735
6736 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6737
6738 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
dd811e70 6739
232ce337
VS		 6740 /* WaVSRefCountFullforceMissDisable:chv */
6741 /* WaDSRefCountFullforceMissDisable:chv */
6742 I915_WRITE(GEN7_FF_THREAD_MODE,
6743 I915_READ(GEN7_FF_THREAD_MODE) &
6744 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6745
6746 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6747 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6748 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6749
6750 /* WaDisableCSUnitClockGating:chv */
6751 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6752 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6753
6754 /* WaDisableSDEUnitClockGating:chv */
6755 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6756 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
e0d34ce7 6757
e4443e45
VS		 6758 /* WaDisableGunitClockGating:chv (pre-production hw) */
6759 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
6760 GINT_DIS);
6761
6762 /* WaDisableFfDopClockGating:chv (pre-production hw) */
6763 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6764 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
6765
6766 /* WaDisableDopClockGating:chv (pre-production hw) */
e4443e45
VS		 6767 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6768 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS		 6769}
6770
1fa61106 6771static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6772{
6773 struct drm_i915_private *dev_priv = dev->dev_private;
6774 uint32_t dspclk_gate;
6775
6776 I915_WRITE(RENCLK_GATE_D1, 0);
6777 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6778 GS_UNIT_CLOCK_GATE_DISABLE |
6779 CL_UNIT_CLOCK_GATE_DISABLE);
6780 I915_WRITE(RAMCLK_GATE_D, 0);
6781 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6782 OVRUNIT_CLOCK_GATE_DISABLE |
6783 OVCUNIT_CLOCK_GATE_DISABLE;
6784 if (IS_GM45(dev))
6785 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6786 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6787
6788 /* WaDisableRenderCachePipelinedFlush */
6789 I915_WRITE(CACHE_MODE_0,
6790 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6791
4e04632e
AG		 6792 /* WaDisable_RenderCache_OperationalFlush:g4x */
6793 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6794
0e088b8f 6795 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6796}
6797
1fa61106 6798static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6799{
6800 struct drm_i915_private *dev_priv = dev->dev_private;
6801
6802 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6803 I915_WRITE(RENCLK_GATE_D2, 0);
6804 I915_WRITE(DSPCLK_GATE_D, 0);
6805 I915_WRITE(RAMCLK_GATE_D, 0);
6806 I915_WRITE16(DEUC, 0);
20f94967
VS		 6807 I915_WRITE(MI_ARB_STATE,
6808 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6809
6810 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6811 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6812}
6813
1fa61106 6814static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6815{
6816 struct drm_i915_private *dev_priv = dev->dev_private;
6817
6818 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6819 I965_RCC_CLOCK_GATE_DISABLE |
6820 I965_RCPB_CLOCK_GATE_DISABLE |
6821 I965_ISC_CLOCK_GATE_DISABLE |
6822 I965_FBC_CLOCK_GATE_DISABLE);
6823 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6824 I915_WRITE(MI_ARB_STATE,
6825 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6826
6827 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6828 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6829}
6830
1fa61106 6831static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6832{
6833 struct drm_i915_private *dev_priv = dev->dev_private;
6834 u32 dstate = I915_READ(D_STATE);
6835
6836 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6837 DSTATE_DOT_CLOCK_GATING;
6838 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6839
6840 if (IS_PINEVIEW(dev))
6841 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6842
6843 /* IIR "flip pending" means done if this bit is set */
6844 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6845
6846 /* interrupts should cause a wake up from C3 */
3299254f 6847 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6848
6849 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6850 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6851
6852 I915_WRITE(MI_ARB_STATE,
6853 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6854}
6855
1fa61106 6856static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6857{
6858 struct drm_i915_private *dev_priv = dev->dev_private;
6859
6860 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6861
6862 /* interrupts should cause a wake up from C3 */
6863 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6864 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6865
6866 I915_WRITE(MEM_MODE,
6867 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6868}
6869
1fa61106 6870static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6871{
6872 struct drm_i915_private *dev_priv = dev->dev_private;
6873
6874 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6875
6876 I915_WRITE(MEM_MODE,
6877 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6878 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6879}
6880
6f1d69b0
ED		 6881void intel_init_clock_gating(struct drm_device *dev)
6882{
6883 struct drm_i915_private *dev_priv = dev->dev_private;
6884
6885 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6886}
6887
7d708ee4
ID		 6888void intel_suspend_hw(struct drm_device *dev)
6889{
6890 if (HAS_PCH_LPT(dev))
6891 lpt_suspend_hw(dev);
6892}
6893
d2dee86c
PZ		 6894static void intel_init_fbc(struct drm_i915_private *dev_priv)
6895{
9adccc60
PZ		 6896 if (!HAS_FBC(dev_priv)) {
6897 dev_priv->fbc.enabled = false;
d2dee86c 6898 return;
9adccc60 6899 }
d2dee86c
PZ		 6900
6901 if (INTEL_INFO(dev_priv)->gen >= 7) {
6902 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6903 dev_priv->display.enable_fbc = gen7_enable_fbc;
6904 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6905 } else if (INTEL_INFO(dev_priv)->gen >= 5) {
6906 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6907 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6908 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6909 } else if (IS_GM45(dev_priv)) {
6910 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6911 dev_priv->display.enable_fbc = g4x_enable_fbc;
6912 dev_priv->display.disable_fbc = g4x_disable_fbc;
6913 } else {
6914 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6915 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6916 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6917
6918 /* This value was pulled out of someone's hat */
6919 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6920 }
9adccc60
PZ		 6921
6922 dev_priv->fbc.enabled = dev_priv->display.fbc_enabled(dev_priv->dev);
d2dee86c
PZ		 6923}
6924
1fa61106
ED		 6925/* Set up chip specific power management-related functions */
6926void intel_init_pm(struct drm_device *dev)
6927{
6928 struct drm_i915_private *dev_priv = dev->dev_private;
6929
d2dee86c 6930 intel_init_fbc(dev_priv);
1fa61106 6931
c921aba8
DV		 6932 /* For cxsr */
6933 if (IS_PINEVIEW(dev))
6934 i915_pineview_get_mem_freq(dev);
6935 else if (IS_GEN5(dev))
6936 i915_ironlake_get_mem_freq(dev);
6937
1fa61106 6938 /* For FIFO watermark updates */
c83155a6 6939 if (IS_GEN9(dev)) {
2af30a5c
PB		 6940 skl_setup_wm_latency(dev);
6941
c83155a6 6942 dev_priv->display.init_clock_gating = gen9_init_clock_gating;
2d41c0b5
PB		 6943 dev_priv->display.update_wm = skl_update_wm;
6944 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 6945 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6946 ilk_setup_wm_latency(dev);
53615a5e 6947
bd602544
VS		 6948 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6949 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6950 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6951 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6952 dev_priv->display.update_wm = ilk_update_wm;
6953 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6954 } else {
6955 DRM_DEBUG_KMS("Failed to read display plane latency. "
6956 "Disable CxSR\n");
6957 }
6958
6959 if (IS_GEN5(dev))
1fa61106 6960 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6961 else if (IS_GEN6(dev))
1fa61106 6962 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6963 else if (IS_IVYBRIDGE(dev))
1fa61106 6964 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6965 else if (IS_HASWELL(dev))
cad2a2d7 6966 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6967 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 6968 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 6969 } else if (IS_CHERRYVIEW(dev)) {
3c2777fd 6970 dev_priv->display.update_wm = cherryview_update_wm;
01e184cc 6971 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
a4565da8
VS		 6972 dev_priv->display.init_clock_gating =
6973 cherryview_init_clock_gating;
1fa61106
ED		 6974 } else if (IS_VALLEYVIEW(dev)) {
6975 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6976 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
1fa61106
ED		 6977 dev_priv->display.init_clock_gating =
6978 valleyview_init_clock_gating;
1fa61106
ED		 6979 } else if (IS_PINEVIEW(dev)) {
6980 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6981 dev_priv->is_ddr3,
6982 dev_priv->fsb_freq,
6983 dev_priv->mem_freq)) {
6984 DRM_INFO("failed to find known CxSR latency "
6985 "(found ddr%s fsb freq %d, mem freq %d), "
6986 "disabling CxSR\n",
6987 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6988 dev_priv->fsb_freq, dev_priv->mem_freq);
6989 /* Disable CxSR and never update its watermark again */
5209b1f4 6990 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 6991 dev_priv->display.update_wm = NULL;
6992 } else
6993 dev_priv->display.update_wm = pineview_update_wm;
6994 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6995 } else if (IS_G4X(dev)) {
6996 dev_priv->display.update_wm = g4x_update_wm;
6997 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6998 } else if (IS_GEN4(dev)) {
6999 dev_priv->display.update_wm = i965_update_wm;
7000 if (IS_CRESTLINE(dev))
7001 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7002 else if (IS_BROADWATER(dev))
7003 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7004 } else if (IS_GEN3(dev)) {
7005 dev_priv->display.update_wm = i9xx_update_wm;
7006 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7007 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7008 } else if (IS_GEN2(dev)) {
7009 if (INTEL_INFO(dev)->num_pipes == 1) {
7010 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7011 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7012 } else {
7013 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7014 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7015 }
7016
7017 if (IS_I85X(dev) || IS_I865G(dev))
7018 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7019 else
7020 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7021 } else {
7022 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7023 }
7024}
7025
42c0526c
BW		 7026int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
7027{
4fc688ce 7028 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7029
7030 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7031 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7032 return -EAGAIN;
7033 }
7034
7035 I915_WRITE(GEN6_PCODE_DATA, *val);
2af30a5c
PB		 7036 if (INTEL_INFO(dev_priv)->gen >= 9)
7037 I915_WRITE(GEN9_PCODE_DATA1, 0);
42c0526c
BW		 7038 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7039
7040 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7041 500)) {
7042 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7043 return -ETIMEDOUT;
7044 }
7045
7046 *val = I915_READ(GEN6_PCODE_DATA);
7047 I915_WRITE(GEN6_PCODE_DATA, 0);
7048
7049 return 0;
7050}
7051
7052int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
7053{
4fc688ce 7054 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7055
7056 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7057 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7058 return -EAGAIN;
7059 }
7060
7061 I915_WRITE(GEN6_PCODE_DATA, val);
7062 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7063
7064 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7065 500)) {
7066 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7067 return -ETIMEDOUT;
7068 }
7069
7070 I915_WRITE(GEN6_PCODE_DATA, 0);
7071
7072 return 0;
7073}
a0e4e199 7074
b55dd647 7075static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 7076{
07ab118b 7077 int div;
855ba3be 7078
07ab118b 7079 /* 4 x czclk */
2ec3815f 7080 switch (dev_priv->mem_freq) {
855ba3be 7081 case 800:
07ab118b 7082 div = 10;
855ba3be
JB		 7083 break;
7084 case 1066:
07ab118b 7085 div = 12;
855ba3be
JB		 7086 break;
7087 case 1333:
07ab118b 7088 div = 16;
855ba3be
JB		 7089 break;
7090 default:
7091 return -1;
7092 }
7093
2ec3815f 7094 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 7095}
7096
b55dd647 7097static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7098{
07ab118b 7099 int mul;
855ba3be 7100
07ab118b 7101 /* 4 x czclk */
2ec3815f 7102 switch (dev_priv->mem_freq) {
855ba3be 7103 case 800:
07ab118b 7104 mul = 10;
855ba3be
JB		 7105 break;
7106 case 1066:
07ab118b 7107 mul = 12;
855ba3be
JB		 7108 break;
7109 case 1333:
07ab118b 7110 mul = 16;
855ba3be
JB		 7111 break;
7112 default:
7113 return -1;
7114 }
7115
2ec3815f 7116 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 7117}
7118
b55dd647 7119static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8
D		 7120{
7121 int div, freq;
7122
7123 switch (dev_priv->rps.cz_freq) {
7124 case 200:
7125 div = 5;
7126 break;
7127 case 267:
7128 div = 6;
7129 break;
7130 case 320:
7131 case 333:
7132 case 400:
7133 div = 8;
7134 break;
7135 default:
7136 return -1;
7137 }
7138
7139 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
7140
7141 return freq;
7142}
7143
b55dd647 7144static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8
D		 7145{
7146 int mul, opcode;
7147
7148 switch (dev_priv->rps.cz_freq) {
7149 case 200:
7150 mul = 5;
7151 break;
7152 case 267:
7153 mul = 6;
7154 break;
7155 case 320:
7156 case 333:
7157 case 400:
7158 mul = 8;
7159 break;
7160 default:
7161 return -1;
7162 }
7163
1c14762d 7164 /* CHV needs even values */
22b1b2f8
D		 7165 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7166
7167 return opcode;
7168}
7169
7170int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7171{
7172 int ret = -1;
7173
7174 if (IS_CHERRYVIEW(dev_priv->dev))
7175 ret = chv_gpu_freq(dev_priv, val);
7176 else if (IS_VALLEYVIEW(dev_priv->dev))
7177 ret = byt_gpu_freq(dev_priv, val);
7178
7179 return ret;
7180}
7181
7182int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7183{
7184 int ret = -1;
7185
7186 if (IS_CHERRYVIEW(dev_priv->dev))
7187 ret = chv_freq_opcode(dev_priv, val);
7188 else if (IS_VALLEYVIEW(dev_priv->dev))
7189 ret = byt_freq_opcode(dev_priv, val);
7190
7191 return ret;
7192}
7193
f742a552 7194void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7195{
7196 struct drm_i915_private *dev_priv = dev->dev_private;
7197
f742a552
DV		 7198 mutex_init(&dev_priv->rps.hw_lock);
7199
907b28c5
CW		 7200 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7201 intel_gen6_powersave_work);
5d584b2e 7202
33688d95 7203 dev_priv->pm.suspended = false;
907b28c5 7204}
Linux kernel - Deliverables
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