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drm/i915: Extract intel_encoder_has_connectors()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7 34/**
18afd443
JN		 35 * DOC: RC6
36 *
dc39fff7
BW		 37 * RC6 is a special power stage which allows the GPU to enter an very
38 * low-voltage mode when idle, using down to 0V while at this stage. This
39 * stage is entered automatically when the GPU is idle when RC6 support is
40 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
41 *
42 * There are different RC6 modes available in Intel GPU, which differentiate
43 * among each other with the latency required to enter and leave RC6 and
44 * voltage consumed by the GPU in different states.
45 *
46 * The combination of the following flags define which states GPU is allowed
47 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
48 * RC6pp is deepest RC6. Their support by hardware varies according to the
49 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
50 * which brings the most power savings; deeper states save more power, but
51 * require higher latency to switch to and wake up.
52 */
53#define INTEL_RC6_ENABLE (1<<0)
54#define INTEL_RC6p_ENABLE (1<<1)
55#define INTEL_RC6pp_ENABLE (1<<2)
56
a82abe43
ID		 57static void bxt_init_clock_gating(struct drm_device *dev)
58{
32608ca2
ID		 59 struct drm_i915_private *dev_priv = dev->dev_private;
60
a7546159
NH		 61 /* WaDisableSDEUnitClockGating:bxt */
62 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
63 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
64
32608ca2
ID		 65 /*
66 * FIXME:
868434c5 67 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 68 */
32608ca2 69 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 70 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 71
72 /*
73 * Wa: Backlight PWM may stop in the asserted state, causing backlight
74 * to stay fully on.
75 */
76 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
77 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
78 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 79}
80
c921aba8
DV		 81static void i915_pineview_get_mem_freq(struct drm_device *dev)
82{
50227e1c 83 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 84 u32 tmp;
85
86 tmp = I915_READ(CLKCFG);
87
88 switch (tmp & CLKCFG_FSB_MASK) {
89 case CLKCFG_FSB_533:
90 dev_priv->fsb_freq = 533; /* 133*4 */
91 break;
92 case CLKCFG_FSB_800:
93 dev_priv->fsb_freq = 800; /* 200*4 */
94 break;
95 case CLKCFG_FSB_667:
96 dev_priv->fsb_freq = 667; /* 167*4 */
97 break;
98 case CLKCFG_FSB_400:
99 dev_priv->fsb_freq = 400; /* 100*4 */
100 break;
101 }
102
103 switch (tmp & CLKCFG_MEM_MASK) {
104 case CLKCFG_MEM_533:
105 dev_priv->mem_freq = 533;
106 break;
107 case CLKCFG_MEM_667:
108 dev_priv->mem_freq = 667;
109 break;
110 case CLKCFG_MEM_800:
111 dev_priv->mem_freq = 800;
112 break;
113 }
114
115 /* detect pineview DDR3 setting */
116 tmp = I915_READ(CSHRDDR3CTL);
117 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
118}
119
120static void i915_ironlake_get_mem_freq(struct drm_device *dev)
121{
50227e1c 122 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 123 u16 ddrpll, csipll;
124
125 ddrpll = I915_READ16(DDRMPLL1);
126 csipll = I915_READ16(CSIPLL0);
127
128 switch (ddrpll & 0xff) {
129 case 0xc:
130 dev_priv->mem_freq = 800;
131 break;
132 case 0x10:
133 dev_priv->mem_freq = 1066;
134 break;
135 case 0x14:
136 dev_priv->mem_freq = 1333;
137 break;
138 case 0x18:
139 dev_priv->mem_freq = 1600;
140 break;
141 default:
142 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
143 ddrpll & 0xff);
144 dev_priv->mem_freq = 0;
145 break;
146 }
147
20e4d407 148 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 149
150 switch (csipll & 0x3ff) {
151 case 0x00c:
152 dev_priv->fsb_freq = 3200;
153 break;
154 case 0x00e:
155 dev_priv->fsb_freq = 3733;
156 break;
157 case 0x010:
158 dev_priv->fsb_freq = 4266;
159 break;
160 case 0x012:
161 dev_priv->fsb_freq = 4800;
162 break;
163 case 0x014:
164 dev_priv->fsb_freq = 5333;
165 break;
166 case 0x016:
167 dev_priv->fsb_freq = 5866;
168 break;
169 case 0x018:
170 dev_priv->fsb_freq = 6400;
171 break;
172 default:
173 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
174 csipll & 0x3ff);
175 dev_priv->fsb_freq = 0;
176 break;
177 }
178
179 if (dev_priv->fsb_freq == 3200) {
20e4d407 180 dev_priv->ips.c_m = 0;
c921aba8 181 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 182 dev_priv->ips.c_m = 1;
c921aba8 183 } else {
20e4d407 184 dev_priv->ips.c_m = 2;
c921aba8
DV		 185 }
186}
187
b445e3b0
ED		 188static const struct cxsr_latency cxsr_latency_table[] = {
189 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
190 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
191 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
192 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
193 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
194
195 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
196 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
197 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
198 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
199 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
200
201 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
202 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
203 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
204 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
205 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
206
207 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
208 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
209 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
210 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
211 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
212
213 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
214 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
215 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
216 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
217 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
218
219 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
220 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
221 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
222 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
223 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
224};
225
63c62275 226static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 227 int is_ddr3,
228 int fsb,
229 int mem)
230{
231 const struct cxsr_latency *latency;
232 int i;
233
234 if (fsb == 0 || mem == 0)
235 return NULL;
236
237 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
238 latency = &cxsr_latency_table[i];
239 if (is_desktop == latency->is_desktop &&
240 is_ddr3 == latency->is_ddr3 &&
241 fsb == latency->fsb_freq && mem == latency->mem_freq)
242 return latency;
243 }
244
245 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
246
247 return NULL;
248}
249
fc1ac8de
VS		 250static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
251{
252 u32 val;
253
254 mutex_lock(&dev_priv->rps.hw_lock);
255
256 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
257 if (enable)
258 val &= ~FORCE_DDR_HIGH_FREQ;
259 else
260 val |= FORCE_DDR_HIGH_FREQ;
261 val &= ~FORCE_DDR_LOW_FREQ;
262 val |= FORCE_DDR_FREQ_REQ_ACK;
263 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
264
265 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
266 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
267 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
268
269 mutex_unlock(&dev_priv->rps.hw_lock);
270}
271
cfb41411
VS		 272static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
273{
274 u32 val;
275
276 mutex_lock(&dev_priv->rps.hw_lock);
277
278 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
279 if (enable)
280 val |= DSP_MAXFIFO_PM5_ENABLE;
281 else
282 val &= ~DSP_MAXFIFO_PM5_ENABLE;
283 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
284
285 mutex_unlock(&dev_priv->rps.hw_lock);
286}
287
f4998963
VS		 288#define FW_WM(value, plane) \
289 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
290
5209b1f4 291void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 292{
5209b1f4
ID		 293 struct drm_device *dev = dev_priv->dev;
294 u32 val;
b445e3b0 295
666a4537 296 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 297 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 298 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 299 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 300 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
301 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 302 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 303 } else if (IS_PINEVIEW(dev)) {
304 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
305 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
306 I915_WRITE(DSPFW3, val);
a7a6c498 307 POSTING_READ(DSPFW3);
5209b1f4
ID		 308 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
309 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
310 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
311 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 312 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 313 } else if (IS_I915GM(dev)) {
314 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
315 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
316 I915_WRITE(INSTPM, val);
a7a6c498 317 POSTING_READ(INSTPM);
5209b1f4
ID		 318 } else {
319 return;
320 }
b445e3b0 321
5209b1f4
ID		 322 DRM_DEBUG_KMS("memory self-refresh is %s\n",
323 enable ? "enabled" : "disabled");
b445e3b0
ED		 324}
325
fc1ac8de 326
b445e3b0
ED		 327/*
328 * Latency for FIFO fetches is dependent on several factors:
329 * - memory configuration (speed, channels)
330 * - chipset
331 * - current MCH state
332 * It can be fairly high in some situations, so here we assume a fairly
333 * pessimal value. It's a tradeoff between extra memory fetches (if we
334 * set this value too high, the FIFO will fetch frequently to stay full)
335 * and power consumption (set it too low to save power and we might see
336 * FIFO underruns and display "flicker").
337 *
338 * A value of 5us seems to be a good balance; safe for very low end
339 * platforms but not overly aggressive on lower latency configs.
340 */
5aef6003 341static const int pessimal_latency_ns = 5000;
b445e3b0 342
b5004720
VS		 343#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
344 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
345
346static int vlv_get_fifo_size(struct drm_device *dev,
347 enum pipe pipe, int plane)
348{
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 int sprite0_start, sprite1_start, size;
351
352 switch (pipe) {
353 uint32_t dsparb, dsparb2, dsparb3;
354 case PIPE_A:
355 dsparb = I915_READ(DSPARB);
356 dsparb2 = I915_READ(DSPARB2);
357 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
358 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
359 break;
360 case PIPE_B:
361 dsparb = I915_READ(DSPARB);
362 dsparb2 = I915_READ(DSPARB2);
363 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
364 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
365 break;
366 case PIPE_C:
367 dsparb2 = I915_READ(DSPARB2);
368 dsparb3 = I915_READ(DSPARB3);
369 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
370 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
371 break;
372 default:
373 return 0;
374 }
375
376 switch (plane) {
377 case 0:
378 size = sprite0_start;
379 break;
380 case 1:
381 size = sprite1_start - sprite0_start;
382 break;
383 case 2:
384 size = 512 - 1 - sprite1_start;
385 break;
386 default:
387 return 0;
388 }
389
390 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
391 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
392 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
393 size);
394
395 return size;
396}
397
1fa61106 398static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 399{
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t dsparb = I915_READ(DSPARB);
402 int size;
403
404 size = dsparb & 0x7f;
405 if (plane)
406 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
407
408 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
409 plane ? "B" : "A", size);
410
411 return size;
412}
413
feb56b93 414static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 415{
416 struct drm_i915_private *dev_priv = dev->dev_private;
417 uint32_t dsparb = I915_READ(DSPARB);
418 int size;
419
420 size = dsparb & 0x1ff;
421 if (plane)
422 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
423 size >>= 1; /* Convert to cachelines */
424
425 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
426 plane ? "B" : "A", size);
427
428 return size;
429}
430
1fa61106 431static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 432{
433 struct drm_i915_private *dev_priv = dev->dev_private;
434 uint32_t dsparb = I915_READ(DSPARB);
435 int size;
436
437 size = dsparb & 0x7f;
438 size >>= 2; /* Convert to cachelines */
439
440 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
441 plane ? "B" : "A",
442 size);
443
444 return size;
445}
446
b445e3b0
ED		 447/* Pineview has different values for various configs */
448static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 449 .fifo_size = PINEVIEW_DISPLAY_FIFO,
450 .max_wm = PINEVIEW_MAX_WM,
451 .default_wm = PINEVIEW_DFT_WM,
452 .guard_size = PINEVIEW_GUARD_WM,
453 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 454};
455static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 456 .fifo_size = PINEVIEW_DISPLAY_FIFO,
457 .max_wm = PINEVIEW_MAX_WM,
458 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
459 .guard_size = PINEVIEW_GUARD_WM,
460 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 461};
462static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 463 .fifo_size = PINEVIEW_CURSOR_FIFO,
464 .max_wm = PINEVIEW_CURSOR_MAX_WM,
465 .default_wm = PINEVIEW_CURSOR_DFT_WM,
466 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
467 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 468};
469static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 470 .fifo_size = PINEVIEW_CURSOR_FIFO,
471 .max_wm = PINEVIEW_CURSOR_MAX_WM,
472 .default_wm = PINEVIEW_CURSOR_DFT_WM,
473 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
474 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 475};
476static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 477 .fifo_size = G4X_FIFO_SIZE,
478 .max_wm = G4X_MAX_WM,
479 .default_wm = G4X_MAX_WM,
480 .guard_size = 2,
481 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 482};
483static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 484 .fifo_size = I965_CURSOR_FIFO,
485 .max_wm = I965_CURSOR_MAX_WM,
486 .default_wm = I965_CURSOR_DFT_WM,
487 .guard_size = 2,
488 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 489};
490static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 491 .fifo_size = VALLEYVIEW_FIFO_SIZE,
492 .max_wm = VALLEYVIEW_MAX_WM,
493 .default_wm = VALLEYVIEW_MAX_WM,
494 .guard_size = 2,
495 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 496};
497static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 498 .fifo_size = I965_CURSOR_FIFO,
499 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
500 .default_wm = I965_CURSOR_DFT_WM,
501 .guard_size = 2,
502 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 503};
504static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 505 .fifo_size = I965_CURSOR_FIFO,
506 .max_wm = I965_CURSOR_MAX_WM,
507 .default_wm = I965_CURSOR_DFT_WM,
508 .guard_size = 2,
509 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 510};
511static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 512 .fifo_size = I945_FIFO_SIZE,
513 .max_wm = I915_MAX_WM,
514 .default_wm = 1,
515 .guard_size = 2,
516 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 517};
518static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 519 .fifo_size = I915_FIFO_SIZE,
520 .max_wm = I915_MAX_WM,
521 .default_wm = 1,
522 .guard_size = 2,
523 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 524};
9d539105 525static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 526 .fifo_size = I855GM_FIFO_SIZE,
527 .max_wm = I915_MAX_WM,
528 .default_wm = 1,
529 .guard_size = 2,
530 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 531};
9d539105
VS		 532static const struct intel_watermark_params i830_bc_wm_info = {
533 .fifo_size = I855GM_FIFO_SIZE,
534 .max_wm = I915_MAX_WM/2,
535 .default_wm = 1,
536 .guard_size = 2,
537 .cacheline_size = I830_FIFO_LINE_SIZE,
538};
feb56b93 539static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 540 .fifo_size = I830_FIFO_SIZE,
541 .max_wm = I915_MAX_WM,
542 .default_wm = 1,
543 .guard_size = 2,
544 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 545};
546
b445e3b0
ED		 547/**
548 * intel_calculate_wm - calculate watermark level
549 * @clock_in_khz: pixel clock
550 * @wm: chip FIFO params
ac484963 551 * @cpp: bytes per pixel
b445e3b0
ED		 552 * @latency_ns: memory latency for the platform
553 *
554 * Calculate the watermark level (the level at which the display plane will
555 * start fetching from memory again). Each chip has a different display
556 * FIFO size and allocation, so the caller needs to figure that out and pass
557 * in the correct intel_watermark_params structure.
558 *
559 * As the pixel clock runs, the FIFO will be drained at a rate that depends
560 * on the pixel size. When it reaches the watermark level, it'll start
561 * fetching FIFO line sized based chunks from memory until the FIFO fills
562 * past the watermark point. If the FIFO drains completely, a FIFO underrun
563 * will occur, and a display engine hang could result.
564 */
565static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
566 const struct intel_watermark_params *wm,
ac484963 567 int fifo_size, int cpp,
b445e3b0
ED		 568 unsigned long latency_ns)
569{
570 long entries_required, wm_size;
571
572 /*
573 * Note: we need to make sure we don't overflow for various clock &
574 * latency values.
575 * clocks go from a few thousand to several hundred thousand.
576 * latency is usually a few thousand
577 */
ac484963 578 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 579 1000;
580 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
581
582 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
583
584 wm_size = fifo_size - (entries_required + wm->guard_size);
585
586 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
587
588 /* Don't promote wm_size to unsigned... */
589 if (wm_size > (long)wm->max_wm)
590 wm_size = wm->max_wm;
591 if (wm_size <= 0)
592 wm_size = wm->default_wm;
d6feb196
VS		 593
594 /*
595 * Bspec seems to indicate that the value shouldn't be lower than
596 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
597 * Lets go for 8 which is the burst size since certain platforms
598 * already use a hardcoded 8 (which is what the spec says should be
599 * done).
600 */
601 if (wm_size <= 8)
602 wm_size = 8;
603
b445e3b0
ED		 604 return wm_size;
605}
606
607static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
608{
609 struct drm_crtc *crtc, *enabled = NULL;
610
70e1e0ec 611 for_each_crtc(dev, crtc) {
3490ea5d 612 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 613 if (enabled)
614 return NULL;
615 enabled = crtc;
616 }
617 }
618
619 return enabled;
620}
621
46ba614c 622static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 623{
46ba614c 624 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 625 struct drm_i915_private *dev_priv = dev->dev_private;
626 struct drm_crtc *crtc;
627 const struct cxsr_latency *latency;
628 u32 reg;
629 unsigned long wm;
630
631 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
632 dev_priv->fsb_freq, dev_priv->mem_freq);
633 if (!latency) {
634 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 635 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 636 return;
637 }
638
639 crtc = single_enabled_crtc(dev);
640 if (crtc) {
7c5f93b0 641 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 642 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 643 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 644
645 /* Display SR */
646 wm = intel_calculate_wm(clock, &pineview_display_wm,
647 pineview_display_wm.fifo_size,
ac484963 648 cpp, latency->display_sr);
b445e3b0
ED		 649 reg = I915_READ(DSPFW1);
650 reg &= ~DSPFW_SR_MASK;
f4998963 651 reg |= FW_WM(wm, SR);
b445e3b0
ED		 652 I915_WRITE(DSPFW1, reg);
653 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
654
655 /* cursor SR */
656 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
657 pineview_display_wm.fifo_size,
ac484963 658 cpp, latency->cursor_sr);
b445e3b0
ED		 659 reg = I915_READ(DSPFW3);
660 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 661 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 662 I915_WRITE(DSPFW3, reg);
663
664 /* Display HPLL off SR */
665 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
666 pineview_display_hplloff_wm.fifo_size,
ac484963 667 cpp, latency->display_hpll_disable);
b445e3b0
ED		 668 reg = I915_READ(DSPFW3);
669 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 670 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 671 I915_WRITE(DSPFW3, reg);
672
673 /* cursor HPLL off SR */
674 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
675 pineview_display_hplloff_wm.fifo_size,
ac484963 676 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 677 reg = I915_READ(DSPFW3);
678 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 679 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 680 I915_WRITE(DSPFW3, reg);
681 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
682
5209b1f4 683 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 684 } else {
5209b1f4 685 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 686 }
687}
688
689static bool g4x_compute_wm0(struct drm_device *dev,
690 int plane,
691 const struct intel_watermark_params *display,
692 int display_latency_ns,
693 const struct intel_watermark_params *cursor,
694 int cursor_latency_ns,
695 int *plane_wm,
696 int *cursor_wm)
697{
698 struct drm_crtc *crtc;
4fe8590a 699 const struct drm_display_mode *adjusted_mode;
ac484963 700 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 701 int line_time_us, line_count;
702 int entries, tlb_miss;
703
704 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 705 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 706 *cursor_wm = cursor->guard_size;
707 *plane_wm = display->guard_size;
708 return false;
709 }
710
6e3c9717 711 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 712 clock = adjusted_mode->crtc_clock;
fec8cba3 713 htotal = adjusted_mode->crtc_htotal;
6e3c9717 714 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 715 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 716
717 /* Use the small buffer method to calculate plane watermark */
ac484963 718 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 719 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
720 if (tlb_miss > 0)
721 entries += tlb_miss;
722 entries = DIV_ROUND_UP(entries, display->cacheline_size);
723 *plane_wm = entries + display->guard_size;
724 if (*plane_wm > (int)display->max_wm)
725 *plane_wm = display->max_wm;
726
727 /* Use the large buffer method to calculate cursor watermark */
922044c9 728 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 729 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 730 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 731 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
732 if (tlb_miss > 0)
733 entries += tlb_miss;
734 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
735 *cursor_wm = entries + cursor->guard_size;
736 if (*cursor_wm > (int)cursor->max_wm)
737 *cursor_wm = (int)cursor->max_wm;
738
739 return true;
740}
741
742/*
743 * Check the wm result.
744 *
745 * If any calculated watermark values is larger than the maximum value that
746 * can be programmed into the associated watermark register, that watermark
747 * must be disabled.
748 */
749static bool g4x_check_srwm(struct drm_device *dev,
750 int display_wm, int cursor_wm,
751 const struct intel_watermark_params *display,
752 const struct intel_watermark_params *cursor)
753{
754 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
755 display_wm, cursor_wm);
756
757 if (display_wm > display->max_wm) {
758 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
759 display_wm, display->max_wm);
760 return false;
761 }
762
763 if (cursor_wm > cursor->max_wm) {
764 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
765 cursor_wm, cursor->max_wm);
766 return false;
767 }
768
769 if (!(display_wm || cursor_wm)) {
770 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
771 return false;
772 }
773
774 return true;
775}
776
777static bool g4x_compute_srwm(struct drm_device *dev,
778 int plane,
779 int latency_ns,
780 const struct intel_watermark_params *display,
781 const struct intel_watermark_params *cursor,
782 int *display_wm, int *cursor_wm)
783{
784 struct drm_crtc *crtc;
4fe8590a 785 const struct drm_display_mode *adjusted_mode;
ac484963 786 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 787 unsigned long line_time_us;
788 int line_count, line_size;
789 int small, large;
790 int entries;
791
792 if (!latency_ns) {
793 *display_wm = *cursor_wm = 0;
794 return false;
795 }
796
797 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 798 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 799 clock = adjusted_mode->crtc_clock;
fec8cba3 800 htotal = adjusted_mode->crtc_htotal;
6e3c9717 801 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 802 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 803
922044c9 804 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 805 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 806 line_size = hdisplay * cpp;
b445e3b0
ED		 807
808 /* Use the minimum of the small and large buffer method for primary */
ac484963 809 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 810 large = line_count * line_size;
811
812 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
813 *display_wm = entries + display->guard_size;
814
815 /* calculate the self-refresh watermark for display cursor */
ac484963 816 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 817 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
818 *cursor_wm = entries + cursor->guard_size;
819
820 return g4x_check_srwm(dev,
821 *display_wm, *cursor_wm,
822 display, cursor);
823}
824
15665979
VS		 825#define FW_WM_VLV(value, plane) \
826 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
827
0018fda1
VS		 828static void vlv_write_wm_values(struct intel_crtc *crtc,
829 const struct vlv_wm_values *wm)
830{
831 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
832 enum pipe pipe = crtc->pipe;
833
834 I915_WRITE(VLV_DDL(pipe),
835 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
836 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
837 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
838 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
839
ae80152d 840 I915_WRITE(DSPFW1,
15665979
VS		 841 FW_WM(wm->sr.plane, SR) |
842 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
843 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
844 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 845 I915_WRITE(DSPFW2,
15665979
VS		 846 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
847 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
848 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 849 I915_WRITE(DSPFW3,
15665979 850 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 851
852 if (IS_CHERRYVIEW(dev_priv)) {
853 I915_WRITE(DSPFW7_CHV,
15665979
VS		 854 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
855 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 856 I915_WRITE(DSPFW8_CHV,
15665979
VS		 857 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
858 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 859 I915_WRITE(DSPFW9_CHV,
15665979
VS		 860 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
861 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 862 I915_WRITE(DSPHOWM,
15665979
VS		 863 FW_WM(wm->sr.plane >> 9, SR_HI) |
864 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
865 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
866 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
867 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
868 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
869 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
870 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
871 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
872 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 873 } else {
874 I915_WRITE(DSPFW7,
15665979
VS		 875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
876 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 877 I915_WRITE(DSPHOWM,
15665979
VS		 878 FW_WM(wm->sr.plane >> 9, SR_HI) |
879 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
880 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
881 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
882 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
883 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
884 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 885 }
886
2cb389b7
VS		 887 /* zero (unused) WM1 watermarks */
888 I915_WRITE(DSPFW4, 0);
889 I915_WRITE(DSPFW5, 0);
890 I915_WRITE(DSPFW6, 0);
891 I915_WRITE(DSPHOWM1, 0);
892
ae80152d 893 POSTING_READ(DSPFW1);
0018fda1
VS		 894}
895
15665979
VS		 896#undef FW_WM_VLV
897
6eb1a681
VS		 898enum vlv_wm_level {
899 VLV_WM_LEVEL_PM2,
900 VLV_WM_LEVEL_PM5,
901 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 902};
903
262cd2e1
VS		 904/* latency must be in 0.1us units. */
905static unsigned int vlv_wm_method2(unsigned int pixel_rate,
906 unsigned int pipe_htotal,
907 unsigned int horiz_pixels,
ac484963 908 unsigned int cpp,
262cd2e1
VS		 909 unsigned int latency)
910{
911 unsigned int ret;
912
913 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 914 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 915 ret = DIV_ROUND_UP(ret, 64);
916
917 return ret;
918}
919
920static void vlv_setup_wm_latency(struct drm_device *dev)
921{
922 struct drm_i915_private *dev_priv = dev->dev_private;
923
924 /* all latencies in usec */
925 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
926
58590c14
VS		 927 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
928
262cd2e1
VS		 929 if (IS_CHERRYVIEW(dev_priv)) {
930 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
931 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 932
933 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 934 }
935}
936
937static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
938 struct intel_crtc *crtc,
939 const struct intel_plane_state *state,
940 int level)
941{
942 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 943 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 944
945 if (dev_priv->wm.pri_latency[level] == 0)
946 return USHRT_MAX;
947
948 if (!state->visible)
949 return 0;
950
ac484963 951 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 952 clock = crtc->config->base.adjusted_mode.crtc_clock;
953 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
954 width = crtc->config->pipe_src_w;
955 if (WARN_ON(htotal == 0))
956 htotal = 1;
957
958 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
959 /*
960 * FIXME the formula gives values that are
961 * too big for the cursor FIFO, and hence we
962 * would never be able to use cursors. For
963 * now just hardcode the watermark.
964 */
965 wm = 63;
966 } else {
ac484963 967 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 968 dev_priv->wm.pri_latency[level] * 10);
969 }
970
971 return min_t(int, wm, USHRT_MAX);
972}
973
54f1b6e1
VS		 974static void vlv_compute_fifo(struct intel_crtc *crtc)
975{
976 struct drm_device *dev = crtc->base.dev;
977 struct vlv_wm_state *wm_state = &crtc->wm_state;
978 struct intel_plane *plane;
979 unsigned int total_rate = 0;
980 const int fifo_size = 512 - 1;
981 int fifo_extra, fifo_left = fifo_size;
982
983 for_each_intel_plane_on_crtc(dev, crtc, plane) {
984 struct intel_plane_state *state =
985 to_intel_plane_state(plane->base.state);
986
987 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
988 continue;
989
990 if (state->visible) {
991 wm_state->num_active_planes++;
992 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
993 }
994 }
995
996 for_each_intel_plane_on_crtc(dev, crtc, plane) {
997 struct intel_plane_state *state =
998 to_intel_plane_state(plane->base.state);
999 unsigned int rate;
1000
1001 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1002 plane->wm.fifo_size = 63;
1003 continue;
1004 }
1005
1006 if (!state->visible) {
1007 plane->wm.fifo_size = 0;
1008 continue;
1009 }
1010
1011 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1012 plane->wm.fifo_size = fifo_size * rate / total_rate;
1013 fifo_left -= plane->wm.fifo_size;
1014 }
1015
1016 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1017
1018 /* spread the remainder evenly */
1019 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1020 int plane_extra;
1021
1022 if (fifo_left == 0)
1023 break;
1024
1025 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1026 continue;
1027
1028 /* give it all to the first plane if none are active */
1029 if (plane->wm.fifo_size == 0 &&
1030 wm_state->num_active_planes)
1031 continue;
1032
1033 plane_extra = min(fifo_extra, fifo_left);
1034 plane->wm.fifo_size += plane_extra;
1035 fifo_left -= plane_extra;
1036 }
1037
1038 WARN_ON(fifo_left != 0);
1039}
1040
262cd2e1
VS		 1041static void vlv_invert_wms(struct intel_crtc *crtc)
1042{
1043 struct vlv_wm_state *wm_state = &crtc->wm_state;
1044 int level;
1045
1046 for (level = 0; level < wm_state->num_levels; level++) {
1047 struct drm_device *dev = crtc->base.dev;
1048 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1049 struct intel_plane *plane;
1050
1051 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1052 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1053
1054 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1055 switch (plane->base.type) {
1056 int sprite;
1057 case DRM_PLANE_TYPE_CURSOR:
1058 wm_state->wm[level].cursor = plane->wm.fifo_size -
1059 wm_state->wm[level].cursor;
1060 break;
1061 case DRM_PLANE_TYPE_PRIMARY:
1062 wm_state->wm[level].primary = plane->wm.fifo_size -
1063 wm_state->wm[level].primary;
1064 break;
1065 case DRM_PLANE_TYPE_OVERLAY:
1066 sprite = plane->plane;
1067 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1068 wm_state->wm[level].sprite[sprite];
1069 break;
1070 }
1071 }
1072 }
1073}
1074
26e1fe4f 1075static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1076{
1077 struct drm_device *dev = crtc->base.dev;
1078 struct vlv_wm_state *wm_state = &crtc->wm_state;
1079 struct intel_plane *plane;
1080 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1081 int level;
1082
1083 memset(wm_state, 0, sizeof(*wm_state));
1084
852eb00d 1085 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1086 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1087
1088 wm_state->num_active_planes = 0;
262cd2e1 1089
54f1b6e1 1090 vlv_compute_fifo(crtc);
262cd2e1
VS		 1091
1092 if (wm_state->num_active_planes != 1)
1093 wm_state->cxsr = false;
1094
1095 if (wm_state->cxsr) {
1096 for (level = 0; level < wm_state->num_levels; level++) {
1097 wm_state->sr[level].plane = sr_fifo_size;
1098 wm_state->sr[level].cursor = 63;
1099 }
1100 }
1101
1102 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1103 struct intel_plane_state *state =
1104 to_intel_plane_state(plane->base.state);
1105
1106 if (!state->visible)
1107 continue;
1108
1109 /* normal watermarks */
1110 for (level = 0; level < wm_state->num_levels; level++) {
1111 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1112 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1113
1114 /* hack */
1115 if (WARN_ON(level == 0 && wm > max_wm))
1116 wm = max_wm;
1117
1118 if (wm > plane->wm.fifo_size)
1119 break;
1120
1121 switch (plane->base.type) {
1122 int sprite;
1123 case DRM_PLANE_TYPE_CURSOR:
1124 wm_state->wm[level].cursor = wm;
1125 break;
1126 case DRM_PLANE_TYPE_PRIMARY:
1127 wm_state->wm[level].primary = wm;
1128 break;
1129 case DRM_PLANE_TYPE_OVERLAY:
1130 sprite = plane->plane;
1131 wm_state->wm[level].sprite[sprite] = wm;
1132 break;
1133 }
1134 }
1135
1136 wm_state->num_levels = level;
1137
1138 if (!wm_state->cxsr)
1139 continue;
1140
1141 /* maxfifo watermarks */
1142 switch (plane->base.type) {
1143 int sprite, level;
1144 case DRM_PLANE_TYPE_CURSOR:
1145 for (level = 0; level < wm_state->num_levels; level++)
1146 wm_state->sr[level].cursor =
5a37ed0a 1147 wm_state->wm[level].cursor;
262cd2e1
VS		 1148 break;
1149 case DRM_PLANE_TYPE_PRIMARY:
1150 for (level = 0; level < wm_state->num_levels; level++)
1151 wm_state->sr[level].plane =
1152 min(wm_state->sr[level].plane,
1153 wm_state->wm[level].primary);
1154 break;
1155 case DRM_PLANE_TYPE_OVERLAY:
1156 sprite = plane->plane;
1157 for (level = 0; level < wm_state->num_levels; level++)
1158 wm_state->sr[level].plane =
1159 min(wm_state->sr[level].plane,
1160 wm_state->wm[level].sprite[sprite]);
1161 break;
1162 }
1163 }
1164
1165 /* clear any (partially) filled invalid levels */
58590c14 1166 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1167 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1168 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1169 }
1170
1171 vlv_invert_wms(crtc);
1172}
1173
54f1b6e1
VS		 1174#define VLV_FIFO(plane, value) \
1175 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1176
1177static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1178{
1179 struct drm_device *dev = crtc->base.dev;
1180 struct drm_i915_private *dev_priv = to_i915(dev);
1181 struct intel_plane *plane;
1182 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1183
1184 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1185 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1186 WARN_ON(plane->wm.fifo_size != 63);
1187 continue;
1188 }
1189
1190 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1191 sprite0_start = plane->wm.fifo_size;
1192 else if (plane->plane == 0)
1193 sprite1_start = sprite0_start + plane->wm.fifo_size;
1194 else
1195 fifo_size = sprite1_start + plane->wm.fifo_size;
1196 }
1197
1198 WARN_ON(fifo_size != 512 - 1);
1199
1200 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1201 pipe_name(crtc->pipe), sprite0_start,
1202 sprite1_start, fifo_size);
1203
1204 switch (crtc->pipe) {
1205 uint32_t dsparb, dsparb2, dsparb3;
1206 case PIPE_A:
1207 dsparb = I915_READ(DSPARB);
1208 dsparb2 = I915_READ(DSPARB2);
1209
1210 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1211 VLV_FIFO(SPRITEB, 0xff));
1212 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1213 VLV_FIFO(SPRITEB, sprite1_start));
1214
1215 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1216 VLV_FIFO(SPRITEB_HI, 0x1));
1217 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1218 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1219
1220 I915_WRITE(DSPARB, dsparb);
1221 I915_WRITE(DSPARB2, dsparb2);
1222 break;
1223 case PIPE_B:
1224 dsparb = I915_READ(DSPARB);
1225 dsparb2 = I915_READ(DSPARB2);
1226
1227 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1228 VLV_FIFO(SPRITED, 0xff));
1229 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1230 VLV_FIFO(SPRITED, sprite1_start));
1231
1232 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1233 VLV_FIFO(SPRITED_HI, 0xff));
1234 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1235 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1236
1237 I915_WRITE(DSPARB, dsparb);
1238 I915_WRITE(DSPARB2, dsparb2);
1239 break;
1240 case PIPE_C:
1241 dsparb3 = I915_READ(DSPARB3);
1242 dsparb2 = I915_READ(DSPARB2);
1243
1244 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1245 VLV_FIFO(SPRITEF, 0xff));
1246 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1247 VLV_FIFO(SPRITEF, sprite1_start));
1248
1249 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1250 VLV_FIFO(SPRITEF_HI, 0xff));
1251 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1252 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1253
1254 I915_WRITE(DSPARB3, dsparb3);
1255 I915_WRITE(DSPARB2, dsparb2);
1256 break;
1257 default:
1258 break;
1259 }
1260}
1261
1262#undef VLV_FIFO
1263
262cd2e1
VS		 1264static void vlv_merge_wm(struct drm_device *dev,
1265 struct vlv_wm_values *wm)
1266{
1267 struct intel_crtc *crtc;
1268 int num_active_crtcs = 0;
1269
58590c14 1270 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1271 wm->cxsr = true;
1272
1273 for_each_intel_crtc(dev, crtc) {
1274 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1275
1276 if (!crtc->active)
1277 continue;
1278
1279 if (!wm_state->cxsr)
1280 wm->cxsr = false;
1281
1282 num_active_crtcs++;
1283 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1284 }
1285
1286 if (num_active_crtcs != 1)
1287 wm->cxsr = false;
1288
6f9c784b
VS		 1289 if (num_active_crtcs > 1)
1290 wm->level = VLV_WM_LEVEL_PM2;
1291
262cd2e1
VS		 1292 for_each_intel_crtc(dev, crtc) {
1293 struct vlv_wm_state *wm_state = &crtc->wm_state;
1294 enum pipe pipe = crtc->pipe;
1295
1296 if (!crtc->active)
1297 continue;
1298
1299 wm->pipe[pipe] = wm_state->wm[wm->level];
1300 if (wm->cxsr)
1301 wm->sr = wm_state->sr[wm->level];
1302
1303 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1304 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1305 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1306 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1307 }
1308}
1309
1310static void vlv_update_wm(struct drm_crtc *crtc)
1311{
1312 struct drm_device *dev = crtc->dev;
1313 struct drm_i915_private *dev_priv = dev->dev_private;
1314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1315 enum pipe pipe = intel_crtc->pipe;
1316 struct vlv_wm_values wm = {};
1317
26e1fe4f 1318 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1319 vlv_merge_wm(dev, &wm);
1320
54f1b6e1
VS		 1321 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1322 /* FIXME should be part of crtc atomic commit */
1323 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1324 return;
54f1b6e1 1325 }
262cd2e1
VS		 1326
1327 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1328 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1329 chv_set_memory_dvfs(dev_priv, false);
1330
1331 if (wm.level < VLV_WM_LEVEL_PM5 &&
1332 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1333 chv_set_memory_pm5(dev_priv, false);
1334
852eb00d 1335 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1336 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1337
54f1b6e1
VS		 1338 /* FIXME should be part of crtc atomic commit */
1339 vlv_pipe_set_fifo_size(intel_crtc);
1340
262cd2e1
VS		 1341 vlv_write_wm_values(intel_crtc, &wm);
1342
1343 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1344 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1345 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1346 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1347 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1348
852eb00d 1349 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1350 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1351
1352 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1353 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1354 chv_set_memory_pm5(dev_priv, true);
1355
1356 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1357 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1358 chv_set_memory_dvfs(dev_priv, true);
1359
1360 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1361}
1362
ae80152d
VS		 1363#define single_plane_enabled(mask) is_power_of_2(mask)
1364
46ba614c 1365static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1366{
46ba614c 1367 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1368 static const int sr_latency_ns = 12000;
1369 struct drm_i915_private *dev_priv = dev->dev_private;
1370 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1371 int plane_sr, cursor_sr;
1372 unsigned int enabled = 0;
9858425c 1373 bool cxsr_enabled;
b445e3b0 1374
51cea1f4 1375 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1376 &g4x_wm_info, pessimal_latency_ns,
1377 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1378 &planea_wm, &cursora_wm))
51cea1f4 1379 enabled |= 1 << PIPE_A;
b445e3b0 1380
51cea1f4 1381 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1382 &g4x_wm_info, pessimal_latency_ns,
1383 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1384 &planeb_wm, &cursorb_wm))
51cea1f4 1385 enabled |= 1 << PIPE_B;
b445e3b0 1386
b445e3b0
ED		 1387 if (single_plane_enabled(enabled) &&
1388 g4x_compute_srwm(dev, ffs(enabled) - 1,
1389 sr_latency_ns,
1390 &g4x_wm_info,
1391 &g4x_cursor_wm_info,
52bd02d8 1392 &plane_sr, &cursor_sr)) {
9858425c 1393 cxsr_enabled = true;
52bd02d8 1394 } else {
9858425c 1395 cxsr_enabled = false;
5209b1f4 1396 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1397 plane_sr = cursor_sr = 0;
1398 }
b445e3b0 1399
a5043453
VS		 1400 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1401 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1402 planea_wm, cursora_wm,
1403 planeb_wm, cursorb_wm,
1404 plane_sr, cursor_sr);
1405
1406 I915_WRITE(DSPFW1,
f4998963
VS		 1407 FW_WM(plane_sr, SR) |
1408 FW_WM(cursorb_wm, CURSORB) |
1409 FW_WM(planeb_wm, PLANEB) |
1410 FW_WM(planea_wm, PLANEA));
b445e3b0 1411 I915_WRITE(DSPFW2,
8c919b28 1412 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1413 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1414 /* HPLL off in SR has some issues on G4x... disable it */
1415 I915_WRITE(DSPFW3,
8c919b28 1416 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1417 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1418
1419 if (cxsr_enabled)
1420 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1421}
1422
46ba614c 1423static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1424{
46ba614c 1425 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1426 struct drm_i915_private *dev_priv = dev->dev_private;
1427 struct drm_crtc *crtc;
1428 int srwm = 1;
1429 int cursor_sr = 16;
9858425c 1430 bool cxsr_enabled;
b445e3b0
ED		 1431
1432 /* Calc sr entries for one plane configs */
1433 crtc = single_enabled_crtc(dev);
1434 if (crtc) {
1435 /* self-refresh has much higher latency */
1436 static const int sr_latency_ns = 12000;
124abe07 1437 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1438 int clock = adjusted_mode->crtc_clock;
fec8cba3 1439 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1440 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1441 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1442 unsigned long line_time_us;
1443 int entries;
1444
922044c9 1445 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1446
1447 /* Use ns/us then divide to preserve precision */
1448 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1449 cpp * hdisplay;
b445e3b0
ED		 1450 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1451 srwm = I965_FIFO_SIZE - entries;
1452 if (srwm < 0)
1453 srwm = 1;
1454 srwm &= 0x1ff;
1455 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1456 entries, srwm);
1457
1458 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1459 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1460 entries = DIV_ROUND_UP(entries,
1461 i965_cursor_wm_info.cacheline_size);
1462 cursor_sr = i965_cursor_wm_info.fifo_size -
1463 (entries + i965_cursor_wm_info.guard_size);
1464
1465 if (cursor_sr > i965_cursor_wm_info.max_wm)
1466 cursor_sr = i965_cursor_wm_info.max_wm;
1467
1468 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1469 "cursor %d\n", srwm, cursor_sr);
1470
9858425c 1471 cxsr_enabled = true;
b445e3b0 1472 } else {
9858425c 1473 cxsr_enabled = false;
b445e3b0 1474 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1475 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1476 }
1477
1478 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1479 srwm);
1480
1481 /* 965 has limitations... */
f4998963
VS		 1482 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1483 FW_WM(8, CURSORB) |
1484 FW_WM(8, PLANEB) |
1485 FW_WM(8, PLANEA));
1486 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1487 FW_WM(8, PLANEC_OLD));
b445e3b0 1488 /* update cursor SR watermark */
f4998963 1489 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1490
1491 if (cxsr_enabled)
1492 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1493}
1494
f4998963
VS		 1495#undef FW_WM
1496
46ba614c 1497static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1498{
46ba614c 1499 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1500 struct drm_i915_private *dev_priv = dev->dev_private;
1501 const struct intel_watermark_params *wm_info;
1502 uint32_t fwater_lo;
1503 uint32_t fwater_hi;
1504 int cwm, srwm = 1;
1505 int fifo_size;
1506 int planea_wm, planeb_wm;
1507 struct drm_crtc *crtc, *enabled = NULL;
1508
1509 if (IS_I945GM(dev))
1510 wm_info = &i945_wm_info;
1511 else if (!IS_GEN2(dev))
1512 wm_info = &i915_wm_info;
1513 else
9d539105 1514 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1515
1516 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1517 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1518 if (intel_crtc_active(crtc)) {
241bfc38 1519 const struct drm_display_mode *adjusted_mode;
ac484963 1520 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1521 if (IS_GEN2(dev))
1522 cpp = 4;
1523
6e3c9717 1524 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1525 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1526 wm_info, fifo_size, cpp,
5aef6003 1527 pessimal_latency_ns);
b445e3b0 1528 enabled = crtc;
9d539105 1529 } else {
b445e3b0 1530 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1531 if (planea_wm > (long)wm_info->max_wm)
1532 planea_wm = wm_info->max_wm;
1533 }
1534
1535 if (IS_GEN2(dev))
1536 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1537
1538 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1539 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1540 if (intel_crtc_active(crtc)) {
241bfc38 1541 const struct drm_display_mode *adjusted_mode;
ac484963 1542 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1543 if (IS_GEN2(dev))
1544 cpp = 4;
1545
6e3c9717 1546 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1547 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1548 wm_info, fifo_size, cpp,
5aef6003 1549 pessimal_latency_ns);
b445e3b0
ED		 1550 if (enabled == NULL)
1551 enabled = crtc;
1552 else
1553 enabled = NULL;
9d539105 1554 } else {
b445e3b0 1555 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1556 if (planeb_wm > (long)wm_info->max_wm)
1557 planeb_wm = wm_info->max_wm;
1558 }
b445e3b0
ED		 1559
1560 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1561
2ab1bc9d 1562 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1563 struct drm_i915_gem_object *obj;
2ab1bc9d 1564
59bea882 1565 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1566
1567 /* self-refresh seems busted with untiled */
2ff8fde1 1568 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1569 enabled = NULL;
1570 }
1571
b445e3b0
ED		 1572 /*
1573 * Overlay gets an aggressive default since video jitter is bad.
1574 */
1575 cwm = 2;
1576
1577 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1578 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1579
1580 /* Calc sr entries for one plane configs */
1581 if (HAS_FW_BLC(dev) && enabled) {
1582 /* self-refresh has much higher latency */
1583 static const int sr_latency_ns = 6000;
124abe07 1584 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1585 int clock = adjusted_mode->crtc_clock;
fec8cba3 1586 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1587 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1588 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1589 unsigned long line_time_us;
1590 int entries;
1591
922044c9 1592 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1593
1594 /* Use ns/us then divide to preserve precision */
1595 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1596 cpp * hdisplay;
b445e3b0
ED		 1597 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1598 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1599 srwm = wm_info->fifo_size - entries;
1600 if (srwm < 0)
1601 srwm = 1;
1602
1603 if (IS_I945G(dev) || IS_I945GM(dev))
1604 I915_WRITE(FW_BLC_SELF,
1605 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1606 else if (IS_I915GM(dev))
1607 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1608 }
1609
1610 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1611 planea_wm, planeb_wm, cwm, srwm);
1612
1613 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1614 fwater_hi = (cwm & 0x1f);
1615
1616 /* Set request length to 8 cachelines per fetch */
1617 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1618 fwater_hi = fwater_hi | (1 << 8);
1619
1620 I915_WRITE(FW_BLC, fwater_lo);
1621 I915_WRITE(FW_BLC2, fwater_hi);
1622
5209b1f4
ID		 1623 if (enabled)
1624 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1625}
1626
feb56b93 1627static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1628{
46ba614c 1629 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631 struct drm_crtc *crtc;
241bfc38 1632 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1633 uint32_t fwater_lo;
1634 int planea_wm;
1635
1636 crtc = single_enabled_crtc(dev);
1637 if (crtc == NULL)
1638 return;
1639
6e3c9717 1640 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1641 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1642 &i845_wm_info,
b445e3b0 1643 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1644 4, pessimal_latency_ns);
b445e3b0
ED		 1645 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1646 fwater_lo |= (3<<8) | planea_wm;
1647
1648 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1649
1650 I915_WRITE(FW_BLC, fwater_lo);
1651}
1652
8cfb3407 1653uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1654{
fd4daa9c 1655 uint32_t pixel_rate;
801bcfff 1656
8cfb3407 1657 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1658
1659 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1660 * adjust the pixel_rate here. */
1661
8cfb3407 1662 if (pipe_config->pch_pfit.enabled) {
801bcfff 1663 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1664 uint32_t pfit_size = pipe_config->pch_pfit.size;
1665
1666 pipe_w = pipe_config->pipe_src_w;
1667 pipe_h = pipe_config->pipe_src_h;
801bcfff 1668
801bcfff
PZ		 1669 pfit_w = (pfit_size >> 16) & 0xFFFF;
1670 pfit_h = pfit_size & 0xFFFF;
1671 if (pipe_w < pfit_w)
1672 pipe_w = pfit_w;
1673 if (pipe_h < pfit_h)
1674 pipe_h = pfit_h;
1675
15126882
MR		 1676 if (WARN_ON(!pfit_w || !pfit_h))
1677 return pixel_rate;
1678
801bcfff
PZ		 1679 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1680 pfit_w * pfit_h);
1681 }
1682
1683 return pixel_rate;
1684}
1685
37126462 1686/* latency must be in 0.1us units. */
ac484963 1687static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1688{
1689 uint64_t ret;
1690
3312ba65
VS		 1691 if (WARN(latency == 0, "Latency value missing\n"))
1692 return UINT_MAX;
1693
ac484963 1694 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1695 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1696
1697 return ret;
1698}
1699
37126462 1700/* latency must be in 0.1us units. */
23297044 1701static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1702 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1703 uint32_t latency)
1704{
1705 uint32_t ret;
1706
3312ba65
VS		 1707 if (WARN(latency == 0, "Latency value missing\n"))
1708 return UINT_MAX;
15126882
MR		 1709 if (WARN_ON(!pipe_htotal))
1710 return UINT_MAX;
3312ba65 1711
801bcfff 1712 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1713 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1714 ret = DIV_ROUND_UP(ret, 64) + 2;
1715 return ret;
1716}
1717
23297044 1718static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1719 uint8_t cpp)
cca32e9a 1720{
15126882
MR		 1721 /*
1722 * Neither of these should be possible since this function shouldn't be
1723 * called if the CRTC is off or the plane is invisible. But let's be
1724 * extra paranoid to avoid a potential divide-by-zero if we screw up
1725 * elsewhere in the driver.
1726 */
ac484963 1727 if (WARN_ON(!cpp))
15126882
MR		 1728 return 0;
1729 if (WARN_ON(!horiz_pixels))
1730 return 0;
1731
ac484963 1732 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1733}
1734
820c1980 1735struct ilk_wm_maximums {
cca32e9a
PZ		 1736 uint16_t pri;
1737 uint16_t spr;
1738 uint16_t cur;
1739 uint16_t fbc;
1740};
1741
37126462
VS		 1742/*
1743 * For both WM_PIPE and WM_LP.
1744 * mem_value must be in 0.1us units.
1745 */
7221fc33 1746static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1747 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1748 uint32_t mem_value,
1749 bool is_lp)
801bcfff 1750{
ac484963
VS		 1751 int cpp = pstate->base.fb ?
1752 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1753 uint32_t method1, method2;
1754
7221fc33 1755 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1756 return 0;
1757
ac484963 1758 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1759
1760 if (!is_lp)
1761 return method1;
1762
7221fc33
MR		 1763 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1764 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1765 drm_rect_width(&pstate->dst),
ac484963 1766 cpp, mem_value);
cca32e9a
PZ		 1767
1768 return min(method1, method2);
801bcfff
PZ		 1769}
1770
37126462
VS		 1771/*
1772 * For both WM_PIPE and WM_LP.
1773 * mem_value must be in 0.1us units.
1774 */
7221fc33 1775static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1776 const struct intel_plane_state *pstate,
801bcfff
PZ		 1777 uint32_t mem_value)
1778{
ac484963
VS		 1779 int cpp = pstate->base.fb ?
1780 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1781 uint32_t method1, method2;
1782
7221fc33 1783 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1784 return 0;
1785
ac484963 1786 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1787 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1788 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1789 drm_rect_width(&pstate->dst),
ac484963 1790 cpp, mem_value);
801bcfff
PZ		 1791 return min(method1, method2);
1792}
1793
37126462
VS		 1794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
7221fc33 1798static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1799 const struct intel_plane_state *pstate,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
b2435692
MR		 1802 /*
1803 * We treat the cursor plane as always-on for the purposes of watermark
1804 * calculation. Until we have two-stage watermark programming merged,
1805 * this is necessary to avoid flickering.
1806 */
1807 int cpp = 4;
1808 int width = pstate->visible ? pstate->base.crtc_w : 64;
43d59eda 1809
b2435692 1810 if (!cstate->base.active)
801bcfff
PZ		 1811 return 0;
1812
7221fc33
MR		 1813 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1814 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1815 width, cpp, mem_value);
801bcfff
PZ		 1816}
1817
cca32e9a 1818/* Only for WM_LP. */
7221fc33 1819static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1820 const struct intel_plane_state *pstate,
1fda9882 1821 uint32_t pri_val)
cca32e9a 1822{
ac484963
VS		 1823 int cpp = pstate->base.fb ?
1824 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1825
7221fc33 1826 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1827 return 0;
1828
ac484963 1829 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
cca32e9a
PZ		 1830}
1831
158ae64f
VS		 1832static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1833{
416f4727
VS		 1834 if (INTEL_INFO(dev)->gen >= 8)
1835 return 3072;
1836 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1837 return 768;
1838 else
1839 return 512;
1840}
1841
4e975081
VS		 1842static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1843 int level, bool is_sprite)
1844{
1845 if (INTEL_INFO(dev)->gen >= 8)
1846 /* BDW primary/sprite plane watermarks */
1847 return level == 0 ? 255 : 2047;
1848 else if (INTEL_INFO(dev)->gen >= 7)
1849 /* IVB/HSW primary/sprite plane watermarks */
1850 return level == 0 ? 127 : 1023;
1851 else if (!is_sprite)
1852 /* ILK/SNB primary plane watermarks */
1853 return level == 0 ? 127 : 511;
1854 else
1855 /* ILK/SNB sprite plane watermarks */
1856 return level == 0 ? 63 : 255;
1857}
1858
1859static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1860 int level)
1861{
1862 if (INTEL_INFO(dev)->gen >= 7)
1863 return level == 0 ? 63 : 255;
1864 else
1865 return level == 0 ? 31 : 63;
1866}
1867
1868static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1869{
1870 if (INTEL_INFO(dev)->gen >= 8)
1871 return 31;
1872 else
1873 return 15;
1874}
1875
158ae64f
VS		 1876/* Calculate the maximum primary/sprite plane watermark */
1877static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1878 int level,
240264f4 1879 const struct intel_wm_config *config,
158ae64f
VS		 1880 enum intel_ddb_partitioning ddb_partitioning,
1881 bool is_sprite)
1882{
1883 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1884
1885 /* if sprites aren't enabled, sprites get nothing */
240264f4 1886 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1887 return 0;
1888
1889 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1890 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1891 fifo_size /= INTEL_INFO(dev)->num_pipes;
1892
1893 /*
1894 * For some reason the non self refresh
1895 * FIFO size is only half of the self
1896 * refresh FIFO size on ILK/SNB.
1897 */
1898 if (INTEL_INFO(dev)->gen <= 6)
1899 fifo_size /= 2;
1900 }
1901
240264f4 1902 if (config->sprites_enabled) {
158ae64f
VS		 1903 /* level 0 is always calculated with 1:1 split */
1904 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1905 if (is_sprite)
1906 fifo_size *= 5;
1907 fifo_size /= 6;
1908 } else {
1909 fifo_size /= 2;
1910 }
1911 }
1912
1913 /* clamp to max that the registers can hold */
4e975081 1914 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1915}
1916
1917/* Calculate the maximum cursor plane watermark */
1918static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1919 int level,
1920 const struct intel_wm_config *config)
158ae64f
VS		 1921{
1922 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1923 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1924 return 64;
1925
1926 /* otherwise just report max that registers can hold */
4e975081 1927 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1928}
1929
d34ff9c6 1930static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1931 int level,
1932 const struct intel_wm_config *config,
1933 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1934 struct ilk_wm_maximums *max)
158ae64f 1935{
240264f4
VS		 1936 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1937 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1938 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1939 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1940}
1941
a3cb4048
VS		 1942static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1943 int level,
1944 struct ilk_wm_maximums *max)
1945{
1946 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1947 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1948 max->cur = ilk_cursor_wm_reg_max(dev, level);
1949 max->fbc = ilk_fbc_wm_reg_max(dev);
1950}
1951
d9395655 1952static bool ilk_validate_wm_level(int level,
820c1980 1953 const struct ilk_wm_maximums *max,
d9395655 1954 struct intel_wm_level *result)
a9786a11
VS		 1955{
1956 bool ret;
1957
1958 /* already determined to be invalid? */
1959 if (!result->enable)
1960 return false;
1961
1962 result->enable = result->pri_val <= max->pri &&
1963 result->spr_val <= max->spr &&
1964 result->cur_val <= max->cur;
1965
1966 ret = result->enable;
1967
1968 /*
1969 * HACK until we can pre-compute everything,
1970 * and thus fail gracefully if LP0 watermarks
1971 * are exceeded...
1972 */
1973 if (level == 0 && !result->enable) {
1974 if (result->pri_val > max->pri)
1975 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1976 level, result->pri_val, max->pri);
1977 if (result->spr_val > max->spr)
1978 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1979 level, result->spr_val, max->spr);
1980 if (result->cur_val > max->cur)
1981 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1982 level, result->cur_val, max->cur);
1983
1984 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1985 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1986 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1987 result->enable = true;
1988 }
1989
a9786a11
VS		 1990 return ret;
1991}
1992
d34ff9c6 1993static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 1994 const struct intel_crtc *intel_crtc,
6f5ddd17 1995 int level,
7221fc33 1996 struct intel_crtc_state *cstate,
86c8bbbe
MR		 1997 struct intel_plane_state *pristate,
1998 struct intel_plane_state *sprstate,
1999 struct intel_plane_state *curstate,
1fd527cc 2000 struct intel_wm_level *result)
6f5ddd17
VS		 2001{
2002 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2003 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2004 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2005
2006 /* WM1+ latency values stored in 0.5us units */
2007 if (level > 0) {
2008 pri_latency *= 5;
2009 spr_latency *= 5;
2010 cur_latency *= 5;
2011 }
2012
86c8bbbe
MR		 2013 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2014 pri_latency, level);
2015 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2016 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2017 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
6f5ddd17
VS		 2018 result->enable = true;
2019}
2020
801bcfff 2021static uint32_t
ee91a159
MR		 2022hsw_compute_linetime_wm(struct drm_device *dev,
2023 struct intel_crtc_state *cstate)
1f8eeabf
ED		 2024{
2025 struct drm_i915_private *dev_priv = dev->dev_private;
ee91a159
MR		 2026 const struct drm_display_mode *adjusted_mode =
2027 &cstate->base.adjusted_mode;
85a02deb 2028 u32 linetime, ips_linetime;
1f8eeabf 2029
ee91a159
MR		 2030 if (!cstate->base.active)
2031 return 0;
2032 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2033 return 0;
2034 if (WARN_ON(dev_priv->cdclk_freq == 0))
801bcfff 2035 return 0;
1011d8c4 2036
1f8eeabf
ED		 2037 /* The WM are computed with base on how long it takes to fill a single
2038 * row at the given clock rate, multiplied by 8.
2039 * */
124abe07
VS		 2040 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2041 adjusted_mode->crtc_clock);
2042 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
05024da3 2043 dev_priv->cdclk_freq);
1f8eeabf 2044
801bcfff
PZ		 2045 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2046 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2047}
2048
2af30a5c 2049static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2050{
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052
2af30a5c
PB		 2053 if (IS_GEN9(dev)) {
2054 uint32_t val;
4f947386 2055 int ret, i;
367294be 2056 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2057
2058 /* read the first set of memory latencies[0:3] */
2059 val = 0; /* data0 to be programmed to 0 for first set */
2060 mutex_lock(&dev_priv->rps.hw_lock);
2061 ret = sandybridge_pcode_read(dev_priv,
2062 GEN9_PCODE_READ_MEM_LATENCY,
2063 &val);
2064 mutex_unlock(&dev_priv->rps.hw_lock);
2065
2066 if (ret) {
2067 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2068 return;
2069 }
2070
2071 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2072 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2073 GEN9_MEM_LATENCY_LEVEL_MASK;
2074 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2075 GEN9_MEM_LATENCY_LEVEL_MASK;
2076 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2077 GEN9_MEM_LATENCY_LEVEL_MASK;
2078
2079 /* read the second set of memory latencies[4:7] */
2080 val = 1; /* data0 to be programmed to 1 for second set */
2081 mutex_lock(&dev_priv->rps.hw_lock);
2082 ret = sandybridge_pcode_read(dev_priv,
2083 GEN9_PCODE_READ_MEM_LATENCY,
2084 &val);
2085 mutex_unlock(&dev_priv->rps.hw_lock);
2086 if (ret) {
2087 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2088 return;
2089 }
2090
2091 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2092 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2093 GEN9_MEM_LATENCY_LEVEL_MASK;
2094 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2095 GEN9_MEM_LATENCY_LEVEL_MASK;
2096 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2097 GEN9_MEM_LATENCY_LEVEL_MASK;
2098
367294be 2099 /*
6f97235b
DL		 2100 * WaWmMemoryReadLatency:skl
2101 *
367294be
VK		 2102 * punit doesn't take into account the read latency so we need
2103 * to add 2us to the various latency levels we retrieve from
2104 * the punit.
2105 * - W0 is a bit special in that it's the only level that
2106 * can't be disabled if we want to have display working, so
2107 * we always add 2us there.
2108 * - For levels >=1, punit returns 0us latency when they are
2109 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2110 *
2111 * Additionally, if a level n (n > 1) has a 0us latency, all
2112 * levels m (m >= n) need to be disabled. We make sure to
2113 * sanitize the values out of the punit to satisfy this
2114 * requirement.
367294be
VK		 2115 */
2116 wm[0] += 2;
2117 for (level = 1; level <= max_level; level++)
2118 if (wm[level] != 0)
2119 wm[level] += 2;
4f947386
VK		 2120 else {
2121 for (i = level + 1; i <= max_level; i++)
2122 wm[i] = 0;
367294be 2123
4f947386
VK		 2124 break;
2125 }
2af30a5c 2126 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2127 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2128
2129 wm[0] = (sskpd >> 56) & 0xFF;
2130 if (wm[0] == 0)
2131 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2132 wm[1] = (sskpd >> 4) & 0xFF;
2133 wm[2] = (sskpd >> 12) & 0xFF;
2134 wm[3] = (sskpd >> 20) & 0x1FF;
2135 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2136 } else if (INTEL_INFO(dev)->gen >= 6) {
2137 uint32_t sskpd = I915_READ(MCH_SSKPD);
2138
2139 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2140 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2141 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2142 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2143 } else if (INTEL_INFO(dev)->gen >= 5) {
2144 uint32_t mltr = I915_READ(MLTR_ILK);
2145
2146 /* ILK primary LP0 latency is 700 ns */
2147 wm[0] = 7;
2148 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2149 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2150 }
2151}
2152
53615a5e
VS		 2153static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2154{
2155 /* ILK sprite LP0 latency is 1300 ns */
2156 if (INTEL_INFO(dev)->gen == 5)
2157 wm[0] = 13;
2158}
2159
2160static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2161{
2162 /* ILK cursor LP0 latency is 1300 ns */
2163 if (INTEL_INFO(dev)->gen == 5)
2164 wm[0] = 13;
2165
2166 /* WaDoubleCursorLP3Latency:ivb */
2167 if (IS_IVYBRIDGE(dev))
2168 wm[3] *= 2;
2169}
2170
546c81fd 2171int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2172{
26ec971e 2173 /* how many WM levels are we expecting */
b6e742f6 2174 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2175 return 7;
2176 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2177 return 4;
26ec971e 2178 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2179 return 3;
26ec971e 2180 else
ad0d6dc4
VS		 2181 return 2;
2182}
7526ed79 2183
ad0d6dc4
VS		 2184static void intel_print_wm_latency(struct drm_device *dev,
2185 const char *name,
2af30a5c 2186 const uint16_t wm[8])
ad0d6dc4
VS		 2187{
2188 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2189
2190 for (level = 0; level <= max_level; level++) {
2191 unsigned int latency = wm[level];
2192
2193 if (latency == 0) {
2194 DRM_ERROR("%s WM%d latency not provided\n",
2195 name, level);
2196 continue;
2197 }
2198
2af30a5c
PB		 2199 /*
2200 * - latencies are in us on gen9.
2201 * - before then, WM1+ latency values are in 0.5us units
2202 */
2203 if (IS_GEN9(dev))
2204 latency *= 10;
2205 else if (level > 0)
26ec971e
VS		 2206 latency *= 5;
2207
2208 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2209 name, level, wm[level],
2210 latency / 10, latency % 10);
2211 }
2212}
2213
e95a2f75
VS		 2214static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2215 uint16_t wm[5], uint16_t min)
2216{
2217 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2218
2219 if (wm[0] >= min)
2220 return false;
2221
2222 wm[0] = max(wm[0], min);
2223 for (level = 1; level <= max_level; level++)
2224 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2225
2226 return true;
2227}
2228
2229static void snb_wm_latency_quirk(struct drm_device *dev)
2230{
2231 struct drm_i915_private *dev_priv = dev->dev_private;
2232 bool changed;
2233
2234 /*
2235 * The BIOS provided WM memory latency values are often
2236 * inadequate for high resolution displays. Adjust them.
2237 */
2238 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2239 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2240 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2241
2242 if (!changed)
2243 return;
2244
2245 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2246 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2247 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2248 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2249}
2250
fa50ad61 2251static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2252{
2253 struct drm_i915_private *dev_priv = dev->dev_private;
2254
2255 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2256
2257 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2258 sizeof(dev_priv->wm.pri_latency));
2259 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2260 sizeof(dev_priv->wm.pri_latency));
2261
2262 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2263 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2264
2265 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2266 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2267 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2268
2269 if (IS_GEN6(dev))
2270 snb_wm_latency_quirk(dev);
53615a5e
VS		 2271}
2272
2af30a5c
PB		 2273static void skl_setup_wm_latency(struct drm_device *dev)
2274{
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276
2277 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2278 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2279}
2280
0b2ae6d7 2281/* Compute new watermarks for the pipe */
86c8bbbe
MR		 2282static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2283 struct drm_atomic_state *state)
0b2ae6d7 2284{
86c8bbbe
MR		 2285 struct intel_pipe_wm *pipe_wm;
2286 struct drm_device *dev = intel_crtc->base.dev;
d34ff9c6 2287 const struct drm_i915_private *dev_priv = dev->dev_private;
86c8bbbe 2288 struct intel_crtc_state *cstate = NULL;
43d59eda 2289 struct intel_plane *intel_plane;
86c8bbbe
MR		 2290 struct drm_plane_state *ps;
2291 struct intel_plane_state *pristate = NULL;
43d59eda 2292 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2293 struct intel_plane_state *curstate = NULL;
0b2ae6d7 2294 int level, max_level = ilk_wm_max_level(dev);
bf220452
MR		 2295 /* LP0 watermark maximums depend on this pipe alone */
2296 struct intel_wm_config config = {
2297 .num_pipes_active = 1,
2298 };
820c1980 2299 struct ilk_wm_maximums max;
0b2ae6d7 2300
86c8bbbe
MR		 2301 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2302 if (IS_ERR(cstate))
2303 return PTR_ERR(cstate);
2304
2305 pipe_wm = &cstate->wm.optimal.ilk;
f1ecaf8f 2306 memset(pipe_wm, 0, sizeof(*pipe_wm));
86c8bbbe 2307
43d59eda 2308 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
86c8bbbe
MR		 2309 ps = drm_atomic_get_plane_state(state,
2310 &intel_plane->base);
2311 if (IS_ERR(ps))
2312 return PTR_ERR(ps);
2313
2314 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2315 pristate = to_intel_plane_state(ps);
2316 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2317 sprstate = to_intel_plane_state(ps);
2318 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2319 curstate = to_intel_plane_state(ps);
43d59eda
MR		 2320 }
2321
bf220452
MR		 2322 config.sprites_enabled = sprstate->visible;
2323 config.sprites_scaled = sprstate->visible &&
43d59eda
MR		 2324 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2325 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2326
bf220452
MR		 2327 pipe_wm->pipe_enabled = cstate->base.active;
2328 pipe_wm->sprites_enabled = config.sprites_enabled;
2329 pipe_wm->sprites_scaled = config.sprites_scaled;
2330
7b39a0b7 2331 /* ILK/SNB: LP2+ watermarks only w/o sprites */
43d59eda 2332 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
7b39a0b7
VS		 2333 max_level = 1;
2334
2335 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
bf220452 2336 if (config.sprites_scaled)
7b39a0b7
VS		 2337 max_level = 0;
2338
86c8bbbe
MR		 2339 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2340 pristate, sprstate, curstate, &pipe_wm->wm[0]);
0b2ae6d7 2341
a42a5719 2342 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ee91a159 2343 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
0b2ae6d7 2344
bf220452
MR		 2345 /* LP0 watermarks always use 1/2 DDB partitioning */
2346 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2347
2348 /* At least LP0 must be valid */
2349 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2350 return -EINVAL;
a3cb4048
VS		 2351
2352 ilk_compute_wm_reg_maximums(dev, 1, &max);
2353
2354 for (level = 1; level <= max_level; level++) {
2355 struct intel_wm_level wm = {};
2356
86c8bbbe
MR		 2357 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2358 pristate, sprstate, curstate, &wm);
a3cb4048
VS		 2359
2360 /*
2361 * Disable any watermark level that exceeds the
2362 * register maximums since such watermarks are
2363 * always invalid.
2364 */
2365 if (!ilk_validate_wm_level(level, &max, &wm))
2366 break;
2367
2368 pipe_wm->wm[level] = wm;
2369 }
2370
86c8bbbe 2371 return 0;
0b2ae6d7
VS		 2372}
2373
2374/*
2375 * Merge the watermarks from all active pipes for a specific level.
2376 */
2377static void ilk_merge_wm_level(struct drm_device *dev,
2378 int level,
2379 struct intel_wm_level *ret_wm)
2380{
2381 const struct intel_crtc *intel_crtc;
2382
d52fea5b
VS		 2383 ret_wm->enable = true;
2384
d3fcc808 2385 for_each_intel_crtc(dev, intel_crtc) {
bf220452
MR		 2386 const struct intel_crtc_state *cstate =
2387 to_intel_crtc_state(intel_crtc->base.state);
2388 const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
fe392efd
VS		 2389 const struct intel_wm_level *wm = &active->wm[level];
2390
2391 if (!active->pipe_enabled)
2392 continue;
0b2ae6d7 2393
d52fea5b
VS		 2394 /*
2395 * The watermark values may have been used in the past,
2396 * so we must maintain them in the registers for some
2397 * time even if the level is now disabled.
2398 */
0b2ae6d7 2399 if (!wm->enable)
d52fea5b 2400 ret_wm->enable = false;
0b2ae6d7
VS		 2401
2402 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2403 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2404 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2405 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2406 }
0b2ae6d7
VS		 2407}
2408
2409/*
2410 * Merge all low power watermarks for all active pipes.
2411 */
2412static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2413 const struct intel_wm_config *config,
820c1980 2414 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2415 struct intel_pipe_wm *merged)
2416{
7733b49b 2417 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2418 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2419 int last_enabled_level = max_level;
0b2ae6d7 2420
0ba22e26
VS		 2421 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2422 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2423 config->num_pipes_active > 1)
2424 return;
2425
6c8b6c28
VS		 2426 /* ILK: FBC WM must be disabled always */
2427 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2428
2429 /* merge each WM1+ level */
2430 for (level = 1; level <= max_level; level++) {
2431 struct intel_wm_level *wm = &merged->wm[level];
2432
2433 ilk_merge_wm_level(dev, level, wm);
2434
d52fea5b
VS		 2435 if (level > last_enabled_level)
2436 wm->enable = false;
2437 else if (!ilk_validate_wm_level(level, max, wm))
2438 /* make sure all following levels get disabled */
2439 last_enabled_level = level - 1;
0b2ae6d7
VS		 2440
2441 /*
2442 * The spec says it is preferred to disable
2443 * FBC WMs instead of disabling a WM level.
2444 */
2445 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2446 if (wm->enable)
2447 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2448 wm->fbc_val = 0;
2449 }
2450 }
6c8b6c28
VS		 2451
2452 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2453 /*
2454 * FIXME this is racy. FBC might get enabled later.
2455 * What we should check here is whether FBC can be
2456 * enabled sometime later.
2457 */
7733b49b 2458 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2459 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2460 for (level = 2; level <= max_level; level++) {
2461 struct intel_wm_level *wm = &merged->wm[level];
2462
2463 wm->enable = false;
2464 }
2465 }
0b2ae6d7
VS		 2466}
2467
b380ca3c
VS		 2468static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2469{
2470 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2471 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2472}
2473
a68d68ee
VS		 2474/* The value we need to program into the WM_LPx latency field */
2475static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2476{
2477 struct drm_i915_private *dev_priv = dev->dev_private;
2478
a42a5719 2479 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2480 return 2 * level;
2481 else
2482 return dev_priv->wm.pri_latency[level];
2483}
2484
820c1980 2485static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2486 const struct intel_pipe_wm *merged,
609cedef 2487 enum intel_ddb_partitioning partitioning,
820c1980 2488 struct ilk_wm_values *results)
801bcfff 2489{
0b2ae6d7
VS		 2490 struct intel_crtc *intel_crtc;
2491 int level, wm_lp;
cca32e9a 2492
0362c781 2493 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2494 results->partitioning = partitioning;
cca32e9a 2495
0b2ae6d7 2496 /* LP1+ register values */
cca32e9a 2497 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2498 const struct intel_wm_level *r;
801bcfff 2499
b380ca3c 2500 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2501
0362c781 2502 r = &merged->wm[level];
cca32e9a 2503
d52fea5b
VS		 2504 /*
2505 * Maintain the watermark values even if the level is
2506 * disabled. Doing otherwise could cause underruns.
2507 */
2508 results->wm_lp[wm_lp - 1] =
a68d68ee 2509 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2510 (r->pri_val << WM1_LP_SR_SHIFT) |
2511 r->cur_val;
2512
d52fea5b
VS		 2513 if (r->enable)
2514 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2515
416f4727
VS		 2516 if (INTEL_INFO(dev)->gen >= 8)
2517 results->wm_lp[wm_lp - 1] |=
2518 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2519 else
2520 results->wm_lp[wm_lp - 1] |=
2521 r->fbc_val << WM1_LP_FBC_SHIFT;
2522
d52fea5b
VS		 2523 /*
2524 * Always set WM1S_LP_EN when spr_val != 0, even if the
2525 * level is disabled. Doing otherwise could cause underruns.
2526 */
6cef2b8a
VS		 2527 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2528 WARN_ON(wm_lp != 1);
2529 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2530 } else
2531 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2532 }
801bcfff 2533
0b2ae6d7 2534 /* LP0 register values */
d3fcc808 2535 for_each_intel_crtc(dev, intel_crtc) {
bf220452
MR		 2536 const struct intel_crtc_state *cstate =
2537 to_intel_crtc_state(intel_crtc->base.state);
0b2ae6d7 2538 enum pipe pipe = intel_crtc->pipe;
bf220452 2539 const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
0b2ae6d7
VS		 2540
2541 if (WARN_ON(!r->enable))
2542 continue;
2543
bf220452 2544 results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
1011d8c4 2545
0b2ae6d7
VS		 2546 results->wm_pipe[pipe] =
2547 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2548 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2549 r->cur_val;
801bcfff
PZ		 2550 }
2551}
2552
861f3389
PZ		 2553/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2554 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2555static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2556 struct intel_pipe_wm *r1,
2557 struct intel_pipe_wm *r2)
861f3389 2558{
198a1e9b
VS		 2559 int level, max_level = ilk_wm_max_level(dev);
2560 int level1 = 0, level2 = 0;
861f3389 2561
198a1e9b
VS		 2562 for (level = 1; level <= max_level; level++) {
2563 if (r1->wm[level].enable)
2564 level1 = level;
2565 if (r2->wm[level].enable)
2566 level2 = level;
861f3389
PZ		 2567 }
2568
198a1e9b
VS		 2569 if (level1 == level2) {
2570 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2571 return r2;
2572 else
2573 return r1;
198a1e9b 2574 } else if (level1 > level2) {
861f3389
PZ		 2575 return r1;
2576 } else {
2577 return r2;
2578 }
2579}
2580
49a687c4
VS		 2581/* dirty bits used to track which watermarks need changes */
2582#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2583#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2584#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2585#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2586#define WM_DIRTY_FBC (1 << 24)
2587#define WM_DIRTY_DDB (1 << 25)
2588
055e393f 2589static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2590 const struct ilk_wm_values *old,
2591 const struct ilk_wm_values *new)
49a687c4
VS		 2592{
2593 unsigned int dirty = 0;
2594 enum pipe pipe;
2595 int wm_lp;
2596
055e393f 2597 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2598 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2599 dirty |= WM_DIRTY_LINETIME(pipe);
2600 /* Must disable LP1+ watermarks too */
2601 dirty |= WM_DIRTY_LP_ALL;
2602 }
2603
2604 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2605 dirty |= WM_DIRTY_PIPE(pipe);
2606 /* Must disable LP1+ watermarks too */
2607 dirty |= WM_DIRTY_LP_ALL;
2608 }
2609 }
2610
2611 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2612 dirty |= WM_DIRTY_FBC;
2613 /* Must disable LP1+ watermarks too */
2614 dirty |= WM_DIRTY_LP_ALL;
2615 }
2616
2617 if (old->partitioning != new->partitioning) {
2618 dirty |= WM_DIRTY_DDB;
2619 /* Must disable LP1+ watermarks too */
2620 dirty |= WM_DIRTY_LP_ALL;
2621 }
2622
2623 /* LP1+ watermarks already deemed dirty, no need to continue */
2624 if (dirty & WM_DIRTY_LP_ALL)
2625 return dirty;
2626
2627 /* Find the lowest numbered LP1+ watermark in need of an update... */
2628 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2629 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2630 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2631 break;
2632 }
2633
2634 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2635 for (; wm_lp <= 3; wm_lp++)
2636 dirty |= WM_DIRTY_LP(wm_lp);
2637
2638 return dirty;
2639}
2640
8553c18e
VS		 2641static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2642 unsigned int dirty)
801bcfff 2643{
820c1980 2644 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2645 bool changed = false;
801bcfff 2646
facd619b
VS		 2647 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2648 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2649 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2650 changed = true;
facd619b
VS		 2651 }
2652 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2653 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2654 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2655 changed = true;
facd619b
VS		 2656 }
2657 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2658 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2659 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2660 changed = true;
facd619b 2661 }
801bcfff 2662
facd619b
VS		 2663 /*
2664 * Don't touch WM1S_LP_EN here.
2665 * Doing so could cause underruns.
2666 */
6cef2b8a 2667
8553c18e
VS		 2668 return changed;
2669}
2670
2671/*
2672 * The spec says we shouldn't write when we don't need, because every write
2673 * causes WMs to be re-evaluated, expending some power.
2674 */
820c1980
ID		 2675static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2676 struct ilk_wm_values *results)
8553c18e
VS		 2677{
2678 struct drm_device *dev = dev_priv->dev;
820c1980 2679 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2680 unsigned int dirty;
2681 uint32_t val;
2682
055e393f 2683 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2684 if (!dirty)
2685 return;
2686
2687 _ilk_disable_lp_wm(dev_priv, dirty);
2688
49a687c4 2689 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2690 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2691 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2692 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2693 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2694 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2695
49a687c4 2696 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2697 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2698 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2699 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2700 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2701 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2702
49a687c4 2703 if (dirty & WM_DIRTY_DDB) {
a42a5719 2704 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2705 val = I915_READ(WM_MISC);
2706 if (results->partitioning == INTEL_DDB_PART_1_2)
2707 val &= ~WM_MISC_DATA_PARTITION_5_6;
2708 else
2709 val |= WM_MISC_DATA_PARTITION_5_6;
2710 I915_WRITE(WM_MISC, val);
2711 } else {
2712 val = I915_READ(DISP_ARB_CTL2);
2713 if (results->partitioning == INTEL_DDB_PART_1_2)
2714 val &= ~DISP_DATA_PARTITION_5_6;
2715 else
2716 val |= DISP_DATA_PARTITION_5_6;
2717 I915_WRITE(DISP_ARB_CTL2, val);
2718 }
1011d8c4
PZ		 2719 }
2720
49a687c4 2721 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2722 val = I915_READ(DISP_ARB_CTL);
2723 if (results->enable_fbc_wm)
2724 val &= ~DISP_FBC_WM_DIS;
2725 else
2726 val |= DISP_FBC_WM_DIS;
2727 I915_WRITE(DISP_ARB_CTL, val);
2728 }
2729
954911eb
ID		 2730 if (dirty & WM_DIRTY_LP(1) &&
2731 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2732 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2733
2734 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2735 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2736 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2737 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2738 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2739 }
801bcfff 2740
facd619b 2741 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2742 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2743 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2744 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2745 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2746 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2747
2748 dev_priv->wm.hw = *results;
801bcfff
PZ		 2749}
2750
bf220452 2751static bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e
VS		 2752{
2753 struct drm_i915_private *dev_priv = dev->dev_private;
2754
2755 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2756}
2757
b9cec075
DL		 2758/*
2759 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2760 * different active planes.
2761 */
2762
2763#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2764#define BXT_DDB_SIZE 512
b9cec075 2765
024c9045
MR		 2766/*
2767 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2768 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2769 * other universal planes are in indices 1..n. Note that this may leave unused
2770 * indices between the top "sprite" plane and the cursor.
2771 */
2772static int
2773skl_wm_plane_id(const struct intel_plane *plane)
2774{
2775 switch (plane->base.type) {
2776 case DRM_PLANE_TYPE_PRIMARY:
2777 return 0;
2778 case DRM_PLANE_TYPE_CURSOR:
2779 return PLANE_CURSOR;
2780 case DRM_PLANE_TYPE_OVERLAY:
2781 return plane->plane + 1;
2782 default:
2783 MISSING_CASE(plane->base.type);
2784 return plane->plane;
2785 }
2786}
2787
b9cec075
DL		 2788static void
2789skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2790 const struct intel_crtc_state *cstate,
b9cec075 2791 const struct intel_wm_config *config,
b9cec075
DL		 2792 struct skl_ddb_entry *alloc /* out */)
2793{
024c9045 2794 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2795 struct drm_crtc *crtc;
2796 unsigned int pipe_size, ddb_size;
2797 int nth_active_pipe;
2798
024c9045 2799 if (!cstate->base.active) {
b9cec075
DL		 2800 alloc->start = 0;
2801 alloc->end = 0;
2802 return;
2803 }
2804
43d735a6
DL		 2805 if (IS_BROXTON(dev))
2806 ddb_size = BXT_DDB_SIZE;
2807 else
2808 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2809
2810 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2811
2812 nth_active_pipe = 0;
2813 for_each_crtc(dev, crtc) {
3ef00284 2814 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2815 continue;
2816
2817 if (crtc == for_crtc)
2818 break;
2819
2820 nth_active_pipe++;
2821 }
2822
2823 pipe_size = ddb_size / config->num_pipes_active;
2824 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2825 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2826}
2827
2828static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2829{
2830 if (config->num_pipes_active == 1)
2831 return 32;
2832
2833 return 8;
2834}
2835
a269c583
DL		 2836static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2837{
2838 entry->start = reg & 0x3ff;
2839 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2840 if (entry->end)
2841 entry->end += 1;
a269c583
DL		 2842}
2843
08db6652
DL		 2844void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2845 struct skl_ddb_allocation *ddb /* out */)
a269c583 2846{
a269c583
DL		 2847 enum pipe pipe;
2848 int plane;
2849 u32 val;
2850
b10f1b20
ML		 2851 memset(ddb, 0, sizeof(*ddb));
2852
a269c583 2853 for_each_pipe(dev_priv, pipe) {
b10f1b20
ML		 2854 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
2855 continue;
2856
dd740780 2857 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2858 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2859 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2860 val);
2861 }
2862
2863 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2864 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2865 val);
a269c583
DL		 2866 }
2867}
2868
b9cec075 2869static unsigned int
024c9045
MR		 2870skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2871 const struct drm_plane_state *pstate,
2872 int y)
b9cec075 2873{
024c9045
MR		 2874 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2875 struct drm_framebuffer *fb = pstate->fb;
2cd601c6
CK		 2876
2877 /* for planar format */
024c9045 2878 if (fb->pixel_format == DRM_FORMAT_NV12) {
2cd601c6 2879 if (y) /* y-plane data rate */
024c9045
MR		 2880 return intel_crtc->config->pipe_src_w *
2881 intel_crtc->config->pipe_src_h *
2882 drm_format_plane_cpp(fb->pixel_format, 0);
2cd601c6 2883 else /* uv-plane data rate */
024c9045
MR		 2884 return (intel_crtc->config->pipe_src_w/2) *
2885 (intel_crtc->config->pipe_src_h/2) *
2886 drm_format_plane_cpp(fb->pixel_format, 1);
2cd601c6
CK		 2887 }
2888
2889 /* for packed formats */
024c9045
MR		 2890 return intel_crtc->config->pipe_src_w *
2891 intel_crtc->config->pipe_src_h *
2892 drm_format_plane_cpp(fb->pixel_format, 0);
b9cec075
DL		 2893}
2894
2895/*
2896 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2897 * a 8192x4096@32bpp framebuffer:
2898 * 3 * 4096 * 8192 * 4 < 2^32
2899 */
2900static unsigned int
024c9045 2901skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
b9cec075 2902{
024c9045
MR		 2903 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2904 struct drm_device *dev = intel_crtc->base.dev;
2905 const struct intel_plane *intel_plane;
b9cec075 2906 unsigned int total_data_rate = 0;
b9cec075 2907
024c9045
MR		 2908 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2909 const struct drm_plane_state *pstate = intel_plane->base.state;
b9cec075 2910
024c9045 2911 if (pstate->fb == NULL)
b9cec075
DL		 2912 continue;
2913
024c9045
MR		 2914 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2915 continue;
2916
2917 /* packed/uv */
2918 total_data_rate += skl_plane_relative_data_rate(cstate,
2919 pstate,
2920 0);
2921
2922 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2923 /* y-plane */
2924 total_data_rate += skl_plane_relative_data_rate(cstate,
2925 pstate,
2926 1);
b9cec075
DL		 2927 }
2928
2929 return total_data_rate;
2930}
2931
2932static void
024c9045 2933skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 2934 struct skl_ddb_allocation *ddb /* out */)
2935{
024c9045 2936 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075 2937 struct drm_device *dev = crtc->dev;
aa363136
MR		 2938 struct drm_i915_private *dev_priv = to_i915(dev);
2939 struct intel_wm_config *config = &dev_priv->wm.config;
b9cec075 2940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 2941 struct intel_plane *intel_plane;
b9cec075 2942 enum pipe pipe = intel_crtc->pipe;
34bb56af 2943 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2944 uint16_t alloc_size, start, cursor_blocks;
80958155 2945 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2946 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075 2947 unsigned int total_data_rate;
b9cec075 2948
024c9045 2949 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
34bb56af 2950 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2951 if (alloc_size == 0) {
2952 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4969d33e
MR		 2953 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2954 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
b9cec075
DL		 2955 return;
2956 }
2957
2958 cursor_blocks = skl_cursor_allocation(config);
4969d33e
MR		 2959 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2960 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 2961
2962 alloc_size -= cursor_blocks;
34bb56af 2963 alloc->end -= cursor_blocks;
b9cec075 2964
80958155 2965 /* 1. Allocate the mininum required blocks for each active plane */
024c9045
MR		 2966 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2967 struct drm_plane *plane = &intel_plane->base;
2968 struct drm_framebuffer *fb = plane->state->fb;
2969 int id = skl_wm_plane_id(intel_plane);
80958155 2970
024c9045
MR		 2971 if (fb == NULL)
2972 continue;
2973 if (plane->type == DRM_PLANE_TYPE_CURSOR)
80958155
DL		 2974 continue;
2975
024c9045
MR		 2976 minimum[id] = 8;
2977 alloc_size -= minimum[id];
2978 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
2979 alloc_size -= y_minimum[id];
80958155
DL		 2980 }
2981
b9cec075 2982 /*
80958155
DL		 2983 * 2. Distribute the remaining space in proportion to the amount of
2984 * data each plane needs to fetch from memory.
b9cec075
DL		 2985 *
2986 * FIXME: we may not allocate every single block here.
2987 */
024c9045 2988 total_data_rate = skl_get_total_relative_data_rate(cstate);
b9cec075 2989
34bb56af 2990 start = alloc->start;
024c9045
MR		 2991 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2992 struct drm_plane *plane = &intel_plane->base;
2993 struct drm_plane_state *pstate = intel_plane->base.state;
2cd601c6
CK		 2994 unsigned int data_rate, y_data_rate;
2995 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 2996 int id = skl_wm_plane_id(intel_plane);
b9cec075 2997
024c9045
MR		 2998 if (pstate->fb == NULL)
2999 continue;
3000 if (plane->type == DRM_PLANE_TYPE_CURSOR)
b9cec075
DL		 3001 continue;
3002
024c9045 3003 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
b9cec075
DL		 3004
3005 /*
2cd601c6 3006 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3007 * promote the expression to 64 bits to avoid overflowing, the
3008 * result is < available as data_rate / total_data_rate < 1
3009 */
024c9045 3010 plane_blocks = minimum[id];
80958155
DL		 3011 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3012 total_data_rate);
b9cec075 3013
024c9045
MR		 3014 ddb->plane[pipe][id].start = start;
3015 ddb->plane[pipe][id].end = start + plane_blocks;
b9cec075
DL		 3016
3017 start += plane_blocks;
2cd601c6
CK		 3018
3019 /*
3020 * allocation for y_plane part of planar format:
3021 */
024c9045
MR		 3022 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3023 y_data_rate = skl_plane_relative_data_rate(cstate,
3024 pstate,
3025 1);
3026 y_plane_blocks = y_minimum[id];
2cd601c6
CK		 3027 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3028 total_data_rate);
3029
024c9045
MR		 3030 ddb->y_plane[pipe][id].start = start;
3031 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
2cd601c6
CK		 3032
3033 start += y_plane_blocks;
3034 }
3035
b9cec075
DL		 3036 }
3037
3038}
3039
5cec258b 3040static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3041{
3042 /* TODO: Take into account the scalers once we support them */
2d112de7 3043 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3044}
3045
3046/*
3047 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3048 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3049 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3050 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3051*/
ac484963 3052static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3053{
3054 uint32_t wm_intermediate_val, ret;
3055
3056 if (latency == 0)
3057 return UINT_MAX;
3058
ac484963 3059 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3060 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3061
3062 return ret;
3063}
3064
3065static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3066 uint32_t horiz_pixels, uint8_t cpp,
0fda6568 3067 uint64_t tiling, uint32_t latency)
2d41c0b5 3068{
d4c2aa60
TU		 3069 uint32_t ret;
3070 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3071 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3072
3073 if (latency == 0)
3074 return UINT_MAX;
3075
ac484963 3076 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3077
3078 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3079 tiling == I915_FORMAT_MOD_Yf_TILED) {
3080 plane_bytes_per_line *= 4;
3081 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3082 plane_blocks_per_line /= 4;
3083 } else {
3084 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3085 }
3086
2d41c0b5
PB		 3087 wm_intermediate_val = latency * pixel_rate;
3088 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3089 plane_blocks_per_line;
2d41c0b5
PB		 3090
3091 return ret;
3092}
3093
2d41c0b5
PB		 3094static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3095 const struct intel_crtc *intel_crtc)
3096{
3097 struct drm_device *dev = intel_crtc->base.dev;
3098 struct drm_i915_private *dev_priv = dev->dev_private;
3099 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2d41c0b5 3100
e6d90023
KM		 3101 /*
3102 * If ddb allocation of pipes changed, it may require recalculation of
3103 * watermarks
3104 */
3105 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
2d41c0b5
PB		 3106 return true;
3107
3108 return false;
3109}
3110
d4c2aa60 3111static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
024c9045
MR		 3112 struct intel_crtc_state *cstate,
3113 struct intel_plane *intel_plane,
afb024aa 3114 uint16_t ddb_allocation,
d4c2aa60 3115 int level,
afb024aa
DL		 3116 uint16_t *out_blocks, /* out */
3117 uint8_t *out_lines /* out */)
2d41c0b5 3118{
024c9045
MR		 3119 struct drm_plane *plane = &intel_plane->base;
3120 struct drm_framebuffer *fb = plane->state->fb;
d4c2aa60
TU		 3121 uint32_t latency = dev_priv->wm.skl_latency[level];
3122 uint32_t method1, method2;
3123 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3124 uint32_t res_blocks, res_lines;
3125 uint32_t selected_result;
ac484963 3126 uint8_t cpp;
2d41c0b5 3127
024c9045 3128 if (latency == 0 || !cstate->base.active || !fb)
2d41c0b5
PB		 3129 return false;
3130
ac484963 3131 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
024c9045 3132 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
ac484963 3133 cpp, latency);
024c9045
MR		 3134 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3135 cstate->base.adjusted_mode.crtc_htotal,
3136 cstate->pipe_src_w,
ac484963 3137 cpp, fb->modifier[0],
d4c2aa60 3138 latency);
2d41c0b5 3139
ac484963 3140 plane_bytes_per_line = cstate->pipe_src_w * cpp;
d4c2aa60 3141 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3142
024c9045
MR		 3143 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3144 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3145 uint32_t min_scanlines = 4;
3146 uint32_t y_tile_minimum;
024c9045 3147 if (intel_rotation_90_or_270(plane->state->rotation)) {
ac484963 3148 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
024c9045
MR		 3149 drm_format_plane_cpp(fb->pixel_format, 1) :
3150 drm_format_plane_cpp(fb->pixel_format, 0);
3151
ac484963 3152 switch (cpp) {
1fc0a8f7
TU		 3153 case 1:
3154 min_scanlines = 16;
3155 break;
3156 case 2:
3157 min_scanlines = 8;
3158 break;
3159 case 8:
3160 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3161 }
1fc0a8f7
TU		 3162 }
3163 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3164 selected_result = max(method2, y_tile_minimum);
3165 } else {
3166 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3167 selected_result = min(method1, method2);
3168 else
3169 selected_result = method1;
3170 }
2d41c0b5 3171
d4c2aa60
TU		 3172 res_blocks = selected_result + 1;
3173 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3174
0fda6568 3175 if (level >= 1 && level <= 7) {
024c9045
MR		 3176 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3177 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3178 res_lines += 4;
3179 else
3180 res_blocks++;
3181 }
e6d66171 3182
d4c2aa60 3183 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3184 return false;
3185
3186 *out_blocks = res_blocks;
3187 *out_lines = res_lines;
2d41c0b5
PB		 3188
3189 return true;
3190}
3191
3192static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3193 struct skl_ddb_allocation *ddb,
024c9045 3194 struct intel_crtc_state *cstate,
2d41c0b5 3195 int level,
2d41c0b5
PB		 3196 struct skl_wm_level *result)
3197{
024c9045
MR		 3198 struct drm_device *dev = dev_priv->dev;
3199 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3200 struct intel_plane *intel_plane;
2d41c0b5 3201 uint16_t ddb_blocks;
024c9045
MR		 3202 enum pipe pipe = intel_crtc->pipe;
3203
3204 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3205 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3206
2d41c0b5
PB		 3207 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3208
d4c2aa60 3209 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
024c9045
MR		 3210 cstate,
3211 intel_plane,
2d41c0b5 3212 ddb_blocks,
d4c2aa60 3213 level,
2d41c0b5
PB		 3214 &result->plane_res_b[i],
3215 &result->plane_res_l[i]);
3216 }
2d41c0b5
PB		 3217}
3218
407b50f3 3219static uint32_t
024c9045 3220skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3221{
024c9045 3222 if (!cstate->base.active)
407b50f3
DL		 3223 return 0;
3224
024c9045 3225 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3226 return 0;
407b50f3 3227
024c9045
MR		 3228 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3229 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3230}
3231
024c9045 3232static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3233 struct skl_wm_level *trans_wm /* out */)
407b50f3 3234{
024c9045 3235 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3237 struct intel_plane *intel_plane;
9414f563 3238
024c9045 3239 if (!cstate->base.active)
407b50f3 3240 return;
9414f563
DL		 3241
3242 /* Until we know more, just disable transition WMs */
024c9045
MR		 3243 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3244 int i = skl_wm_plane_id(intel_plane);
3245
9414f563 3246 trans_wm->plane_en[i] = false;
024c9045 3247 }
407b50f3
DL		 3248}
3249
024c9045 3250static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
2d41c0b5 3251 struct skl_ddb_allocation *ddb,
2d41c0b5
PB		 3252 struct skl_pipe_wm *pipe_wm)
3253{
024c9045 3254 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3255 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5
PB		 3256 int level, max_level = ilk_wm_max_level(dev);
3257
3258 for (level = 0; level <= max_level; level++) {
024c9045
MR		 3259 skl_compute_wm_level(dev_priv, ddb, cstate,
3260 level, &pipe_wm->wm[level]);
2d41c0b5 3261 }
024c9045 3262 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3263
024c9045 3264 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
2d41c0b5
PB		 3265}
3266
3267static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3268 struct skl_pipe_wm *p_wm,
3269 struct skl_wm_values *r,
3270 struct intel_crtc *intel_crtc)
3271{
3272 int level, max_level = ilk_wm_max_level(dev);
3273 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3274 uint32_t temp;
3275 int i;
2d41c0b5
PB		 3276
3277 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3278 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3279 temp = 0;
2d41c0b5
PB		 3280
3281 temp |= p_wm->wm[level].plane_res_l[i] <<
3282 PLANE_WM_LINES_SHIFT;
3283 temp |= p_wm->wm[level].plane_res_b[i];
3284 if (p_wm->wm[level].plane_en[i])
3285 temp |= PLANE_WM_EN;
3286
3287 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3288 }
3289
3290 temp = 0;
2d41c0b5 3291
4969d33e
MR		 3292 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3293 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3294
4969d33e 3295 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3296 temp |= PLANE_WM_EN;
3297
4969d33e 3298 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3299
3300 }
3301
9414f563
DL		 3302 /* transition WMs */
3303 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3304 temp = 0;
3305 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3306 temp |= p_wm->trans_wm.plane_res_b[i];
3307 if (p_wm->trans_wm.plane_en[i])
3308 temp |= PLANE_WM_EN;
3309
3310 r->plane_trans[pipe][i] = temp;
3311 }
3312
3313 temp = 0;
4969d33e
MR		 3314 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3315 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3316 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3317 temp |= PLANE_WM_EN;
3318
4969d33e 3319 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3320
2d41c0b5
PB		 3321 r->wm_linetime[pipe] = p_wm->linetime;
3322}
3323
f0f59a00
VS		 3324static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3325 i915_reg_t reg,
16160e3d
DL		 3326 const struct skl_ddb_entry *entry)
3327{
3328 if (entry->end)
3329 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3330 else
3331 I915_WRITE(reg, 0);
3332}
3333
2d41c0b5
PB		 3334static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3335 const struct skl_wm_values *new)
3336{
3337 struct drm_device *dev = dev_priv->dev;
3338 struct intel_crtc *crtc;
3339
19c8054c 3340 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3341 int i, level, max_level = ilk_wm_max_level(dev);
3342 enum pipe pipe = crtc->pipe;
3343
5d374d96
DL		 3344 if (!new->dirty[pipe])
3345 continue;
8211bd5b 3346
5d374d96 3347 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3348
5d374d96
DL		 3349 for (level = 0; level <= max_level; level++) {
3350 for (i = 0; i < intel_num_planes(crtc); i++)
3351 I915_WRITE(PLANE_WM(pipe, i, level),
3352 new->plane[pipe][i][level]);
3353 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3354 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3355 }
5d374d96
DL		 3356 for (i = 0; i < intel_num_planes(crtc); i++)
3357 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3358 new->plane_trans[pipe][i]);
4969d33e
MR		 3359 I915_WRITE(CUR_WM_TRANS(pipe),
3360 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3361
2cd601c6 3362 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3363 skl_ddb_entry_write(dev_priv,
3364 PLANE_BUF_CFG(pipe, i),
3365 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3366 skl_ddb_entry_write(dev_priv,
3367 PLANE_NV12_BUF_CFG(pipe, i),
3368 &new->ddb.y_plane[pipe][i]);
3369 }
5d374d96
DL		 3370
3371 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3372 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3373 }
2d41c0b5
PB		 3374}
3375
0e8fb7ba
DL		 3376/*
3377 * When setting up a new DDB allocation arrangement, we need to correctly
3378 * sequence the times at which the new allocations for the pipes are taken into
3379 * account or we'll have pipes fetching from space previously allocated to
3380 * another pipe.
3381 *
3382 * Roughly the sequence looks like:
3383 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3384 * overlapping with a previous light-up pipe (another way to put it is:
3385 * pipes with their new allocation strickly included into their old ones).
3386 * 2. re-allocate the other pipes that get their allocation reduced
3387 * 3. allocate the pipes having their allocation increased
3388 *
3389 * Steps 1. and 2. are here to take care of the following case:
3390 * - Initially DDB looks like this:
3391 * | B | C |
3392 * - enable pipe A.
3393 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3394 * allocation
3395 * | A | B | C |
3396 *
3397 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3398 */
3399
d21b795c
DL		 3400static void
3401skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3402{
0e8fb7ba
DL		 3403 int plane;
3404
d21b795c
DL		 3405 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3406
dd740780 3407 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3408 I915_WRITE(PLANE_SURF(pipe, plane),
3409 I915_READ(PLANE_SURF(pipe, plane)));
3410 }
3411 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3412}
3413
3414static bool
3415skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3416 const struct skl_ddb_allocation *new,
3417 enum pipe pipe)
3418{
3419 uint16_t old_size, new_size;
3420
3421 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3422 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3423
3424 return old_size != new_size &&
3425 new->pipe[pipe].start >= old->pipe[pipe].start &&
3426 new->pipe[pipe].end <= old->pipe[pipe].end;
3427}
3428
3429static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3430 struct skl_wm_values *new_values)
3431{
3432 struct drm_device *dev = dev_priv->dev;
3433 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3434 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3435 struct intel_crtc *crtc;
3436 enum pipe pipe;
3437
3438 new_ddb = &new_values->ddb;
3439 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3440
3441 /*
3442 * First pass: flush the pipes with the new allocation contained into
3443 * the old space.
3444 *
3445 * We'll wait for the vblank on those pipes to ensure we can safely
3446 * re-allocate the freed space without this pipe fetching from it.
3447 */
3448 for_each_intel_crtc(dev, crtc) {
3449 if (!crtc->active)
3450 continue;
3451
3452 pipe = crtc->pipe;
3453
3454 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3455 continue;
3456
d21b795c 3457 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3458 intel_wait_for_vblank(dev, pipe);
3459
3460 reallocated[pipe] = true;
3461 }
3462
3463
3464 /*
3465 * Second pass: flush the pipes that are having their allocation
3466 * reduced, but overlapping with a previous allocation.
3467 *
3468 * Here as well we need to wait for the vblank to make sure the freed
3469 * space is not used anymore.
3470 */
3471 for_each_intel_crtc(dev, crtc) {
3472 if (!crtc->active)
3473 continue;
3474
3475 pipe = crtc->pipe;
3476
3477 if (reallocated[pipe])
3478 continue;
3479
3480 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3481 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3482 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3483 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3484 reallocated[pipe] = true;
0e8fb7ba 3485 }
0e8fb7ba
DL		 3486 }
3487
3488 /*
3489 * Third pass: flush the pipes that got more space allocated.
3490 *
3491 * We don't need to actively wait for the update here, next vblank
3492 * will just get more DDB space with the correct WM values.
3493 */
3494 for_each_intel_crtc(dev, crtc) {
3495 if (!crtc->active)
3496 continue;
3497
3498 pipe = crtc->pipe;
3499
3500 /*
3501 * At this point, only the pipes more space than before are
3502 * left to re-allocate.
3503 */
3504 if (reallocated[pipe])
3505 continue;
3506
d21b795c 3507 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3508 }
3509}
3510
2d41c0b5 3511static bool skl_update_pipe_wm(struct drm_crtc *crtc,
2d41c0b5
PB		 3512 struct skl_ddb_allocation *ddb, /* out */
3513 struct skl_pipe_wm *pipe_wm /* out */)
3514{
3515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3516 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
2d41c0b5 3517
aa363136 3518 skl_allocate_pipe_ddb(cstate, ddb);
024c9045 3519 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
2d41c0b5 3520
4e0963c7 3521 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
2d41c0b5
PB		 3522 return false;
3523
4e0963c7 3524 intel_crtc->wm.active.skl = *pipe_wm;
2cd601c6 3525
2d41c0b5
PB		 3526 return true;
3527}
3528
3529static void skl_update_other_pipe_wm(struct drm_device *dev,
3530 struct drm_crtc *crtc,
2d41c0b5
PB		 3531 struct skl_wm_values *r)
3532{
3533 struct intel_crtc *intel_crtc;
3534 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3535
3536 /*
3537 * If the WM update hasn't changed the allocation for this_crtc (the
3538 * crtc we are currently computing the new WM values for), other
3539 * enabled crtcs will keep the same allocation and we don't need to
3540 * recompute anything for them.
3541 */
3542 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3543 return;
3544
3545 /*
3546 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3547 * other active pipes need new DDB allocation and WM values.
3548 */
19c8054c 3549 for_each_intel_crtc(dev, intel_crtc) {
2d41c0b5
PB		 3550 struct skl_pipe_wm pipe_wm = {};
3551 bool wm_changed;
3552
3553 if (this_crtc->pipe == intel_crtc->pipe)
3554 continue;
3555
3556 if (!intel_crtc->active)
3557 continue;
3558
aa363136 3559 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
2d41c0b5
PB		 3560 &r->ddb, &pipe_wm);
3561
3562 /*
3563 * If we end up re-computing the other pipe WM values, it's
3564 * because it was really needed, so we expect the WM values to
3565 * be different.
3566 */
3567 WARN_ON(!wm_changed);
3568
024c9045 3569 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
2d41c0b5
PB		 3570 r->dirty[intel_crtc->pipe] = true;
3571 }
3572}
3573
adda50b8
BP		 3574static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3575{
3576 watermarks->wm_linetime[pipe] = 0;
3577 memset(watermarks->plane[pipe], 0,
3578 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
adda50b8
BP		 3579 memset(watermarks->plane_trans[pipe],
3580 0, sizeof(uint32_t) * I915_MAX_PLANES);
4969d33e 3581 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
adda50b8
BP		 3582
3583 /* Clear ddb entries for pipe */
3584 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3585 memset(&watermarks->ddb.plane[pipe], 0,
3586 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3587 memset(&watermarks->ddb.y_plane[pipe], 0,
3588 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
4969d33e
MR		 3589 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3590 sizeof(struct skl_ddb_entry));
adda50b8
BP		 3591
3592}
3593
2d41c0b5
PB		 3594static void skl_update_wm(struct drm_crtc *crtc)
3595{
3596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3597 struct drm_device *dev = crtc->dev;
3598 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3599 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7
MR		 3600 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3601 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
2d41c0b5 3602
adda50b8
BP		 3603
3604 /* Clear all dirty flags */
3605 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3606
3607 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5 3608
aa363136 3609 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
2d41c0b5
PB		 3610 return;
3611
4e0963c7 3612 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
2d41c0b5
PB		 3613 results->dirty[intel_crtc->pipe] = true;
3614
aa363136 3615 skl_update_other_pipe_wm(dev, crtc, results);
2d41c0b5 3616 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3617 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3618
3619 /* store the new configuration */
3620 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3621}
3622
d890565c
VS		 3623static void ilk_compute_wm_config(struct drm_device *dev,
3624 struct intel_wm_config *config)
3625{
3626 struct intel_crtc *crtc;
3627
3628 /* Compute the currently _active_ config */
3629 for_each_intel_crtc(dev, crtc) {
3630 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3631
3632 if (!wm->pipe_enabled)
3633 continue;
3634
3635 config->sprites_enabled |= wm->sprites_enabled;
3636 config->sprites_scaled |= wm->sprites_scaled;
3637 config->num_pipes_active++;
3638 }
3639}
3640
bf220452 3641static void ilk_program_watermarks(struct intel_crtc_state *cstate)
801bcfff 3642{
bf220452
MR		 3643 struct drm_crtc *crtc = cstate->base.crtc;
3644 struct drm_device *dev = crtc->dev;
3645 struct drm_i915_private *dev_priv = to_i915(dev);
b9d5c839 3646 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 3647 struct ilk_wm_maximums max;
d890565c 3648 struct intel_wm_config config = {};
820c1980 3649 struct ilk_wm_values results = {};
77c122bc 3650 enum intel_ddb_partitioning partitioning;
261a27d1 3651
d890565c
VS		 3652 ilk_compute_wm_config(dev, &config);
3653
3654 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3655 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3656
3657 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 3658 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 3659 config.num_pipes_active == 1 && config.sprites_enabled) {
3660 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3661 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3662
820c1980 3663 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3664 } else {
198a1e9b 3665 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3666 }
3667
198a1e9b 3668 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3669 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3670
820c1980 3671 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3672
820c1980 3673 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3674}
3675
bf220452 3676static void ilk_update_wm(struct drm_crtc *crtc)
b9d5c839 3677{
bf220452
MR		 3678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3679 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
b9d5c839 3680
bf220452 3681 WARN_ON(cstate->base.active != intel_crtc->active);
b9d5c839 3682
bf220452
MR		 3683 /*
3684 * IVB workaround: must disable low power watermarks for at least
3685 * one frame before enabling scaling. LP watermarks can be re-enabled
3686 * when scaling is disabled.
3687 *
3688 * WaCxSRDisabledForSpriteScaling:ivb
3689 */
3690 if (cstate->disable_lp_wm) {
3691 ilk_disable_lp_wm(crtc->dev);
3692 intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
396e33ae 3693 }
bf220452
MR		 3694
3695 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3696
3697 ilk_program_watermarks(cstate);
b9d5c839
VS		 3698}
3699
3078999f
PB		 3700static void skl_pipe_wm_active_state(uint32_t val,
3701 struct skl_pipe_wm *active,
3702 bool is_transwm,
3703 bool is_cursor,
3704 int i,
3705 int level)
3706{
3707 bool is_enabled = (val & PLANE_WM_EN) != 0;
3708
3709 if (!is_transwm) {
3710 if (!is_cursor) {
3711 active->wm[level].plane_en[i] = is_enabled;
3712 active->wm[level].plane_res_b[i] =
3713 val & PLANE_WM_BLOCKS_MASK;
3714 active->wm[level].plane_res_l[i] =
3715 (val >> PLANE_WM_LINES_SHIFT) &
3716 PLANE_WM_LINES_MASK;
3717 } else {
4969d33e
MR		 3718 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3719 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 3720 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3721 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3722 (val >> PLANE_WM_LINES_SHIFT) &
3723 PLANE_WM_LINES_MASK;
3724 }
3725 } else {
3726 if (!is_cursor) {
3727 active->trans_wm.plane_en[i] = is_enabled;
3728 active->trans_wm.plane_res_b[i] =
3729 val & PLANE_WM_BLOCKS_MASK;
3730 active->trans_wm.plane_res_l[i] =
3731 (val >> PLANE_WM_LINES_SHIFT) &
3732 PLANE_WM_LINES_MASK;
3733 } else {
4969d33e
MR		 3734 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3735 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 3736 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3737 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3738 (val >> PLANE_WM_LINES_SHIFT) &
3739 PLANE_WM_LINES_MASK;
3740 }
3741 }
3742}
3743
3744static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3745{
3746 struct drm_device *dev = crtc->dev;
3747 struct drm_i915_private *dev_priv = dev->dev_private;
3748 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3750 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3751 struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3078999f
PB		 3752 enum pipe pipe = intel_crtc->pipe;
3753 int level, i, max_level;
3754 uint32_t temp;
3755
3756 max_level = ilk_wm_max_level(dev);
3757
3758 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3759
3760 for (level = 0; level <= max_level; level++) {
3761 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3762 hw->plane[pipe][i][level] =
3763 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 3764 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 3765 }
3766
3767 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3768 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 3769 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 3770
3ef00284 3771 if (!intel_crtc->active)
3078999f
PB		 3772 return;
3773
3774 hw->dirty[pipe] = true;
3775
3776 active->linetime = hw->wm_linetime[pipe];
3777
3778 for (level = 0; level <= max_level; level++) {
3779 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3780 temp = hw->plane[pipe][i][level];
3781 skl_pipe_wm_active_state(temp, active, false,
3782 false, i, level);
3783 }
4969d33e 3784 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 3785 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3786 }
3787
3788 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3789 temp = hw->plane_trans[pipe][i];
3790 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3791 }
3792
4969d33e 3793 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 3794 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 3795
3796 intel_crtc->wm.active.skl = *active;
3078999f
PB		 3797}
3798
3799void skl_wm_get_hw_state(struct drm_device *dev)
3800{
a269c583
DL		 3801 struct drm_i915_private *dev_priv = dev->dev_private;
3802 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3803 struct drm_crtc *crtc;
3804
a269c583 3805 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3806 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3807 skl_pipe_wm_get_hw_state(crtc);
3808}
3809
243e6a44
VS		 3810static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3811{
3812 struct drm_device *dev = crtc->dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3814 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 3815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3816 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3817 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
243e6a44 3818 enum pipe pipe = intel_crtc->pipe;
f0f59a00 3819 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 3820 [PIPE_A] = WM0_PIPEA_ILK,
3821 [PIPE_B] = WM0_PIPEB_ILK,
3822 [PIPE_C] = WM0_PIPEC_IVB,
3823 };
3824
3825 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3826 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3827 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3828
3ef00284 3829 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3830
3831 if (active->pipe_enabled) {
243e6a44
VS		 3832 u32 tmp = hw->wm_pipe[pipe];
3833
3834 /*
3835 * For active pipes LP0 watermark is marked as
3836 * enabled, and LP1+ watermaks as disabled since
3837 * we can't really reverse compute them in case
3838 * multiple pipes are active.
3839 */
3840 active->wm[0].enable = true;
3841 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3842 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3843 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3844 active->linetime = hw->wm_linetime[pipe];
3845 } else {
3846 int level, max_level = ilk_wm_max_level(dev);
3847
3848 /*
3849 * For inactive pipes, all watermark levels
3850 * should be marked as enabled but zeroed,
3851 * which is what we'd compute them to.
3852 */
3853 for (level = 0; level <= max_level; level++)
3854 active->wm[level].enable = true;
3855 }
4e0963c7
MR		 3856
3857 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 3858}
3859
6eb1a681
VS		 3860#define _FW_WM(value, plane) \
3861 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3862#define _FW_WM_VLV(value, plane) \
3863 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3864
3865static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3866 struct vlv_wm_values *wm)
3867{
3868 enum pipe pipe;
3869 uint32_t tmp;
3870
3871 for_each_pipe(dev_priv, pipe) {
3872 tmp = I915_READ(VLV_DDL(pipe));
3873
3874 wm->ddl[pipe].primary =
3875 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3876 wm->ddl[pipe].cursor =
3877 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3878 wm->ddl[pipe].sprite[0] =
3879 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3880 wm->ddl[pipe].sprite[1] =
3881 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3882 }
3883
3884 tmp = I915_READ(DSPFW1);
3885 wm->sr.plane = _FW_WM(tmp, SR);
3886 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3887 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3888 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3889
3890 tmp = I915_READ(DSPFW2);
3891 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3892 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3893 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3894
3895 tmp = I915_READ(DSPFW3);
3896 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3897
3898 if (IS_CHERRYVIEW(dev_priv)) {
3899 tmp = I915_READ(DSPFW7_CHV);
3900 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3901 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3902
3903 tmp = I915_READ(DSPFW8_CHV);
3904 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3905 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3906
3907 tmp = I915_READ(DSPFW9_CHV);
3908 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3909 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3910
3911 tmp = I915_READ(DSPHOWM);
3912 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3913 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3914 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3915 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3916 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3917 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3918 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3919 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3920 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3921 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3922 } else {
3923 tmp = I915_READ(DSPFW7);
3924 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3925 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3926
3927 tmp = I915_READ(DSPHOWM);
3928 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3929 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3930 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3931 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3932 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3933 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3934 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3935 }
3936}
3937
3938#undef _FW_WM
3939#undef _FW_WM_VLV
3940
3941void vlv_wm_get_hw_state(struct drm_device *dev)
3942{
3943 struct drm_i915_private *dev_priv = to_i915(dev);
3944 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3945 struct intel_plane *plane;
3946 enum pipe pipe;
3947 u32 val;
3948
3949 vlv_read_wm_values(dev_priv, wm);
3950
3951 for_each_intel_plane(dev, plane) {
3952 switch (plane->base.type) {
3953 int sprite;
3954 case DRM_PLANE_TYPE_CURSOR:
3955 plane->wm.fifo_size = 63;
3956 break;
3957 case DRM_PLANE_TYPE_PRIMARY:
3958 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3959 break;
3960 case DRM_PLANE_TYPE_OVERLAY:
3961 sprite = plane->plane;
3962 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
3963 break;
3964 }
3965 }
3966
3967 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3968 wm->level = VLV_WM_LEVEL_PM2;
3969
3970 if (IS_CHERRYVIEW(dev_priv)) {
3971 mutex_lock(&dev_priv->rps.hw_lock);
3972
3973 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3974 if (val & DSP_MAXFIFO_PM5_ENABLE)
3975 wm->level = VLV_WM_LEVEL_PM5;
3976
58590c14
VS		 3977 /*
3978 * If DDR DVFS is disabled in the BIOS, Punit
3979 * will never ack the request. So if that happens
3980 * assume we don't have to enable/disable DDR DVFS
3981 * dynamically. To test that just set the REQ_ACK
3982 * bit to poke the Punit, but don't change the
3983 * HIGH/LOW bits so that we don't actually change
3984 * the current state.
3985 */
6eb1a681 3986 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 3987 val |= FORCE_DDR_FREQ_REQ_ACK;
3988 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
3989
3990 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
3991 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
3992 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
3993 "assuming DDR DVFS is disabled\n");
3994 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
3995 } else {
3996 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3997 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
3998 wm->level = VLV_WM_LEVEL_DDR_DVFS;
3999 }
6eb1a681
VS		 4000
4001 mutex_unlock(&dev_priv->rps.hw_lock);
4002 }
4003
4004 for_each_pipe(dev_priv, pipe)
4005 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4006 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4007 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4008
4009 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4010 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4011}
4012
243e6a44
VS		 4013void ilk_wm_get_hw_state(struct drm_device *dev)
4014{
4015 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4016 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4017 struct drm_crtc *crtc;
4018
70e1e0ec 4019 for_each_crtc(dev, crtc)
243e6a44
VS		 4020 ilk_pipe_wm_get_hw_state(crtc);
4021
4022 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4023 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4024 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4025
4026 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4027 if (INTEL_INFO(dev)->gen >= 7) {
4028 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4029 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4030 }
243e6a44 4031
a42a5719 4032 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4033 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4034 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4035 else if (IS_IVYBRIDGE(dev))
4036 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4037 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4038
4039 hw->enable_fbc_wm =
4040 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4041}
4042
b445e3b0
ED		 4043/**
4044 * intel_update_watermarks - update FIFO watermark values based on current modes
4045 *
4046 * Calculate watermark values for the various WM regs based on current mode
4047 * and plane configuration.
4048 *
4049 * There are several cases to deal with here:
4050 * - normal (i.e. non-self-refresh)
4051 * - self-refresh (SR) mode
4052 * - lines are large relative to FIFO size (buffer can hold up to 2)
4053 * - lines are small relative to FIFO size (buffer can hold more than 2
4054 * lines), so need to account for TLB latency
4055 *
4056 * The normal calculation is:
4057 * watermark = dotclock * bytes per pixel * latency
4058 * where latency is platform & configuration dependent (we assume pessimal
4059 * values here).
4060 *
4061 * The SR calculation is:
4062 * watermark = (trunc(latency/line time)+1) * surface width *
4063 * bytes per pixel
4064 * where
4065 * line time = htotal / dotclock
4066 * surface width = hdisplay for normal plane and 64 for cursor
4067 * and latency is assumed to be high, as above.
4068 *
4069 * The final value programmed to the register should always be rounded up,
4070 * and include an extra 2 entries to account for clock crossings.
4071 *
4072 * We don't use the sprite, so we can ignore that. And on Crestline we have
4073 * to set the non-SR watermarks to 8.
4074 */
46ba614c 4075void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4076{
46ba614c 4077 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4078
4079 if (dev_priv->display.update_wm)
46ba614c 4080 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4081}
4082
e2828914 4083/*
9270388e 4084 * Lock protecting IPS related data structures
9270388e
DV		 4085 */
4086DEFINE_SPINLOCK(mchdev_lock);
4087
4088/* Global for IPS driver to get at the current i915 device. Protected by
4089 * mchdev_lock. */
4090static struct drm_i915_private *i915_mch_dev;
4091
2b4e57bd
ED		 4092bool ironlake_set_drps(struct drm_device *dev, u8 val)
4093{
4094 struct drm_i915_private *dev_priv = dev->dev_private;
4095 u16 rgvswctl;
4096
9270388e
DV		 4097 assert_spin_locked(&mchdev_lock);
4098
2b4e57bd
ED		 4099 rgvswctl = I915_READ16(MEMSWCTL);
4100 if (rgvswctl & MEMCTL_CMD_STS) {
4101 DRM_DEBUG("gpu busy, RCS change rejected\n");
4102 return false; /* still busy with another command */
4103 }
4104
4105 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4106 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4107 I915_WRITE16(MEMSWCTL, rgvswctl);
4108 POSTING_READ16(MEMSWCTL);
4109
4110 rgvswctl |= MEMCTL_CMD_STS;
4111 I915_WRITE16(MEMSWCTL, rgvswctl);
4112
4113 return true;
4114}
4115
8090c6b9 4116static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4117{
4118 struct drm_i915_private *dev_priv = dev->dev_private;
84f1b20f 4119 u32 rgvmodectl;
2b4e57bd
ED		 4120 u8 fmax, fmin, fstart, vstart;
4121
9270388e
DV		 4122 spin_lock_irq(&mchdev_lock);
4123
84f1b20f
TU		 4124 rgvmodectl = I915_READ(MEMMODECTL);
4125
2b4e57bd
ED		 4126 /* Enable temp reporting */
4127 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4128 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4129
4130 /* 100ms RC evaluation intervals */
4131 I915_WRITE(RCUPEI, 100000);
4132 I915_WRITE(RCDNEI, 100000);
4133
4134 /* Set max/min thresholds to 90ms and 80ms respectively */
4135 I915_WRITE(RCBMAXAVG, 90000);
4136 I915_WRITE(RCBMINAVG, 80000);
4137
4138 I915_WRITE(MEMIHYST, 1);
4139
4140 /* Set up min, max, and cur for interrupt handling */
4141 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4142 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4143 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4144 MEMMODE_FSTART_SHIFT;
4145
616847e7 4146 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4147 PXVFREQ_PX_SHIFT;
4148
20e4d407
DV		 4149 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4150 dev_priv->ips.fstart = fstart;
2b4e57bd 4151
20e4d407
DV		 4152 dev_priv->ips.max_delay = fstart;
4153 dev_priv->ips.min_delay = fmin;
4154 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4155
4156 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4157 fmax, fmin, fstart);
4158
4159 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4160
4161 /*
4162 * Interrupts will be enabled in ironlake_irq_postinstall
4163 */
4164
4165 I915_WRITE(VIDSTART, vstart);
4166 POSTING_READ(VIDSTART);
4167
4168 rgvmodectl |= MEMMODE_SWMODE_EN;
4169 I915_WRITE(MEMMODECTL, rgvmodectl);
4170
9270388e 4171 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4172 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4173 mdelay(1);
2b4e57bd
ED		 4174
4175 ironlake_set_drps(dev, fstart);
4176
7d81c3e0
VS		 4177 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4178 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4179 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4180 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4181 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4182
4183 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4184}
4185
8090c6b9 4186static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4187{
4188 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4189 u16 rgvswctl;
4190
4191 spin_lock_irq(&mchdev_lock);
4192
4193 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4194
4195 /* Ack interrupts, disable EFC interrupt */
4196 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4197 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4198 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4199 I915_WRITE(DEIIR, DE_PCU_EVENT);
4200 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4201
4202 /* Go back to the starting frequency */
20e4d407 4203 ironlake_set_drps(dev, dev_priv->ips.fstart);
dd92d8de 4204 mdelay(1);
2b4e57bd
ED		 4205 rgvswctl |= MEMCTL_CMD_STS;
4206 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4207 mdelay(1);
2b4e57bd 4208
9270388e 4209 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4210}
4211
acbe9475
DV		 4212/* There's a funny hw issue where the hw returns all 0 when reading from
4213 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4214 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4215 * all limits and the gpu stuck at whatever frequency it is at atm).
4216 */
74ef1173 4217static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4218{
7b9e0ae6 4219 u32 limits;
2b4e57bd 4220
20b46e59
DV		 4221 /* Only set the down limit when we've reached the lowest level to avoid
4222 * getting more interrupts, otherwise leave this clear. This prevents a
4223 * race in the hw when coming out of rc6: There's a tiny window where
4224 * the hw runs at the minimal clock before selecting the desired
4225 * frequency, if the down threshold expires in that window we will not
4226 * receive a down interrupt. */
74ef1173
AG		 4227 if (IS_GEN9(dev_priv->dev)) {
4228 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4229 if (val <= dev_priv->rps.min_freq_softlimit)
4230 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4231 } else {
4232 limits = dev_priv->rps.max_freq_softlimit << 24;
4233 if (val <= dev_priv->rps.min_freq_softlimit)
4234 limits |= dev_priv->rps.min_freq_softlimit << 16;
4235 }
20b46e59
DV		 4236
4237 return limits;
4238}
4239
dd75fdc8
CW		 4240static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4241{
4242 int new_power;
8a586437
AG		 4243 u32 threshold_up = 0, threshold_down = 0; /* in % */
4244 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4245
4246 new_power = dev_priv->rps.power;
4247 switch (dev_priv->rps.power) {
4248 case LOW_POWER:
b39fb297 4249 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4250 new_power = BETWEEN;
4251 break;
4252
4253 case BETWEEN:
b39fb297 4254 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4255 new_power = LOW_POWER;
b39fb297 4256 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4257 new_power = HIGH_POWER;
4258 break;
4259
4260 case HIGH_POWER:
b39fb297 4261 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4262 new_power = BETWEEN;
4263 break;
4264 }
4265 /* Max/min bins are special */
aed242ff 4266 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4267 new_power = LOW_POWER;
aed242ff 4268 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4269 new_power = HIGH_POWER;
4270 if (new_power == dev_priv->rps.power)
4271 return;
4272
4273 /* Note the units here are not exactly 1us, but 1280ns. */
4274 switch (new_power) {
4275 case LOW_POWER:
4276 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4277 ei_up = 16000;
4278 threshold_up = 95;
dd75fdc8
CW		 4279
4280 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4281 ei_down = 32000;
4282 threshold_down = 85;
dd75fdc8
CW		 4283 break;
4284
4285 case BETWEEN:
4286 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4287 ei_up = 13000;
4288 threshold_up = 90;
dd75fdc8
CW		 4289
4290 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4291 ei_down = 32000;
4292 threshold_down = 75;
dd75fdc8
CW		 4293 break;
4294
4295 case HIGH_POWER:
4296 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4297 ei_up = 10000;
4298 threshold_up = 85;
dd75fdc8
CW		 4299
4300 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4301 ei_down = 32000;
4302 threshold_down = 60;
dd75fdc8
CW		 4303 break;
4304 }
4305
8a586437
AG		 4306 I915_WRITE(GEN6_RP_UP_EI,
4307 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4308 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4309 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4310
4311 I915_WRITE(GEN6_RP_DOWN_EI,
4312 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4313 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4314 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4315
4316 I915_WRITE(GEN6_RP_CONTROL,
4317 GEN6_RP_MEDIA_TURBO |
4318 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4319 GEN6_RP_MEDIA_IS_GFX |
4320 GEN6_RP_ENABLE |
4321 GEN6_RP_UP_BUSY_AVG |
4322 GEN6_RP_DOWN_IDLE_AVG);
4323
dd75fdc8 4324 dev_priv->rps.power = new_power;
8fb55197
CW		 4325 dev_priv->rps.up_threshold = threshold_up;
4326 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4327 dev_priv->rps.last_adj = 0;
4328}
4329
2876ce73
CW		 4330static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4331{
4332 u32 mask = 0;
4333
4334 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4335 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4336 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4337 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4338
7b3c29f6
CW		 4339 mask &= dev_priv->pm_rps_events;
4340
59d02a1f 4341 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4342}
4343
b8a5ff8d
JM		 4344/* gen6_set_rps is called to update the frequency request, but should also be
4345 * called when the range (min_delay and max_delay) is modified so that we can
4346 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4347static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4348{
4349 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4350
23eafea6 4351 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4352 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
23eafea6
SAK		 4353 return;
4354
4fc688ce 4355 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4356 WARN_ON(val > dev_priv->rps.max_freq);
4357 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4358
eb64cad1
CW		 4359 /* min/max delay may still have been modified so be sure to
4360 * write the limits value.
4361 */
4362 if (val != dev_priv->rps.cur_freq) {
4363 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4364
5704195c
AG		 4365 if (IS_GEN9(dev))
4366 I915_WRITE(GEN6_RPNSWREQ,
4367 GEN9_FREQUENCY(val));
4368 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4369 I915_WRITE(GEN6_RPNSWREQ,
4370 HSW_FREQUENCY(val));
4371 else
4372 I915_WRITE(GEN6_RPNSWREQ,
4373 GEN6_FREQUENCY(val) |
4374 GEN6_OFFSET(0) |
4375 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4376 }
7b9e0ae6 4377
7b9e0ae6
CW		 4378 /* Make sure we continue to get interrupts
4379 * until we hit the minimum or maximum frequencies.
4380 */
74ef1173 4381 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4382 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4383
d5570a72
BW		 4384 POSTING_READ(GEN6_RPNSWREQ);
4385
b39fb297 4386 dev_priv->rps.cur_freq = val;
0f94592e 4387 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4388}
4389
ffe02b40
VS		 4390static void valleyview_set_rps(struct drm_device *dev, u8 val)
4391{
4392 struct drm_i915_private *dev_priv = dev->dev_private;
4393
4394 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4395 WARN_ON(val > dev_priv->rps.max_freq);
4396 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4397
4398 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4399 "Odd GPU freq value\n"))
4400 val &= ~1;
4401
cd25dd5b
D		 4402 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4403
8fb55197 4404 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4405 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4406 if (!IS_CHERRYVIEW(dev_priv))
4407 gen6_set_rps_thresholds(dev_priv, val);
4408 }
ffe02b40 4409
ffe02b40
VS		 4410 dev_priv->rps.cur_freq = val;
4411 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4412}
4413
a7f6e231 4414/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4415 *
4416 * * If Gfx is Idle, then
a7f6e231
D		 4417 * 1. Forcewake Media well.
4418 * 2. Request idle freq.
4419 * 3. Release Forcewake of Media well.
76c3552f
D		 4420*/
4421static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4422{
aed242ff 4423 u32 val = dev_priv->rps.idle_freq;
5549d25f 4424
aed242ff 4425 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4426 return;
4427
a7f6e231
D		 4428 /* Wake up the media well, as that takes a lot less
4429 * power than the Render well. */
4430 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4431 valleyview_set_rps(dev_priv->dev, val);
4432 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4433}
4434
43cf3bf0
CW		 4435void gen6_rps_busy(struct drm_i915_private *dev_priv)
4436{
4437 mutex_lock(&dev_priv->rps.hw_lock);
4438 if (dev_priv->rps.enabled) {
4439 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4440 gen6_rps_reset_ei(dev_priv);
4441 I915_WRITE(GEN6_PMINTRMSK,
4442 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4443 }
4444 mutex_unlock(&dev_priv->rps.hw_lock);
4445}
4446
b29c19b6
CW		 4447void gen6_rps_idle(struct drm_i915_private *dev_priv)
4448{
691bb717
DL		 4449 struct drm_device *dev = dev_priv->dev;
4450
b29c19b6 4451 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4452 if (dev_priv->rps.enabled) {
666a4537 4453 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
76c3552f 4454 vlv_set_rps_idle(dev_priv);
7526ed79 4455 else
aed242ff 4456 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4457 dev_priv->rps.last_adj = 0;
43cf3bf0 4458 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4459 }
8d3afd7d 4460 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4461
8d3afd7d 4462 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4463 while (!list_empty(&dev_priv->rps.clients))
4464 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4465 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4466}
4467
1854d5ca 4468void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4469 struct intel_rps_client *rps,
4470 unsigned long submitted)
b29c19b6 4471{
8d3afd7d
CW		 4472 /* This is intentionally racy! We peek at the state here, then
4473 * validate inside the RPS worker.
4474 */
4475 if (!(dev_priv->mm.busy &&
4476 dev_priv->rps.enabled &&
4477 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4478 return;
43cf3bf0 4479
e61b9958
CW		 4480 /* Force a RPS boost (and don't count it against the client) if
4481 * the GPU is severely congested.
4482 */
d0bc54f2 4483 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4484 rps = NULL;
4485
8d3afd7d
CW		 4486 spin_lock(&dev_priv->rps.client_lock);
4487 if (rps == NULL || list_empty(&rps->link)) {
4488 spin_lock_irq(&dev_priv->irq_lock);
4489 if (dev_priv->rps.interrupts_enabled) {
4490 dev_priv->rps.client_boost = true;
4491 queue_work(dev_priv->wq, &dev_priv->rps.work);
4492 }
4493 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4494
2e1b8730
CW		 4495 if (rps != NULL) {
4496 list_add(&rps->link, &dev_priv->rps.clients);
4497 rps->boosts++;
1854d5ca
CW		 4498 } else
4499 dev_priv->rps.boosts++;
c0951f0c 4500 }
8d3afd7d 4501 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4502}
4503
ffe02b40 4504void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4505{
666a4537 4506 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
ffe02b40
VS		 4507 valleyview_set_rps(dev, val);
4508 else
4509 gen6_set_rps(dev, val);
0a073b84
JB		 4510}
4511
20e49366
ZW		 4512static void gen9_disable_rps(struct drm_device *dev)
4513{
4514 struct drm_i915_private *dev_priv = dev->dev_private;
4515
4516 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4517 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4518}
4519
44fc7d5c 4520static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4521{
4522 struct drm_i915_private *dev_priv = dev->dev_private;
4523
4524 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4525 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4526}
4527
38807746
D		 4528static void cherryview_disable_rps(struct drm_device *dev)
4529{
4530 struct drm_i915_private *dev_priv = dev->dev_private;
4531
4532 I915_WRITE(GEN6_RC_CONTROL, 0);
4533}
4534
44fc7d5c
DV		 4535static void valleyview_disable_rps(struct drm_device *dev)
4536{
4537 struct drm_i915_private *dev_priv = dev->dev_private;
4538
98a2e5f9
D		 4539 /* we're doing forcewake before Disabling RC6,
4540 * This what the BIOS expects when going into suspend */
59bad947 4541 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4542
44fc7d5c 4543 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4544
59bad947 4545 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4546}
4547
dc39fff7
BW		 4548static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4549{
666a4537 4550 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
91ca689a
ID		 4551 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4552 mode = GEN6_RC_CTL_RC6_ENABLE;
4553 else
4554 mode = 0;
4555 }
58abf1da
RV		 4556 if (HAS_RC6p(dev))
4557 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
87ad3212
JN		 4558 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4559 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4560 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 4561
4562 else
4563 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
87ad3212 4564 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 4565}
4566
274008e8
SAK		 4567static bool bxt_check_bios_rc6_setup(const struct drm_device *dev)
4568{
4569 struct drm_i915_private *dev_priv = dev->dev_private;
4570 bool enable_rc6 = true;
4571 unsigned long rc6_ctx_base;
4572
4573 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4574 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4575 enable_rc6 = false;
4576 }
4577
4578 /*
4579 * The exact context size is not known for BXT, so assume a page size
4580 * for this check.
4581 */
4582 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4583 if (!((rc6_ctx_base >= dev_priv->gtt.stolen_reserved_base) &&
4584 (rc6_ctx_base + PAGE_SIZE <= dev_priv->gtt.stolen_reserved_base +
4585 dev_priv->gtt.stolen_reserved_size))) {
4586 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4587 enable_rc6 = false;
4588 }
4589
4590 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4591 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4592 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4593 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4594 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4595 enable_rc6 = false;
4596 }
4597
4598 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4599 GEN6_RC_CTL_HW_ENABLE)) &&
4600 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4601 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4602 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4603 enable_rc6 = false;
4604 }
4605
4606 return enable_rc6;
4607}
4608
4609int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4610{
e7d66d89
DV		 4611 /* No RC6 before Ironlake and code is gone for ilk. */
4612 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4613 return 0;
4614
274008e8
SAK		 4615 if (!enable_rc6)
4616 return 0;
4617
4618 if (IS_BROXTON(dev) && !bxt_check_bios_rc6_setup(dev)) {
4619 DRM_INFO("RC6 disabled by BIOS\n");
4620 return 0;
4621 }
4622
456470eb 4623 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4624 if (enable_rc6 >= 0) {
4625 int mask;
4626
58abf1da 4627 if (HAS_RC6p(dev))
e6069ca8
ID		 4628 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4629 INTEL_RC6pp_ENABLE;
4630 else
4631 mask = INTEL_RC6_ENABLE;
4632
4633 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4634 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4635 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4636
4637 return enable_rc6 & mask;
4638 }
2b4e57bd 4639
8bade1ad 4640 if (IS_IVYBRIDGE(dev))
cca84a1f 4641 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4642
4643 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4644}
4645
e6069ca8
ID		 4646int intel_enable_rc6(const struct drm_device *dev)
4647{
4648 return i915.enable_rc6;
4649}
4650
93ee2920 4651static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4652{
93ee2920
TR		 4653 struct drm_i915_private *dev_priv = dev->dev_private;
4654 uint32_t rp_state_cap;
4655 u32 ddcc_status = 0;
4656 int ret;
4657
3280e8b0
BW		 4658 /* All of these values are in units of 50MHz */
4659 dev_priv->rps.cur_freq = 0;
93ee2920 4660 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4661 if (IS_BROXTON(dev)) {
4662 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4663 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4664 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4665 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4666 } else {
4667 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4668 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4669 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4670 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4671 }
4672
3280e8b0
BW		 4673 /* hw_max = RP0 until we check for overclocking */
4674 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4675
93ee2920 4676 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
ef11bdb3
RV		 4677 if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4678 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
93ee2920
TR		 4679 ret = sandybridge_pcode_read(dev_priv,
4680 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4681 &ddcc_status);
4682 if (0 == ret)
4683 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4684 clamp_t(u8,
4685 ((ddcc_status >> 8) & 0xff),
4686 dev_priv->rps.min_freq,
4687 dev_priv->rps.max_freq);
93ee2920
TR		 4688 }
4689
ef11bdb3 4690 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
c5e0688c
AG		 4691 /* Store the frequency values in 16.66 MHZ units, which is
4692 the natural hardware unit for SKL */
4693 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4694 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4695 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4696 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4697 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4698 }
4699
aed242ff
CW		 4700 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4701
3280e8b0
BW		 4702 /* Preserve min/max settings in case of re-init */
4703 if (dev_priv->rps.max_freq_softlimit == 0)
4704 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4705
93ee2920
TR		 4706 if (dev_priv->rps.min_freq_softlimit == 0) {
4707 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4708 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4709 max_t(int, dev_priv->rps.efficient_freq,
4710 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4711 else
4712 dev_priv->rps.min_freq_softlimit =
4713 dev_priv->rps.min_freq;
4714 }
3280e8b0
BW		 4715}
4716
b6fef0ef 4717/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4718static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4719{
4720 struct drm_i915_private *dev_priv = dev->dev_private;
4721
4722 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4723
ba1c554c
DL		 4724 gen6_init_rps_frequencies(dev);
4725
23eafea6 4726 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4727 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
23eafea6
SAK		 4728 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4729 return;
4730 }
4731
0beb059a
AG		 4732 /* Program defaults and thresholds for RPS*/
4733 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4734 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4735
4736 /* 1 second timeout*/
4737 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4738 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4739
b6fef0ef 4740 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4741
0beb059a
AG		 4742 /* Leaning on the below call to gen6_set_rps to program/setup the
4743 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4744 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4745 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4746 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4747
4748 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4749}
4750
4751static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4752{
4753 struct drm_i915_private *dev_priv = dev->dev_private;
4754 struct intel_engine_cs *ring;
4755 uint32_t rc6_mask = 0;
4756 int unused;
4757
4758 /* 1a: Software RC state - RC0 */
4759 I915_WRITE(GEN6_RC_STATE, 0);
4760
4761 /* 1b: Get forcewake during program sequence. Although the driver
4762 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4763 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4764
4765 /* 2a: Disable RC states. */
4766 I915_WRITE(GEN6_RC_CONTROL, 0);
4767
4768 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4769
4770 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
e7674b8c 4771 if (IS_SKYLAKE(dev))
63a4dec2
SAK		 4772 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4773 else
4774 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 4775 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4776 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4777 for_each_ring(ring, dev_priv, unused)
4778 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
97c322e7
SAK		 4779
4780 if (HAS_GUC_UCODE(dev))
4781 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4782
20e49366 4783 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 4784
38c23527
ZW		 4785 /* 2c: Program Coarse Power Gating Policies. */
4786 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4787 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4788
20e49366
ZW		 4789 /* 3a: Enable RC6 */
4790 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4791 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 4792 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 4793 /* WaRsUseTimeoutMode */
e87a005d 4794 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
cbdc12a9 4795 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
3e7732a0 4796 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 4797 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4798 GEN7_RC_CTL_TO_MODE |
4799 rc6_mask);
3e7732a0
SAK		 4800 } else {
4801 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 4802 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4803 GEN6_RC_CTL_EI_MODE(1) |
4804 rc6_mask);
3e7732a0 4805 }
20e49366 4806
cb07bae0
SK		 4807 /*
4808 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 4809 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 4810 */
06e668ac 4811 if (NEEDS_WaRsDisableCoarsePowerGating(dev))
f2d2fe95
SAK		 4812 I915_WRITE(GEN9_PG_ENABLE, 0);
4813 else
4814 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4815 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 4816
59bad947 4817 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4818
4819}
4820
6edee7f3
BW		 4821static void gen8_enable_rps(struct drm_device *dev)
4822{
4823 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4824 struct intel_engine_cs *ring;
93ee2920 4825 uint32_t rc6_mask = 0;
6edee7f3
BW		 4826 int unused;
4827
4828 /* 1a: Software RC state - RC0 */
4829 I915_WRITE(GEN6_RC_STATE, 0);
4830
4831 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4832 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4833 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4834
4835 /* 2a: Disable RC states. */
4836 I915_WRITE(GEN6_RC_CONTROL, 0);
4837
93ee2920
TR		 4838 /* Initialize rps frequencies */
4839 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4840
4841 /* 2b: Program RC6 thresholds.*/
4842 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4843 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4844 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4845 for_each_ring(ring, dev_priv, unused)
4846 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4847 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4848 if (IS_BROADWELL(dev))
4849 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4850 else
4851 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4852
4853 /* 3: Enable RC6 */
4854 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4855 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4856 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4857 if (IS_BROADWELL(dev))
4858 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4859 GEN7_RC_CTL_TO_MODE |
4860 rc6_mask);
4861 else
4862 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4863 GEN6_RC_CTL_EI_MODE(1) |
4864 rc6_mask);
6edee7f3
BW		 4865
4866 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4867 I915_WRITE(GEN6_RPNSWREQ,
4868 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4869 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4870 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4871 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4872 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4873
4874 /* Docs recommend 900MHz, and 300 MHz respectively */
4875 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4876 dev_priv->rps.max_freq_softlimit << 24 |
4877 dev_priv->rps.min_freq_softlimit << 16);
4878
4879 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4880 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4881 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4882 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4883
4884 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4885
4886 /* 5: Enable RPS */
7526ed79
DV		 4887 I915_WRITE(GEN6_RP_CONTROL,
4888 GEN6_RP_MEDIA_TURBO |
4889 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4890 GEN6_RP_MEDIA_IS_GFX |
4891 GEN6_RP_ENABLE |
4892 GEN6_RP_UP_BUSY_AVG |
4893 GEN6_RP_DOWN_IDLE_AVG);
4894
4895 /* 6: Ring frequency + overclocking (our driver does this later */
4896
c7f3153a 4897 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4898 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4899
59bad947 4900 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4901}
4902
79f5b2c7 4903static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4904{
79f5b2c7 4905 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4906 struct intel_engine_cs *ring;
d060c169 4907 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4908 u32 gtfifodbg;
2b4e57bd 4909 int rc6_mode;
42c0526c 4910 int i, ret;
2b4e57bd 4911
4fc688ce 4912 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4913
2b4e57bd
ED		 4914 /* Here begins a magic sequence of register writes to enable
4915 * auto-downclocking.
4916 *
4917 * Perhaps there might be some value in exposing these to
4918 * userspace...
4919 */
4920 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4921
4922 /* Clear the DBG now so we don't confuse earlier errors */
4923 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4924 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4925 I915_WRITE(GTFIFODBG, gtfifodbg);
4926 }
4927
59bad947 4928 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4929
93ee2920
TR		 4930 /* Initialize rps frequencies */
4931 gen6_init_rps_frequencies(dev);
dd0a1aa1 4932
2b4e57bd
ED		 4933 /* disable the counters and set deterministic thresholds */
4934 I915_WRITE(GEN6_RC_CONTROL, 0);
4935
4936 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4937 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4938 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4939 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4940 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4941
b4519513
CW		 4942 for_each_ring(ring, dev_priv, i)
4943 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4944
4945 I915_WRITE(GEN6_RC_SLEEP, 0);
4946 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4947 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4948 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4949 else
4950 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4951 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4952 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4953
5a7dc92a 4954 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4955 rc6_mode = intel_enable_rc6(dev_priv->dev);
4956 if (rc6_mode & INTEL_RC6_ENABLE)
4957 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4958
5a7dc92a
ED		 4959 /* We don't use those on Haswell */
4960 if (!IS_HASWELL(dev)) {
4961 if (rc6_mode & INTEL_RC6p_ENABLE)
4962 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4963
5a7dc92a
ED		 4964 if (rc6_mode & INTEL_RC6pp_ENABLE)
4965 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4966 }
2b4e57bd 4967
dc39fff7 4968 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4969
4970 I915_WRITE(GEN6_RC_CONTROL,
4971 rc6_mask |
4972 GEN6_RC_CTL_EI_MODE(1) |
4973 GEN6_RC_CTL_HW_ENABLE);
4974
dd75fdc8
CW		 4975 /* Power down if completely idle for over 50ms */
4976 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4977 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4978
42c0526c 4979 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4980 if (ret)
42c0526c 4981 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4982
4983 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4984 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4985 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4986 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4987 (pcu_mbox & 0xff) * 50);
b39fb297 4988 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4989 }
4990
dd75fdc8 4991 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4992 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 4993
31643d54
BW		 4994 rc6vids = 0;
4995 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4996 if (IS_GEN6(dev) && ret) {
4997 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4998 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4999 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5000 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5001 rc6vids &= 0xffff00;
5002 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5003 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5004 if (ret)
5005 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5006 }
5007
59bad947 5008 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5009}
5010
c2bc2fc5 5011static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 5012{
79f5b2c7 5013 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 5014 int min_freq = 15;
3ebecd07
CW		 5015 unsigned int gpu_freq;
5016 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5017 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5018 int scaling_factor = 180;
eda79642 5019 struct cpufreq_policy *policy;
2b4e57bd 5020
4fc688ce 5021 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5022
eda79642
BW		 5023 policy = cpufreq_cpu_get(0);
5024 if (policy) {
5025 max_ia_freq = policy->cpuinfo.max_freq;
5026 cpufreq_cpu_put(policy);
5027 } else {
5028 /*
5029 * Default to measured freq if none found, PCU will ensure we
5030 * don't go over
5031 */
2b4e57bd 5032 max_ia_freq = tsc_khz;
eda79642 5033 }
2b4e57bd
ED		 5034
5035 /* Convert from kHz to MHz */
5036 max_ia_freq /= 1000;
5037
153b4b95 5038 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5039 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5040 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5041
ef11bdb3 5042 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 5043 /* Convert GT frequency to 50 HZ units */
5044 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5045 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5046 } else {
5047 min_gpu_freq = dev_priv->rps.min_freq;
5048 max_gpu_freq = dev_priv->rps.max_freq;
5049 }
5050
2b4e57bd
ED		 5051 /*
5052 * For each potential GPU frequency, load a ring frequency we'd like
5053 * to use for memory access. We do this by specifying the IA frequency
5054 * the PCU should use as a reference to determine the ring frequency.
5055 */
4c8c7743
AG		 5056 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5057 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5058 unsigned int ia_freq = 0, ring_freq = 0;
5059
ef11bdb3 5060 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 5061 /*
5062 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5063 * No floor required for ring frequency on SKL.
5064 */
5065 ring_freq = gpu_freq;
5066 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 5067 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5068 ring_freq = max(min_ring_freq, gpu_freq);
5069 } else if (IS_HASWELL(dev)) {
f6aca45c 5070 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5071 ring_freq = max(min_ring_freq, ring_freq);
5072 /* leave ia_freq as the default, chosen by cpufreq */
5073 } else {
5074 /* On older processors, there is no separate ring
5075 * clock domain, so in order to boost the bandwidth
5076 * of the ring, we need to upclock the CPU (ia_freq).
5077 *
5078 * For GPU frequencies less than 750MHz,
5079 * just use the lowest ring freq.
5080 */
5081 if (gpu_freq < min_freq)
5082 ia_freq = 800;
5083 else
5084 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5085 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5086 }
2b4e57bd 5087
42c0526c
BW		 5088 sandybridge_pcode_write(dev_priv,
5089 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5090 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5091 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5092 gpu_freq);
2b4e57bd 5093 }
2b4e57bd
ED		 5094}
5095
c2bc2fc5
ID		 5096void gen6_update_ring_freq(struct drm_device *dev)
5097{
5098 struct drm_i915_private *dev_priv = dev->dev_private;
5099
97d3308a 5100 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5101 return;
5102
5103 mutex_lock(&dev_priv->rps.hw_lock);
5104 __gen6_update_ring_freq(dev);
5105 mutex_unlock(&dev_priv->rps.hw_lock);
5106}
5107
03af2045 5108static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5109{
095acd5f 5110 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5111 u32 val, rp0;
5112
5b5929cb 5113 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5114
5b5929cb
JN		 5115 switch (INTEL_INFO(dev)->eu_total) {
5116 case 8:
5117 /* (2 * 4) config */
5118 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5119 break;
5120 case 12:
5121 /* (2 * 6) config */
5122 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5123 break;
5124 case 16:
5125 /* (2 * 8) config */
5126 default:
5127 /* Setting (2 * 8) Min RP0 for any other combination */
5128 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5129 break;
095acd5f 5130 }
5b5929cb
JN		 5131
5132 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5133
2b6b3a09
D		 5134 return rp0;
5135}
5136
5137static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5138{
5139 u32 val, rpe;
5140
5141 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5142 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5143
5144 return rpe;
5145}
5146
7707df4a
D		 5147static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5148{
5149 u32 val, rp1;
5150
5b5929cb
JN		 5151 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5152 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5153
7707df4a
D		 5154 return rp1;
5155}
5156
f8f2b001
D		 5157static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5158{
5159 u32 val, rp1;
5160
5161 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5162
5163 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5164
5165 return rp1;
5166}
5167
03af2045 5168static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5169{
5170 u32 val, rp0;
5171
64936258 5172 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5173
5174 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5175 /* Clamp to max */
5176 rp0 = min_t(u32, rp0, 0xea);
5177
5178 return rp0;
5179}
5180
5181static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5182{
5183 u32 val, rpe;
5184
64936258 5185 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5186 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5187 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5188 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5189
5190 return rpe;
5191}
5192
03af2045 5193static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5194{
36146035
ID		 5195 u32 val;
5196
5197 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5198 /*
5199 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5200 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5201 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5202 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5203 * to make sure it matches what Punit accepts.
5204 */
5205 return max_t(u32, val, 0xc0);
0a073b84
JB		 5206}
5207
ae48434c
ID		 5208/* Check that the pctx buffer wasn't move under us. */
5209static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5210{
5211 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5212
5213 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5214 dev_priv->vlv_pctx->stolen->start);
5215}
5216
38807746
D		 5217
5218/* Check that the pcbr address is not empty. */
5219static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5220{
5221 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5222
5223 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5224}
5225
5226static void cherryview_setup_pctx(struct drm_device *dev)
5227{
5228 struct drm_i915_private *dev_priv = dev->dev_private;
5229 unsigned long pctx_paddr, paddr;
5230 struct i915_gtt *gtt = &dev_priv->gtt;
5231 u32 pcbr;
5232 int pctx_size = 32*1024;
5233
38807746
D		 5234 pcbr = I915_READ(VLV_PCBR);
5235 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5236 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5237 paddr = (dev_priv->mm.stolen_base +
5238 (gtt->stolen_size - pctx_size));
5239
5240 pctx_paddr = (paddr & (~4095));
5241 I915_WRITE(VLV_PCBR, pctx_paddr);
5242 }
ce611ef8
VS		 5243
5244 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5245}
5246
c9cddffc
JB		 5247static void valleyview_setup_pctx(struct drm_device *dev)
5248{
5249 struct drm_i915_private *dev_priv = dev->dev_private;
5250 struct drm_i915_gem_object *pctx;
5251 unsigned long pctx_paddr;
5252 u32 pcbr;
5253 int pctx_size = 24*1024;
5254
ee504898 5255 mutex_lock(&dev->struct_mutex);
17b0c1f7 5256
c9cddffc
JB		 5257 pcbr = I915_READ(VLV_PCBR);
5258 if (pcbr) {
5259 /* BIOS set it up already, grab the pre-alloc'd space */
5260 int pcbr_offset;
5261
5262 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5263 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5264 pcbr_offset,
190d6cd5 5265 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5266 pctx_size);
5267 goto out;
5268 }
5269
ce611ef8
VS		 5270 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5271
c9cddffc
JB		 5272 /*
5273 * From the Gunit register HAS:
5274 * The Gfx driver is expected to program this register and ensure
5275 * proper allocation within Gfx stolen memory. For example, this
5276 * register should be programmed such than the PCBR range does not
5277 * overlap with other ranges, such as the frame buffer, protected
5278 * memory, or any other relevant ranges.
5279 */
5280 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5281 if (!pctx) {
5282 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5283 goto out;
c9cddffc
JB		 5284 }
5285
5286 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5287 I915_WRITE(VLV_PCBR, pctx_paddr);
5288
5289out:
ce611ef8 5290 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc 5291 dev_priv->vlv_pctx = pctx;
ee504898 5292 mutex_unlock(&dev->struct_mutex);
c9cddffc
JB		 5293}
5294
ae48434c
ID		 5295static void valleyview_cleanup_pctx(struct drm_device *dev)
5296{
5297 struct drm_i915_private *dev_priv = dev->dev_private;
5298
5299 if (WARN_ON(!dev_priv->vlv_pctx))
5300 return;
5301
ee504898 5302 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
ae48434c
ID		 5303 dev_priv->vlv_pctx = NULL;
5304}
5305
4e80519e
ID		 5306static void valleyview_init_gt_powersave(struct drm_device *dev)
5307{
5308 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5309 u32 val;
4e80519e
ID		 5310
5311 valleyview_setup_pctx(dev);
5312
5313 mutex_lock(&dev_priv->rps.hw_lock);
5314
2bb25c17
VS		 5315 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5316 switch ((val >> 6) & 3) {
5317 case 0:
5318 case 1:
5319 dev_priv->mem_freq = 800;
5320 break;
5321 case 2:
5322 dev_priv->mem_freq = 1066;
5323 break;
5324 case 3:
5325 dev_priv->mem_freq = 1333;
5326 break;
5327 }
80b83b62 5328 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5329
4e80519e
ID		 5330 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5331 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5332 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5333 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5334 dev_priv->rps.max_freq);
5335
5336 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5337 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5338 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5339 dev_priv->rps.efficient_freq);
5340
f8f2b001
D		 5341 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5342 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5343 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5344 dev_priv->rps.rp1_freq);
5345
4e80519e
ID		 5346 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5347 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5348 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5349 dev_priv->rps.min_freq);
5350
aed242ff
CW		 5351 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5352
4e80519e
ID		 5353 /* Preserve min/max settings in case of re-init */
5354 if (dev_priv->rps.max_freq_softlimit == 0)
5355 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5356
5357 if (dev_priv->rps.min_freq_softlimit == 0)
5358 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5359
5360 mutex_unlock(&dev_priv->rps.hw_lock);
5361}
5362
38807746
D		 5363static void cherryview_init_gt_powersave(struct drm_device *dev)
5364{
2b6b3a09 5365 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5366 u32 val;
2b6b3a09 5367
38807746 5368 cherryview_setup_pctx(dev);
2b6b3a09
D		 5369
5370 mutex_lock(&dev_priv->rps.hw_lock);
5371
a580516d 5372 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5373 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5374 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5375
2bb25c17 5376 switch ((val >> 2) & 0x7) {
2bb25c17 5377 case 3:
2bb25c17
VS		 5378 dev_priv->mem_freq = 2000;
5379 break;
bfa7df01 5380 default:
2bb25c17
VS		 5381 dev_priv->mem_freq = 1600;
5382 break;
5383 }
80b83b62 5384 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5385
2b6b3a09
D		 5386 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5387 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5388 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5389 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5390 dev_priv->rps.max_freq);
5391
5392 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5393 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5394 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5395 dev_priv->rps.efficient_freq);
5396
7707df4a
D		 5397 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5398 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5399 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5400 dev_priv->rps.rp1_freq);
5401
5b7c91b7
D		 5402 /* PUnit validated range is only [RPe, RP0] */
5403 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5404 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5405 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5406 dev_priv->rps.min_freq);
5407
1c14762d
VS		 5408 WARN_ONCE((dev_priv->rps.max_freq |
5409 dev_priv->rps.efficient_freq |
5410 dev_priv->rps.rp1_freq |
5411 dev_priv->rps.min_freq) & 1,
5412 "Odd GPU freq values\n");
5413
aed242ff
CW		 5414 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5415
2b6b3a09
D		 5416 /* Preserve min/max settings in case of re-init */
5417 if (dev_priv->rps.max_freq_softlimit == 0)
5418 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5419
5420 if (dev_priv->rps.min_freq_softlimit == 0)
5421 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5422
5423 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5424}
5425
4e80519e
ID		 5426static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5427{
5428 valleyview_cleanup_pctx(dev);
5429}
5430
38807746
D		 5431static void cherryview_enable_rps(struct drm_device *dev)
5432{
5433 struct drm_i915_private *dev_priv = dev->dev_private;
5434 struct intel_engine_cs *ring;
2b6b3a09 5435 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5436 int i;
5437
5438 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5439
5440 gtfifodbg = I915_READ(GTFIFODBG);
5441 if (gtfifodbg) {
5442 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5443 gtfifodbg);
5444 I915_WRITE(GTFIFODBG, gtfifodbg);
5445 }
5446
5447 cherryview_check_pctx(dev_priv);
5448
5449 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5450 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5451 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5452
160614a2
VS		 5453 /* Disable RC states. */
5454 I915_WRITE(GEN6_RC_CONTROL, 0);
5455
38807746
D		 5456 /* 2a: Program RC6 thresholds.*/
5457 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5458 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5459 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5460
5461 for_each_ring(ring, dev_priv, i)
5462 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5463 I915_WRITE(GEN6_RC_SLEEP, 0);
5464
f4f71c7d
D		 5465 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5466 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5467
5468 /* allows RC6 residency counter to work */
5469 I915_WRITE(VLV_COUNTER_CONTROL,
5470 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5471 VLV_MEDIA_RC6_COUNT_EN |
5472 VLV_RENDER_RC6_COUNT_EN));
5473
5474 /* For now we assume BIOS is allocating and populating the PCBR */
5475 pcbr = I915_READ(VLV_PCBR);
5476
38807746
D		 5477 /* 3: Enable RC6 */
5478 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5479 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5480 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5481
5482 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5483
2b6b3a09 5484 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5485 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5486 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5487 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5488 I915_WRITE(GEN6_RP_UP_EI, 66000);
5489 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5490
5491 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5492
5493 /* 5: Enable RPS */
5494 I915_WRITE(GEN6_RP_CONTROL,
5495 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5496 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5497 GEN6_RP_ENABLE |
5498 GEN6_RP_UP_BUSY_AVG |
5499 GEN6_RP_DOWN_IDLE_AVG);
5500
3ef62342
D		 5501 /* Setting Fixed Bias */
5502 val = VLV_OVERRIDE_EN |
5503 VLV_SOC_TDP_EN |
5504 CHV_BIAS_CPU_50_SOC_50;
5505 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5506
2b6b3a09
D		 5507 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5508
8d40c3ae
VS		 5509 /* RPS code assumes GPLL is used */
5510 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5511
742f491d 5512 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5513 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5514
5515 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5516 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5517 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5518 dev_priv->rps.cur_freq);
5519
5520 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5521 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5522 dev_priv->rps.efficient_freq);
5523
5524 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5525
59bad947 5526 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5527}
5528
0a073b84
JB		 5529static void valleyview_enable_rps(struct drm_device *dev)
5530{
5531 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5532 struct intel_engine_cs *ring;
2a5913a8 5533 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5534 int i;
5535
5536 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5537
ae48434c
ID		 5538 valleyview_check_pctx(dev_priv);
5539
0a073b84 5540 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5541 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5542 gtfifodbg);
0a073b84
JB		 5543 I915_WRITE(GTFIFODBG, gtfifodbg);
5544 }
5545
c8d9a590 5546 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5547 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5548
160614a2
VS		 5549 /* Disable RC states. */
5550 I915_WRITE(GEN6_RC_CONTROL, 0);
5551
cad725fe 5552 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5553 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5554 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5555 I915_WRITE(GEN6_RP_UP_EI, 66000);
5556 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5557
5558 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5559
5560 I915_WRITE(GEN6_RP_CONTROL,
5561 GEN6_RP_MEDIA_TURBO |
5562 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5563 GEN6_RP_MEDIA_IS_GFX |
5564 GEN6_RP_ENABLE |
5565 GEN6_RP_UP_BUSY_AVG |
5566 GEN6_RP_DOWN_IDLE_CONT);
5567
5568 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5569 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5570 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5571
5572 for_each_ring(ring, dev_priv, i)
5573 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5574
2f0aa304 5575 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5576
5577 /* allows RC6 residency counter to work */
49798eb2 5578 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5579 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5580 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5581 VLV_MEDIA_RC6_COUNT_EN |
5582 VLV_RENDER_RC6_COUNT_EN));
31685c25 5583
a2b23fe0 5584 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5585 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5586
5587 intel_print_rc6_info(dev, rc6_mode);
5588
a2b23fe0 5589 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5590
3ef62342
D		 5591 /* Setting Fixed Bias */
5592 val = VLV_OVERRIDE_EN |
5593 VLV_SOC_TDP_EN |
5594 VLV_BIAS_CPU_125_SOC_875;
5595 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5596
64936258 5597 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5598
8d40c3ae
VS		 5599 /* RPS code assumes GPLL is used */
5600 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5601
742f491d 5602 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5603 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5604
b39fb297 5605 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5606 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5607 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5608 dev_priv->rps.cur_freq);
0a073b84 5609
73008b98 5610 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5611 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5612 dev_priv->rps.efficient_freq);
0a073b84 5613
b39fb297 5614 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5615
59bad947 5616 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5617}
5618
dde18883
ED		 5619static unsigned long intel_pxfreq(u32 vidfreq)
5620{
5621 unsigned long freq;
5622 int div = (vidfreq & 0x3f0000) >> 16;
5623 int post = (vidfreq & 0x3000) >> 12;
5624 int pre = (vidfreq & 0x7);
5625
5626 if (!pre)
5627 return 0;
5628
5629 freq = ((div * 133333) / ((1<<post) * pre));
5630
5631 return freq;
5632}
5633
eb48eb00
DV		 5634static const struct cparams {
5635 u16 i;
5636 u16 t;
5637 u16 m;
5638 u16 c;
5639} cparams[] = {
5640 { 1, 1333, 301, 28664 },
5641 { 1, 1066, 294, 24460 },
5642 { 1, 800, 294, 25192 },
5643 { 0, 1333, 276, 27605 },
5644 { 0, 1066, 276, 27605 },
5645 { 0, 800, 231, 23784 },
5646};
5647
f531dcb2 5648static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5649{
5650 u64 total_count, diff, ret;
5651 u32 count1, count2, count3, m = 0, c = 0;
5652 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5653 int i;
5654
02d71956
DV		 5655 assert_spin_locked(&mchdev_lock);
5656
20e4d407 5657 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5658
5659 /* Prevent division-by-zero if we are asking too fast.
5660 * Also, we don't get interesting results if we are polling
5661 * faster than once in 10ms, so just return the saved value
5662 * in such cases.
5663 */
5664 if (diff1 <= 10)
20e4d407 5665 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5666
5667 count1 = I915_READ(DMIEC);
5668 count2 = I915_READ(DDREC);
5669 count3 = I915_READ(CSIEC);
5670
5671 total_count = count1 + count2 + count3;
5672
5673 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5674 if (total_count < dev_priv->ips.last_count1) {
5675 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5676 diff += total_count;
5677 } else {
20e4d407 5678 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5679 }
5680
5681 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5682 if (cparams[i].i == dev_priv->ips.c_m &&
5683 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5684 m = cparams[i].m;
5685 c = cparams[i].c;
5686 break;
5687 }
5688 }
5689
5690 diff = div_u64(diff, diff1);
5691 ret = ((m * diff) + c);
5692 ret = div_u64(ret, 10);
5693
20e4d407
DV		 5694 dev_priv->ips.last_count1 = total_count;
5695 dev_priv->ips.last_time1 = now;
eb48eb00 5696
20e4d407 5697 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5698
5699 return ret;
5700}
5701
f531dcb2
CW		 5702unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5703{
3d13ef2e 5704 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5705 unsigned long val;
5706
3d13ef2e 5707 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5708 return 0;
5709
5710 spin_lock_irq(&mchdev_lock);
5711
5712 val = __i915_chipset_val(dev_priv);
5713
5714 spin_unlock_irq(&mchdev_lock);
5715
5716 return val;
5717}
5718
eb48eb00
DV		 5719unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5720{
5721 unsigned long m, x, b;
5722 u32 tsfs;
5723
5724 tsfs = I915_READ(TSFS);
5725
5726 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5727 x = I915_READ8(TR1);
5728
5729 b = tsfs & TSFS_INTR_MASK;
5730
5731 return ((m * x) / 127) - b;
5732}
5733
d972d6ee
MK		 5734static int _pxvid_to_vd(u8 pxvid)
5735{
5736 if (pxvid == 0)
5737 return 0;
5738
5739 if (pxvid >= 8 && pxvid < 31)
5740 pxvid = 31;
5741
5742 return (pxvid + 2) * 125;
5743}
5744
5745static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5746{
3d13ef2e 5747 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5748 const int vd = _pxvid_to_vd(pxvid);
5749 const int vm = vd - 1125;
5750
3d13ef2e 5751 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5752 return vm > 0 ? vm : 0;
5753
5754 return vd;
eb48eb00
DV		 5755}
5756
02d71956 5757static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5758{
5ed0bdf2 5759 u64 now, diff, diffms;
eb48eb00
DV		 5760 u32 count;
5761
02d71956 5762 assert_spin_locked(&mchdev_lock);
eb48eb00 5763
5ed0bdf2
TG		 5764 now = ktime_get_raw_ns();
5765 diffms = now - dev_priv->ips.last_time2;
5766 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5767
5768 /* Don't divide by 0 */
eb48eb00
DV		 5769 if (!diffms)
5770 return;
5771
5772 count = I915_READ(GFXEC);
5773
20e4d407
DV		 5774 if (count < dev_priv->ips.last_count2) {
5775 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5776 diff += count;
5777 } else {
20e4d407 5778 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5779 }
5780
20e4d407
DV		 5781 dev_priv->ips.last_count2 = count;
5782 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5783
5784 /* More magic constants... */
5785 diff = diff * 1181;
5786 diff = div_u64(diff, diffms * 10);
20e4d407 5787 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5788}
5789
02d71956
DV		 5790void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5791{
3d13ef2e
DL		 5792 struct drm_device *dev = dev_priv->dev;
5793
5794 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5795 return;
5796
9270388e 5797 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5798
5799 __i915_update_gfx_val(dev_priv);
5800
9270388e 5801 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5802}
5803
f531dcb2 5804static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5805{
5806 unsigned long t, corr, state1, corr2, state2;
5807 u32 pxvid, ext_v;
5808
02d71956
DV		 5809 assert_spin_locked(&mchdev_lock);
5810
616847e7 5811 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 5812 pxvid = (pxvid >> 24) & 0x7f;
5813 ext_v = pvid_to_extvid(dev_priv, pxvid);
5814
5815 state1 = ext_v;
5816
5817 t = i915_mch_val(dev_priv);
5818
5819 /* Revel in the empirically derived constants */
5820
5821 /* Correction factor in 1/100000 units */
5822 if (t > 80)
5823 corr = ((t * 2349) + 135940);
5824 else if (t >= 50)
5825 corr = ((t * 964) + 29317);
5826 else /* < 50 */
5827 corr = ((t * 301) + 1004);
5828
5829 corr = corr * ((150142 * state1) / 10000 - 78642);
5830 corr /= 100000;
20e4d407 5831 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5832
5833 state2 = (corr2 * state1) / 10000;
5834 state2 /= 100; /* convert to mW */
5835
02d71956 5836 __i915_update_gfx_val(dev_priv);
eb48eb00 5837
20e4d407 5838 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5839}
5840
f531dcb2
CW		 5841unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5842{
3d13ef2e 5843 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5844 unsigned long val;
5845
3d13ef2e 5846 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5847 return 0;
5848
5849 spin_lock_irq(&mchdev_lock);
5850
5851 val = __i915_gfx_val(dev_priv);
5852
5853 spin_unlock_irq(&mchdev_lock);
5854
5855 return val;
5856}
5857
eb48eb00
DV		 5858/**
5859 * i915_read_mch_val - return value for IPS use
5860 *
5861 * Calculate and return a value for the IPS driver to use when deciding whether
5862 * we have thermal and power headroom to increase CPU or GPU power budget.
5863 */
5864unsigned long i915_read_mch_val(void)
5865{
5866 struct drm_i915_private *dev_priv;
5867 unsigned long chipset_val, graphics_val, ret = 0;
5868
9270388e 5869 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5870 if (!i915_mch_dev)
5871 goto out_unlock;
5872 dev_priv = i915_mch_dev;
5873
f531dcb2
CW		 5874 chipset_val = __i915_chipset_val(dev_priv);
5875 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5876
5877 ret = chipset_val + graphics_val;
5878
5879out_unlock:
9270388e 5880 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5881
5882 return ret;
5883}
5884EXPORT_SYMBOL_GPL(i915_read_mch_val);
5885
5886/**
5887 * i915_gpu_raise - raise GPU frequency limit
5888 *
5889 * Raise the limit; IPS indicates we have thermal headroom.
5890 */
5891bool i915_gpu_raise(void)
5892{
5893 struct drm_i915_private *dev_priv;
5894 bool ret = true;
5895
9270388e 5896 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5897 if (!i915_mch_dev) {
5898 ret = false;
5899 goto out_unlock;
5900 }
5901 dev_priv = i915_mch_dev;
5902
20e4d407
DV		 5903 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5904 dev_priv->ips.max_delay--;
eb48eb00
DV		 5905
5906out_unlock:
9270388e 5907 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5908
5909 return ret;
5910}
5911EXPORT_SYMBOL_GPL(i915_gpu_raise);
5912
5913/**
5914 * i915_gpu_lower - lower GPU frequency limit
5915 *
5916 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5917 * frequency maximum.
5918 */
5919bool i915_gpu_lower(void)
5920{
5921 struct drm_i915_private *dev_priv;
5922 bool ret = true;
5923
9270388e 5924 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5925 if (!i915_mch_dev) {
5926 ret = false;
5927 goto out_unlock;
5928 }
5929 dev_priv = i915_mch_dev;
5930
20e4d407
DV		 5931 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5932 dev_priv->ips.max_delay++;
eb48eb00
DV		 5933
5934out_unlock:
9270388e 5935 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5936
5937 return ret;
5938}
5939EXPORT_SYMBOL_GPL(i915_gpu_lower);
5940
5941/**
5942 * i915_gpu_busy - indicate GPU business to IPS
5943 *
5944 * Tell the IPS driver whether or not the GPU is busy.
5945 */
5946bool i915_gpu_busy(void)
5947{
5948 struct drm_i915_private *dev_priv;
a4872ba6 5949 struct intel_engine_cs *ring;
eb48eb00 5950 bool ret = false;
f047e395 5951 int i;
eb48eb00 5952
9270388e 5953 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5954 if (!i915_mch_dev)
5955 goto out_unlock;
5956 dev_priv = i915_mch_dev;
5957
f047e395
CW		 5958 for_each_ring(ring, dev_priv, i)
5959 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5960
5961out_unlock:
9270388e 5962 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5963
5964 return ret;
5965}
5966EXPORT_SYMBOL_GPL(i915_gpu_busy);
5967
5968/**
5969 * i915_gpu_turbo_disable - disable graphics turbo
5970 *
5971 * Disable graphics turbo by resetting the max frequency and setting the
5972 * current frequency to the default.
5973 */
5974bool i915_gpu_turbo_disable(void)
5975{
5976 struct drm_i915_private *dev_priv;
5977 bool ret = true;
5978
9270388e 5979 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5980 if (!i915_mch_dev) {
5981 ret = false;
5982 goto out_unlock;
5983 }
5984 dev_priv = i915_mch_dev;
5985
20e4d407 5986 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5987
20e4d407 5988 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5989 ret = false;
5990
5991out_unlock:
9270388e 5992 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5993
5994 return ret;
5995}
5996EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5997
5998/**
5999 * Tells the intel_ips driver that the i915 driver is now loaded, if
6000 * IPS got loaded first.
6001 *
6002 * This awkward dance is so that neither module has to depend on the
6003 * other in order for IPS to do the appropriate communication of
6004 * GPU turbo limits to i915.
6005 */
6006static void
6007ips_ping_for_i915_load(void)
6008{
6009 void (*link)(void);
6010
6011 link = symbol_get(ips_link_to_i915_driver);
6012 if (link) {
6013 link();
6014 symbol_put(ips_link_to_i915_driver);
6015 }
6016}
6017
6018void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6019{
02d71956
DV		 6020 /* We only register the i915 ips part with intel-ips once everything is
6021 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6022 spin_lock_irq(&mchdev_lock);
eb48eb00 6023 i915_mch_dev = dev_priv;
9270388e 6024 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6025
6026 ips_ping_for_i915_load();
6027}
6028
6029void intel_gpu_ips_teardown(void)
6030{
9270388e 6031 spin_lock_irq(&mchdev_lock);
eb48eb00 6032 i915_mch_dev = NULL;
9270388e 6033 spin_unlock_irq(&mchdev_lock);
eb48eb00 6034}
76c3552f 6035
8090c6b9 6036static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 6037{
6038 struct drm_i915_private *dev_priv = dev->dev_private;
6039 u32 lcfuse;
6040 u8 pxw[16];
6041 int i;
6042
6043 /* Disable to program */
6044 I915_WRITE(ECR, 0);
6045 POSTING_READ(ECR);
6046
6047 /* Program energy weights for various events */
6048 I915_WRITE(SDEW, 0x15040d00);
6049 I915_WRITE(CSIEW0, 0x007f0000);
6050 I915_WRITE(CSIEW1, 0x1e220004);
6051 I915_WRITE(CSIEW2, 0x04000004);
6052
6053 for (i = 0; i < 5; i++)
616847e7 6054 I915_WRITE(PEW(i), 0);
dde18883 6055 for (i = 0; i < 3; i++)
616847e7 6056 I915_WRITE(DEW(i), 0);
dde18883
ED		 6057
6058 /* Program P-state weights to account for frequency power adjustment */
6059 for (i = 0; i < 16; i++) {
616847e7 6060 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6061 unsigned long freq = intel_pxfreq(pxvidfreq);
6062 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6063 PXVFREQ_PX_SHIFT;
6064 unsigned long val;
6065
6066 val = vid * vid;
6067 val *= (freq / 1000);
6068 val *= 255;
6069 val /= (127*127*900);
6070 if (val > 0xff)
6071 DRM_ERROR("bad pxval: %ld\n", val);
6072 pxw[i] = val;
6073 }
6074 /* Render standby states get 0 weight */
6075 pxw[14] = 0;
6076 pxw[15] = 0;
6077
6078 for (i = 0; i < 4; i++) {
6079 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6080 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6081 I915_WRITE(PXW(i), val);
dde18883
ED		 6082 }
6083
6084 /* Adjust magic regs to magic values (more experimental results) */
6085 I915_WRITE(OGW0, 0);
6086 I915_WRITE(OGW1, 0);
6087 I915_WRITE(EG0, 0x00007f00);
6088 I915_WRITE(EG1, 0x0000000e);
6089 I915_WRITE(EG2, 0x000e0000);
6090 I915_WRITE(EG3, 0x68000300);
6091 I915_WRITE(EG4, 0x42000000);
6092 I915_WRITE(EG5, 0x00140031);
6093 I915_WRITE(EG6, 0);
6094 I915_WRITE(EG7, 0);
6095
6096 for (i = 0; i < 8; i++)
616847e7 6097 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6098
6099 /* Enable PMON + select events */
6100 I915_WRITE(ECR, 0x80000019);
6101
6102 lcfuse = I915_READ(LCFUSE02);
6103
20e4d407 6104 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6105}
6106
ae48434c
ID		 6107void intel_init_gt_powersave(struct drm_device *dev)
6108{
b268c699
ID		 6109 struct drm_i915_private *dev_priv = dev->dev_private;
6110
b268c699
ID		 6111 /*
6112 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6113 * requirement.
6114 */
6115 if (!i915.enable_rc6) {
6116 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6117 intel_runtime_pm_get(dev_priv);
6118 }
e6069ca8 6119
38807746
D		 6120 if (IS_CHERRYVIEW(dev))
6121 cherryview_init_gt_powersave(dev);
6122 else if (IS_VALLEYVIEW(dev))
4e80519e 6123 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6124}
6125
6126void intel_cleanup_gt_powersave(struct drm_device *dev)
6127{
b268c699
ID		 6128 struct drm_i915_private *dev_priv = dev->dev_private;
6129
38807746
D		 6130 if (IS_CHERRYVIEW(dev))
6131 return;
6132 else if (IS_VALLEYVIEW(dev))
4e80519e 6133 valleyview_cleanup_gt_powersave(dev);
b268c699
ID		 6134
6135 if (!i915.enable_rc6)
6136 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6137}
6138
dbea3cea
ID		 6139static void gen6_suspend_rps(struct drm_device *dev)
6140{
6141 struct drm_i915_private *dev_priv = dev->dev_private;
6142
6143 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6144
4c2a8897 6145 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6146}
6147
156c7ca0
JB		 6148/**
6149 * intel_suspend_gt_powersave - suspend PM work and helper threads
6150 * @dev: drm device
6151 *
6152 * We don't want to disable RC6 or other features here, we just want
6153 * to make sure any work we've queued has finished and won't bother
6154 * us while we're suspended.
6155 */
6156void intel_suspend_gt_powersave(struct drm_device *dev)
6157{
6158 struct drm_i915_private *dev_priv = dev->dev_private;
6159
d4d70aa5
ID		 6160 if (INTEL_INFO(dev)->gen < 6)
6161 return;
6162
dbea3cea 6163 gen6_suspend_rps(dev);
b47adc17
D		 6164
6165 /* Force GPU to min freq during suspend */
6166 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6167}
6168
8090c6b9
DV		 6169void intel_disable_gt_powersave(struct drm_device *dev)
6170{
1a01ab3b
JB		 6171 struct drm_i915_private *dev_priv = dev->dev_private;
6172
930ebb46 6173 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6174 ironlake_disable_drps(dev);
38807746 6175 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6176 intel_suspend_gt_powersave(dev);
e494837a 6177
4fc688ce 6178 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6179 if (INTEL_INFO(dev)->gen >= 9)
6180 gen9_disable_rps(dev);
6181 else if (IS_CHERRYVIEW(dev))
38807746
D		 6182 cherryview_disable_rps(dev);
6183 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6184 valleyview_disable_rps(dev);
6185 else
6186 gen6_disable_rps(dev);
e534770a 6187
c0951f0c 6188 dev_priv->rps.enabled = false;
4fc688ce 6189 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6190 }
8090c6b9
DV		 6191}
6192
1a01ab3b
JB		 6193static void intel_gen6_powersave_work(struct work_struct *work)
6194{
6195 struct drm_i915_private *dev_priv =
6196 container_of(work, struct drm_i915_private,
6197 rps.delayed_resume_work.work);
6198 struct drm_device *dev = dev_priv->dev;
6199
4fc688ce 6200 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6201
4c2a8897 6202 gen6_reset_rps_interrupts(dev);
3cc134e3 6203
38807746
D		 6204 if (IS_CHERRYVIEW(dev)) {
6205 cherryview_enable_rps(dev);
6206 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6207 valleyview_enable_rps(dev);
20e49366 6208 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6209 gen9_enable_rc6(dev);
20e49366 6210 gen9_enable_rps(dev);
ef11bdb3 6211 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
cc017fb4 6212 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6213 } else if (IS_BROADWELL(dev)) {
6214 gen8_enable_rps(dev);
c2bc2fc5 6215 __gen6_update_ring_freq(dev);
0a073b84
JB		 6216 } else {
6217 gen6_enable_rps(dev);
c2bc2fc5 6218 __gen6_update_ring_freq(dev);
0a073b84 6219 }
aed242ff
CW		 6220
6221 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6222 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6223
6224 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6225 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6226
c0951f0c 6227 dev_priv->rps.enabled = true;
3cc134e3 6228
4c2a8897 6229 gen6_enable_rps_interrupts(dev);
3cc134e3 6230
4fc688ce 6231 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6232
6233 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6234}
6235
8090c6b9
DV		 6236void intel_enable_gt_powersave(struct drm_device *dev)
6237{
1a01ab3b
JB		 6238 struct drm_i915_private *dev_priv = dev->dev_private;
6239
f61018b1
YZ		 6240 /* Powersaving is controlled by the host when inside a VM */
6241 if (intel_vgpu_active(dev))
6242 return;
6243
8090c6b9
DV		 6244 if (IS_IRONLAKE_M(dev)) {
6245 ironlake_enable_drps(dev);
84f1b20f 6246 mutex_lock(&dev->struct_mutex);
8090c6b9 6247 intel_init_emon(dev);
dc1d0136 6248 mutex_unlock(&dev->struct_mutex);
38807746 6249 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6250 /*
6251 * PCU communication is slow and this doesn't need to be
6252 * done at any specific time, so do this out of our fast path
6253 * to make resume and init faster.
c6df39b5
ID		 6254 *
6255 * We depend on the HW RC6 power context save/restore
6256 * mechanism when entering D3 through runtime PM suspend. So
6257 * disable RPM until RPS/RC6 is properly setup. We can only
6258 * get here via the driver load/system resume/runtime resume
6259 * paths, so the _noresume version is enough (and in case of
6260 * runtime resume it's necessary).
1a01ab3b 6261 */
c6df39b5
ID		 6262 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6263 round_jiffies_up_relative(HZ)))
6264 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6265 }
6266}
6267
c6df39b5
ID		 6268void intel_reset_gt_powersave(struct drm_device *dev)
6269{
6270 struct drm_i915_private *dev_priv = dev->dev_private;
6271
dbea3cea
ID		 6272 if (INTEL_INFO(dev)->gen < 6)
6273 return;
6274
6275 gen6_suspend_rps(dev);
c6df39b5 6276 dev_priv->rps.enabled = false;
c6df39b5
ID		 6277}
6278
3107bd48
DV		 6279static void ibx_init_clock_gating(struct drm_device *dev)
6280{
6281 struct drm_i915_private *dev_priv = dev->dev_private;
6282
6283 /*
6284 * On Ibex Peak and Cougar Point, we need to disable clock
6285 * gating for the panel power sequencer or it will fail to
6286 * start up when no ports are active.
6287 */
6288 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6289}
6290
0e088b8f
VS		 6291static void g4x_disable_trickle_feed(struct drm_device *dev)
6292{
6293 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6294 enum pipe pipe;
0e088b8f 6295
055e393f 6296 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6297 I915_WRITE(DSPCNTR(pipe),
6298 I915_READ(DSPCNTR(pipe)) |
6299 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6300
6301 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6302 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6303 }
6304}
6305
017636cc
VS		 6306static void ilk_init_lp_watermarks(struct drm_device *dev)
6307{
6308 struct drm_i915_private *dev_priv = dev->dev_private;
6309
6310 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6311 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6312 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6313
6314 /*
6315 * Don't touch WM1S_LP_EN here.
6316 * Doing so could cause underruns.
6317 */
6318}
6319
1fa61106 6320static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6321{
6322 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6323 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6324
f1e8fa56
DL		 6325 /*
6326 * Required for FBC
6327 * WaFbcDisableDpfcClockGating:ilk
6328 */
4d47e4f5
DL		 6329 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6330 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6331 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6332
6333 I915_WRITE(PCH_3DCGDIS0,
6334 MARIUNIT_CLOCK_GATE_DISABLE |
6335 SVSMUNIT_CLOCK_GATE_DISABLE);
6336 I915_WRITE(PCH_3DCGDIS1,
6337 VFMUNIT_CLOCK_GATE_DISABLE);
6338
6f1d69b0
ED		 6339 /*
6340 * According to the spec the following bits should be set in
6341 * order to enable memory self-refresh
6342 * The bit 22/21 of 0x42004
6343 * The bit 5 of 0x42020
6344 * The bit 15 of 0x45000
6345 */
6346 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6347 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6348 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6349 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6350 I915_WRITE(DISP_ARB_CTL,
6351 (I915_READ(DISP_ARB_CTL) |
6352 DISP_FBC_WM_DIS));
017636cc
VS		 6353
6354 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6355
6356 /*
6357 * Based on the document from hardware guys the following bits
6358 * should be set unconditionally in order to enable FBC.
6359 * The bit 22 of 0x42000
6360 * The bit 22 of 0x42004
6361 * The bit 7,8,9 of 0x42020.
6362 */
6363 if (IS_IRONLAKE_M(dev)) {
4bb35334 6364 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6365 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6366 I915_READ(ILK_DISPLAY_CHICKEN1) |
6367 ILK_FBCQ_DIS);
6368 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6369 I915_READ(ILK_DISPLAY_CHICKEN2) |
6370 ILK_DPARB_GATE);
6f1d69b0
ED		 6371 }
6372
4d47e4f5
DL		 6373 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6374
6f1d69b0
ED		 6375 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6376 I915_READ(ILK_DISPLAY_CHICKEN2) |
6377 ILK_ELPIN_409_SELECT);
6378 I915_WRITE(_3D_CHICKEN2,
6379 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6380 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6381
ecdb4eb7 6382 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6383 I915_WRITE(CACHE_MODE_0,
6384 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6385
4e04632e
AG		 6386 /* WaDisable_RenderCache_OperationalFlush:ilk */
6387 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6388
0e088b8f 6389 g4x_disable_trickle_feed(dev);
bdad2b2f 6390
3107bd48
DV		 6391 ibx_init_clock_gating(dev);
6392}
6393
6394static void cpt_init_clock_gating(struct drm_device *dev)
6395{
6396 struct drm_i915_private *dev_priv = dev->dev_private;
6397 int pipe;
3f704fa2 6398 uint32_t val;
3107bd48
DV		 6399
6400 /*
6401 * On Ibex Peak and Cougar Point, we need to disable clock
6402 * gating for the panel power sequencer or it will fail to
6403 * start up when no ports are active.
6404 */
cd664078
JB		 6405 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6406 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6407 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6408 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6409 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6410 /* The below fixes the weird display corruption, a few pixels shifted
6411 * downward, on (only) LVDS of some HP laptops with IVY.
6412 */
055e393f 6413 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6414 val = I915_READ(TRANS_CHICKEN2(pipe));
6415 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6416 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6417 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6418 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6419 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6420 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6421 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6422 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6423 }
3107bd48 6424 /* WADP0ClockGatingDisable */
055e393f 6425 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6426 I915_WRITE(TRANS_CHICKEN1(pipe),
6427 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6428 }
6f1d69b0
ED		 6429}
6430
1d7aaa0c
DV		 6431static void gen6_check_mch_setup(struct drm_device *dev)
6432{
6433 struct drm_i915_private *dev_priv = dev->dev_private;
6434 uint32_t tmp;
6435
6436 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6437 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6438 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6439 tmp);
1d7aaa0c
DV		 6440}
6441
1fa61106 6442static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6443{
6444 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6445 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6446
231e54f6 6447 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6448
6449 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6450 I915_READ(ILK_DISPLAY_CHICKEN2) |
6451 ILK_ELPIN_409_SELECT);
6452
ecdb4eb7 6453 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6454 I915_WRITE(_3D_CHICKEN,
6455 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6456
4e04632e
AG		 6457 /* WaDisable_RenderCache_OperationalFlush:snb */
6458 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6459
8d85d272
VS		 6460 /*
6461 * BSpec recoomends 8x4 when MSAA is used,
6462 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6463 *
6464 * Note that PS/WM thread counts depend on the WIZ hashing
6465 * disable bit, which we don't touch here, but it's good
6466 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6467 */
6468 I915_WRITE(GEN6_GT_MODE,
98533251 6469 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6470
017636cc 6471 ilk_init_lp_watermarks(dev);
6f1d69b0 6472
6f1d69b0 6473 I915_WRITE(CACHE_MODE_0,
50743298 6474 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6475
6476 I915_WRITE(GEN6_UCGCTL1,
6477 I915_READ(GEN6_UCGCTL1) |
6478 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6479 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6480
6481 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6482 * gating disable must be set. Failure to set it results in
6483 * flickering pixels due to Z write ordering failures after
6484 * some amount of runtime in the Mesa "fire" demo, and Unigine
6485 * Sanctuary and Tropics, and apparently anything else with
6486 * alpha test or pixel discard.
6487 *
6488 * According to the spec, bit 11 (RCCUNIT) must also be set,
6489 * but we didn't debug actual testcases to find it out.
0f846f81 6490 *
ef59318c
VS		 6491 * WaDisableRCCUnitClockGating:snb
6492 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6493 */
6494 I915_WRITE(GEN6_UCGCTL2,
6495 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6496 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6497
5eb146dd 6498 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6499 I915_WRITE(_3D_CHICKEN3,
6500 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6501
e927ecde
VS		 6502 /*
6503 * Bspec says:
6504 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6505 * 3DSTATE_SF number of SF output attributes is more than 16."
6506 */
6507 I915_WRITE(_3D_CHICKEN3,
6508 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6509
6f1d69b0
ED		 6510 /*
6511 * According to the spec the following bits should be
6512 * set in order to enable memory self-refresh and fbc:
6513 * The bit21 and bit22 of 0x42000
6514 * The bit21 and bit22 of 0x42004
6515 * The bit5 and bit7 of 0x42020
6516 * The bit14 of 0x70180
6517 * The bit14 of 0x71180
4bb35334
DL		 6518 *
6519 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6520 */
6521 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6522 I915_READ(ILK_DISPLAY_CHICKEN1) |
6523 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6524 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6525 I915_READ(ILK_DISPLAY_CHICKEN2) |
6526 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6527 I915_WRITE(ILK_DSPCLK_GATE_D,
6528 I915_READ(ILK_DSPCLK_GATE_D) |
6529 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6530 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6531
0e088b8f 6532 g4x_disable_trickle_feed(dev);
f8f2ac9a 6533
3107bd48 6534 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6535
6536 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6537}
6538
6539static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6540{
6541 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6542
3aad9059 6543 /*
46680e0a 6544 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6545 *
6546 * This actually overrides the dispatch
6547 * mode for all thread types.
6548 */
6f1d69b0
ED		 6549 reg &= ~GEN7_FF_SCHED_MASK;
6550 reg |= GEN7_FF_TS_SCHED_HW;
6551 reg |= GEN7_FF_VS_SCHED_HW;
6552 reg |= GEN7_FF_DS_SCHED_HW;
6553
6554 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6555}
6556
17a303ec
PZ		 6557static void lpt_init_clock_gating(struct drm_device *dev)
6558{
6559 struct drm_i915_private *dev_priv = dev->dev_private;
6560
6561 /*
6562 * TODO: this bit should only be enabled when really needed, then
6563 * disabled when not needed anymore in order to save power.
6564 */
c2699524 6565 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6566 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6567 I915_READ(SOUTH_DSPCLK_GATE_D) |
6568 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6569
6570 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6571 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6572 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6573 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6574}
6575
7d708ee4
ID		 6576static void lpt_suspend_hw(struct drm_device *dev)
6577{
6578 struct drm_i915_private *dev_priv = dev->dev_private;
6579
c2699524 6580 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6581 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6582
6583 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6584 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6585 }
6586}
6587
47c2bd97 6588static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6589{
6590 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6591 enum pipe pipe;
4d487cff 6592 uint32_t misccpctl;
1020a5c2 6593
7ad0dbab 6594 ilk_init_lp_watermarks(dev);
50ed5fbd 6595
ab57fff1 6596 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6597 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6598
ab57fff1 6599 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6600 I915_WRITE(CHICKEN_PAR1_1,
6601 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6602
ab57fff1 6603 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6604 for_each_pipe(dev_priv, pipe) {
07d27e20 6605 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6606 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6607 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6608 }
63801f21 6609
ab57fff1
BW		 6610 /* WaVSRefCountFullforceMissDisable:bdw */
6611 /* WaDSRefCountFullforceMissDisable:bdw */
6612 I915_WRITE(GEN7_FF_THREAD_MODE,
6613 I915_READ(GEN7_FF_THREAD_MODE) &
6614 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6615
295e8bb7
VS		 6616 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6617 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6618
6619 /* WaDisableSDEUnitClockGating:bdw */
6620 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6621 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6622
4d487cff
VS		 6623 /*
6624 * WaProgramL3SqcReg1Default:bdw
6625 * WaTempDisableDOPClkGating:bdw
6626 */
6627 misccpctl = I915_READ(GEN7_MISCCPCTL);
6628 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6629 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6630 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6631
6d50b065
VS		 6632 /*
6633 * WaGttCachingOffByDefault:bdw
6634 * GTT cache may not work with big pages, so if those
6635 * are ever enabled GTT cache may need to be disabled.
6636 */
6637 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6638
89d6b2b8 6639 lpt_init_clock_gating(dev);
1020a5c2
BW		 6640}
6641
cad2a2d7
ED		 6642static void haswell_init_clock_gating(struct drm_device *dev)
6643{
6644 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6645
017636cc 6646 ilk_init_lp_watermarks(dev);
cad2a2d7 6647
f3fc4884
FJ		 6648 /* L3 caching of data atomics doesn't work -- disable it. */
6649 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6650 I915_WRITE(HSW_ROW_CHICKEN3,
6651 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6652
ecdb4eb7 6653 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6654 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6655 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6656 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6657
e36ea7ff
VS		 6658 /* WaVSRefCountFullforceMissDisable:hsw */
6659 I915_WRITE(GEN7_FF_THREAD_MODE,
6660 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6661
4e04632e
AG		 6662 /* WaDisable_RenderCache_OperationalFlush:hsw */
6663 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6664
fe27c606
CW		 6665 /* enable HiZ Raw Stall Optimization */
6666 I915_WRITE(CACHE_MODE_0_GEN7,
6667 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6668
ecdb4eb7 6669 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6670 I915_WRITE(CACHE_MODE_1,
6671 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6672
a12c4967
VS		 6673 /*
6674 * BSpec recommends 8x4 when MSAA is used,
6675 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6676 *
6677 * Note that PS/WM thread counts depend on the WIZ hashing
6678 * disable bit, which we don't touch here, but it's good
6679 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6680 */
6681 I915_WRITE(GEN7_GT_MODE,
98533251 6682 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6683
94411593
KG		 6684 /* WaSampleCChickenBitEnable:hsw */
6685 I915_WRITE(HALF_SLICE_CHICKEN3,
6686 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6687
ecdb4eb7 6688 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6689 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6690
90a88643
PZ		 6691 /* WaRsPkgCStateDisplayPMReq:hsw */
6692 I915_WRITE(CHICKEN_PAR1_1,
6693 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6694
17a303ec 6695 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6696}
6697
1fa61106 6698static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6699{
6700 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6701 uint32_t snpcr;
6f1d69b0 6702
017636cc 6703 ilk_init_lp_watermarks(dev);
6f1d69b0 6704
231e54f6 6705 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6706
ecdb4eb7 6707 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6708 I915_WRITE(_3D_CHICKEN3,
6709 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6710
ecdb4eb7 6711 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6712 I915_WRITE(IVB_CHICKEN3,
6713 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6714 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6715
ecdb4eb7 6716 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6717 if (IS_IVB_GT1(dev))
6718 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6719 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6720
4e04632e
AG		 6721 /* WaDisable_RenderCache_OperationalFlush:ivb */
6722 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6723
ecdb4eb7 6724 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6725 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6726 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6727
ecdb4eb7 6728 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6729 I915_WRITE(GEN7_L3CNTLREG1,
6730 GEN7_WA_FOR_GEN7_L3_CONTROL);
6731 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6732 GEN7_WA_L3_CHICKEN_MODE);
6733 if (IS_IVB_GT1(dev))
6734 I915_WRITE(GEN7_ROW_CHICKEN2,
6735 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6736 else {
6737 /* must write both registers */
6738 I915_WRITE(GEN7_ROW_CHICKEN2,
6739 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6740 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6741 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6742 }
6f1d69b0 6743
ecdb4eb7 6744 /* WaForceL3Serialization:ivb */
61939d97
JB		 6745 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6746 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6747
1b80a19a 6748 /*
0f846f81 6749 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6750 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6751 */
6752 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6753 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6754
ecdb4eb7 6755 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6756 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6757 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6758 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6759
0e088b8f 6760 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6761
6762 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6763
22721343
CW		 6764 if (0) { /* causes HiZ corruption on ivb:gt1 */
6765 /* enable HiZ Raw Stall Optimization */
6766 I915_WRITE(CACHE_MODE_0_GEN7,
6767 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6768 }
116f2b6d 6769
ecdb4eb7 6770 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6771 I915_WRITE(CACHE_MODE_1,
6772 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6773
a607c1a4
VS		 6774 /*
6775 * BSpec recommends 8x4 when MSAA is used,
6776 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6777 *
6778 * Note that PS/WM thread counts depend on the WIZ hashing
6779 * disable bit, which we don't touch here, but it's good
6780 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6781 */
6782 I915_WRITE(GEN7_GT_MODE,
98533251 6783 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6784
20848223
BW		 6785 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6786 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6787 snpcr |= GEN6_MBC_SNPCR_MED;
6788 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6789
ab5c608b
BW		 6790 if (!HAS_PCH_NOP(dev))
6791 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6792
6793 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6794}
6795
c6beb13e
VS		 6796static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6797{
6798 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6799
6800 /*
6801 * Disable trickle feed and enable pnd deadline calculation
6802 */
6803 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6804 I915_WRITE(CBR1_VLV, 0);
6805}
6806
1fa61106 6807static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6808{
6809 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6810
c6beb13e 6811 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6812
ecdb4eb7 6813 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6814 I915_WRITE(_3D_CHICKEN3,
6815 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6816
ecdb4eb7 6817 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6818 I915_WRITE(IVB_CHICKEN3,
6819 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6820 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6821
fad7d36e 6822 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6823 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6824 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6825 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6826 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6827
4e04632e
AG		 6828 /* WaDisable_RenderCache_OperationalFlush:vlv */
6829 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6830
ecdb4eb7 6831 /* WaForceL3Serialization:vlv */
61939d97
JB		 6832 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6833 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6834
ecdb4eb7 6835 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6836 I915_WRITE(GEN7_ROW_CHICKEN2,
6837 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6838
ecdb4eb7 6839 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6840 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6841 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6842 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6843
46680e0a
VS		 6844 gen7_setup_fixed_func_scheduler(dev_priv);
6845
3c0edaeb 6846 /*
0f846f81 6847 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6848 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6849 */
6850 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6851 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6852
c98f5062
AG		 6853 /* WaDisableL3Bank2xClockGate:vlv
6854 * Disabling L3 clock gating- MMIO 940c[25] = 1
6855 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6856 I915_WRITE(GEN7_UCGCTL4,
6857 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6858
afd58e79
VS		 6859 /*
6860 * BSpec says this must be set, even though
6861 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6862 */
6b26c86d
DV		 6863 I915_WRITE(CACHE_MODE_1,
6864 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6865
da2518f9
VS		 6866 /*
6867 * BSpec recommends 8x4 when MSAA is used,
6868 * however in practice 16x4 seems fastest.
6869 *
6870 * Note that PS/WM thread counts depend on the WIZ hashing
6871 * disable bit, which we don't touch here, but it's good
6872 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6873 */
6874 I915_WRITE(GEN7_GT_MODE,
6875 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6876
031994ee
VS		 6877 /*
6878 * WaIncreaseL3CreditsForVLVB0:vlv
6879 * This is the hardware default actually.
6880 */
6881 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6882
2d809570 6883 /*
ecdb4eb7 6884 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6885 * Disable clock gating on th GCFG unit to prevent a delay
6886 * in the reporting of vblank events.
6887 */
7a0d1eed 6888 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6889}
6890
a4565da8
VS		 6891static void cherryview_init_clock_gating(struct drm_device *dev)
6892{
6893 struct drm_i915_private *dev_priv = dev->dev_private;
6894
c6beb13e 6895 vlv_init_display_clock_gating(dev_priv);
dd811e70 6896
232ce337
VS		 6897 /* WaVSRefCountFullforceMissDisable:chv */
6898 /* WaDSRefCountFullforceMissDisable:chv */
6899 I915_WRITE(GEN7_FF_THREAD_MODE,
6900 I915_READ(GEN7_FF_THREAD_MODE) &
6901 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6902
6903 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6904 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6905 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6906
6907 /* WaDisableCSUnitClockGating:chv */
6908 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6909 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6910
6911 /* WaDisableSDEUnitClockGating:chv */
6912 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6913 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 6914
6915 /*
6916 * GTT cache may not work with big pages, so if those
6917 * are ever enabled GTT cache may need to be disabled.
6918 */
6919 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 6920}
6921
1fa61106 6922static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6923{
6924 struct drm_i915_private *dev_priv = dev->dev_private;
6925 uint32_t dspclk_gate;
6926
6927 I915_WRITE(RENCLK_GATE_D1, 0);
6928 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6929 GS_UNIT_CLOCK_GATE_DISABLE |
6930 CL_UNIT_CLOCK_GATE_DISABLE);
6931 I915_WRITE(RAMCLK_GATE_D, 0);
6932 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6933 OVRUNIT_CLOCK_GATE_DISABLE |
6934 OVCUNIT_CLOCK_GATE_DISABLE;
6935 if (IS_GM45(dev))
6936 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6937 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6938
6939 /* WaDisableRenderCachePipelinedFlush */
6940 I915_WRITE(CACHE_MODE_0,
6941 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6942
4e04632e
AG		 6943 /* WaDisable_RenderCache_OperationalFlush:g4x */
6944 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6945
0e088b8f 6946 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6947}
6948
1fa61106 6949static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6950{
6951 struct drm_i915_private *dev_priv = dev->dev_private;
6952
6953 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6954 I915_WRITE(RENCLK_GATE_D2, 0);
6955 I915_WRITE(DSPCLK_GATE_D, 0);
6956 I915_WRITE(RAMCLK_GATE_D, 0);
6957 I915_WRITE16(DEUC, 0);
20f94967
VS		 6958 I915_WRITE(MI_ARB_STATE,
6959 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6960
6961 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6962 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6963}
6964
1fa61106 6965static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6966{
6967 struct drm_i915_private *dev_priv = dev->dev_private;
6968
6969 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6970 I965_RCC_CLOCK_GATE_DISABLE |
6971 I965_RCPB_CLOCK_GATE_DISABLE |
6972 I965_ISC_CLOCK_GATE_DISABLE |
6973 I965_FBC_CLOCK_GATE_DISABLE);
6974 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6975 I915_WRITE(MI_ARB_STATE,
6976 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6977
6978 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6979 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6980}
6981
1fa61106 6982static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6983{
6984 struct drm_i915_private *dev_priv = dev->dev_private;
6985 u32 dstate = I915_READ(D_STATE);
6986
6987 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6988 DSTATE_DOT_CLOCK_GATING;
6989 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6990
6991 if (IS_PINEVIEW(dev))
6992 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6993
6994 /* IIR "flip pending" means done if this bit is set */
6995 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6996
6997 /* interrupts should cause a wake up from C3 */
3299254f 6998 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6999
7000 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7001 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7002
7003 I915_WRITE(MI_ARB_STATE,
7004 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7005}
7006
1fa61106 7007static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7008{
7009 struct drm_i915_private *dev_priv = dev->dev_private;
7010
7011 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7012
7013 /* interrupts should cause a wake up from C3 */
7014 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7015 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7016
7017 I915_WRITE(MEM_MODE,
7018 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7019}
7020
1fa61106 7021static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7022{
7023 struct drm_i915_private *dev_priv = dev->dev_private;
7024
7025 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7026
7027 I915_WRITE(MEM_MODE,
7028 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7029 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7030}
7031
6f1d69b0
ED		 7032void intel_init_clock_gating(struct drm_device *dev)
7033{
7034 struct drm_i915_private *dev_priv = dev->dev_private;
7035
c57e3551
DL		 7036 if (dev_priv->display.init_clock_gating)
7037 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7038}
7039
7d708ee4
ID		 7040void intel_suspend_hw(struct drm_device *dev)
7041{
7042 if (HAS_PCH_LPT(dev))
7043 lpt_suspend_hw(dev);
7044}
7045
1fa61106
ED		 7046/* Set up chip specific power management-related functions */
7047void intel_init_pm(struct drm_device *dev)
7048{
7049 struct drm_i915_private *dev_priv = dev->dev_private;
7050
7ff0ebcc 7051 intel_fbc_init(dev_priv);
1fa61106 7052
c921aba8
DV		 7053 /* For cxsr */
7054 if (IS_PINEVIEW(dev))
7055 i915_pineview_get_mem_freq(dev);
7056 else if (IS_GEN5(dev))
7057 i915_ironlake_get_mem_freq(dev);
7058
1fa61106 7059 /* For FIFO watermark updates */
f5ed50cb 7060 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 7061 skl_setup_wm_latency(dev);
7062
a82abe43
ID		 7063 if (IS_BROXTON(dev))
7064 dev_priv->display.init_clock_gating =
7065 bxt_init_clock_gating;
2d41c0b5 7066 dev_priv->display.update_wm = skl_update_wm;
c83155a6 7067 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7068 ilk_setup_wm_latency(dev);
53615a5e 7069
bd602544
VS		 7070 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7071 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7072 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7073 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
bf220452 7074 dev_priv->display.update_wm = ilk_update_wm;
86c8bbbe 7075 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
bf220452 7076 dev_priv->display.program_watermarks = ilk_program_watermarks;
bd602544
VS		 7077 } else {
7078 DRM_DEBUG_KMS("Failed to read display plane latency. "
7079 "Disable CxSR\n");
7080 }
7081
7082 if (IS_GEN5(dev))
1fa61106 7083 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7084 else if (IS_GEN6(dev))
1fa61106 7085 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7086 else if (IS_IVYBRIDGE(dev))
1fa61106 7087 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7088 else if (IS_HASWELL(dev))
cad2a2d7 7089 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7090 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 7091 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 7092 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 7093 vlv_setup_wm_latency(dev);
7094
7095 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 7096 dev_priv->display.init_clock_gating =
7097 cherryview_init_clock_gating;
1fa61106 7098 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 7099 vlv_setup_wm_latency(dev);
7100
7101 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7102 dev_priv->display.init_clock_gating =
7103 valleyview_init_clock_gating;
1fa61106
ED		 7104 } else if (IS_PINEVIEW(dev)) {
7105 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7106 dev_priv->is_ddr3,
7107 dev_priv->fsb_freq,
7108 dev_priv->mem_freq)) {
7109 DRM_INFO("failed to find known CxSR latency "
7110 "(found ddr%s fsb freq %d, mem freq %d), "
7111 "disabling CxSR\n",
7112 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7113 dev_priv->fsb_freq, dev_priv->mem_freq);
7114 /* Disable CxSR and never update its watermark again */
5209b1f4 7115 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7116 dev_priv->display.update_wm = NULL;
7117 } else
7118 dev_priv->display.update_wm = pineview_update_wm;
7119 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7120 } else if (IS_G4X(dev)) {
7121 dev_priv->display.update_wm = g4x_update_wm;
7122 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7123 } else if (IS_GEN4(dev)) {
7124 dev_priv->display.update_wm = i965_update_wm;
7125 if (IS_CRESTLINE(dev))
7126 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7127 else if (IS_BROADWATER(dev))
7128 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7129 } else if (IS_GEN3(dev)) {
7130 dev_priv->display.update_wm = i9xx_update_wm;
7131 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7132 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7133 } else if (IS_GEN2(dev)) {
7134 if (INTEL_INFO(dev)->num_pipes == 1) {
7135 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7136 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7137 } else {
7138 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7139 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7140 }
7141
7142 if (IS_I85X(dev) || IS_I865G(dev))
7143 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7144 else
7145 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7146 } else {
7147 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7148 }
7149}
7150
151a49d0 7151int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7152{
4fc688ce 7153 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7154
7155 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7156 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7157 return -EAGAIN;
7158 }
7159
7160 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7161 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7162 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7163
7164 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7165 500)) {
7166 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7167 return -ETIMEDOUT;
7168 }
7169
7170 *val = I915_READ(GEN6_PCODE_DATA);
7171 I915_WRITE(GEN6_PCODE_DATA, 0);
7172
7173 return 0;
7174}
7175
151a49d0 7176int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7177{
4fc688ce 7178 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7179
7180 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7181 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7182 return -EAGAIN;
7183 }
7184
7185 I915_WRITE(GEN6_PCODE_DATA, val);
7186 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7187
7188 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7189 500)) {
7190 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7191 return -ETIMEDOUT;
7192 }
7193
7194 I915_WRITE(GEN6_PCODE_DATA, 0);
7195
7196 return 0;
7197}
a0e4e199 7198
dd06f88c 7199static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7200{
dd06f88c
VS		 7201 switch (czclk_freq) {
7202 case 200:
7203 return 10;
7204 case 267:
7205 return 12;
7206 case 320:
7207 case 333:
dd06f88c 7208 return 16;
ab3fb157
VS		 7209 case 400:
7210 return 20;
855ba3be
JB		 7211 default:
7212 return -1;
7213 }
dd06f88c 7214}
855ba3be 7215
dd06f88c
VS		 7216static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7217{
bfa7df01 7218 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
dd06f88c
VS		 7219
7220 div = vlv_gpu_freq_div(czclk_freq);
7221 if (div < 0)
7222 return div;
7223
7224 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7225}
7226
b55dd647 7227static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7228{
bfa7df01 7229 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
855ba3be 7230
dd06f88c
VS		 7231 mul = vlv_gpu_freq_div(czclk_freq);
7232 if (mul < 0)
7233 return mul;
855ba3be 7234
dd06f88c 7235 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7236}
7237
b55dd647 7238static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7239{
bfa7df01 7240 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7241
9c06f674 7242 div = vlv_gpu_freq_div(czclk_freq);
dd06f88c
VS		 7243 if (div < 0)
7244 return div;
9c06f674 7245 div /= 2;
22b1b2f8 7246
dd06f88c 7247 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7248}
7249
b55dd647 7250static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7251{
bfa7df01 7252 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7253
9c06f674 7254 mul = vlv_gpu_freq_div(czclk_freq);
dd06f88c
VS		 7255 if (mul < 0)
7256 return mul;
9c06f674 7257 mul /= 2;
22b1b2f8 7258
1c14762d 7259 /* CHV needs even values */
dd06f88c 7260 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7261}
7262
616bc820 7263int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7264{
80b6dda4 7265 if (IS_GEN9(dev_priv->dev))
500a3d2e
MK		 7266 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7267 GEN9_FREQ_SCALER);
80b6dda4 7268 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7269 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7270 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7271 return byt_gpu_freq(dev_priv, val);
7272 else
7273 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7274}
7275
616bc820
VS		 7276int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7277{
80b6dda4 7278 if (IS_GEN9(dev_priv->dev))
500a3d2e
MK		 7279 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7280 GT_FREQUENCY_MULTIPLIER);
80b6dda4 7281 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7282 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7283 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7284 return byt_freq_opcode(dev_priv, val);
7285 else
500a3d2e 7286 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7287}
22b1b2f8 7288
6ad790c0
CW		 7289struct request_boost {
7290 struct work_struct work;
eed29a5b 7291 struct drm_i915_gem_request *req;
6ad790c0
CW		 7292};
7293
7294static void __intel_rps_boost_work(struct work_struct *work)
7295{
7296 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7297 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7298
e61b9958
CW		 7299 if (!i915_gem_request_completed(req, true))
7300 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7301 req->emitted_jiffies);
6ad790c0 7302
e61b9958 7303 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7304 kfree(boost);
7305}
7306
7307void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7308 struct drm_i915_gem_request *req)
6ad790c0
CW		 7309{
7310 struct request_boost *boost;
7311
eed29a5b 7312 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7313 return;
7314
e61b9958
CW		 7315 if (i915_gem_request_completed(req, true))
7316 return;
7317
6ad790c0
CW		 7318 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7319 if (boost == NULL)
7320 return;
7321
eed29a5b
DV		 7322 i915_gem_request_reference(req);
7323 boost->req = req;
6ad790c0
CW		 7324
7325 INIT_WORK(&boost->work, __intel_rps_boost_work);
7326 queue_work(to_i915(dev)->wq, &boost->work);
7327}
7328
f742a552 7329void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7330{
7331 struct drm_i915_private *dev_priv = dev->dev_private;
7332
f742a552 7333 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7334 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7335
907b28c5
CW		 7336 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7337 intel_gen6_powersave_work);
1854d5ca 7338 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7339 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7340 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7341
33688d95 7342 dev_priv->pm.suspended = false;
1f814dac 7343 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7344 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7345}
Linux kernel - Deliverables
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