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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
a0442461 CW |
37 | /* Rough estimate of the typical request size, performing a flush, |
38 | * set-context and then emitting the batch. | |
39 | */ | |
40 | #define LEGACY_REQUEST_SIZE 200 | |
41 | ||
82e104cc | 42 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 43 | { |
4f54741e DG |
44 | int space = head - tail; |
45 | if (space <= 0) | |
1cf0ba14 | 46 | space += size; |
4f54741e | 47 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
48 | } |
49 | ||
ebd0fd4b DG |
50 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf) |
51 | { | |
52 | if (ringbuf->last_retired_head != -1) { | |
53 | ringbuf->head = ringbuf->last_retired_head; | |
54 | ringbuf->last_retired_head = -1; | |
55 | } | |
56 | ||
57 | ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, | |
58 | ringbuf->tail, ringbuf->size); | |
59 | } | |
60 | ||
0bc40be8 | 61 | static void __intel_ring_advance(struct intel_engine_cs *engine) |
88b4aa87 | 62 | { |
0bc40be8 | 63 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 64 | ringbuf->tail &= ringbuf->size - 1; |
0bc40be8 | 65 | engine->write_tail(engine, ringbuf->tail); |
09246732 CW |
66 | } |
67 | ||
b72f3acb | 68 | static int |
a84c3ae1 | 69 | gen2_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
70 | u32 invalidate_domains, |
71 | u32 flush_domains) | |
72 | { | |
4a570db5 | 73 | struct intel_engine_cs *engine = req->engine; |
46f0f8d1 CW |
74 | u32 cmd; |
75 | int ret; | |
76 | ||
77 | cmd = MI_FLUSH; | |
31b14c9f | 78 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
79 | cmd |= MI_NO_WRITE_FLUSH; |
80 | ||
81 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
82 | cmd |= MI_READ_FLUSH; | |
83 | ||
5fb9de1a | 84 | ret = intel_ring_begin(req, 2); |
46f0f8d1 CW |
85 | if (ret) |
86 | return ret; | |
87 | ||
e2f80391 TU |
88 | intel_ring_emit(engine, cmd); |
89 | intel_ring_emit(engine, MI_NOOP); | |
90 | intel_ring_advance(engine); | |
46f0f8d1 CW |
91 | |
92 | return 0; | |
93 | } | |
94 | ||
95 | static int | |
a84c3ae1 | 96 | gen4_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
97 | u32 invalidate_domains, |
98 | u32 flush_domains) | |
62fdfeaf | 99 | { |
4a570db5 | 100 | struct intel_engine_cs *engine = req->engine; |
6f392d54 | 101 | u32 cmd; |
b72f3acb | 102 | int ret; |
6f392d54 | 103 | |
36d527de CW |
104 | /* |
105 | * read/write caches: | |
106 | * | |
107 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
108 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
109 | * also flushed at 2d versus 3d pipeline switches. | |
110 | * | |
111 | * read-only caches: | |
112 | * | |
113 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
114 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
115 | * | |
116 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
117 | * | |
118 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
119 | * invalidated when MI_EXE_FLUSH is set. | |
120 | * | |
121 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
122 | * invalidated with every MI_FLUSH. | |
123 | * | |
124 | * TLBs: | |
125 | * | |
126 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
127 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
128 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
129 | * are flushed at any MI_FLUSH. | |
130 | */ | |
131 | ||
132 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 133 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 134 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
135 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
136 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 137 | |
36d527de | 138 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
c033666a | 139 | (IS_G4X(req->i915) || IS_GEN5(req->i915))) |
36d527de | 140 | cmd |= MI_INVALIDATE_ISP; |
70eac33e | 141 | |
5fb9de1a | 142 | ret = intel_ring_begin(req, 2); |
36d527de CW |
143 | if (ret) |
144 | return ret; | |
b72f3acb | 145 | |
e2f80391 TU |
146 | intel_ring_emit(engine, cmd); |
147 | intel_ring_emit(engine, MI_NOOP); | |
148 | intel_ring_advance(engine); | |
b72f3acb CW |
149 | |
150 | return 0; | |
8187a2b7 ZN |
151 | } |
152 | ||
8d315287 JB |
153 | /** |
154 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
155 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
156 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
157 | * | |
158 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
159 | * produced by non-pipelined state commands), software needs to first | |
160 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
161 | * 0. | |
162 | * | |
163 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
164 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
165 | * | |
166 | * And the workaround for these two requires this workaround first: | |
167 | * | |
168 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
169 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
170 | * flushes. | |
171 | * | |
172 | * And this last workaround is tricky because of the requirements on | |
173 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
174 | * volume 2 part 1: | |
175 | * | |
176 | * "1 of the following must also be set: | |
177 | * - Render Target Cache Flush Enable ([12] of DW1) | |
178 | * - Depth Cache Flush Enable ([0] of DW1) | |
179 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
180 | * - Depth Stall ([13] of DW1) | |
181 | * - Post-Sync Operation ([13] of DW1) | |
182 | * - Notify Enable ([8] of DW1)" | |
183 | * | |
184 | * The cache flushes require the workaround flush that triggered this | |
185 | * one, so we can't use it. Depth stall would trigger the same. | |
186 | * Post-sync nonzero is what triggered this second workaround, so we | |
187 | * can't use that one either. Notify enable is IRQs, which aren't | |
188 | * really our business. That leaves only stall at scoreboard. | |
189 | */ | |
190 | static int | |
f2cf1fcc | 191 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 192 | { |
4a570db5 | 193 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 194 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
195 | int ret; |
196 | ||
5fb9de1a | 197 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
198 | if (ret) |
199 | return ret; | |
200 | ||
e2f80391 TU |
201 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
202 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | | |
8d315287 | 203 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
e2f80391 TU |
204 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
205 | intel_ring_emit(engine, 0); /* low dword */ | |
206 | intel_ring_emit(engine, 0); /* high dword */ | |
207 | intel_ring_emit(engine, MI_NOOP); | |
208 | intel_ring_advance(engine); | |
8d315287 | 209 | |
5fb9de1a | 210 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
211 | if (ret) |
212 | return ret; | |
213 | ||
e2f80391 TU |
214 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
215 | intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE); | |
216 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
217 | intel_ring_emit(engine, 0); | |
218 | intel_ring_emit(engine, 0); | |
219 | intel_ring_emit(engine, MI_NOOP); | |
220 | intel_ring_advance(engine); | |
8d315287 JB |
221 | |
222 | return 0; | |
223 | } | |
224 | ||
225 | static int | |
a84c3ae1 JH |
226 | gen6_render_ring_flush(struct drm_i915_gem_request *req, |
227 | u32 invalidate_domains, u32 flush_domains) | |
8d315287 | 228 | { |
4a570db5 | 229 | struct intel_engine_cs *engine = req->engine; |
8d315287 | 230 | u32 flags = 0; |
e2f80391 | 231 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
232 | int ret; |
233 | ||
b3111509 | 234 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 235 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
236 | if (ret) |
237 | return ret; | |
238 | ||
8d315287 JB |
239 | /* Just flush everything. Experiments have shown that reducing the |
240 | * number of bits based on the write domains has little performance | |
241 | * impact. | |
242 | */ | |
7d54a904 CW |
243 | if (flush_domains) { |
244 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
245 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
246 | /* | |
247 | * Ensure that any following seqno writes only happen | |
248 | * when the render cache is indeed flushed. | |
249 | */ | |
97f209bc | 250 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
251 | } |
252 | if (invalidate_domains) { | |
253 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
254 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
255 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
256 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
257 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
258 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
259 | /* | |
260 | * TLB invalidate requires a post-sync write. | |
261 | */ | |
3ac78313 | 262 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 263 | } |
8d315287 | 264 | |
5fb9de1a | 265 | ret = intel_ring_begin(req, 4); |
8d315287 JB |
266 | if (ret) |
267 | return ret; | |
268 | ||
e2f80391 TU |
269 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
270 | intel_ring_emit(engine, flags); | |
271 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
272 | intel_ring_emit(engine, 0); | |
273 | intel_ring_advance(engine); | |
8d315287 JB |
274 | |
275 | return 0; | |
276 | } | |
277 | ||
f3987631 | 278 | static int |
f2cf1fcc | 279 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 280 | { |
4a570db5 | 281 | struct intel_engine_cs *engine = req->engine; |
f3987631 PZ |
282 | int ret; |
283 | ||
5fb9de1a | 284 | ret = intel_ring_begin(req, 4); |
f3987631 PZ |
285 | if (ret) |
286 | return ret; | |
287 | ||
e2f80391 TU |
288 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
289 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | | |
f3987631 | 290 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
e2f80391 TU |
291 | intel_ring_emit(engine, 0); |
292 | intel_ring_emit(engine, 0); | |
293 | intel_ring_advance(engine); | |
f3987631 PZ |
294 | |
295 | return 0; | |
296 | } | |
297 | ||
4772eaeb | 298 | static int |
a84c3ae1 | 299 | gen7_render_ring_flush(struct drm_i915_gem_request *req, |
4772eaeb PZ |
300 | u32 invalidate_domains, u32 flush_domains) |
301 | { | |
4a570db5 | 302 | struct intel_engine_cs *engine = req->engine; |
4772eaeb | 303 | u32 flags = 0; |
e2f80391 | 304 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
305 | int ret; |
306 | ||
f3987631 PZ |
307 | /* |
308 | * Ensure that any following seqno writes only happen when the render | |
309 | * cache is indeed flushed. | |
310 | * | |
311 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
312 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
313 | * don't try to be clever and just set it unconditionally. | |
314 | */ | |
315 | flags |= PIPE_CONTROL_CS_STALL; | |
316 | ||
4772eaeb PZ |
317 | /* Just flush everything. Experiments have shown that reducing the |
318 | * number of bits based on the write domains has little performance | |
319 | * impact. | |
320 | */ | |
321 | if (flush_domains) { | |
322 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
323 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 324 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 325 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb PZ |
326 | } |
327 | if (invalidate_domains) { | |
328 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
329 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
330 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
331 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
332 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
333 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 334 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
335 | /* |
336 | * TLB invalidate requires a post-sync write. | |
337 | */ | |
338 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 339 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 340 | |
add284a3 CW |
341 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
342 | ||
f3987631 PZ |
343 | /* Workaround: we must issue a pipe_control with CS-stall bit |
344 | * set before a pipe_control command that has the state cache | |
345 | * invalidate bit set. */ | |
f2cf1fcc | 346 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
347 | } |
348 | ||
5fb9de1a | 349 | ret = intel_ring_begin(req, 4); |
4772eaeb PZ |
350 | if (ret) |
351 | return ret; | |
352 | ||
e2f80391 TU |
353 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
354 | intel_ring_emit(engine, flags); | |
355 | intel_ring_emit(engine, scratch_addr); | |
356 | intel_ring_emit(engine, 0); | |
357 | intel_ring_advance(engine); | |
4772eaeb PZ |
358 | |
359 | return 0; | |
360 | } | |
361 | ||
884ceace | 362 | static int |
f2cf1fcc | 363 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
884ceace KG |
364 | u32 flags, u32 scratch_addr) |
365 | { | |
4a570db5 | 366 | struct intel_engine_cs *engine = req->engine; |
884ceace KG |
367 | int ret; |
368 | ||
5fb9de1a | 369 | ret = intel_ring_begin(req, 6); |
884ceace KG |
370 | if (ret) |
371 | return ret; | |
372 | ||
e2f80391 TU |
373 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6)); |
374 | intel_ring_emit(engine, flags); | |
375 | intel_ring_emit(engine, scratch_addr); | |
376 | intel_ring_emit(engine, 0); | |
377 | intel_ring_emit(engine, 0); | |
378 | intel_ring_emit(engine, 0); | |
379 | intel_ring_advance(engine); | |
884ceace KG |
380 | |
381 | return 0; | |
382 | } | |
383 | ||
a5f3d68e | 384 | static int |
a84c3ae1 | 385 | gen8_render_ring_flush(struct drm_i915_gem_request *req, |
a5f3d68e BW |
386 | u32 invalidate_domains, u32 flush_domains) |
387 | { | |
388 | u32 flags = 0; | |
4a570db5 | 389 | u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 390 | int ret; |
a5f3d68e BW |
391 | |
392 | flags |= PIPE_CONTROL_CS_STALL; | |
393 | ||
394 | if (flush_domains) { | |
395 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
396 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 397 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 398 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e BW |
399 | } |
400 | if (invalidate_domains) { | |
401 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
402 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
403 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
404 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
405 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
406 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
407 | flags |= PIPE_CONTROL_QW_WRITE; | |
408 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
409 | |
410 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
f2cf1fcc | 411 | ret = gen8_emit_pipe_control(req, |
02c9f7e3 KG |
412 | PIPE_CONTROL_CS_STALL | |
413 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
414 | 0); | |
415 | if (ret) | |
416 | return ret; | |
a5f3d68e BW |
417 | } |
418 | ||
f2cf1fcc | 419 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
a5f3d68e BW |
420 | } |
421 | ||
0bc40be8 | 422 | static void ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 423 | u32 value) |
d46eefa2 | 424 | { |
c033666a | 425 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 426 | I915_WRITE_TAIL(engine, value); |
d46eefa2 XH |
427 | } |
428 | ||
0bc40be8 | 429 | u64 intel_ring_get_active_head(struct intel_engine_cs *engine) |
8187a2b7 | 430 | { |
c033666a | 431 | struct drm_i915_private *dev_priv = engine->i915; |
50877445 | 432 | u64 acthd; |
8187a2b7 | 433 | |
c033666a | 434 | if (INTEL_GEN(dev_priv) >= 8) |
0bc40be8 TU |
435 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), |
436 | RING_ACTHD_UDW(engine->mmio_base)); | |
c033666a | 437 | else if (INTEL_GEN(dev_priv) >= 4) |
0bc40be8 | 438 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); |
50877445 CW |
439 | else |
440 | acthd = I915_READ(ACTHD); | |
441 | ||
442 | return acthd; | |
8187a2b7 ZN |
443 | } |
444 | ||
0bc40be8 | 445 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 446 | { |
c033666a | 447 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
448 | u32 addr; |
449 | ||
450 | addr = dev_priv->status_page_dmah->busaddr; | |
c033666a | 451 | if (INTEL_GEN(dev_priv) >= 4) |
035dc1e0 DV |
452 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
453 | I915_WRITE(HWS_PGA, addr); | |
454 | } | |
455 | ||
0bc40be8 | 456 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 457 | { |
c033666a | 458 | struct drm_i915_private *dev_priv = engine->i915; |
f0f59a00 | 459 | i915_reg_t mmio; |
af75f269 DL |
460 | |
461 | /* The ring status page addresses are no longer next to the rest of | |
462 | * the ring registers as of gen7. | |
463 | */ | |
c033666a | 464 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 465 | switch (engine->id) { |
af75f269 DL |
466 | case RCS: |
467 | mmio = RENDER_HWS_PGA_GEN7; | |
468 | break; | |
469 | case BCS: | |
470 | mmio = BLT_HWS_PGA_GEN7; | |
471 | break; | |
472 | /* | |
473 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
474 | * gcc switch check warning | |
475 | */ | |
476 | case VCS2: | |
477 | case VCS: | |
478 | mmio = BSD_HWS_PGA_GEN7; | |
479 | break; | |
480 | case VECS: | |
481 | mmio = VEBOX_HWS_PGA_GEN7; | |
482 | break; | |
483 | } | |
c033666a | 484 | } else if (IS_GEN6(dev_priv)) { |
0bc40be8 | 485 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 DL |
486 | } else { |
487 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 488 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
489 | } |
490 | ||
0bc40be8 | 491 | I915_WRITE(mmio, (u32)engine->status_page.gfx_addr); |
af75f269 DL |
492 | POSTING_READ(mmio); |
493 | ||
494 | /* | |
495 | * Flush the TLB for this page | |
496 | * | |
497 | * FIXME: These two bits have disappeared on gen8, so a question | |
498 | * arises: do we still need this and if so how should we go about | |
499 | * invalidating the TLB? | |
500 | */ | |
ac657f64 | 501 | if (IS_GEN(dev_priv, 6, 7)) { |
0bc40be8 | 502 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
503 | |
504 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 505 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
506 | |
507 | I915_WRITE(reg, | |
508 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
509 | INSTPM_SYNC_FLUSH)); | |
25ab57f4 CW |
510 | if (intel_wait_for_register(dev_priv, |
511 | reg, INSTPM_SYNC_FLUSH, 0, | |
512 | 1000)) | |
af75f269 | 513 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
0bc40be8 | 514 | engine->name); |
af75f269 DL |
515 | } |
516 | } | |
517 | ||
0bc40be8 | 518 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 519 | { |
c033666a | 520 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 521 | |
c033666a | 522 | if (!IS_GEN2(dev_priv)) { |
0bc40be8 | 523 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
524 | if (intel_wait_for_register(dev_priv, |
525 | RING_MI_MODE(engine->mmio_base), | |
526 | MODE_IDLE, | |
527 | MODE_IDLE, | |
528 | 1000)) { | |
0bc40be8 TU |
529 | DRM_ERROR("%s : timed out trying to stop ring\n", |
530 | engine->name); | |
9bec9b13 CW |
531 | /* Sometimes we observe that the idle flag is not |
532 | * set even though the ring is empty. So double | |
533 | * check before giving up. | |
534 | */ | |
0bc40be8 | 535 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 536 | return false; |
9991ae78 CW |
537 | } |
538 | } | |
b7884eb4 | 539 | |
0bc40be8 TU |
540 | I915_WRITE_CTL(engine, 0); |
541 | I915_WRITE_HEAD(engine, 0); | |
542 | engine->write_tail(engine, 0); | |
8187a2b7 | 543 | |
c033666a | 544 | if (!IS_GEN2(dev_priv)) { |
0bc40be8 TU |
545 | (void)I915_READ_CTL(engine); |
546 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 547 | } |
a51435a3 | 548 | |
0bc40be8 | 549 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 550 | } |
8187a2b7 | 551 | |
fc0768ce TE |
552 | void intel_engine_init_hangcheck(struct intel_engine_cs *engine) |
553 | { | |
554 | memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); | |
555 | } | |
556 | ||
0bc40be8 | 557 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 558 | { |
c033666a | 559 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 560 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 561 | struct drm_i915_gem_object *obj = ringbuf->obj; |
9991ae78 CW |
562 | int ret = 0; |
563 | ||
59bad947 | 564 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 565 | |
0bc40be8 | 566 | if (!stop_ring(engine)) { |
9991ae78 | 567 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
568 | DRM_DEBUG_KMS("%s head not reset to zero " |
569 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
570 | engine->name, |
571 | I915_READ_CTL(engine), | |
572 | I915_READ_HEAD(engine), | |
573 | I915_READ_TAIL(engine), | |
574 | I915_READ_START(engine)); | |
8187a2b7 | 575 | |
0bc40be8 | 576 | if (!stop_ring(engine)) { |
6fd0d56e CW |
577 | DRM_ERROR("failed to set %s head to zero " |
578 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
579 | engine->name, |
580 | I915_READ_CTL(engine), | |
581 | I915_READ_HEAD(engine), | |
582 | I915_READ_TAIL(engine), | |
583 | I915_READ_START(engine)); | |
9991ae78 CW |
584 | ret = -EIO; |
585 | goto out; | |
6fd0d56e | 586 | } |
8187a2b7 ZN |
587 | } |
588 | ||
c033666a | 589 | if (I915_NEED_GFX_HWS(dev_priv)) |
0bc40be8 | 590 | intel_ring_setup_status_page(engine); |
9991ae78 | 591 | else |
0bc40be8 | 592 | ring_setup_phys_status_page(engine); |
9991ae78 | 593 | |
ece4a17d | 594 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 595 | I915_READ_HEAD(engine); |
ece4a17d | 596 | |
0d8957c8 DV |
597 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
598 | * registers with the above sequence (the readback of the HEAD registers | |
599 | * also enforces ordering), otherwise the hw might lose the new ring | |
600 | * register values. */ | |
0bc40be8 | 601 | I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
602 | |
603 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 604 | if (I915_READ_HEAD(engine)) |
95468892 | 605 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 TU |
606 | engine->name, I915_READ_HEAD(engine)); |
607 | I915_WRITE_HEAD(engine, 0); | |
608 | (void)I915_READ_HEAD(engine); | |
95468892 | 609 | |
0bc40be8 | 610 | I915_WRITE_CTL(engine, |
93b0a4e0 | 611 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 612 | | RING_VALID); |
8187a2b7 | 613 | |
8187a2b7 | 614 | /* If the head is still not zero, the ring is dead */ |
0bc40be8 TU |
615 | if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 && |
616 | I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) && | |
617 | (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 | 618 | DRM_ERROR("%s initialization failed " |
48e48a0b | 619 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
0bc40be8 TU |
620 | engine->name, |
621 | I915_READ_CTL(engine), | |
622 | I915_READ_CTL(engine) & RING_VALID, | |
623 | I915_READ_HEAD(engine), I915_READ_TAIL(engine), | |
624 | I915_READ_START(engine), | |
625 | (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
626 | ret = -EIO; |
627 | goto out; | |
8187a2b7 ZN |
628 | } |
629 | ||
ebd0fd4b | 630 | ringbuf->last_retired_head = -1; |
0bc40be8 TU |
631 | ringbuf->head = I915_READ_HEAD(engine); |
632 | ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR; | |
ebd0fd4b | 633 | intel_ring_update_space(ringbuf); |
1ec14ad3 | 634 | |
fc0768ce | 635 | intel_engine_init_hangcheck(engine); |
50f018df | 636 | |
b7884eb4 | 637 | out: |
59bad947 | 638 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
639 | |
640 | return ret; | |
8187a2b7 ZN |
641 | } |
642 | ||
f8291952 | 643 | void intel_fini_pipe_control(struct intel_engine_cs *engine) |
9b1136d5 | 644 | { |
0bc40be8 | 645 | if (engine->scratch.obj == NULL) |
9b1136d5 OM |
646 | return; |
647 | ||
f8291952 | 648 | i915_gem_object_ggtt_unpin(engine->scratch.obj); |
0bc40be8 TU |
649 | drm_gem_object_unreference(&engine->scratch.obj->base); |
650 | engine->scratch.obj = NULL; | |
9b1136d5 OM |
651 | } |
652 | ||
7d5ea807 | 653 | int intel_init_pipe_control(struct intel_engine_cs *engine, int size) |
c6df541c | 654 | { |
f8291952 | 655 | struct drm_i915_gem_object *obj; |
c6df541c CW |
656 | int ret; |
657 | ||
0bc40be8 | 658 | WARN_ON(engine->scratch.obj); |
c6df541c | 659 | |
91c8a326 | 660 | obj = i915_gem_object_create_stolen(&engine->i915->drm, size); |
de8fe166 | 661 | if (!obj) |
91c8a326 | 662 | obj = i915_gem_object_create(&engine->i915->drm, size); |
f8291952 CW |
663 | if (IS_ERR(obj)) { |
664 | DRM_ERROR("Failed to allocate scratch page\n"); | |
665 | ret = PTR_ERR(obj); | |
c6df541c CW |
666 | goto err; |
667 | } | |
e4ffd173 | 668 | |
f8291952 | 669 | ret = i915_gem_obj_ggtt_pin(obj, 4096, PIN_HIGH); |
a9cc726c DV |
670 | if (ret) |
671 | goto err_unref; | |
c6df541c | 672 | |
f8291952 CW |
673 | engine->scratch.obj = obj; |
674 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
2b1086cc | 675 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0bc40be8 | 676 | engine->name, engine->scratch.gtt_offset); |
c6df541c CW |
677 | return 0; |
678 | ||
c6df541c | 679 | err_unref: |
0bc40be8 | 680 | drm_gem_object_unreference(&engine->scratch.obj->base); |
c6df541c | 681 | err: |
c6df541c CW |
682 | return ret; |
683 | } | |
684 | ||
e2be4faf | 685 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
86d7f238 | 686 | { |
4a570db5 | 687 | struct intel_engine_cs *engine = req->engine; |
c033666a CW |
688 | struct i915_workarounds *w = &req->i915->workarounds; |
689 | int ret, i; | |
888b5995 | 690 | |
02235808 | 691 | if (w->count == 0) |
7225342a | 692 | return 0; |
888b5995 | 693 | |
e2f80391 | 694 | engine->gpu_caches_dirty = true; |
4866d729 | 695 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
696 | if (ret) |
697 | return ret; | |
888b5995 | 698 | |
5fb9de1a | 699 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
7225342a MK |
700 | if (ret) |
701 | return ret; | |
702 | ||
e2f80391 | 703 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 704 | for (i = 0; i < w->count; i++) { |
e2f80391 TU |
705 | intel_ring_emit_reg(engine, w->reg[i].addr); |
706 | intel_ring_emit(engine, w->reg[i].value); | |
7225342a | 707 | } |
e2f80391 | 708 | intel_ring_emit(engine, MI_NOOP); |
7225342a | 709 | |
e2f80391 | 710 | intel_ring_advance(engine); |
7225342a | 711 | |
e2f80391 | 712 | engine->gpu_caches_dirty = true; |
4866d729 | 713 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
714 | if (ret) |
715 | return ret; | |
888b5995 | 716 | |
7225342a | 717 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 718 | |
7225342a | 719 | return 0; |
86d7f238 AS |
720 | } |
721 | ||
8753181e | 722 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
723 | { |
724 | int ret; | |
725 | ||
e2be4faf | 726 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
727 | if (ret != 0) |
728 | return ret; | |
729 | ||
be01363f | 730 | ret = i915_gem_render_state_init(req); |
8f0e2b9d | 731 | if (ret) |
e26e1b97 | 732 | return ret; |
8f0e2b9d | 733 | |
e26e1b97 | 734 | return 0; |
8f0e2b9d DV |
735 | } |
736 | ||
7225342a | 737 | static int wa_add(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
738 | i915_reg_t addr, |
739 | const u32 mask, const u32 val) | |
7225342a MK |
740 | { |
741 | const u32 idx = dev_priv->workarounds.count; | |
742 | ||
743 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
744 | return -ENOSPC; | |
745 | ||
746 | dev_priv->workarounds.reg[idx].addr = addr; | |
747 | dev_priv->workarounds.reg[idx].value = val; | |
748 | dev_priv->workarounds.reg[idx].mask = mask; | |
749 | ||
750 | dev_priv->workarounds.count++; | |
751 | ||
752 | return 0; | |
86d7f238 AS |
753 | } |
754 | ||
ca5a0fbd | 755 | #define WA_REG(addr, mask, val) do { \ |
cf4b0de6 | 756 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
7225342a MK |
757 | if (r) \ |
758 | return r; \ | |
ca5a0fbd | 759 | } while (0) |
7225342a MK |
760 | |
761 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
26459343 | 762 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
7225342a MK |
763 | |
764 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
26459343 | 765 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
7225342a | 766 | |
98533251 | 767 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
cf4b0de6 | 768 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
7225342a | 769 | |
cf4b0de6 DL |
770 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
771 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
7225342a | 772 | |
cf4b0de6 | 773 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
7225342a | 774 | |
0bc40be8 TU |
775 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
776 | i915_reg_t reg) | |
33136b06 | 777 | { |
c033666a | 778 | struct drm_i915_private *dev_priv = engine->i915; |
33136b06 | 779 | struct i915_workarounds *wa = &dev_priv->workarounds; |
0bc40be8 | 780 | const uint32_t index = wa->hw_whitelist_count[engine->id]; |
33136b06 AS |
781 | |
782 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
783 | return -EINVAL; | |
784 | ||
0bc40be8 | 785 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
33136b06 | 786 | i915_mmio_reg_offset(reg)); |
0bc40be8 | 787 | wa->hw_whitelist_count[engine->id]++; |
33136b06 AS |
788 | |
789 | return 0; | |
790 | } | |
791 | ||
0bc40be8 | 792 | static int gen8_init_workarounds(struct intel_engine_cs *engine) |
e9a64ada | 793 | { |
c033666a | 794 | struct drm_i915_private *dev_priv = engine->i915; |
68c6198b AS |
795 | |
796 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
e9a64ada | 797 | |
717d84d6 AS |
798 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
799 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
800 | ||
d0581194 AS |
801 | /* WaDisablePartialInstShootdown:bdw,chv */ |
802 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
803 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
804 | ||
a340af58 AS |
805 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
806 | * workaround for for a possible hang in the unlikely event a TLB | |
807 | * invalidation occurs during a PSD flush. | |
808 | */ | |
809 | /* WaForceEnableNonCoherent:bdw,chv */ | |
120f5d28 | 810 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
a340af58 | 811 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
120f5d28 | 812 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
a340af58 AS |
813 | HDC_FORCE_NON_COHERENT); |
814 | ||
6def8fdd AS |
815 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
816 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
817 | * polygons in the same 8x4 pixel/sample area to be processed without | |
818 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
819 | * buffer." | |
820 | * | |
821 | * This optimization is off by default for BDW and CHV; turn it on. | |
822 | */ | |
823 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
824 | ||
48404636 AS |
825 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
826 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
827 | ||
7eebcde6 AS |
828 | /* |
829 | * BSpec recommends 8x4 when MSAA is used, | |
830 | * however in practice 16x4 seems fastest. | |
831 | * | |
832 | * Note that PS/WM thread counts depend on the WIZ hashing | |
833 | * disable bit, which we don't touch here, but it's good | |
834 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
835 | */ | |
836 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
837 | GEN6_WIZ_HASHING_MASK, | |
838 | GEN6_WIZ_HASHING_16x4); | |
839 | ||
e9a64ada AS |
840 | return 0; |
841 | } | |
842 | ||
0bc40be8 | 843 | static int bdw_init_workarounds(struct intel_engine_cs *engine) |
86d7f238 | 844 | { |
c033666a | 845 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 846 | int ret; |
86d7f238 | 847 | |
0bc40be8 | 848 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
849 | if (ret) |
850 | return ret; | |
851 | ||
101b376d | 852 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
d0581194 | 853 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
86d7f238 | 854 | |
101b376d | 855 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
856 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
857 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 858 | |
7225342a MK |
859 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
860 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 | 861 | |
7225342a | 862 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
35cb6f3b DL |
863 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
864 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
35cb6f3b | 865 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
c033666a | 866 | (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 | 867 | |
86d7f238 AS |
868 | return 0; |
869 | } | |
870 | ||
0bc40be8 | 871 | static int chv_init_workarounds(struct intel_engine_cs *engine) |
00e1e623 | 872 | { |
c033666a | 873 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 874 | int ret; |
00e1e623 | 875 | |
0bc40be8 | 876 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
877 | if (ret) |
878 | return ret; | |
879 | ||
00e1e623 | 880 | /* WaDisableThreadStallDopClockGating:chv */ |
d0581194 | 881 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
00e1e623 | 882 | |
d60de81d KG |
883 | /* Improve HiZ throughput on CHV. */ |
884 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
885 | ||
7225342a MK |
886 | return 0; |
887 | } | |
888 | ||
0bc40be8 | 889 | static int gen9_init_workarounds(struct intel_engine_cs *engine) |
3b106531 | 890 | { |
c033666a | 891 | struct drm_i915_private *dev_priv = engine->i915; |
e0f3fa09 | 892 | int ret; |
ab0dfafe | 893 | |
a8ab5ed5 TG |
894 | /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ |
895 | I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); | |
896 | ||
e5f81d65 | 897 | /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ |
9c4cbf82 MK |
898 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
899 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
900 | ||
e5f81d65 | 901 | /* WaDisableKillLogic:bxt,skl,kbl */ |
9c4cbf82 MK |
902 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
903 | ECOCHK_DIS_TLB); | |
904 | ||
e5f81d65 MK |
905 | /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ |
906 | /* WaDisablePartialInstShootdown:skl,bxt,kbl */ | |
ab0dfafe | 907 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
950b2aae | 908 | FLOW_CONTROL_ENABLE | |
ab0dfafe HN |
909 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
910 | ||
e5f81d65 | 911 | /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ |
8424171e NH |
912 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
913 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
914 | ||
e87a005d | 915 | /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ |
c033666a CW |
916 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
917 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
a86eb582 DL |
918 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
919 | GEN9_DG_MIRROR_FIX_ENABLE); | |
1de4582f | 920 | |
e87a005d | 921 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
c033666a CW |
922 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
923 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
183c6dac DL |
924 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
925 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
9b01435d AS |
926 | /* |
927 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
928 | * but we do that in per ctx batchbuffer as there is an issue | |
929 | * with this register not getting restored on ctx restore | |
930 | */ | |
183c6dac DL |
931 | } |
932 | ||
e5f81d65 MK |
933 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */ |
934 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */ | |
bfd8ad4e TG |
935 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
936 | GEN9_ENABLE_YV12_BUGFIX | | |
937 | GEN9_ENABLE_GPGPU_PREEMPTION); | |
cac23df4 | 938 | |
e5f81d65 MK |
939 | /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ |
940 | /* WaDisablePartialResolveInVc:skl,bxt,kbl */ | |
60294683 AS |
941 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
942 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
9370cd98 | 943 | |
e5f81d65 | 944 | /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ |
e2db7071 DL |
945 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
946 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
947 | ||
5a2ae95e | 948 | /* WaDisableMaskBasedCammingInRCC:skl,bxt */ |
c033666a CW |
949 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) || |
950 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
38a39a7b BW |
951 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
952 | PIXEL_MASK_CAMMING_DISABLE); | |
953 | ||
5b0e3659 MK |
954 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */ |
955 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
956 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
957 | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); | |
8ea6f892 | 958 | |
bbaefe72 MK |
959 | /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are |
960 | * both tied to WaForceContextSaveRestoreNonCoherent | |
961 | * in some hsds for skl. We keep the tie for all gen9. The | |
962 | * documentation is a bit hazy and so we want to get common behaviour, | |
963 | * even though there is no clear evidence we would need both on kbl/bxt. | |
964 | * This area has been source of system hangs so we play it safe | |
965 | * and mimic the skl regardless of what bspec says. | |
966 | * | |
967 | * Use Force Non-Coherent whenever executing a 3D context. This | |
968 | * is a workaround for a possible hang in the unlikely event | |
969 | * a TLB invalidation occurs during a PSD flush. | |
970 | */ | |
971 | ||
972 | /* WaForceEnableNonCoherent:skl,bxt,kbl */ | |
973 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
974 | HDC_FORCE_NON_COHERENT); | |
975 | ||
976 | /* WaDisableHDCInvalidation:skl,bxt,kbl */ | |
977 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
978 | BDW_DISABLE_HDC_INVALIDATION); | |
979 | ||
e5f81d65 MK |
980 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */ |
981 | if (IS_SKYLAKE(dev_priv) || | |
982 | IS_KABYLAKE(dev_priv) || | |
983 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
8c761609 AS |
984 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
985 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
8c761609 | 986 | |
e5f81d65 | 987 | /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ |
6b6d5626 RB |
988 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
989 | ||
e5f81d65 | 990 | /* WaOCLCoherentLineFlush:skl,bxt,kbl */ |
6ecf56ae AS |
991 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
992 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
993 | ||
6bb62855 | 994 | /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ |
995 | ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); | |
996 | if (ret) | |
997 | return ret; | |
998 | ||
e5f81d65 | 999 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */ |
0bc40be8 | 1000 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
e0f3fa09 AS |
1001 | if (ret) |
1002 | return ret; | |
1003 | ||
e5f81d65 | 1004 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ |
0bc40be8 | 1005 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
3669ab61 AS |
1006 | if (ret) |
1007 | return ret; | |
1008 | ||
3b106531 HN |
1009 | return 0; |
1010 | } | |
1011 | ||
0bc40be8 | 1012 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) |
b7668791 | 1013 | { |
c033666a | 1014 | struct drm_i915_private *dev_priv = engine->i915; |
b7668791 DL |
1015 | u8 vals[3] = { 0, 0, 0 }; |
1016 | unsigned int i; | |
1017 | ||
1018 | for (i = 0; i < 3; i++) { | |
1019 | u8 ss; | |
1020 | ||
1021 | /* | |
1022 | * Only consider slices where one, and only one, subslice has 7 | |
1023 | * EUs | |
1024 | */ | |
a4d8a0fe | 1025 | if (!is_power_of_2(dev_priv->info.subslice_7eu[i])) |
b7668791 DL |
1026 | continue; |
1027 | ||
1028 | /* | |
1029 | * subslice_7eu[i] != 0 (because of the check above) and | |
1030 | * ss_max == 4 (maximum number of subslices possible per slice) | |
1031 | * | |
1032 | * -> 0 <= ss <= 3; | |
1033 | */ | |
1034 | ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; | |
1035 | vals[i] = 3 - ss; | |
1036 | } | |
1037 | ||
1038 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
1039 | return 0; | |
1040 | ||
1041 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
1042 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
1043 | GEN9_IZ_HASHING_MASK(2) | | |
1044 | GEN9_IZ_HASHING_MASK(1) | | |
1045 | GEN9_IZ_HASHING_MASK(0), | |
1046 | GEN9_IZ_HASHING(2, vals[2]) | | |
1047 | GEN9_IZ_HASHING(1, vals[1]) | | |
1048 | GEN9_IZ_HASHING(0, vals[0])); | |
1049 | ||
1050 | return 0; | |
1051 | } | |
1052 | ||
0bc40be8 | 1053 | static int skl_init_workarounds(struct intel_engine_cs *engine) |
8d205494 | 1054 | { |
c033666a | 1055 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 1056 | int ret; |
d0bbbc4f | 1057 | |
0bc40be8 | 1058 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1059 | if (ret) |
1060 | return ret; | |
8d205494 | 1061 | |
a78536e7 AS |
1062 | /* |
1063 | * Actual WA is to disable percontext preemption granularity control | |
1064 | * until D0 which is the default case so this is equivalent to | |
1065 | * !WaDisablePerCtxtPreemptionGranularityControl:skl | |
1066 | */ | |
c033666a | 1067 | if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) { |
a78536e7 AS |
1068 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, |
1069 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
1070 | } | |
1071 | ||
71dce58c | 1072 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) { |
9c4cbf82 MK |
1073 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
1074 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | |
1075 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); | |
1076 | } | |
1077 | ||
1078 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes | |
1079 | * involving this register should also be added to WA batch as required. | |
1080 | */ | |
c033666a | 1081 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) |
9c4cbf82 MK |
1082 | /* WaDisableLSQCROPERFforOCL:skl */ |
1083 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1084 | GEN8_LQSC_RO_PERF_DIS); | |
1085 | ||
1086 | /* WaEnableGapsTsvCreditFix:skl */ | |
c033666a | 1087 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) { |
9c4cbf82 MK |
1088 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
1089 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1090 | } | |
1091 | ||
d0bbbc4f | 1092 | /* WaDisablePowerCompilerClockGating:skl */ |
c033666a | 1093 | if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0)) |
d0bbbc4f DL |
1094 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
1095 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); | |
1096 | ||
e87a005d | 1097 | /* WaBarrierPerformanceFixDisable:skl */ |
c033666a | 1098 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0)) |
5b6fd12a VS |
1099 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1100 | HDC_FENCE_DEST_SLM_DISABLE | | |
1101 | HDC_BARRIER_PERFORMANCE_DISABLE); | |
1102 | ||
9bd9dfb4 | 1103 | /* WaDisableSbeCacheDispatchPortSharing:skl */ |
c033666a | 1104 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0)) |
9bd9dfb4 MK |
1105 | WA_SET_BIT_MASKED( |
1106 | GEN7_HALF_SLICE_CHICKEN1, | |
1107 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
9bd9dfb4 | 1108 | |
eee8efb0 MK |
1109 | /* WaDisableGafsUnitClkGating:skl */ |
1110 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1111 | ||
6107497e | 1112 | /* WaDisableLSQCROPERFforOCL:skl */ |
0bc40be8 | 1113 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
6107497e AS |
1114 | if (ret) |
1115 | return ret; | |
1116 | ||
0bc40be8 | 1117 | return skl_tune_iz_hashing(engine); |
7225342a MK |
1118 | } |
1119 | ||
0bc40be8 | 1120 | static int bxt_init_workarounds(struct intel_engine_cs *engine) |
cae0437f | 1121 | { |
c033666a | 1122 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 1123 | int ret; |
dfb601e6 | 1124 | |
0bc40be8 | 1125 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1126 | if (ret) |
1127 | return ret; | |
cae0437f | 1128 | |
9c4cbf82 MK |
1129 | /* WaStoreMultiplePTEenable:bxt */ |
1130 | /* This is a requirement according to Hardware specification */ | |
c033666a | 1131 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
9c4cbf82 MK |
1132 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
1133 | ||
1134 | /* WaSetClckGatingDisableMedia:bxt */ | |
c033666a | 1135 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
9c4cbf82 MK |
1136 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
1137 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1138 | } | |
1139 | ||
dfb601e6 NH |
1140 | /* WaDisableThreadStallDopClockGating:bxt */ |
1141 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1142 | STALL_DOP_GATING_DISABLE); | |
1143 | ||
780f0aeb | 1144 | /* WaDisablePooledEuLoadBalancingFix:bxt */ |
1145 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) { | |
1146 | WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2, | |
1147 | GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); | |
1148 | } | |
1149 | ||
983b4b9d | 1150 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
c033666a | 1151 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) { |
983b4b9d NH |
1152 | WA_SET_BIT_MASKED( |
1153 | GEN7_HALF_SLICE_CHICKEN1, | |
1154 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1155 | } | |
1156 | ||
2c8580e4 AS |
1157 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
1158 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
1159 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
a786d53a | 1160 | /* WaDisableLSQCROPERFforOCL:bxt */ |
c033666a | 1161 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
0bc40be8 | 1162 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); |
2c8580e4 AS |
1163 | if (ret) |
1164 | return ret; | |
a786d53a | 1165 | |
0bc40be8 | 1166 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
a786d53a AS |
1167 | if (ret) |
1168 | return ret; | |
2c8580e4 AS |
1169 | } |
1170 | ||
050fc465 | 1171 | /* WaProgramL3SqcReg1DefaultForPerf:bxt */ |
c033666a | 1172 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) |
36579cb6 ID |
1173 | I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) | |
1174 | L3_HIGH_PRIO_CREDITS(2)); | |
050fc465 | 1175 | |
ad2bdb44 MK |
1176 | /* WaInsertDummyPushConstPs:bxt */ |
1177 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
1178 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1179 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1180 | ||
cae0437f NH |
1181 | return 0; |
1182 | } | |
1183 | ||
e5f81d65 MK |
1184 | static int kbl_init_workarounds(struct intel_engine_cs *engine) |
1185 | { | |
e587f6cb | 1186 | struct drm_i915_private *dev_priv = engine->i915; |
e5f81d65 MK |
1187 | int ret; |
1188 | ||
1189 | ret = gen9_init_workarounds(engine); | |
1190 | if (ret) | |
1191 | return ret; | |
1192 | ||
e587f6cb MK |
1193 | /* WaEnableGapsTsvCreditFix:kbl */ |
1194 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1195 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1196 | ||
c0b730d5 MK |
1197 | /* WaDisableDynamicCreditSharing:kbl */ |
1198 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1199 | WA_SET_BIT(GAMT_CHKN_BIT_REG, | |
1200 | GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); | |
1201 | ||
8401d42f MK |
1202 | /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ |
1203 | if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) | |
1204 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1205 | HDC_FENCE_DEST_SLM_DISABLE); | |
1206 | ||
fe905819 MK |
1207 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes |
1208 | * involving this register should also be added to WA batch as required. | |
1209 | */ | |
1210 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) | |
1211 | /* WaDisableLSQCROPERFforOCL:kbl */ | |
1212 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1213 | GEN8_LQSC_RO_PERF_DIS); | |
1214 | ||
ad2bdb44 MK |
1215 | /* WaInsertDummyPushConstPs:kbl */ |
1216 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1217 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1218 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1219 | ||
4de5d7cc MK |
1220 | /* WaDisableGafsUnitClkGating:kbl */ |
1221 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1222 | ||
954337aa MK |
1223 | /* WaDisableSbeCacheDispatchPortSharing:kbl */ |
1224 | WA_SET_BIT_MASKED( | |
1225 | GEN7_HALF_SLICE_CHICKEN1, | |
1226 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1227 | ||
fe905819 MK |
1228 | /* WaDisableLSQCROPERFforOCL:kbl */ |
1229 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1230 | if (ret) | |
1231 | return ret; | |
1232 | ||
e5f81d65 MK |
1233 | return 0; |
1234 | } | |
1235 | ||
0bc40be8 | 1236 | int init_workarounds_ring(struct intel_engine_cs *engine) |
7225342a | 1237 | { |
c033666a | 1238 | struct drm_i915_private *dev_priv = engine->i915; |
7225342a | 1239 | |
0bc40be8 | 1240 | WARN_ON(engine->id != RCS); |
7225342a MK |
1241 | |
1242 | dev_priv->workarounds.count = 0; | |
33136b06 | 1243 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
7225342a | 1244 | |
c033666a | 1245 | if (IS_BROADWELL(dev_priv)) |
0bc40be8 | 1246 | return bdw_init_workarounds(engine); |
7225342a | 1247 | |
c033666a | 1248 | if (IS_CHERRYVIEW(dev_priv)) |
0bc40be8 | 1249 | return chv_init_workarounds(engine); |
00e1e623 | 1250 | |
c033666a | 1251 | if (IS_SKYLAKE(dev_priv)) |
0bc40be8 | 1252 | return skl_init_workarounds(engine); |
cae0437f | 1253 | |
c033666a | 1254 | if (IS_BROXTON(dev_priv)) |
0bc40be8 | 1255 | return bxt_init_workarounds(engine); |
3b106531 | 1256 | |
e5f81d65 MK |
1257 | if (IS_KABYLAKE(dev_priv)) |
1258 | return kbl_init_workarounds(engine); | |
1259 | ||
00e1e623 VS |
1260 | return 0; |
1261 | } | |
1262 | ||
0bc40be8 | 1263 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 1264 | { |
c033666a | 1265 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 1266 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
1267 | if (ret) |
1268 | return ret; | |
a69ffdbf | 1269 | |
61a563a2 | 1270 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
ac657f64 | 1271 | if (IS_GEN(dev_priv, 4, 6)) |
6b26c86d | 1272 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
1273 | |
1274 | /* We need to disable the AsyncFlip performance optimisations in order | |
1275 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1276 | * programmed to '1' on all products. | |
8693a824 | 1277 | * |
2441f877 | 1278 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 1279 | */ |
ac657f64 | 1280 | if (IS_GEN(dev_priv, 6, 7)) |
1c8c38c5 CW |
1281 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
1282 | ||
f05bb0c7 | 1283 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 1284 | /* WaEnableFlushTlbInvalidationMode:snb */ |
c033666a | 1285 | if (IS_GEN6(dev_priv)) |
f05bb0c7 | 1286 | I915_WRITE(GFX_MODE, |
aa83e30d | 1287 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 1288 | |
01fa0302 | 1289 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
c033666a | 1290 | if (IS_GEN7(dev_priv)) |
1c8c38c5 | 1291 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 1292 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 1293 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 1294 | |
c033666a | 1295 | if (IS_GEN6(dev_priv)) { |
3a69ddd6 KG |
1296 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
1297 | * "If this bit is set, STCunit will have LRA as replacement | |
1298 | * policy. [...] This bit must be reset. LRA replacement | |
1299 | * policy is not supported." | |
1300 | */ | |
1301 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 1302 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
1303 | } |
1304 | ||
ac657f64 | 1305 | if (IS_GEN(dev_priv, 6, 7)) |
6b26c86d | 1306 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 1307 | |
b224c4dc VS |
1308 | if (INTEL_INFO(dev_priv)->gen >= 6) |
1309 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); | |
15b9f80e | 1310 | |
0bc40be8 | 1311 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
1312 | } |
1313 | ||
0bc40be8 | 1314 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 1315 | { |
c033666a | 1316 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a BW |
1317 | |
1318 | if (dev_priv->semaphore_obj) { | |
1319 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
1320 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
1321 | dev_priv->semaphore_obj = NULL; | |
1322 | } | |
b45305fc | 1323 | |
0bc40be8 | 1324 | intel_fini_pipe_control(engine); |
c6df541c CW |
1325 | } |
1326 | ||
f7169687 | 1327 | static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1328 | unsigned int num_dwords) |
1329 | { | |
1330 | #define MBOX_UPDATE_DWORDS 8 | |
4a570db5 | 1331 | struct intel_engine_cs *signaller = signaller_req->engine; |
c033666a | 1332 | struct drm_i915_private *dev_priv = signaller_req->i915; |
3e78998a | 1333 | struct intel_engine_cs *waiter; |
c3232b18 DG |
1334 | enum intel_engine_id id; |
1335 | int ret, num_rings; | |
3e78998a | 1336 | |
c033666a | 1337 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
3e78998a BW |
1338 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
1339 | #undef MBOX_UPDATE_DWORDS | |
1340 | ||
5fb9de1a | 1341 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1342 | if (ret) |
1343 | return ret; | |
1344 | ||
c3232b18 | 1345 | for_each_engine_id(waiter, dev_priv, id) { |
c3232b18 | 1346 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
3e78998a BW |
1347 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1348 | continue; | |
1349 | ||
1350 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); | |
1351 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1352 | PIPE_CONTROL_QW_WRITE | | |
f9a4ea35 | 1353 | PIPE_CONTROL_CS_STALL); |
3e78998a BW |
1354 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); |
1355 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
1b7744e7 | 1356 | intel_ring_emit(signaller, signaller_req->seqno); |
3e78998a BW |
1357 | intel_ring_emit(signaller, 0); |
1358 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
215a7e32 | 1359 | MI_SEMAPHORE_TARGET(waiter->hw_id)); |
3e78998a BW |
1360 | intel_ring_emit(signaller, 0); |
1361 | } | |
1362 | ||
1363 | return 0; | |
1364 | } | |
1365 | ||
f7169687 | 1366 | static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1367 | unsigned int num_dwords) |
1368 | { | |
1369 | #define MBOX_UPDATE_DWORDS 6 | |
4a570db5 | 1370 | struct intel_engine_cs *signaller = signaller_req->engine; |
c033666a | 1371 | struct drm_i915_private *dev_priv = signaller_req->i915; |
3e78998a | 1372 | struct intel_engine_cs *waiter; |
c3232b18 DG |
1373 | enum intel_engine_id id; |
1374 | int ret, num_rings; | |
3e78998a | 1375 | |
c033666a | 1376 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
3e78998a BW |
1377 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
1378 | #undef MBOX_UPDATE_DWORDS | |
1379 | ||
5fb9de1a | 1380 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1381 | if (ret) |
1382 | return ret; | |
1383 | ||
c3232b18 | 1384 | for_each_engine_id(waiter, dev_priv, id) { |
c3232b18 | 1385 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
3e78998a BW |
1386 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1387 | continue; | |
1388 | ||
1389 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | | |
1390 | MI_FLUSH_DW_OP_STOREDW); | |
1391 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
1392 | MI_FLUSH_DW_USE_GTT); | |
1393 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
1b7744e7 | 1394 | intel_ring_emit(signaller, signaller_req->seqno); |
3e78998a | 1395 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
215a7e32 | 1396 | MI_SEMAPHORE_TARGET(waiter->hw_id)); |
3e78998a BW |
1397 | intel_ring_emit(signaller, 0); |
1398 | } | |
1399 | ||
1400 | return 0; | |
1401 | } | |
1402 | ||
f7169687 | 1403 | static int gen6_signal(struct drm_i915_gem_request *signaller_req, |
024a43e1 | 1404 | unsigned int num_dwords) |
1ec14ad3 | 1405 | { |
4a570db5 | 1406 | struct intel_engine_cs *signaller = signaller_req->engine; |
c033666a | 1407 | struct drm_i915_private *dev_priv = signaller_req->i915; |
a4872ba6 | 1408 | struct intel_engine_cs *useless; |
c3232b18 DG |
1409 | enum intel_engine_id id; |
1410 | int ret, num_rings; | |
78325f2d | 1411 | |
a1444b79 | 1412 | #define MBOX_UPDATE_DWORDS 3 |
c033666a | 1413 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
a1444b79 BW |
1414 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); |
1415 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 | 1416 | |
5fb9de1a | 1417 | ret = intel_ring_begin(signaller_req, num_dwords); |
024a43e1 BW |
1418 | if (ret) |
1419 | return ret; | |
024a43e1 | 1420 | |
c3232b18 DG |
1421 | for_each_engine_id(useless, dev_priv, id) { |
1422 | i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id]; | |
f0f59a00 VS |
1423 | |
1424 | if (i915_mmio_reg_valid(mbox_reg)) { | |
78325f2d | 1425 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
f92a9162 | 1426 | intel_ring_emit_reg(signaller, mbox_reg); |
1b7744e7 | 1427 | intel_ring_emit(signaller, signaller_req->seqno); |
78325f2d BW |
1428 | } |
1429 | } | |
024a43e1 | 1430 | |
a1444b79 BW |
1431 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1432 | if (num_rings % 2 == 0) | |
1433 | intel_ring_emit(signaller, MI_NOOP); | |
1434 | ||
024a43e1 | 1435 | return 0; |
1ec14ad3 CW |
1436 | } |
1437 | ||
c8c99b0f BW |
1438 | /** |
1439 | * gen6_add_request - Update the semaphore mailbox registers | |
ee044a88 JH |
1440 | * |
1441 | * @request - request to write to the ring | |
c8c99b0f BW |
1442 | * |
1443 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1444 | * This acts like a signal in the canonical semaphore. | |
1445 | */ | |
1ec14ad3 | 1446 | static int |
ee044a88 | 1447 | gen6_add_request(struct drm_i915_gem_request *req) |
1ec14ad3 | 1448 | { |
4a570db5 | 1449 | struct intel_engine_cs *engine = req->engine; |
024a43e1 | 1450 | int ret; |
52ed2325 | 1451 | |
e2f80391 TU |
1452 | if (engine->semaphore.signal) |
1453 | ret = engine->semaphore.signal(req, 4); | |
707d9cf9 | 1454 | else |
5fb9de1a | 1455 | ret = intel_ring_begin(req, 4); |
707d9cf9 | 1456 | |
1ec14ad3 CW |
1457 | if (ret) |
1458 | return ret; | |
1459 | ||
e2f80391 TU |
1460 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
1461 | intel_ring_emit(engine, | |
1462 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1b7744e7 | 1463 | intel_ring_emit(engine, req->seqno); |
e2f80391 TU |
1464 | intel_ring_emit(engine, MI_USER_INTERRUPT); |
1465 | __intel_ring_advance(engine); | |
1ec14ad3 | 1466 | |
1ec14ad3 CW |
1467 | return 0; |
1468 | } | |
1469 | ||
a58c01aa CW |
1470 | static int |
1471 | gen8_render_add_request(struct drm_i915_gem_request *req) | |
1472 | { | |
1473 | struct intel_engine_cs *engine = req->engine; | |
1474 | int ret; | |
1475 | ||
1476 | if (engine->semaphore.signal) | |
1477 | ret = engine->semaphore.signal(req, 8); | |
1478 | else | |
1479 | ret = intel_ring_begin(req, 8); | |
1480 | if (ret) | |
1481 | return ret; | |
1482 | ||
1483 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6)); | |
1484 | intel_ring_emit(engine, (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1485 | PIPE_CONTROL_CS_STALL | | |
1486 | PIPE_CONTROL_QW_WRITE)); | |
1487 | intel_ring_emit(engine, intel_hws_seqno_address(req->engine)); | |
1488 | intel_ring_emit(engine, 0); | |
1489 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1490 | /* We're thrashing one dword of HWS. */ | |
1491 | intel_ring_emit(engine, 0); | |
1492 | intel_ring_emit(engine, MI_USER_INTERRUPT); | |
1493 | intel_ring_emit(engine, MI_NOOP); | |
1494 | __intel_ring_advance(engine); | |
1495 | ||
1496 | return 0; | |
1497 | } | |
1498 | ||
c033666a | 1499 | static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv, |
f72b3435 MK |
1500 | u32 seqno) |
1501 | { | |
f72b3435 MK |
1502 | return dev_priv->last_seqno < seqno; |
1503 | } | |
1504 | ||
c8c99b0f BW |
1505 | /** |
1506 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1507 | * | |
1508 | * @waiter - ring that is waiting | |
1509 | * @signaller - ring which has, or will signal | |
1510 | * @seqno - seqno which the waiter will block on | |
1511 | */ | |
5ee426ca BW |
1512 | |
1513 | static int | |
599d924c | 1514 | gen8_ring_sync(struct drm_i915_gem_request *waiter_req, |
5ee426ca BW |
1515 | struct intel_engine_cs *signaller, |
1516 | u32 seqno) | |
1517 | { | |
4a570db5 | 1518 | struct intel_engine_cs *waiter = waiter_req->engine; |
c033666a | 1519 | struct drm_i915_private *dev_priv = waiter_req->i915; |
c38c651b | 1520 | u64 offset = GEN8_WAIT_OFFSET(waiter, signaller->id); |
6ef48d7f | 1521 | struct i915_hw_ppgtt *ppgtt; |
5ee426ca BW |
1522 | int ret; |
1523 | ||
5fb9de1a | 1524 | ret = intel_ring_begin(waiter_req, 4); |
5ee426ca BW |
1525 | if (ret) |
1526 | return ret; | |
1527 | ||
1528 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
1529 | MI_SEMAPHORE_GLOBAL_GTT | | |
1530 | MI_SEMAPHORE_SAD_GTE_SDD); | |
1531 | intel_ring_emit(waiter, seqno); | |
c38c651b TU |
1532 | intel_ring_emit(waiter, lower_32_bits(offset)); |
1533 | intel_ring_emit(waiter, upper_32_bits(offset)); | |
5ee426ca | 1534 | intel_ring_advance(waiter); |
6ef48d7f CW |
1535 | |
1536 | /* When the !RCS engines idle waiting upon a semaphore, they lose their | |
1537 | * pagetables and we must reload them before executing the batch. | |
1538 | * We do this on the i915_switch_context() following the wait and | |
1539 | * before the dispatch. | |
1540 | */ | |
1541 | ppgtt = waiter_req->ctx->ppgtt; | |
1542 | if (ppgtt && waiter_req->engine->id != RCS) | |
1543 | ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine); | |
5ee426ca BW |
1544 | return 0; |
1545 | } | |
1546 | ||
c8c99b0f | 1547 | static int |
599d924c | 1548 | gen6_ring_sync(struct drm_i915_gem_request *waiter_req, |
a4872ba6 | 1549 | struct intel_engine_cs *signaller, |
686cb5f9 | 1550 | u32 seqno) |
1ec14ad3 | 1551 | { |
4a570db5 | 1552 | struct intel_engine_cs *waiter = waiter_req->engine; |
c8c99b0f BW |
1553 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1554 | MI_SEMAPHORE_COMPARE | | |
1555 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
1556 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
1557 | int ret; | |
1ec14ad3 | 1558 | |
1500f7ea BW |
1559 | /* Throughout all of the GEM code, seqno passed implies our current |
1560 | * seqno is >= the last seqno executed. However for hardware the | |
1561 | * comparison is strictly greater than. | |
1562 | */ | |
1563 | seqno -= 1; | |
1564 | ||
ebc348b2 | 1565 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1566 | |
5fb9de1a | 1567 | ret = intel_ring_begin(waiter_req, 4); |
1ec14ad3 CW |
1568 | if (ret) |
1569 | return ret; | |
1570 | ||
f72b3435 | 1571 | /* If seqno wrap happened, omit the wait with no-ops */ |
c033666a | 1572 | if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) { |
ebc348b2 | 1573 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
1574 | intel_ring_emit(waiter, seqno); |
1575 | intel_ring_emit(waiter, 0); | |
1576 | intel_ring_emit(waiter, MI_NOOP); | |
1577 | } else { | |
1578 | intel_ring_emit(waiter, MI_NOOP); | |
1579 | intel_ring_emit(waiter, MI_NOOP); | |
1580 | intel_ring_emit(waiter, MI_NOOP); | |
1581 | intel_ring_emit(waiter, MI_NOOP); | |
1582 | } | |
c8c99b0f | 1583 | intel_ring_advance(waiter); |
1ec14ad3 CW |
1584 | |
1585 | return 0; | |
1586 | } | |
1587 | ||
f8973c21 CW |
1588 | static void |
1589 | gen5_seqno_barrier(struct intel_engine_cs *ring) | |
c6df541c | 1590 | { |
f8973c21 CW |
1591 | /* MI_STORE are internally buffered by the GPU and not flushed |
1592 | * either by MI_FLUSH or SyncFlush or any other combination of | |
1593 | * MI commands. | |
c6df541c | 1594 | * |
f8973c21 CW |
1595 | * "Only the submission of the store operation is guaranteed. |
1596 | * The write result will be complete (coherent) some time later | |
1597 | * (this is practically a finite period but there is no guaranteed | |
1598 | * latency)." | |
1599 | * | |
1600 | * Empirically, we observe that we need a delay of at least 75us to | |
1601 | * be sure that the seqno write is visible by the CPU. | |
c6df541c | 1602 | */ |
f8973c21 | 1603 | usleep_range(125, 250); |
c6df541c CW |
1604 | } |
1605 | ||
c04e0f3b CW |
1606 | static void |
1607 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 1608 | { |
c033666a | 1609 | struct drm_i915_private *dev_priv = engine->i915; |
bcbdb6d0 | 1610 | |
4cd53c0c DV |
1611 | /* Workaround to force correct ordering between irq and seqno writes on |
1612 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
1613 | * ACTHD) before reading the status page. |
1614 | * | |
1615 | * Note that this effectively stalls the read by the time it takes to | |
1616 | * do a memory transaction, which more or less ensures that the write | |
1617 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
1618 | * Alternatively we could delay the interrupt from the CS ring to give | |
1619 | * the write time to land, but that would incur a delay after every | |
1620 | * batch i.e. much more frequent than a delay when waiting for the | |
1621 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
1622 | * |
1623 | * Also note that to prevent whole machine hangs on gen7, we have to | |
1624 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 1625 | */ |
bcbdb6d0 | 1626 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 1627 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 1628 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
1629 | } |
1630 | ||
31bb59cc CW |
1631 | static void |
1632 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 1633 | { |
31bb59cc | 1634 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
1635 | } |
1636 | ||
1637 | static void | |
31bb59cc | 1638 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 1639 | { |
31bb59cc | 1640 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
1641 | } |
1642 | ||
31bb59cc CW |
1643 | static void |
1644 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 1645 | { |
c033666a | 1646 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 1647 | |
31bb59cc CW |
1648 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1649 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1650 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
1651 | } |
1652 | ||
8187a2b7 | 1653 | static void |
31bb59cc | 1654 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 1655 | { |
c033666a | 1656 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 1657 | |
31bb59cc CW |
1658 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1659 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
1660 | } |
1661 | ||
31bb59cc CW |
1662 | static void |
1663 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 1664 | { |
c033666a | 1665 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1666 | |
31bb59cc CW |
1667 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1668 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1669 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
1670 | } |
1671 | ||
1672 | static void | |
31bb59cc | 1673 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 1674 | { |
c033666a | 1675 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1676 | |
31bb59cc CW |
1677 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1678 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
1679 | } |
1680 | ||
b72f3acb | 1681 | static int |
a84c3ae1 | 1682 | bsd_ring_flush(struct drm_i915_gem_request *req, |
78501eac CW |
1683 | u32 invalidate_domains, |
1684 | u32 flush_domains) | |
d1b851fc | 1685 | { |
4a570db5 | 1686 | struct intel_engine_cs *engine = req->engine; |
b72f3acb CW |
1687 | int ret; |
1688 | ||
5fb9de1a | 1689 | ret = intel_ring_begin(req, 2); |
b72f3acb CW |
1690 | if (ret) |
1691 | return ret; | |
1692 | ||
e2f80391 TU |
1693 | intel_ring_emit(engine, MI_FLUSH); |
1694 | intel_ring_emit(engine, MI_NOOP); | |
1695 | intel_ring_advance(engine); | |
b72f3acb | 1696 | return 0; |
d1b851fc ZN |
1697 | } |
1698 | ||
3cce469c | 1699 | static int |
ee044a88 | 1700 | i9xx_add_request(struct drm_i915_gem_request *req) |
d1b851fc | 1701 | { |
4a570db5 | 1702 | struct intel_engine_cs *engine = req->engine; |
3cce469c CW |
1703 | int ret; |
1704 | ||
5fb9de1a | 1705 | ret = intel_ring_begin(req, 4); |
3cce469c CW |
1706 | if (ret) |
1707 | return ret; | |
6f392d54 | 1708 | |
e2f80391 TU |
1709 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
1710 | intel_ring_emit(engine, | |
1711 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1b7744e7 | 1712 | intel_ring_emit(engine, req->seqno); |
e2f80391 TU |
1713 | intel_ring_emit(engine, MI_USER_INTERRUPT); |
1714 | __intel_ring_advance(engine); | |
d1b851fc | 1715 | |
3cce469c | 1716 | return 0; |
d1b851fc ZN |
1717 | } |
1718 | ||
31bb59cc CW |
1719 | static void |
1720 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1721 | { |
c033666a | 1722 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1723 | |
61ff75ac CW |
1724 | I915_WRITE_IMR(engine, |
1725 | ~(engine->irq_enable_mask | | |
1726 | engine->irq_keep_mask)); | |
31bb59cc | 1727 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
1728 | } |
1729 | ||
1730 | static void | |
31bb59cc | 1731 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1732 | { |
c033666a | 1733 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1734 | |
61ff75ac | 1735 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 1736 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
1737 | } |
1738 | ||
31bb59cc CW |
1739 | static void |
1740 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1741 | { |
c033666a | 1742 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1743 | |
31bb59cc CW |
1744 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
1745 | gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 BW |
1746 | } |
1747 | ||
1748 | static void | |
31bb59cc | 1749 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1750 | { |
c033666a | 1751 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1752 | |
31bb59cc CW |
1753 | I915_WRITE_IMR(engine, ~0); |
1754 | gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 BW |
1755 | } |
1756 | ||
31bb59cc CW |
1757 | static void |
1758 | gen8_irq_enable(struct intel_engine_cs *engine) | |
abd58f01 | 1759 | { |
c033666a | 1760 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1761 | |
61ff75ac CW |
1762 | I915_WRITE_IMR(engine, |
1763 | ~(engine->irq_enable_mask | | |
1764 | engine->irq_keep_mask)); | |
31bb59cc | 1765 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1766 | } |
1767 | ||
1768 | static void | |
31bb59cc | 1769 | gen8_irq_disable(struct intel_engine_cs *engine) |
abd58f01 | 1770 | { |
c033666a | 1771 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1772 | |
61ff75ac | 1773 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
abd58f01 BW |
1774 | } |
1775 | ||
d1b851fc | 1776 | static int |
53fddaf7 | 1777 | i965_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1778 | u64 offset, u32 length, |
8e004efc | 1779 | unsigned dispatch_flags) |
d1b851fc | 1780 | { |
4a570db5 | 1781 | struct intel_engine_cs *engine = req->engine; |
e1f99ce6 | 1782 | int ret; |
78501eac | 1783 | |
5fb9de1a | 1784 | ret = intel_ring_begin(req, 2); |
e1f99ce6 CW |
1785 | if (ret) |
1786 | return ret; | |
1787 | ||
e2f80391 | 1788 | intel_ring_emit(engine, |
65f56876 CW |
1789 | MI_BATCH_BUFFER_START | |
1790 | MI_BATCH_GTT | | |
8e004efc JH |
1791 | (dispatch_flags & I915_DISPATCH_SECURE ? |
1792 | 0 : MI_BATCH_NON_SECURE_I965)); | |
e2f80391 TU |
1793 | intel_ring_emit(engine, offset); |
1794 | intel_ring_advance(engine); | |
78501eac | 1795 | |
d1b851fc ZN |
1796 | return 0; |
1797 | } | |
1798 | ||
b45305fc DV |
1799 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1800 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1801 | #define I830_TLB_ENTRIES (2) |
1802 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1803 | static int |
53fddaf7 | 1804 | i830_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
1805 | u64 offset, u32 len, |
1806 | unsigned dispatch_flags) | |
62fdfeaf | 1807 | { |
4a570db5 | 1808 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 1809 | u32 cs_offset = engine->scratch.gtt_offset; |
c4e7a414 | 1810 | int ret; |
62fdfeaf | 1811 | |
5fb9de1a | 1812 | ret = intel_ring_begin(req, 6); |
c4d69da1 CW |
1813 | if (ret) |
1814 | return ret; | |
62fdfeaf | 1815 | |
c4d69da1 | 1816 | /* Evict the invalid PTE TLBs */ |
e2f80391 TU |
1817 | intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
1818 | intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1819 | intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1820 | intel_ring_emit(engine, cs_offset); | |
1821 | intel_ring_emit(engine, 0xdeadbeef); | |
1822 | intel_ring_emit(engine, MI_NOOP); | |
1823 | intel_ring_advance(engine); | |
b45305fc | 1824 | |
8e004efc | 1825 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1826 | if (len > I830_BATCH_LIMIT) |
1827 | return -ENOSPC; | |
1828 | ||
5fb9de1a | 1829 | ret = intel_ring_begin(req, 6 + 2); |
b45305fc DV |
1830 | if (ret) |
1831 | return ret; | |
c4d69da1 CW |
1832 | |
1833 | /* Blit the batch (which has now all relocs applied) to the | |
1834 | * stable batch scratch bo area (so that the CS never | |
1835 | * stumbles over its tlb invalidation bug) ... | |
1836 | */ | |
e2f80391 TU |
1837 | intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
1838 | intel_ring_emit(engine, | |
1839 | BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); | |
1840 | intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096); | |
1841 | intel_ring_emit(engine, cs_offset); | |
1842 | intel_ring_emit(engine, 4096); | |
1843 | intel_ring_emit(engine, offset); | |
1844 | ||
1845 | intel_ring_emit(engine, MI_FLUSH); | |
1846 | intel_ring_emit(engine, MI_NOOP); | |
1847 | intel_ring_advance(engine); | |
b45305fc DV |
1848 | |
1849 | /* ... and execute it. */ | |
c4d69da1 | 1850 | offset = cs_offset; |
b45305fc | 1851 | } |
e1f99ce6 | 1852 | |
9d611c03 | 1853 | ret = intel_ring_begin(req, 2); |
c4d69da1 CW |
1854 | if (ret) |
1855 | return ret; | |
1856 | ||
e2f80391 TU |
1857 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1858 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1859 | 0 : MI_BATCH_NON_SECURE)); | |
1860 | intel_ring_advance(engine); | |
c4d69da1 | 1861 | |
fb3256da DV |
1862 | return 0; |
1863 | } | |
1864 | ||
1865 | static int | |
53fddaf7 | 1866 | i915_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1867 | u64 offset, u32 len, |
8e004efc | 1868 | unsigned dispatch_flags) |
fb3256da | 1869 | { |
4a570db5 | 1870 | struct intel_engine_cs *engine = req->engine; |
fb3256da DV |
1871 | int ret; |
1872 | ||
5fb9de1a | 1873 | ret = intel_ring_begin(req, 2); |
fb3256da DV |
1874 | if (ret) |
1875 | return ret; | |
1876 | ||
e2f80391 TU |
1877 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1878 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1879 | 0 : MI_BATCH_NON_SECURE)); | |
1880 | intel_ring_advance(engine); | |
62fdfeaf | 1881 | |
62fdfeaf EA |
1882 | return 0; |
1883 | } | |
1884 | ||
0bc40be8 | 1885 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 1886 | { |
c033666a | 1887 | struct drm_i915_private *dev_priv = engine->i915; |
7d3fdfff VS |
1888 | |
1889 | if (!dev_priv->status_page_dmah) | |
1890 | return; | |
1891 | ||
91c8a326 | 1892 | drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah); |
0bc40be8 | 1893 | engine->status_page.page_addr = NULL; |
7d3fdfff VS |
1894 | } |
1895 | ||
0bc40be8 | 1896 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1897 | { |
05394f39 | 1898 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1899 | |
0bc40be8 | 1900 | obj = engine->status_page.obj; |
8187a2b7 | 1901 | if (obj == NULL) |
62fdfeaf | 1902 | return; |
62fdfeaf | 1903 | |
9da3da66 | 1904 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1905 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 1906 | drm_gem_object_unreference(&obj->base); |
0bc40be8 | 1907 | engine->status_page.obj = NULL; |
62fdfeaf EA |
1908 | } |
1909 | ||
0bc40be8 | 1910 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1911 | { |
0bc40be8 | 1912 | struct drm_i915_gem_object *obj = engine->status_page.obj; |
62fdfeaf | 1913 | |
7d3fdfff | 1914 | if (obj == NULL) { |
1f767e02 | 1915 | unsigned flags; |
e3efda49 | 1916 | int ret; |
e4ffd173 | 1917 | |
91c8a326 | 1918 | obj = i915_gem_object_create(&engine->i915->drm, 4096); |
fe3db79b | 1919 | if (IS_ERR(obj)) { |
e3efda49 | 1920 | DRM_ERROR("Failed to allocate status page\n"); |
fe3db79b | 1921 | return PTR_ERR(obj); |
e3efda49 | 1922 | } |
62fdfeaf | 1923 | |
e3efda49 CW |
1924 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1925 | if (ret) | |
1926 | goto err_unref; | |
1927 | ||
1f767e02 | 1928 | flags = 0; |
c033666a | 1929 | if (!HAS_LLC(engine->i915)) |
1f767e02 CW |
1930 | /* On g33, we cannot place HWS above 256MiB, so |
1931 | * restrict its pinning to the low mappable arena. | |
1932 | * Though this restriction is not documented for | |
1933 | * gen4, gen5, or byt, they also behave similarly | |
1934 | * and hang if the HWS is placed at the top of the | |
1935 | * GTT. To generalise, it appears that all !llc | |
1936 | * platforms have issues with us placing the HWS | |
1937 | * above the mappable region (even though we never | |
1938 | * actualy map it). | |
1939 | */ | |
1940 | flags |= PIN_MAPPABLE; | |
1941 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
1942 | if (ret) { |
1943 | err_unref: | |
1944 | drm_gem_object_unreference(&obj->base); | |
1945 | return ret; | |
1946 | } | |
1947 | ||
0bc40be8 | 1948 | engine->status_page.obj = obj; |
e3efda49 | 1949 | } |
62fdfeaf | 1950 | |
0bc40be8 TU |
1951 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
1952 | engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); | |
1953 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 1954 | |
8187a2b7 | 1955 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
0bc40be8 | 1956 | engine->name, engine->status_page.gfx_addr); |
62fdfeaf EA |
1957 | |
1958 | return 0; | |
62fdfeaf EA |
1959 | } |
1960 | ||
0bc40be8 | 1961 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 1962 | { |
c033666a | 1963 | struct drm_i915_private *dev_priv = engine->i915; |
6b8294a4 CW |
1964 | |
1965 | if (!dev_priv->status_page_dmah) { | |
1966 | dev_priv->status_page_dmah = | |
91c8a326 | 1967 | drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE); |
6b8294a4 CW |
1968 | if (!dev_priv->status_page_dmah) |
1969 | return -ENOMEM; | |
1970 | } | |
1971 | ||
0bc40be8 TU |
1972 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1973 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
1974 | |
1975 | return 0; | |
1976 | } | |
1977 | ||
7ba717cf | 1978 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 | 1979 | { |
3d77e9be CW |
1980 | GEM_BUG_ON(ringbuf->vma == NULL); |
1981 | GEM_BUG_ON(ringbuf->virtual_start == NULL); | |
1982 | ||
def0c5f6 | 1983 | if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen) |
0a798eb9 | 1984 | i915_gem_object_unpin_map(ringbuf->obj); |
def0c5f6 | 1985 | else |
3d77e9be | 1986 | i915_vma_unpin_iomap(ringbuf->vma); |
8305216f | 1987 | ringbuf->virtual_start = NULL; |
3d77e9be | 1988 | |
2919d291 | 1989 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
3d77e9be | 1990 | ringbuf->vma = NULL; |
7ba717cf TD |
1991 | } |
1992 | ||
c033666a | 1993 | int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv, |
7ba717cf TD |
1994 | struct intel_ringbuffer *ringbuf) |
1995 | { | |
7ba717cf | 1996 | struct drm_i915_gem_object *obj = ringbuf->obj; |
a687a43a CW |
1997 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
1998 | unsigned flags = PIN_OFFSET_BIAS | 4096; | |
8305216f | 1999 | void *addr; |
7ba717cf TD |
2000 | int ret; |
2001 | ||
def0c5f6 | 2002 | if (HAS_LLC(dev_priv) && !obj->stolen) { |
a687a43a | 2003 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags); |
def0c5f6 CW |
2004 | if (ret) |
2005 | return ret; | |
7ba717cf | 2006 | |
def0c5f6 | 2007 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
d2cad535 CW |
2008 | if (ret) |
2009 | goto err_unpin; | |
def0c5f6 | 2010 | |
8305216f DG |
2011 | addr = i915_gem_object_pin_map(obj); |
2012 | if (IS_ERR(addr)) { | |
2013 | ret = PTR_ERR(addr); | |
d2cad535 | 2014 | goto err_unpin; |
def0c5f6 CW |
2015 | } |
2016 | } else { | |
a687a43a CW |
2017 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, |
2018 | flags | PIN_MAPPABLE); | |
def0c5f6 CW |
2019 | if (ret) |
2020 | return ret; | |
7ba717cf | 2021 | |
def0c5f6 | 2022 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
d2cad535 CW |
2023 | if (ret) |
2024 | goto err_unpin; | |
def0c5f6 | 2025 | |
ff3dc087 DCS |
2026 | /* Access through the GTT requires the device to be awake. */ |
2027 | assert_rpm_wakelock_held(dev_priv); | |
2028 | ||
3d77e9be CW |
2029 | addr = i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj)); |
2030 | if (IS_ERR(addr)) { | |
2031 | ret = PTR_ERR(addr); | |
d2cad535 | 2032 | goto err_unpin; |
def0c5f6 | 2033 | } |
7ba717cf TD |
2034 | } |
2035 | ||
8305216f | 2036 | ringbuf->virtual_start = addr; |
0eb973d3 | 2037 | ringbuf->vma = i915_gem_obj_to_ggtt(obj); |
7ba717cf | 2038 | return 0; |
d2cad535 CW |
2039 | |
2040 | err_unpin: | |
2041 | i915_gem_object_ggtt_unpin(obj); | |
2042 | return ret; | |
7ba717cf TD |
2043 | } |
2044 | ||
01101fa7 | 2045 | static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
7ba717cf | 2046 | { |
2919d291 OM |
2047 | drm_gem_object_unreference(&ringbuf->obj->base); |
2048 | ringbuf->obj = NULL; | |
2049 | } | |
2050 | ||
01101fa7 CW |
2051 | static int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
2052 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 2053 | { |
05394f39 | 2054 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2055 | |
ebc052e0 CW |
2056 | obj = NULL; |
2057 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 2058 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 2059 | if (obj == NULL) |
d37cd8a8 | 2060 | obj = i915_gem_object_create(dev, ringbuf->size); |
fe3db79b CW |
2061 | if (IS_ERR(obj)) |
2062 | return PTR_ERR(obj); | |
8187a2b7 | 2063 | |
24f3a8cf AG |
2064 | /* mark ring buffers as read-only from GPU side by default */ |
2065 | obj->gt_ro = 1; | |
2066 | ||
93b0a4e0 | 2067 | ringbuf->obj = obj; |
e3efda49 | 2068 | |
7ba717cf | 2069 | return 0; |
e3efda49 CW |
2070 | } |
2071 | ||
01101fa7 CW |
2072 | struct intel_ringbuffer * |
2073 | intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size) | |
2074 | { | |
2075 | struct intel_ringbuffer *ring; | |
2076 | int ret; | |
2077 | ||
2078 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
608c1a52 CW |
2079 | if (ring == NULL) { |
2080 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
2081 | engine->name); | |
01101fa7 | 2082 | return ERR_PTR(-ENOMEM); |
608c1a52 | 2083 | } |
01101fa7 | 2084 | |
4a570db5 | 2085 | ring->engine = engine; |
608c1a52 | 2086 | list_add(&ring->link, &engine->buffers); |
01101fa7 CW |
2087 | |
2088 | ring->size = size; | |
2089 | /* Workaround an erratum on the i830 which causes a hang if | |
2090 | * the TAIL pointer points to within the last 2 cachelines | |
2091 | * of the buffer. | |
2092 | */ | |
2093 | ring->effective_size = size; | |
c033666a | 2094 | if (IS_I830(engine->i915) || IS_845G(engine->i915)) |
01101fa7 CW |
2095 | ring->effective_size -= 2 * CACHELINE_BYTES; |
2096 | ||
2097 | ring->last_retired_head = -1; | |
2098 | intel_ring_update_space(ring); | |
2099 | ||
91c8a326 | 2100 | ret = intel_alloc_ringbuffer_obj(&engine->i915->drm, ring); |
01101fa7 | 2101 | if (ret) { |
608c1a52 CW |
2102 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n", |
2103 | engine->name, ret); | |
2104 | list_del(&ring->link); | |
01101fa7 CW |
2105 | kfree(ring); |
2106 | return ERR_PTR(ret); | |
2107 | } | |
2108 | ||
2109 | return ring; | |
2110 | } | |
2111 | ||
2112 | void | |
2113 | intel_ringbuffer_free(struct intel_ringbuffer *ring) | |
2114 | { | |
2115 | intel_destroy_ringbuffer_obj(ring); | |
608c1a52 | 2116 | list_del(&ring->link); |
01101fa7 CW |
2117 | kfree(ring); |
2118 | } | |
2119 | ||
0cb26a8e CW |
2120 | static int intel_ring_context_pin(struct i915_gem_context *ctx, |
2121 | struct intel_engine_cs *engine) | |
2122 | { | |
2123 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2124 | int ret; | |
2125 | ||
91c8a326 | 2126 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e CW |
2127 | |
2128 | if (ce->pin_count++) | |
2129 | return 0; | |
2130 | ||
2131 | if (ce->state) { | |
2132 | ret = i915_gem_obj_ggtt_pin(ce->state, ctx->ggtt_alignment, 0); | |
2133 | if (ret) | |
2134 | goto error; | |
2135 | } | |
2136 | ||
c7c3c07d CW |
2137 | /* The kernel context is only used as a placeholder for flushing the |
2138 | * active context. It is never used for submitting user rendering and | |
2139 | * as such never requires the golden render context, and so we can skip | |
2140 | * emitting it when we switch to the kernel context. This is required | |
2141 | * as during eviction we cannot allocate and pin the renderstate in | |
2142 | * order to initialise the context. | |
2143 | */ | |
2144 | if (ctx == ctx->i915->kernel_context) | |
2145 | ce->initialised = true; | |
2146 | ||
0cb26a8e CW |
2147 | i915_gem_context_reference(ctx); |
2148 | return 0; | |
2149 | ||
2150 | error: | |
2151 | ce->pin_count = 0; | |
2152 | return ret; | |
2153 | } | |
2154 | ||
2155 | static void intel_ring_context_unpin(struct i915_gem_context *ctx, | |
2156 | struct intel_engine_cs *engine) | |
2157 | { | |
2158 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2159 | ||
91c8a326 | 2160 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e CW |
2161 | |
2162 | if (--ce->pin_count) | |
2163 | return; | |
2164 | ||
2165 | if (ce->state) | |
2166 | i915_gem_object_ggtt_unpin(ce->state); | |
2167 | ||
2168 | i915_gem_context_unreference(ctx); | |
2169 | } | |
2170 | ||
e3efda49 | 2171 | static int intel_init_ring_buffer(struct drm_device *dev, |
0bc40be8 | 2172 | struct intel_engine_cs *engine) |
e3efda49 | 2173 | { |
c033666a | 2174 | struct drm_i915_private *dev_priv = to_i915(dev); |
bfc882b4 | 2175 | struct intel_ringbuffer *ringbuf; |
e3efda49 CW |
2176 | int ret; |
2177 | ||
0bc40be8 | 2178 | WARN_ON(engine->buffer); |
bfc882b4 | 2179 | |
c033666a | 2180 | engine->i915 = dev_priv; |
0bc40be8 TU |
2181 | INIT_LIST_HEAD(&engine->active_list); |
2182 | INIT_LIST_HEAD(&engine->request_list); | |
2183 | INIT_LIST_HEAD(&engine->execlist_queue); | |
2184 | INIT_LIST_HEAD(&engine->buffers); | |
2185 | i915_gem_batch_pool_init(dev, &engine->batch_pool); | |
2186 | memset(engine->semaphore.sync_seqno, 0, | |
2187 | sizeof(engine->semaphore.sync_seqno)); | |
e3efda49 | 2188 | |
688e6c72 CW |
2189 | ret = intel_engine_init_breadcrumbs(engine); |
2190 | if (ret) | |
2191 | goto error; | |
e3efda49 | 2192 | |
0cb26a8e CW |
2193 | /* We may need to do things with the shrinker which |
2194 | * require us to immediately switch back to the default | |
2195 | * context. This can cause a problem as pinning the | |
2196 | * default context also requires GTT space which may not | |
2197 | * be available. To avoid this we always pin the default | |
2198 | * context. | |
2199 | */ | |
2200 | ret = intel_ring_context_pin(dev_priv->kernel_context, engine); | |
2201 | if (ret) | |
2202 | goto error; | |
2203 | ||
0bc40be8 | 2204 | ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE); |
b0366a54 DG |
2205 | if (IS_ERR(ringbuf)) { |
2206 | ret = PTR_ERR(ringbuf); | |
2207 | goto error; | |
2208 | } | |
0bc40be8 | 2209 | engine->buffer = ringbuf; |
01101fa7 | 2210 | |
c033666a | 2211 | if (I915_NEED_GFX_HWS(dev_priv)) { |
0bc40be8 | 2212 | ret = init_status_page(engine); |
e3efda49 | 2213 | if (ret) |
8ee14975 | 2214 | goto error; |
e3efda49 | 2215 | } else { |
0bc40be8 TU |
2216 | WARN_ON(engine->id != RCS); |
2217 | ret = init_phys_status_page(engine); | |
e3efda49 | 2218 | if (ret) |
8ee14975 | 2219 | goto error; |
e3efda49 CW |
2220 | } |
2221 | ||
c033666a | 2222 | ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf); |
bfc882b4 DV |
2223 | if (ret) { |
2224 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", | |
0bc40be8 | 2225 | engine->name, ret); |
bfc882b4 DV |
2226 | intel_destroy_ringbuffer_obj(ringbuf); |
2227 | goto error; | |
e3efda49 | 2228 | } |
62fdfeaf | 2229 | |
0bc40be8 | 2230 | ret = i915_cmd_parser_init_ring(engine); |
44e895a8 | 2231 | if (ret) |
8ee14975 OM |
2232 | goto error; |
2233 | ||
8ee14975 | 2234 | return 0; |
351e3db2 | 2235 | |
8ee14975 | 2236 | error: |
117897f4 | 2237 | intel_cleanup_engine(engine); |
8ee14975 | 2238 | return ret; |
62fdfeaf EA |
2239 | } |
2240 | ||
117897f4 | 2241 | void intel_cleanup_engine(struct intel_engine_cs *engine) |
62fdfeaf | 2242 | { |
6402c330 | 2243 | struct drm_i915_private *dev_priv; |
33626e6a | 2244 | |
117897f4 | 2245 | if (!intel_engine_initialized(engine)) |
62fdfeaf EA |
2246 | return; |
2247 | ||
c033666a | 2248 | dev_priv = engine->i915; |
6402c330 | 2249 | |
0bc40be8 | 2250 | if (engine->buffer) { |
117897f4 | 2251 | intel_stop_engine(engine); |
c033666a | 2252 | WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0); |
33626e6a | 2253 | |
0bc40be8 TU |
2254 | intel_unpin_ringbuffer_obj(engine->buffer); |
2255 | intel_ringbuffer_free(engine->buffer); | |
2256 | engine->buffer = NULL; | |
b0366a54 | 2257 | } |
78501eac | 2258 | |
0bc40be8 TU |
2259 | if (engine->cleanup) |
2260 | engine->cleanup(engine); | |
8d19215b | 2261 | |
c033666a | 2262 | if (I915_NEED_GFX_HWS(dev_priv)) { |
0bc40be8 | 2263 | cleanup_status_page(engine); |
7d3fdfff | 2264 | } else { |
0bc40be8 TU |
2265 | WARN_ON(engine->id != RCS); |
2266 | cleanup_phys_status_page(engine); | |
7d3fdfff | 2267 | } |
44e895a8 | 2268 | |
0bc40be8 TU |
2269 | i915_cmd_parser_fini_ring(engine); |
2270 | i915_gem_batch_pool_fini(&engine->batch_pool); | |
688e6c72 | 2271 | intel_engine_fini_breadcrumbs(engine); |
0cb26a8e CW |
2272 | |
2273 | intel_ring_context_unpin(dev_priv->kernel_context, engine); | |
2274 | ||
c033666a | 2275 | engine->i915 = NULL; |
62fdfeaf EA |
2276 | } |
2277 | ||
666796da | 2278 | int intel_engine_idle(struct intel_engine_cs *engine) |
3e960501 | 2279 | { |
a4b3a571 | 2280 | struct drm_i915_gem_request *req; |
3e960501 | 2281 | |
3e960501 | 2282 | /* Wait upon the last request to be completed */ |
0bc40be8 | 2283 | if (list_empty(&engine->request_list)) |
3e960501 CW |
2284 | return 0; |
2285 | ||
0bc40be8 TU |
2286 | req = list_entry(engine->request_list.prev, |
2287 | struct drm_i915_gem_request, | |
2288 | list); | |
b4716185 CW |
2289 | |
2290 | /* Make sure we do not trigger any retires */ | |
2291 | return __i915_wait_request(req, | |
c19ae989 | 2292 | req->i915->mm.interruptible, |
b4716185 | 2293 | NULL, NULL); |
3e960501 CW |
2294 | } |
2295 | ||
6689cb2b | 2296 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
9d773091 | 2297 | { |
6310346e CW |
2298 | int ret; |
2299 | ||
2300 | /* Flush enough space to reduce the likelihood of waiting after | |
2301 | * we start building the request - in which case we will just | |
2302 | * have to repeat work. | |
2303 | */ | |
a0442461 | 2304 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 2305 | |
4a570db5 | 2306 | request->ringbuf = request->engine->buffer; |
6310346e CW |
2307 | |
2308 | ret = intel_ring_begin(request, 0); | |
2309 | if (ret) | |
2310 | return ret; | |
2311 | ||
a0442461 | 2312 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 2313 | return 0; |
9d773091 CW |
2314 | } |
2315 | ||
987046ad CW |
2316 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) |
2317 | { | |
2318 | struct intel_ringbuffer *ringbuf = req->ringbuf; | |
2319 | struct intel_engine_cs *engine = req->engine; | |
2320 | struct drm_i915_gem_request *target; | |
2321 | ||
2322 | intel_ring_update_space(ringbuf); | |
2323 | if (ringbuf->space >= bytes) | |
2324 | return 0; | |
2325 | ||
2326 | /* | |
2327 | * Space is reserved in the ringbuffer for finalising the request, | |
2328 | * as that cannot be allowed to fail. During request finalisation, | |
2329 | * reserved_space is set to 0 to stop the overallocation and the | |
2330 | * assumption is that then we never need to wait (which has the | |
2331 | * risk of failing with EINTR). | |
2332 | * | |
2333 | * See also i915_gem_request_alloc() and i915_add_request(). | |
2334 | */ | |
0251a963 | 2335 | GEM_BUG_ON(!req->reserved_space); |
987046ad CW |
2336 | |
2337 | list_for_each_entry(target, &engine->request_list, list) { | |
2338 | unsigned space; | |
2339 | ||
79bbcc29 | 2340 | /* |
987046ad CW |
2341 | * The request queue is per-engine, so can contain requests |
2342 | * from multiple ringbuffers. Here, we must ignore any that | |
2343 | * aren't from the ringbuffer we're considering. | |
79bbcc29 | 2344 | */ |
987046ad CW |
2345 | if (target->ringbuf != ringbuf) |
2346 | continue; | |
2347 | ||
2348 | /* Would completion of this request free enough space? */ | |
2349 | space = __intel_ring_space(target->postfix, ringbuf->tail, | |
2350 | ringbuf->size); | |
2351 | if (space >= bytes) | |
2352 | break; | |
79bbcc29 | 2353 | } |
29b1b415 | 2354 | |
987046ad CW |
2355 | if (WARN_ON(&target->list == &engine->request_list)) |
2356 | return -ENOSPC; | |
2357 | ||
2358 | return i915_wait_request(target); | |
29b1b415 JH |
2359 | } |
2360 | ||
987046ad | 2361 | int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
cbcc80df | 2362 | { |
987046ad | 2363 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
79bbcc29 | 2364 | int remain_actual = ringbuf->size - ringbuf->tail; |
987046ad CW |
2365 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
2366 | int bytes = num_dwords * sizeof(u32); | |
2367 | int total_bytes, wait_bytes; | |
79bbcc29 | 2368 | bool need_wrap = false; |
29b1b415 | 2369 | |
0251a963 | 2370 | total_bytes = bytes + req->reserved_space; |
29b1b415 | 2371 | |
79bbcc29 JH |
2372 | if (unlikely(bytes > remain_usable)) { |
2373 | /* | |
2374 | * Not enough space for the basic request. So need to flush | |
2375 | * out the remainder and then wait for base + reserved. | |
2376 | */ | |
2377 | wait_bytes = remain_actual + total_bytes; | |
2378 | need_wrap = true; | |
987046ad CW |
2379 | } else if (unlikely(total_bytes > remain_usable)) { |
2380 | /* | |
2381 | * The base request will fit but the reserved space | |
2382 | * falls off the end. So we don't need an immediate wrap | |
2383 | * and only need to effectively wait for the reserved | |
2384 | * size space from the start of ringbuffer. | |
2385 | */ | |
0251a963 | 2386 | wait_bytes = remain_actual + req->reserved_space; |
79bbcc29 | 2387 | } else { |
987046ad CW |
2388 | /* No wrapping required, just waiting. */ |
2389 | wait_bytes = total_bytes; | |
cbcc80df MK |
2390 | } |
2391 | ||
987046ad CW |
2392 | if (wait_bytes > ringbuf->space) { |
2393 | int ret = wait_for_space(req, wait_bytes); | |
cbcc80df MK |
2394 | if (unlikely(ret)) |
2395 | return ret; | |
79bbcc29 | 2396 | |
987046ad | 2397 | intel_ring_update_space(ringbuf); |
e075a32f CW |
2398 | if (unlikely(ringbuf->space < wait_bytes)) |
2399 | return -EAGAIN; | |
cbcc80df MK |
2400 | } |
2401 | ||
987046ad CW |
2402 | if (unlikely(need_wrap)) { |
2403 | GEM_BUG_ON(remain_actual > ringbuf->space); | |
2404 | GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size); | |
78501eac | 2405 | |
987046ad CW |
2406 | /* Fill the tail with MI_NOOP */ |
2407 | memset(ringbuf->virtual_start + ringbuf->tail, | |
2408 | 0, remain_actual); | |
2409 | ringbuf->tail = 0; | |
2410 | ringbuf->space -= remain_actual; | |
2411 | } | |
304d695c | 2412 | |
987046ad CW |
2413 | ringbuf->space -= bytes; |
2414 | GEM_BUG_ON(ringbuf->space < 0); | |
304d695c | 2415 | return 0; |
8187a2b7 | 2416 | } |
78501eac | 2417 | |
753b1ad4 | 2418 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 2419 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 2420 | { |
4a570db5 | 2421 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2422 | int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
2423 | int ret; |
2424 | ||
2425 | if (num_dwords == 0) | |
2426 | return 0; | |
2427 | ||
18393f63 | 2428 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
5fb9de1a | 2429 | ret = intel_ring_begin(req, num_dwords); |
753b1ad4 VS |
2430 | if (ret) |
2431 | return ret; | |
2432 | ||
2433 | while (num_dwords--) | |
e2f80391 | 2434 | intel_ring_emit(engine, MI_NOOP); |
753b1ad4 | 2435 | |
e2f80391 | 2436 | intel_ring_advance(engine); |
753b1ad4 VS |
2437 | |
2438 | return 0; | |
2439 | } | |
2440 | ||
0bc40be8 | 2441 | void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno) |
498d2ac1 | 2442 | { |
c033666a | 2443 | struct drm_i915_private *dev_priv = engine->i915; |
498d2ac1 | 2444 | |
29dcb570 CW |
2445 | /* Our semaphore implementation is strictly monotonic (i.e. we proceed |
2446 | * so long as the semaphore value in the register/page is greater | |
2447 | * than the sync value), so whenever we reset the seqno, | |
2448 | * so long as we reset the tracking semaphore value to 0, it will | |
2449 | * always be before the next request's seqno. If we don't reset | |
2450 | * the semaphore value, then when the seqno moves backwards all | |
2451 | * future waits will complete instantly (causing rendering corruption). | |
2452 | */ | |
7e22dbbb | 2453 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
0bc40be8 TU |
2454 | I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); |
2455 | I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); | |
d04bce48 | 2456 | if (HAS_VEBOX(dev_priv)) |
0bc40be8 | 2457 | I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); |
e1f99ce6 | 2458 | } |
a058d934 CW |
2459 | if (dev_priv->semaphore_obj) { |
2460 | struct drm_i915_gem_object *obj = dev_priv->semaphore_obj; | |
2461 | struct page *page = i915_gem_object_get_dirty_page(obj, 0); | |
2462 | void *semaphores = kmap(page); | |
2463 | memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), | |
2464 | 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
2465 | kunmap(page); | |
2466 | } | |
29dcb570 CW |
2467 | memset(engine->semaphore.sync_seqno, 0, |
2468 | sizeof(engine->semaphore.sync_seqno)); | |
d97ed339 | 2469 | |
1b7744e7 CW |
2470 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
2471 | if (engine->irq_seqno_barrier) | |
2472 | engine->irq_seqno_barrier(engine); | |
01347126 | 2473 | engine->last_submitted_seqno = seqno; |
29dcb570 | 2474 | |
0bc40be8 | 2475 | engine->hangcheck.seqno = seqno; |
688e6c72 CW |
2476 | |
2477 | /* After manually advancing the seqno, fake the interrupt in case | |
2478 | * there are any waiters for that seqno. | |
2479 | */ | |
2480 | rcu_read_lock(); | |
2481 | intel_engine_wakeup(engine); | |
2482 | rcu_read_unlock(); | |
8187a2b7 | 2483 | } |
62fdfeaf | 2484 | |
0bc40be8 | 2485 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 2486 | u32 value) |
881f47b6 | 2487 | { |
c033666a | 2488 | struct drm_i915_private *dev_priv = engine->i915; |
881f47b6 | 2489 | |
76f8421f CW |
2490 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2491 | ||
881f47b6 | 2492 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
2493 | |
2494 | /* Disable notification that the ring is IDLE. The GT | |
2495 | * will then assume that it is busy and bring it out of rc6. | |
2496 | */ | |
76f8421f CW |
2497 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2498 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
2499 | |
2500 | /* Clear the context id. Here be magic! */ | |
76f8421f | 2501 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 2502 | |
12f55818 | 2503 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
76f8421f CW |
2504 | if (intel_wait_for_register_fw(dev_priv, |
2505 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
2506 | GEN6_BSD_SLEEP_INDICATOR, | |
2507 | 0, | |
2508 | 50)) | |
12f55818 | 2509 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 2510 | |
12f55818 | 2511 | /* Now that the ring is fully powered up, update the tail */ |
76f8421f CW |
2512 | I915_WRITE_FW(RING_TAIL(engine->mmio_base), value); |
2513 | POSTING_READ_FW(RING_TAIL(engine->mmio_base)); | |
12f55818 CW |
2514 | |
2515 | /* Let the ring send IDLE messages to the GT again, | |
2516 | * and so let it sleep to conserve power when idle. | |
2517 | */ | |
76f8421f CW |
2518 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2519 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
2520 | ||
2521 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
2522 | } |
2523 | ||
a84c3ae1 | 2524 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2525 | u32 invalidate, u32 flush) |
881f47b6 | 2526 | { |
4a570db5 | 2527 | struct intel_engine_cs *engine = req->engine; |
71a77e07 | 2528 | uint32_t cmd; |
b72f3acb CW |
2529 | int ret; |
2530 | ||
5fb9de1a | 2531 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2532 | if (ret) |
2533 | return ret; | |
2534 | ||
71a77e07 | 2535 | cmd = MI_FLUSH_DW; |
c033666a | 2536 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2537 | cmd += 1; |
f0a1fb10 CW |
2538 | |
2539 | /* We always require a command barrier so that subsequent | |
2540 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2541 | * wrt the contents of the write cache being flushed to memory | |
2542 | * (and thus being coherent from the CPU). | |
2543 | */ | |
2544 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2545 | ||
9a289771 JB |
2546 | /* |
2547 | * Bspec vol 1c.5 - video engine command streamer: | |
2548 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2549 | * operation is complete. This bit is only valid when the | |
2550 | * Post-Sync Operation field is a value of 1h or 3h." | |
2551 | */ | |
71a77e07 | 2552 | if (invalidate & I915_GEM_GPU_DOMAINS) |
f0a1fb10 CW |
2553 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
2554 | ||
e2f80391 TU |
2555 | intel_ring_emit(engine, cmd); |
2556 | intel_ring_emit(engine, | |
2557 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
c033666a | 2558 | if (INTEL_GEN(req->i915) >= 8) { |
e2f80391 TU |
2559 | intel_ring_emit(engine, 0); /* upper addr */ |
2560 | intel_ring_emit(engine, 0); /* value */ | |
075b3bba | 2561 | } else { |
e2f80391 TU |
2562 | intel_ring_emit(engine, 0); |
2563 | intel_ring_emit(engine, MI_NOOP); | |
075b3bba | 2564 | } |
e2f80391 | 2565 | intel_ring_advance(engine); |
b72f3acb | 2566 | return 0; |
881f47b6 XH |
2567 | } |
2568 | ||
1c7a0623 | 2569 | static int |
53fddaf7 | 2570 | gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2571 | u64 offset, u32 len, |
8e004efc | 2572 | unsigned dispatch_flags) |
1c7a0623 | 2573 | { |
4a570db5 | 2574 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2575 | bool ppgtt = USES_PPGTT(engine->dev) && |
8e004efc | 2576 | !(dispatch_flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2577 | int ret; |
2578 | ||
5fb9de1a | 2579 | ret = intel_ring_begin(req, 4); |
1c7a0623 BW |
2580 | if (ret) |
2581 | return ret; | |
2582 | ||
2583 | /* FIXME(BDW): Address space and security selectors. */ | |
e2f80391 | 2584 | intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
919032ec AJ |
2585 | (dispatch_flags & I915_DISPATCH_RS ? |
2586 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
e2f80391 TU |
2587 | intel_ring_emit(engine, lower_32_bits(offset)); |
2588 | intel_ring_emit(engine, upper_32_bits(offset)); | |
2589 | intel_ring_emit(engine, MI_NOOP); | |
2590 | intel_ring_advance(engine); | |
1c7a0623 BW |
2591 | |
2592 | return 0; | |
2593 | } | |
2594 | ||
d7d4eedd | 2595 | static int |
53fddaf7 | 2596 | hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
2597 | u64 offset, u32 len, |
2598 | unsigned dispatch_flags) | |
d7d4eedd | 2599 | { |
4a570db5 | 2600 | struct intel_engine_cs *engine = req->engine; |
d7d4eedd CW |
2601 | int ret; |
2602 | ||
5fb9de1a | 2603 | ret = intel_ring_begin(req, 2); |
d7d4eedd CW |
2604 | if (ret) |
2605 | return ret; | |
2606 | ||
e2f80391 | 2607 | intel_ring_emit(engine, |
77072258 | 2608 | MI_BATCH_BUFFER_START | |
8e004efc | 2609 | (dispatch_flags & I915_DISPATCH_SECURE ? |
919032ec AJ |
2610 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
2611 | (dispatch_flags & I915_DISPATCH_RS ? | |
2612 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
d7d4eedd | 2613 | /* bit0-7 is the length on GEN6+ */ |
e2f80391 TU |
2614 | intel_ring_emit(engine, offset); |
2615 | intel_ring_advance(engine); | |
d7d4eedd CW |
2616 | |
2617 | return 0; | |
2618 | } | |
2619 | ||
881f47b6 | 2620 | static int |
53fddaf7 | 2621 | gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2622 | u64 offset, u32 len, |
8e004efc | 2623 | unsigned dispatch_flags) |
881f47b6 | 2624 | { |
4a570db5 | 2625 | struct intel_engine_cs *engine = req->engine; |
0206e353 | 2626 | int ret; |
ab6f8e32 | 2627 | |
5fb9de1a | 2628 | ret = intel_ring_begin(req, 2); |
0206e353 AJ |
2629 | if (ret) |
2630 | return ret; | |
e1f99ce6 | 2631 | |
e2f80391 | 2632 | intel_ring_emit(engine, |
d7d4eedd | 2633 | MI_BATCH_BUFFER_START | |
8e004efc JH |
2634 | (dispatch_flags & I915_DISPATCH_SECURE ? |
2635 | 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 | 2636 | /* bit0-7 is the length on GEN6+ */ |
e2f80391 TU |
2637 | intel_ring_emit(engine, offset); |
2638 | intel_ring_advance(engine); | |
ab6f8e32 | 2639 | |
0206e353 | 2640 | return 0; |
881f47b6 XH |
2641 | } |
2642 | ||
549f7365 CW |
2643 | /* Blitter support (SandyBridge+) */ |
2644 | ||
a84c3ae1 | 2645 | static int gen6_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2646 | u32 invalidate, u32 flush) |
8d19215b | 2647 | { |
4a570db5 | 2648 | struct intel_engine_cs *engine = req->engine; |
71a77e07 | 2649 | uint32_t cmd; |
b72f3acb CW |
2650 | int ret; |
2651 | ||
5fb9de1a | 2652 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2653 | if (ret) |
2654 | return ret; | |
2655 | ||
71a77e07 | 2656 | cmd = MI_FLUSH_DW; |
c033666a | 2657 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2658 | cmd += 1; |
f0a1fb10 CW |
2659 | |
2660 | /* We always require a command barrier so that subsequent | |
2661 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2662 | * wrt the contents of the write cache being flushed to memory | |
2663 | * (and thus being coherent from the CPU). | |
2664 | */ | |
2665 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2666 | ||
9a289771 JB |
2667 | /* |
2668 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2669 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2670 | * operation is complete. This bit is only valid when the | |
2671 | * Post-Sync Operation field is a value of 1h or 3h." | |
2672 | */ | |
71a77e07 | 2673 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
f0a1fb10 | 2674 | cmd |= MI_INVALIDATE_TLB; |
e2f80391 TU |
2675 | intel_ring_emit(engine, cmd); |
2676 | intel_ring_emit(engine, | |
2677 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
c033666a | 2678 | if (INTEL_GEN(req->i915) >= 8) { |
e2f80391 TU |
2679 | intel_ring_emit(engine, 0); /* upper addr */ |
2680 | intel_ring_emit(engine, 0); /* value */ | |
075b3bba | 2681 | } else { |
e2f80391 TU |
2682 | intel_ring_emit(engine, 0); |
2683 | intel_ring_emit(engine, MI_NOOP); | |
075b3bba | 2684 | } |
e2f80391 | 2685 | intel_ring_advance(engine); |
fd3da6c9 | 2686 | |
b72f3acb | 2687 | return 0; |
8d19215b ZN |
2688 | } |
2689 | ||
d9a64610 TU |
2690 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
2691 | struct intel_engine_cs *engine) | |
2692 | { | |
db3d4019 | 2693 | struct drm_i915_gem_object *obj; |
1b9e6650 | 2694 | int ret, i; |
db3d4019 TU |
2695 | |
2696 | if (!i915_semaphore_is_enabled(dev_priv)) | |
2697 | return; | |
2698 | ||
2699 | if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore_obj) { | |
91c8a326 | 2700 | obj = i915_gem_object_create(&dev_priv->drm, 4096); |
db3d4019 TU |
2701 | if (IS_ERR(obj)) { |
2702 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2703 | i915.semaphores = 0; | |
2704 | } else { | |
2705 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2706 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2707 | if (ret != 0) { | |
2708 | drm_gem_object_unreference(&obj->base); | |
2709 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2710 | i915.semaphores = 0; | |
2711 | } else { | |
2712 | dev_priv->semaphore_obj = obj; | |
2713 | } | |
2714 | } | |
2715 | } | |
2716 | ||
d9a64610 TU |
2717 | if (!i915_semaphore_is_enabled(dev_priv)) |
2718 | return; | |
2719 | ||
2720 | if (INTEL_GEN(dev_priv) >= 8) { | |
1b9e6650 TU |
2721 | u64 offset = i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj); |
2722 | ||
d9a64610 TU |
2723 | engine->semaphore.sync_to = gen8_ring_sync; |
2724 | engine->semaphore.signal = gen8_xcs_signal; | |
1b9e6650 TU |
2725 | |
2726 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
2727 | u64 ring_offset; | |
2728 | ||
2729 | if (i != engine->id) | |
2730 | ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i); | |
2731 | else | |
2732 | ring_offset = MI_SEMAPHORE_SYNC_INVALID; | |
2733 | ||
2734 | engine->semaphore.signal_ggtt[i] = ring_offset; | |
2735 | } | |
d9a64610 TU |
2736 | } else if (INTEL_GEN(dev_priv) >= 6) { |
2737 | engine->semaphore.sync_to = gen6_ring_sync; | |
2738 | engine->semaphore.signal = gen6_signal; | |
4b8e38a9 TU |
2739 | |
2740 | /* | |
2741 | * The current semaphore is only applied on pre-gen8 | |
2742 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2743 | * platform. So the semaphore between RCS and VCS2 is | |
2744 | * initialized as INVALID. Gen8 will initialize the | |
2745 | * sema between VCS2 and RCS later. | |
2746 | */ | |
2747 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
2748 | static const struct { | |
2749 | u32 wait_mbox; | |
2750 | i915_reg_t mbox_reg; | |
2751 | } sem_data[I915_NUM_ENGINES][I915_NUM_ENGINES] = { | |
2752 | [RCS] = { | |
2753 | [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, | |
2754 | [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, | |
2755 | [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, | |
2756 | }, | |
2757 | [VCS] = { | |
2758 | [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, | |
2759 | [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, | |
2760 | [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, | |
2761 | }, | |
2762 | [BCS] = { | |
2763 | [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, | |
2764 | [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, | |
2765 | [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, | |
2766 | }, | |
2767 | [VECS] = { | |
2768 | [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, | |
2769 | [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, | |
2770 | [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, | |
2771 | }, | |
2772 | }; | |
2773 | u32 wait_mbox; | |
2774 | i915_reg_t mbox_reg; | |
2775 | ||
2776 | if (i == engine->id || i == VCS2) { | |
2777 | wait_mbox = MI_SEMAPHORE_SYNC_INVALID; | |
2778 | mbox_reg = GEN6_NOSYNC; | |
2779 | } else { | |
2780 | wait_mbox = sem_data[engine->id][i].wait_mbox; | |
2781 | mbox_reg = sem_data[engine->id][i].mbox_reg; | |
2782 | } | |
2783 | ||
2784 | engine->semaphore.mbox.wait[i] = wait_mbox; | |
2785 | engine->semaphore.mbox.signal[i] = mbox_reg; | |
2786 | } | |
d9a64610 TU |
2787 | } |
2788 | } | |
2789 | ||
ed003078 CW |
2790 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
2791 | struct intel_engine_cs *engine) | |
2792 | { | |
2793 | if (INTEL_GEN(dev_priv) >= 8) { | |
31bb59cc CW |
2794 | engine->irq_enable = gen8_irq_enable; |
2795 | engine->irq_disable = gen8_irq_disable; | |
ed003078 CW |
2796 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2797 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
31bb59cc CW |
2798 | engine->irq_enable = gen6_irq_enable; |
2799 | engine->irq_disable = gen6_irq_disable; | |
ed003078 CW |
2800 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2801 | } else if (INTEL_GEN(dev_priv) >= 5) { | |
31bb59cc CW |
2802 | engine->irq_enable = gen5_irq_enable; |
2803 | engine->irq_disable = gen5_irq_disable; | |
f8973c21 | 2804 | engine->irq_seqno_barrier = gen5_seqno_barrier; |
ed003078 | 2805 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
2806 | engine->irq_enable = i9xx_irq_enable; |
2807 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 2808 | } else { |
31bb59cc CW |
2809 | engine->irq_enable = i8xx_irq_enable; |
2810 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
2811 | } |
2812 | } | |
2813 | ||
06a2fe22 TU |
2814 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2815 | struct intel_engine_cs *engine) | |
2816 | { | |
1d8a1337 | 2817 | engine->init_hw = init_ring_common; |
06a2fe22 | 2818 | engine->write_tail = ring_write_tail; |
7445a2a4 | 2819 | |
6f7bef75 CW |
2820 | engine->add_request = i9xx_add_request; |
2821 | if (INTEL_GEN(dev_priv) >= 6) | |
960ecaad | 2822 | engine->add_request = gen6_add_request; |
6f7bef75 CW |
2823 | |
2824 | if (INTEL_GEN(dev_priv) >= 8) | |
2825 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
2826 | else if (INTEL_GEN(dev_priv) >= 6) | |
960ecaad | 2827 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
6f7bef75 | 2828 | else if (INTEL_GEN(dev_priv) >= 4) |
960ecaad | 2829 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
6f7bef75 CW |
2830 | else if (IS_I830(dev_priv) || IS_845G(dev_priv)) |
2831 | engine->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2832 | else | |
2833 | engine->dispatch_execbuffer = i915_dispatch_execbuffer; | |
b9700325 | 2834 | |
ed003078 | 2835 | intel_ring_init_irq(dev_priv, engine); |
d9a64610 | 2836 | intel_ring_init_semaphores(dev_priv, engine); |
06a2fe22 TU |
2837 | } |
2838 | ||
5c1143bb XH |
2839 | int intel_init_render_ring_buffer(struct drm_device *dev) |
2840 | { | |
fac5e23e | 2841 | struct drm_i915_private *dev_priv = to_i915(dev); |
4a570db5 | 2842 | struct intel_engine_cs *engine = &dev_priv->engine[RCS]; |
3e78998a | 2843 | int ret; |
5c1143bb | 2844 | |
e2f80391 TU |
2845 | engine->name = "render ring"; |
2846 | engine->id = RCS; | |
2847 | engine->exec_id = I915_EXEC_RENDER; | |
215a7e32 | 2848 | engine->hw_id = 0; |
e2f80391 | 2849 | engine->mmio_base = RENDER_RING_BASE; |
59465b5f | 2850 | |
06a2fe22 TU |
2851 | intel_ring_default_vfuncs(dev_priv, engine); |
2852 | ||
f8973c21 | 2853 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
61ff75ac CW |
2854 | if (HAS_L3_DPF(dev_priv)) |
2855 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2856 | |
c033666a | 2857 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 2858 | engine->init_context = intel_rcs_ctx_init; |
a58c01aa | 2859 | engine->add_request = gen8_render_add_request; |
e2f80391 | 2860 | engine->flush = gen8_render_ring_flush; |
db3d4019 | 2861 | if (i915_semaphore_is_enabled(dev_priv)) |
e2f80391 | 2862 | engine->semaphore.signal = gen8_rcs_signal; |
c033666a | 2863 | } else if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 2864 | engine->init_context = intel_rcs_ctx_init; |
e2f80391 | 2865 | engine->flush = gen7_render_ring_flush; |
c033666a | 2866 | if (IS_GEN6(dev_priv)) |
e2f80391 | 2867 | engine->flush = gen6_render_ring_flush; |
c033666a | 2868 | } else if (IS_GEN5(dev_priv)) { |
e2f80391 | 2869 | engine->flush = gen4_render_ring_flush; |
59465b5f | 2870 | } else { |
c033666a | 2871 | if (INTEL_GEN(dev_priv) < 4) |
e2f80391 | 2872 | engine->flush = gen2_render_ring_flush; |
46f0f8d1 | 2873 | else |
e2f80391 | 2874 | engine->flush = gen4_render_ring_flush; |
e2f80391 | 2875 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2876 | } |
707d9cf9 | 2877 | |
c033666a | 2878 | if (IS_HASWELL(dev_priv)) |
e2f80391 | 2879 | engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
6f7bef75 | 2880 | |
e2f80391 TU |
2881 | engine->init_hw = init_render_ring; |
2882 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2883 | |
e2f80391 | 2884 | ret = intel_init_ring_buffer(dev, engine); |
99be1dfe DV |
2885 | if (ret) |
2886 | return ret; | |
2887 | ||
f8973c21 | 2888 | if (INTEL_GEN(dev_priv) >= 6) { |
7d5ea807 CW |
2889 | ret = intel_init_pipe_control(engine, 4096); |
2890 | if (ret) | |
2891 | return ret; | |
2892 | } else if (HAS_BROKEN_CS_TLB(dev_priv)) { | |
2893 | ret = intel_init_pipe_control(engine, I830_WA_SIZE); | |
99be1dfe DV |
2894 | if (ret) |
2895 | return ret; | |
2896 | } | |
2897 | ||
2898 | return 0; | |
5c1143bb XH |
2899 | } |
2900 | ||
2901 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
2902 | { | |
fac5e23e | 2903 | struct drm_i915_private *dev_priv = to_i915(dev); |
4a570db5 | 2904 | struct intel_engine_cs *engine = &dev_priv->engine[VCS]; |
5c1143bb | 2905 | |
e2f80391 TU |
2906 | engine->name = "bsd ring"; |
2907 | engine->id = VCS; | |
2908 | engine->exec_id = I915_EXEC_BSD; | |
215a7e32 | 2909 | engine->hw_id = 1; |
58fa3835 | 2910 | |
06a2fe22 TU |
2911 | intel_ring_default_vfuncs(dev_priv, engine); |
2912 | ||
c033666a | 2913 | if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 2914 | engine->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 | 2915 | /* gen6 bsd needs a special wa for tail updates */ |
c033666a | 2916 | if (IS_GEN6(dev_priv)) |
e2f80391 TU |
2917 | engine->write_tail = gen6_bsd_ring_write_tail; |
2918 | engine->flush = gen6_bsd_ring_flush; | |
8d228911 | 2919 | if (INTEL_GEN(dev_priv) >= 8) |
e2f80391 | 2920 | engine->irq_enable_mask = |
abd58f01 | 2921 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
8d228911 | 2922 | else |
e2f80391 | 2923 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 | 2924 | } else { |
e2f80391 TU |
2925 | engine->mmio_base = BSD_RING_BASE; |
2926 | engine->flush = bsd_ring_flush; | |
8d228911 | 2927 | if (IS_GEN5(dev_priv)) |
e2f80391 | 2928 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2929 | else |
e2f80391 | 2930 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2931 | } |
58fa3835 | 2932 | |
e2f80391 | 2933 | return intel_init_ring_buffer(dev, engine); |
5c1143bb | 2934 | } |
549f7365 | 2935 | |
845f74a7 | 2936 | /** |
62659920 | 2937 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 ZY |
2938 | */ |
2939 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
2940 | { | |
fac5e23e | 2941 | struct drm_i915_private *dev_priv = to_i915(dev); |
4a570db5 | 2942 | struct intel_engine_cs *engine = &dev_priv->engine[VCS2]; |
e2f80391 TU |
2943 | |
2944 | engine->name = "bsd2 ring"; | |
2945 | engine->id = VCS2; | |
2946 | engine->exec_id = I915_EXEC_BSD; | |
215a7e32 | 2947 | engine->hw_id = 4; |
e2f80391 | 2948 | engine->mmio_base = GEN8_BSD2_RING_BASE; |
06a2fe22 TU |
2949 | |
2950 | intel_ring_default_vfuncs(dev_priv, engine); | |
2951 | ||
e2f80391 | 2952 | engine->flush = gen6_bsd_ring_flush; |
e2f80391 | 2953 | engine->irq_enable_mask = |
845f74a7 | 2954 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
845f74a7 | 2955 | |
e2f80391 | 2956 | return intel_init_ring_buffer(dev, engine); |
845f74a7 ZY |
2957 | } |
2958 | ||
549f7365 CW |
2959 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
2960 | { | |
fac5e23e | 2961 | struct drm_i915_private *dev_priv = to_i915(dev); |
4a570db5 | 2962 | struct intel_engine_cs *engine = &dev_priv->engine[BCS]; |
e2f80391 TU |
2963 | |
2964 | engine->name = "blitter ring"; | |
2965 | engine->id = BCS; | |
2966 | engine->exec_id = I915_EXEC_BLT; | |
215a7e32 | 2967 | engine->hw_id = 2; |
e2f80391 | 2968 | engine->mmio_base = BLT_RING_BASE; |
06a2fe22 TU |
2969 | |
2970 | intel_ring_default_vfuncs(dev_priv, engine); | |
2971 | ||
e2f80391 | 2972 | engine->flush = gen6_ring_flush; |
8d228911 | 2973 | if (INTEL_GEN(dev_priv) >= 8) |
e2f80391 | 2974 | engine->irq_enable_mask = |
abd58f01 | 2975 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
8d228911 | 2976 | else |
e2f80391 | 2977 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2978 | |
e2f80391 | 2979 | return intel_init_ring_buffer(dev, engine); |
549f7365 | 2980 | } |
a7b9761d | 2981 | |
9a8a2213 BW |
2982 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2983 | { | |
fac5e23e | 2984 | struct drm_i915_private *dev_priv = to_i915(dev); |
4a570db5 | 2985 | struct intel_engine_cs *engine = &dev_priv->engine[VECS]; |
9a8a2213 | 2986 | |
e2f80391 TU |
2987 | engine->name = "video enhancement ring"; |
2988 | engine->id = VECS; | |
2989 | engine->exec_id = I915_EXEC_VEBOX; | |
215a7e32 | 2990 | engine->hw_id = 3; |
e2f80391 | 2991 | engine->mmio_base = VEBOX_RING_BASE; |
06a2fe22 TU |
2992 | |
2993 | intel_ring_default_vfuncs(dev_priv, engine); | |
2994 | ||
e2f80391 | 2995 | engine->flush = gen6_ring_flush; |
abd58f01 | 2996 | |
c033666a | 2997 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 2998 | engine->irq_enable_mask = |
40c499f9 | 2999 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 | 3000 | } else { |
e2f80391 | 3001 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
31bb59cc CW |
3002 | engine->irq_enable = hsw_vebox_irq_enable; |
3003 | engine->irq_disable = hsw_vebox_irq_disable; | |
abd58f01 | 3004 | } |
9a8a2213 | 3005 | |
e2f80391 | 3006 | return intel_init_ring_buffer(dev, engine); |
9a8a2213 BW |
3007 | } |
3008 | ||
a7b9761d | 3009 | int |
4866d729 | 3010 | intel_ring_flush_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3011 | { |
4a570db5 | 3012 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
3013 | int ret; |
3014 | ||
e2f80391 | 3015 | if (!engine->gpu_caches_dirty) |
a7b9761d CW |
3016 | return 0; |
3017 | ||
e2f80391 | 3018 | ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d CW |
3019 | if (ret) |
3020 | return ret; | |
3021 | ||
a84c3ae1 | 3022 | trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d | 3023 | |
e2f80391 | 3024 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3025 | return 0; |
3026 | } | |
3027 | ||
3028 | int | |
2f20055d | 3029 | intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3030 | { |
4a570db5 | 3031 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
3032 | uint32_t flush_domains; |
3033 | int ret; | |
3034 | ||
3035 | flush_domains = 0; | |
e2f80391 | 3036 | if (engine->gpu_caches_dirty) |
a7b9761d CW |
3037 | flush_domains = I915_GEM_GPU_DOMAINS; |
3038 | ||
e2f80391 | 3039 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d CW |
3040 | if (ret) |
3041 | return ret; | |
3042 | ||
a84c3ae1 | 3043 | trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d | 3044 | |
e2f80391 | 3045 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3046 | return 0; |
3047 | } | |
e3efda49 CW |
3048 | |
3049 | void | |
117897f4 | 3050 | intel_stop_engine(struct intel_engine_cs *engine) |
e3efda49 CW |
3051 | { |
3052 | int ret; | |
3053 | ||
117897f4 | 3054 | if (!intel_engine_initialized(engine)) |
e3efda49 CW |
3055 | return; |
3056 | ||
666796da | 3057 | ret = intel_engine_idle(engine); |
f4457ae7 | 3058 | if (ret) |
e3efda49 | 3059 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
0bc40be8 | 3060 | engine->name, ret); |
e3efda49 | 3061 | |
0bc40be8 | 3062 | stop_ring(engine); |
e3efda49 | 3063 | } |