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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
62fdfeaf | 32 | #include "i915_drv.h" |
8187a2b7 | 33 | #include "i915_drm.h" |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
6f392d54 CW |
37 | static u32 i915_gem_get_seqno(struct drm_device *dev) |
38 | { | |
39 | drm_i915_private_t *dev_priv = dev->dev_private; | |
40 | u32 seqno; | |
41 | ||
42 | seqno = dev_priv->next_seqno; | |
43 | ||
44 | /* reserve 0 for non-seqno */ | |
45 | if (++dev_priv->next_seqno == 0) | |
46 | dev_priv->next_seqno = 1; | |
47 | ||
48 | return seqno; | |
49 | } | |
50 | ||
8187a2b7 ZN |
51 | static void |
52 | render_ring_flush(struct drm_device *dev, | |
ab6f8e32 CW |
53 | struct intel_ring_buffer *ring, |
54 | u32 invalidate_domains, | |
55 | u32 flush_domains) | |
62fdfeaf | 56 | { |
6f392d54 CW |
57 | drm_i915_private_t *dev_priv = dev->dev_private; |
58 | u32 cmd; | |
59 | ||
62fdfeaf EA |
60 | #if WATCH_EXEC |
61 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, | |
62 | invalidate_domains, flush_domains); | |
63 | #endif | |
6f392d54 CW |
64 | |
65 | trace_i915_gem_request_flush(dev, dev_priv->next_seqno, | |
62fdfeaf EA |
66 | invalidate_domains, flush_domains); |
67 | ||
62fdfeaf EA |
68 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
69 | /* | |
70 | * read/write caches: | |
71 | * | |
72 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
73 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
74 | * also flushed at 2d versus 3d pipeline switches. | |
75 | * | |
76 | * read-only caches: | |
77 | * | |
78 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
79 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
80 | * | |
81 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
82 | * | |
83 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
84 | * invalidated when MI_EXE_FLUSH is set. | |
85 | * | |
86 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
87 | * invalidated with every MI_FLUSH. | |
88 | * | |
89 | * TLBs: | |
90 | * | |
91 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
92 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
93 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
94 | * are flushed at any MI_FLUSH. | |
95 | */ | |
96 | ||
97 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
98 | if ((invalidate_domains|flush_domains) & | |
99 | I915_GEM_DOMAIN_RENDER) | |
100 | cmd &= ~MI_NO_WRITE_FLUSH; | |
a6c45cf0 | 101 | if (INTEL_INFO(dev)->gen < 4) { |
62fdfeaf EA |
102 | /* |
103 | * On the 965, the sampler cache always gets flushed | |
104 | * and this bit is reserved. | |
105 | */ | |
106 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
107 | cmd |= MI_READ_FLUSH; | |
108 | } | |
109 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) | |
110 | cmd |= MI_EXE_FLUSH; | |
111 | ||
112 | #if WATCH_EXEC | |
113 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); | |
114 | #endif | |
be26a10b | 115 | intel_ring_begin(dev, ring, 2); |
8187a2b7 ZN |
116 | intel_ring_emit(dev, ring, cmd); |
117 | intel_ring_emit(dev, ring, MI_NOOP); | |
118 | intel_ring_advance(dev, ring); | |
62fdfeaf | 119 | } |
8187a2b7 ZN |
120 | } |
121 | ||
870e86dd DV |
122 | static void ring_set_tail(struct drm_device *dev, |
123 | struct intel_ring_buffer *ring, | |
124 | u32 value) | |
d46eefa2 XH |
125 | { |
126 | drm_i915_private_t *dev_priv = dev->dev_private; | |
870e86dd | 127 | I915_WRITE_TAIL(ring, ring->tail); |
d46eefa2 XH |
128 | } |
129 | ||
79f321b7 DV |
130 | u32 intel_ring_get_active_head(struct drm_device *dev, |
131 | struct intel_ring_buffer *ring) | |
8187a2b7 ZN |
132 | { |
133 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3d281d8c DV |
134 | u32 acthd_reg = INTEL_INFO(dev)->gen >= 4 ? |
135 | RING_ACTHD(ring->mmio_base) : ACTHD; | |
8187a2b7 ZN |
136 | |
137 | return I915_READ(acthd_reg); | |
138 | } | |
139 | ||
8187a2b7 | 140 | static int init_ring_common(struct drm_device *dev, |
ab6f8e32 | 141 | struct intel_ring_buffer *ring) |
8187a2b7 ZN |
142 | { |
143 | u32 head; | |
144 | drm_i915_private_t *dev_priv = dev->dev_private; | |
145 | struct drm_i915_gem_object *obj_priv; | |
146 | obj_priv = to_intel_bo(ring->gem_object); | |
147 | ||
148 | /* Stop the ring if it's running. */ | |
7f2ab699 | 149 | I915_WRITE_CTL(ring, 0); |
570ef608 | 150 | I915_WRITE_HEAD(ring, 0); |
870e86dd | 151 | ring->set_tail(dev, ring, 0); |
8187a2b7 ZN |
152 | |
153 | /* Initialize the ring. */ | |
6c0e1c55 | 154 | I915_WRITE_START(ring, obj_priv->gtt_offset); |
570ef608 | 155 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
156 | |
157 | /* G45 ring initialization fails to reset head to zero */ | |
158 | if (head != 0) { | |
159 | DRM_ERROR("%s head not reset to zero " | |
160 | "ctl %08x head %08x tail %08x start %08x\n", | |
161 | ring->name, | |
7f2ab699 | 162 | I915_READ_CTL(ring), |
570ef608 | 163 | I915_READ_HEAD(ring), |
870e86dd | 164 | I915_READ_TAIL(ring), |
6c0e1c55 | 165 | I915_READ_START(ring)); |
8187a2b7 | 166 | |
570ef608 | 167 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 ZN |
168 | |
169 | DRM_ERROR("%s head forced to zero " | |
170 | "ctl %08x head %08x tail %08x start %08x\n", | |
171 | ring->name, | |
7f2ab699 | 172 | I915_READ_CTL(ring), |
570ef608 | 173 | I915_READ_HEAD(ring), |
870e86dd | 174 | I915_READ_TAIL(ring), |
6c0e1c55 | 175 | I915_READ_START(ring)); |
8187a2b7 ZN |
176 | } |
177 | ||
7f2ab699 | 178 | I915_WRITE_CTL(ring, |
8187a2b7 ZN |
179 | ((ring->gem_object->size - PAGE_SIZE) & RING_NR_PAGES) |
180 | | RING_NO_REPORT | RING_VALID); | |
181 | ||
570ef608 | 182 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
183 | /* If the head is still not zero, the ring is dead */ |
184 | if (head != 0) { | |
185 | DRM_ERROR("%s initialization failed " | |
186 | "ctl %08x head %08x tail %08x start %08x\n", | |
187 | ring->name, | |
7f2ab699 | 188 | I915_READ_CTL(ring), |
570ef608 | 189 | I915_READ_HEAD(ring), |
870e86dd | 190 | I915_READ_TAIL(ring), |
6c0e1c55 | 191 | I915_READ_START(ring)); |
8187a2b7 ZN |
192 | return -EIO; |
193 | } | |
194 | ||
195 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
196 | i915_kernel_lost_context(dev); | |
197 | else { | |
570ef608 | 198 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
870e86dd | 199 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
8187a2b7 ZN |
200 | ring->space = ring->head - (ring->tail + 8); |
201 | if (ring->space < 0) | |
202 | ring->space += ring->size; | |
203 | } | |
204 | return 0; | |
205 | } | |
206 | ||
207 | static int init_render_ring(struct drm_device *dev, | |
ab6f8e32 | 208 | struct intel_ring_buffer *ring) |
8187a2b7 ZN |
209 | { |
210 | drm_i915_private_t *dev_priv = dev->dev_private; | |
211 | int ret = init_ring_common(dev, ring); | |
a69ffdbf ZW |
212 | int mode; |
213 | ||
a6c45cf0 | 214 | if (INTEL_INFO(dev)->gen > 3) { |
a69ffdbf ZW |
215 | mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; |
216 | if (IS_GEN6(dev)) | |
217 | mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; | |
218 | I915_WRITE(MI_MODE, mode); | |
8187a2b7 ZN |
219 | } |
220 | return ret; | |
221 | } | |
222 | ||
62fdfeaf | 223 | #define PIPE_CONTROL_FLUSH(addr) \ |
8187a2b7 | 224 | do { \ |
62fdfeaf | 225 | OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \ |
ca76482e | 226 | PIPE_CONTROL_DEPTH_STALL | 2); \ |
62fdfeaf EA |
227 | OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT); \ |
228 | OUT_RING(0); \ | |
229 | OUT_RING(0); \ | |
8187a2b7 | 230 | } while (0) |
62fdfeaf EA |
231 | |
232 | /** | |
233 | * Creates a new sequence number, emitting a write of it to the status page | |
234 | * plus an interrupt, which will trigger i915_user_interrupt_handler. | |
235 | * | |
236 | * Must be called with struct_lock held. | |
237 | * | |
238 | * Returned sequence numbers are nonzero on success. | |
239 | */ | |
8187a2b7 ZN |
240 | static u32 |
241 | render_ring_add_request(struct drm_device *dev, | |
ab6f8e32 | 242 | struct intel_ring_buffer *ring, |
ab6f8e32 | 243 | u32 flush_domains) |
62fdfeaf EA |
244 | { |
245 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6f392d54 CW |
246 | u32 seqno; |
247 | ||
248 | seqno = i915_gem_get_seqno(dev); | |
ca76482e ZW |
249 | |
250 | if (IS_GEN6(dev)) { | |
251 | BEGIN_LP_RING(6); | |
252 | OUT_RING(GFX_OP_PIPE_CONTROL | 3); | |
253 | OUT_RING(PIPE_CONTROL_QW_WRITE | | |
254 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH | | |
255 | PIPE_CONTROL_NOTIFY); | |
256 | OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); | |
257 | OUT_RING(seqno); | |
258 | OUT_RING(0); | |
259 | OUT_RING(0); | |
260 | ADVANCE_LP_RING(); | |
261 | } else if (HAS_PIPE_CONTROL(dev)) { | |
62fdfeaf EA |
262 | u32 scratch_addr = dev_priv->seqno_gfx_addr + 128; |
263 | ||
264 | /* | |
265 | * Workaround qword write incoherence by flushing the | |
266 | * PIPE_NOTIFY buffers out to memory before requesting | |
267 | * an interrupt. | |
268 | */ | |
269 | BEGIN_LP_RING(32); | |
270 | OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | | |
271 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); | |
272 | OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); | |
273 | OUT_RING(seqno); | |
274 | OUT_RING(0); | |
275 | PIPE_CONTROL_FLUSH(scratch_addr); | |
276 | scratch_addr += 128; /* write to separate cachelines */ | |
277 | PIPE_CONTROL_FLUSH(scratch_addr); | |
278 | scratch_addr += 128; | |
279 | PIPE_CONTROL_FLUSH(scratch_addr); | |
280 | scratch_addr += 128; | |
281 | PIPE_CONTROL_FLUSH(scratch_addr); | |
282 | scratch_addr += 128; | |
283 | PIPE_CONTROL_FLUSH(scratch_addr); | |
284 | scratch_addr += 128; | |
285 | PIPE_CONTROL_FLUSH(scratch_addr); | |
286 | OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | | |
287 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | | |
288 | PIPE_CONTROL_NOTIFY); | |
289 | OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); | |
290 | OUT_RING(seqno); | |
291 | OUT_RING(0); | |
292 | ADVANCE_LP_RING(); | |
293 | } else { | |
294 | BEGIN_LP_RING(4); | |
295 | OUT_RING(MI_STORE_DWORD_INDEX); | |
296 | OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
297 | OUT_RING(seqno); | |
298 | ||
299 | OUT_RING(MI_USER_INTERRUPT); | |
300 | ADVANCE_LP_RING(); | |
301 | } | |
302 | return seqno; | |
303 | } | |
304 | ||
8187a2b7 | 305 | static u32 |
f787a5f5 CW |
306 | render_ring_get_seqno(struct drm_device *dev, |
307 | struct intel_ring_buffer *ring) | |
8187a2b7 ZN |
308 | { |
309 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
310 | if (HAS_PIPE_CONTROL(dev)) | |
311 | return ((volatile u32 *)(dev_priv->seqno_page))[0]; | |
312 | else | |
313 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
314 | } | |
315 | ||
316 | static void | |
317 | render_ring_get_user_irq(struct drm_device *dev, | |
ab6f8e32 | 318 | struct intel_ring_buffer *ring) |
62fdfeaf EA |
319 | { |
320 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
321 | unsigned long irqflags; | |
322 | ||
323 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
8187a2b7 | 324 | if (dev->irq_enabled && (++ring->user_irq_refcount == 1)) { |
62fdfeaf EA |
325 | if (HAS_PCH_SPLIT(dev)) |
326 | ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY); | |
327 | else | |
328 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
329 | } | |
330 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | |
331 | } | |
332 | ||
8187a2b7 ZN |
333 | static void |
334 | render_ring_put_user_irq(struct drm_device *dev, | |
ab6f8e32 | 335 | struct intel_ring_buffer *ring) |
62fdfeaf EA |
336 | { |
337 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
338 | unsigned long irqflags; | |
339 | ||
340 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
8187a2b7 ZN |
341 | BUG_ON(dev->irq_enabled && ring->user_irq_refcount <= 0); |
342 | if (dev->irq_enabled && (--ring->user_irq_refcount == 0)) { | |
62fdfeaf EA |
343 | if (HAS_PCH_SPLIT(dev)) |
344 | ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY); | |
345 | else | |
346 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
347 | } | |
348 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | |
349 | } | |
350 | ||
447da187 DV |
351 | void intel_ring_setup_status_page(struct drm_device *dev, |
352 | struct intel_ring_buffer *ring) | |
8187a2b7 ZN |
353 | { |
354 | drm_i915_private_t *dev_priv = dev->dev_private; | |
355 | if (IS_GEN6(dev)) { | |
3d281d8c DV |
356 | I915_WRITE(RING_HWS_PGA_GEN6(ring->mmio_base), |
357 | ring->status_page.gfx_addr); | |
358 | I915_READ(RING_HWS_PGA_GEN6(ring->mmio_base)); /* posting read */ | |
8187a2b7 | 359 | } else { |
3d281d8c DV |
360 | I915_WRITE(RING_HWS_PGA(ring->mmio_base), |
361 | ring->status_page.gfx_addr); | |
362 | I915_READ(RING_HWS_PGA(ring->mmio_base)); /* posting read */ | |
8187a2b7 ZN |
363 | } |
364 | ||
365 | } | |
366 | ||
ab6f8e32 | 367 | static void |
d1b851fc ZN |
368 | bsd_ring_flush(struct drm_device *dev, |
369 | struct intel_ring_buffer *ring, | |
370 | u32 invalidate_domains, | |
371 | u32 flush_domains) | |
372 | { | |
be26a10b | 373 | intel_ring_begin(dev, ring, 2); |
d1b851fc ZN |
374 | intel_ring_emit(dev, ring, MI_FLUSH); |
375 | intel_ring_emit(dev, ring, MI_NOOP); | |
376 | intel_ring_advance(dev, ring); | |
377 | } | |
378 | ||
d1b851fc | 379 | static int init_bsd_ring(struct drm_device *dev, |
ab6f8e32 | 380 | struct intel_ring_buffer *ring) |
d1b851fc ZN |
381 | { |
382 | return init_ring_common(dev, ring); | |
383 | } | |
384 | ||
385 | static u32 | |
549f7365 CW |
386 | ring_add_request(struct drm_device *dev, |
387 | struct intel_ring_buffer *ring, | |
388 | u32 flush_domains) | |
d1b851fc ZN |
389 | { |
390 | u32 seqno; | |
6f392d54 CW |
391 | |
392 | seqno = i915_gem_get_seqno(dev); | |
393 | ||
d1b851fc ZN |
394 | intel_ring_begin(dev, ring, 4); |
395 | intel_ring_emit(dev, ring, MI_STORE_DWORD_INDEX); | |
396 | intel_ring_emit(dev, ring, | |
397 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
398 | intel_ring_emit(dev, ring, seqno); | |
399 | intel_ring_emit(dev, ring, MI_USER_INTERRUPT); | |
400 | intel_ring_advance(dev, ring); | |
401 | ||
402 | DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno); | |
403 | ||
404 | return seqno; | |
405 | } | |
406 | ||
d1b851fc ZN |
407 | static void |
408 | bsd_ring_get_user_irq(struct drm_device *dev, | |
ab6f8e32 | 409 | struct intel_ring_buffer *ring) |
d1b851fc ZN |
410 | { |
411 | /* do nothing */ | |
412 | } | |
413 | static void | |
414 | bsd_ring_put_user_irq(struct drm_device *dev, | |
ab6f8e32 | 415 | struct intel_ring_buffer *ring) |
d1b851fc ZN |
416 | { |
417 | /* do nothing */ | |
418 | } | |
419 | ||
420 | static u32 | |
549f7365 CW |
421 | ring_status_page_get_seqno(struct drm_device *dev, |
422 | struct intel_ring_buffer *ring) | |
d1b851fc ZN |
423 | { |
424 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
425 | } | |
426 | ||
427 | static int | |
549f7365 CW |
428 | ring_dispatch_gem_execbuffer(struct drm_device *dev, |
429 | struct intel_ring_buffer *ring, | |
430 | struct drm_i915_gem_execbuffer2 *exec, | |
431 | struct drm_clip_rect *cliprects, | |
432 | uint64_t exec_offset) | |
d1b851fc ZN |
433 | { |
434 | uint32_t exec_start; | |
435 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
436 | intel_ring_begin(dev, ring, 2); | |
437 | intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START | | |
438 | (2 << 6) | MI_BATCH_NON_SECURE_I965); | |
439 | intel_ring_emit(dev, ring, exec_start); | |
440 | intel_ring_advance(dev, ring); | |
441 | return 0; | |
442 | } | |
443 | ||
8187a2b7 ZN |
444 | static int |
445 | render_ring_dispatch_gem_execbuffer(struct drm_device *dev, | |
ab6f8e32 CW |
446 | struct intel_ring_buffer *ring, |
447 | struct drm_i915_gem_execbuffer2 *exec, | |
448 | struct drm_clip_rect *cliprects, | |
449 | uint64_t exec_offset) | |
62fdfeaf EA |
450 | { |
451 | drm_i915_private_t *dev_priv = dev->dev_private; | |
452 | int nbox = exec->num_cliprects; | |
453 | int i = 0, count; | |
454 | uint32_t exec_start, exec_len; | |
62fdfeaf EA |
455 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
456 | exec_len = (uint32_t) exec->batch_len; | |
457 | ||
6f392d54 | 458 | trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1); |
62fdfeaf EA |
459 | |
460 | count = nbox ? nbox : 1; | |
461 | ||
462 | for (i = 0; i < count; i++) { | |
463 | if (i < nbox) { | |
464 | int ret = i915_emit_box(dev, cliprects, i, | |
465 | exec->DR1, exec->DR4); | |
466 | if (ret) | |
467 | return ret; | |
468 | } | |
469 | ||
470 | if (IS_I830(dev) || IS_845G(dev)) { | |
8187a2b7 ZN |
471 | intel_ring_begin(dev, ring, 4); |
472 | intel_ring_emit(dev, ring, MI_BATCH_BUFFER); | |
473 | intel_ring_emit(dev, ring, | |
474 | exec_start | MI_BATCH_NON_SECURE); | |
475 | intel_ring_emit(dev, ring, exec_start + exec_len - 4); | |
476 | intel_ring_emit(dev, ring, 0); | |
62fdfeaf | 477 | } else { |
c7179667 | 478 | intel_ring_begin(dev, ring, 2); |
a6c45cf0 | 479 | if (INTEL_INFO(dev)->gen >= 4) { |
8187a2b7 ZN |
480 | intel_ring_emit(dev, ring, |
481 | MI_BATCH_BUFFER_START | (2 << 6) | |
482 | | MI_BATCH_NON_SECURE_I965); | |
483 | intel_ring_emit(dev, ring, exec_start); | |
62fdfeaf | 484 | } else { |
8187a2b7 ZN |
485 | intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START |
486 | | (2 << 6)); | |
487 | intel_ring_emit(dev, ring, exec_start | | |
488 | MI_BATCH_NON_SECURE); | |
62fdfeaf | 489 | } |
62fdfeaf | 490 | } |
8187a2b7 | 491 | intel_ring_advance(dev, ring); |
62fdfeaf EA |
492 | } |
493 | ||
f00a3ddf | 494 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
1cafd347 ZN |
495 | intel_ring_begin(dev, ring, 2); |
496 | intel_ring_emit(dev, ring, MI_FLUSH | | |
497 | MI_NO_WRITE_FLUSH | | |
498 | MI_INVALIDATE_ISP ); | |
499 | intel_ring_emit(dev, ring, MI_NOOP); | |
500 | intel_ring_advance(dev, ring); | |
501 | } | |
62fdfeaf | 502 | /* XXX breadcrumb */ |
1cafd347 | 503 | |
62fdfeaf EA |
504 | return 0; |
505 | } | |
506 | ||
8187a2b7 | 507 | static void cleanup_status_page(struct drm_device *dev, |
ab6f8e32 | 508 | struct intel_ring_buffer *ring) |
62fdfeaf EA |
509 | { |
510 | drm_i915_private_t *dev_priv = dev->dev_private; | |
511 | struct drm_gem_object *obj; | |
512 | struct drm_i915_gem_object *obj_priv; | |
513 | ||
8187a2b7 ZN |
514 | obj = ring->status_page.obj; |
515 | if (obj == NULL) | |
62fdfeaf | 516 | return; |
62fdfeaf EA |
517 | obj_priv = to_intel_bo(obj); |
518 | ||
519 | kunmap(obj_priv->pages[0]); | |
520 | i915_gem_object_unpin(obj); | |
521 | drm_gem_object_unreference(obj); | |
8187a2b7 | 522 | ring->status_page.obj = NULL; |
62fdfeaf EA |
523 | |
524 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); | |
62fdfeaf EA |
525 | } |
526 | ||
8187a2b7 | 527 | static int init_status_page(struct drm_device *dev, |
ab6f8e32 | 528 | struct intel_ring_buffer *ring) |
62fdfeaf EA |
529 | { |
530 | drm_i915_private_t *dev_priv = dev->dev_private; | |
531 | struct drm_gem_object *obj; | |
532 | struct drm_i915_gem_object *obj_priv; | |
533 | int ret; | |
534 | ||
62fdfeaf EA |
535 | obj = i915_gem_alloc_object(dev, 4096); |
536 | if (obj == NULL) { | |
537 | DRM_ERROR("Failed to allocate status page\n"); | |
538 | ret = -ENOMEM; | |
539 | goto err; | |
540 | } | |
541 | obj_priv = to_intel_bo(obj); | |
542 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
543 | ||
544 | ret = i915_gem_object_pin(obj, 4096); | |
545 | if (ret != 0) { | |
62fdfeaf EA |
546 | goto err_unref; |
547 | } | |
548 | ||
8187a2b7 ZN |
549 | ring->status_page.gfx_addr = obj_priv->gtt_offset; |
550 | ring->status_page.page_addr = kmap(obj_priv->pages[0]); | |
551 | if (ring->status_page.page_addr == NULL) { | |
62fdfeaf | 552 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
62fdfeaf EA |
553 | goto err_unpin; |
554 | } | |
8187a2b7 ZN |
555 | ring->status_page.obj = obj; |
556 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 557 | |
447da187 | 558 | intel_ring_setup_status_page(dev, ring); |
8187a2b7 ZN |
559 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
560 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
561 | |
562 | return 0; | |
563 | ||
564 | err_unpin: | |
565 | i915_gem_object_unpin(obj); | |
566 | err_unref: | |
567 | drm_gem_object_unreference(obj); | |
568 | err: | |
8187a2b7 | 569 | return ret; |
62fdfeaf EA |
570 | } |
571 | ||
8187a2b7 | 572 | int intel_init_ring_buffer(struct drm_device *dev, |
ab6f8e32 | 573 | struct intel_ring_buffer *ring) |
62fdfeaf | 574 | { |
870e86dd | 575 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 ZN |
576 | struct drm_i915_gem_object *obj_priv; |
577 | struct drm_gem_object *obj; | |
dd785e35 CW |
578 | int ret; |
579 | ||
8187a2b7 | 580 | ring->dev = dev; |
23bc5982 CW |
581 | INIT_LIST_HEAD(&ring->active_list); |
582 | INIT_LIST_HEAD(&ring->request_list); | |
62fdfeaf | 583 | |
8187a2b7 ZN |
584 | if (I915_NEED_GFX_HWS(dev)) { |
585 | ret = init_status_page(dev, ring); | |
586 | if (ret) | |
587 | return ret; | |
588 | } | |
62fdfeaf | 589 | |
8187a2b7 | 590 | obj = i915_gem_alloc_object(dev, ring->size); |
62fdfeaf EA |
591 | if (obj == NULL) { |
592 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 593 | ret = -ENOMEM; |
dd785e35 | 594 | goto err_hws; |
62fdfeaf | 595 | } |
62fdfeaf | 596 | |
8187a2b7 ZN |
597 | ring->gem_object = obj; |
598 | ||
a9db5c8f | 599 | ret = i915_gem_object_pin(obj, PAGE_SIZE); |
dd785e35 CW |
600 | if (ret) |
601 | goto err_unref; | |
62fdfeaf | 602 | |
8187a2b7 ZN |
603 | obj_priv = to_intel_bo(obj); |
604 | ring->map.size = ring->size; | |
62fdfeaf | 605 | ring->map.offset = dev->agp->base + obj_priv->gtt_offset; |
62fdfeaf EA |
606 | ring->map.type = 0; |
607 | ring->map.flags = 0; | |
608 | ring->map.mtrr = 0; | |
609 | ||
610 | drm_core_ioremap_wc(&ring->map, dev); | |
611 | if (ring->map.handle == NULL) { | |
612 | DRM_ERROR("Failed to map ringbuffer.\n"); | |
8187a2b7 | 613 | ret = -EINVAL; |
dd785e35 | 614 | goto err_unpin; |
62fdfeaf EA |
615 | } |
616 | ||
8187a2b7 ZN |
617 | ring->virtual_start = ring->map.handle; |
618 | ret = ring->init(dev, ring); | |
dd785e35 CW |
619 | if (ret) |
620 | goto err_unmap; | |
62fdfeaf | 621 | |
62fdfeaf EA |
622 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
623 | i915_kernel_lost_context(dev); | |
624 | else { | |
570ef608 | 625 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
870e86dd | 626 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
62fdfeaf EA |
627 | ring->space = ring->head - (ring->tail + 8); |
628 | if (ring->space < 0) | |
8187a2b7 | 629 | ring->space += ring->size; |
62fdfeaf | 630 | } |
8187a2b7 | 631 | return ret; |
dd785e35 CW |
632 | |
633 | err_unmap: | |
634 | drm_core_ioremapfree(&ring->map, dev); | |
635 | err_unpin: | |
636 | i915_gem_object_unpin(obj); | |
637 | err_unref: | |
638 | drm_gem_object_unreference(obj); | |
639 | ring->gem_object = NULL; | |
640 | err_hws: | |
8187a2b7 ZN |
641 | cleanup_status_page(dev, ring); |
642 | return ret; | |
62fdfeaf EA |
643 | } |
644 | ||
8187a2b7 | 645 | void intel_cleanup_ring_buffer(struct drm_device *dev, |
ab6f8e32 | 646 | struct intel_ring_buffer *ring) |
62fdfeaf | 647 | { |
8187a2b7 | 648 | if (ring->gem_object == NULL) |
62fdfeaf EA |
649 | return; |
650 | ||
8187a2b7 | 651 | drm_core_ioremapfree(&ring->map, dev); |
62fdfeaf | 652 | |
8187a2b7 ZN |
653 | i915_gem_object_unpin(ring->gem_object); |
654 | drm_gem_object_unreference(ring->gem_object); | |
655 | ring->gem_object = NULL; | |
656 | cleanup_status_page(dev, ring); | |
62fdfeaf EA |
657 | } |
658 | ||
ab6f8e32 CW |
659 | static int intel_wrap_ring_buffer(struct drm_device *dev, |
660 | struct intel_ring_buffer *ring) | |
62fdfeaf | 661 | { |
8187a2b7 | 662 | unsigned int *virt; |
62fdfeaf | 663 | int rem; |
8187a2b7 | 664 | rem = ring->size - ring->tail; |
62fdfeaf | 665 | |
8187a2b7 ZN |
666 | if (ring->space < rem) { |
667 | int ret = intel_wait_ring_buffer(dev, ring, rem); | |
62fdfeaf EA |
668 | if (ret) |
669 | return ret; | |
670 | } | |
62fdfeaf | 671 | |
8187a2b7 | 672 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
1741dd4a CW |
673 | rem /= 8; |
674 | while (rem--) { | |
62fdfeaf | 675 | *virt++ = MI_NOOP; |
1741dd4a CW |
676 | *virt++ = MI_NOOP; |
677 | } | |
62fdfeaf | 678 | |
8187a2b7 | 679 | ring->tail = 0; |
43ed340a | 680 | ring->space = ring->head - 8; |
62fdfeaf EA |
681 | |
682 | return 0; | |
683 | } | |
684 | ||
8187a2b7 | 685 | int intel_wait_ring_buffer(struct drm_device *dev, |
ab6f8e32 | 686 | struct intel_ring_buffer *ring, int n) |
62fdfeaf | 687 | { |
8187a2b7 | 688 | unsigned long end; |
570ef608 | 689 | drm_i915_private_t *dev_priv = dev->dev_private; |
62fdfeaf EA |
690 | |
691 | trace_i915_ring_wait_begin (dev); | |
8187a2b7 ZN |
692 | end = jiffies + 3 * HZ; |
693 | do { | |
570ef608 | 694 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
62fdfeaf EA |
695 | ring->space = ring->head - (ring->tail + 8); |
696 | if (ring->space < 0) | |
8187a2b7 | 697 | ring->space += ring->size; |
62fdfeaf EA |
698 | if (ring->space >= n) { |
699 | trace_i915_ring_wait_end (dev); | |
700 | return 0; | |
701 | } | |
702 | ||
703 | if (dev->primary->master) { | |
704 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
705 | if (master_priv->sarea_priv) | |
706 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
707 | } | |
d1b851fc | 708 | |
e60a0b10 | 709 | msleep(1); |
8187a2b7 ZN |
710 | } while (!time_after(jiffies, end)); |
711 | trace_i915_ring_wait_end (dev); | |
712 | return -EBUSY; | |
713 | } | |
62fdfeaf | 714 | |
8187a2b7 | 715 | void intel_ring_begin(struct drm_device *dev, |
ab6f8e32 CW |
716 | struct intel_ring_buffer *ring, |
717 | int num_dwords) | |
8187a2b7 | 718 | { |
be26a10b | 719 | int n = 4*num_dwords; |
8187a2b7 ZN |
720 | if (unlikely(ring->tail + n > ring->size)) |
721 | intel_wrap_ring_buffer(dev, ring); | |
722 | if (unlikely(ring->space < n)) | |
723 | intel_wait_ring_buffer(dev, ring, n); | |
d97ed339 CW |
724 | |
725 | ring->space -= n; | |
8187a2b7 | 726 | } |
62fdfeaf | 727 | |
8187a2b7 | 728 | void intel_ring_advance(struct drm_device *dev, |
ab6f8e32 | 729 | struct intel_ring_buffer *ring) |
8187a2b7 | 730 | { |
d97ed339 | 731 | ring->tail &= ring->size - 1; |
870e86dd | 732 | ring->set_tail(dev, ring, ring->tail); |
8187a2b7 | 733 | } |
62fdfeaf | 734 | |
e070868e | 735 | static const struct intel_ring_buffer render_ring = { |
8187a2b7 | 736 | .name = "render ring", |
9220434a | 737 | .id = RING_RENDER, |
333e9fe9 | 738 | .mmio_base = RENDER_RING_BASE, |
8187a2b7 | 739 | .size = 32 * PAGE_SIZE, |
8187a2b7 | 740 | .init = init_render_ring, |
870e86dd | 741 | .set_tail = ring_set_tail, |
8187a2b7 ZN |
742 | .flush = render_ring_flush, |
743 | .add_request = render_ring_add_request, | |
f787a5f5 | 744 | .get_seqno = render_ring_get_seqno, |
8187a2b7 ZN |
745 | .user_irq_get = render_ring_get_user_irq, |
746 | .user_irq_put = render_ring_put_user_irq, | |
747 | .dispatch_gem_execbuffer = render_ring_dispatch_gem_execbuffer, | |
8187a2b7 | 748 | }; |
d1b851fc ZN |
749 | |
750 | /* ring buffer for bit-stream decoder */ | |
751 | ||
e070868e | 752 | static const struct intel_ring_buffer bsd_ring = { |
d1b851fc | 753 | .name = "bsd ring", |
9220434a | 754 | .id = RING_BSD, |
333e9fe9 | 755 | .mmio_base = BSD_RING_BASE, |
d1b851fc | 756 | .size = 32 * PAGE_SIZE, |
d1b851fc | 757 | .init = init_bsd_ring, |
870e86dd | 758 | .set_tail = ring_set_tail, |
d1b851fc | 759 | .flush = bsd_ring_flush, |
549f7365 CW |
760 | .add_request = ring_add_request, |
761 | .get_seqno = ring_status_page_get_seqno, | |
d1b851fc ZN |
762 | .user_irq_get = bsd_ring_get_user_irq, |
763 | .user_irq_put = bsd_ring_put_user_irq, | |
549f7365 | 764 | .dispatch_gem_execbuffer = ring_dispatch_gem_execbuffer, |
d1b851fc | 765 | }; |
5c1143bb | 766 | |
881f47b6 | 767 | |
ab6f8e32 CW |
768 | static void gen6_bsd_ring_set_tail(struct drm_device *dev, |
769 | struct intel_ring_buffer *ring, | |
770 | u32 value) | |
881f47b6 XH |
771 | { |
772 | drm_i915_private_t *dev_priv = dev->dev_private; | |
773 | ||
774 | /* Every tail move must follow the sequence below */ | |
775 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, | |
776 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
777 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); | |
778 | I915_WRITE(GEN6_BSD_RNCID, 0x0); | |
779 | ||
780 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & | |
781 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, | |
782 | 50)) | |
783 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); | |
784 | ||
870e86dd | 785 | I915_WRITE_TAIL(ring, value); |
881f47b6 XH |
786 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
787 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
788 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); | |
789 | } | |
790 | ||
549f7365 CW |
791 | static void gen6_ring_flush(struct drm_device *dev, |
792 | struct intel_ring_buffer *ring, | |
793 | u32 invalidate_domains, | |
794 | u32 flush_domains) | |
881f47b6 XH |
795 | { |
796 | intel_ring_begin(dev, ring, 4); | |
797 | intel_ring_emit(dev, ring, MI_FLUSH_DW); | |
798 | intel_ring_emit(dev, ring, 0); | |
799 | intel_ring_emit(dev, ring, 0); | |
800 | intel_ring_emit(dev, ring, 0); | |
801 | intel_ring_advance(dev, ring); | |
802 | } | |
803 | ||
804 | static int | |
549f7365 CW |
805 | gen6_ring_dispatch_gem_execbuffer(struct drm_device *dev, |
806 | struct intel_ring_buffer *ring, | |
807 | struct drm_i915_gem_execbuffer2 *exec, | |
808 | struct drm_clip_rect *cliprects, | |
809 | uint64_t exec_offset) | |
881f47b6 XH |
810 | { |
811 | uint32_t exec_start; | |
ab6f8e32 | 812 | |
881f47b6 | 813 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
ab6f8e32 | 814 | |
881f47b6 | 815 | intel_ring_begin(dev, ring, 2); |
ab6f8e32 CW |
816 | intel_ring_emit(dev, ring, |
817 | MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); | |
818 | /* bit0-7 is the length on GEN6+ */ | |
881f47b6 XH |
819 | intel_ring_emit(dev, ring, exec_start); |
820 | intel_ring_advance(dev, ring); | |
ab6f8e32 | 821 | |
881f47b6 XH |
822 | return 0; |
823 | } | |
824 | ||
825 | /* ring buffer for Video Codec for Gen6+ */ | |
e070868e | 826 | static const struct intel_ring_buffer gen6_bsd_ring = { |
881f47b6 XH |
827 | .name = "gen6 bsd ring", |
828 | .id = RING_BSD, | |
333e9fe9 | 829 | .mmio_base = GEN6_BSD_RING_BASE, |
881f47b6 | 830 | .size = 32 * PAGE_SIZE, |
881f47b6 | 831 | .init = init_bsd_ring, |
881f47b6 | 832 | .set_tail = gen6_bsd_ring_set_tail, |
549f7365 CW |
833 | .flush = gen6_ring_flush, |
834 | .add_request = ring_add_request, | |
835 | .get_seqno = ring_status_page_get_seqno, | |
881f47b6 XH |
836 | .user_irq_get = bsd_ring_get_user_irq, |
837 | .user_irq_put = bsd_ring_put_user_irq, | |
549f7365 CW |
838 | .dispatch_gem_execbuffer = gen6_ring_dispatch_gem_execbuffer, |
839 | }; | |
840 | ||
841 | /* Blitter support (SandyBridge+) */ | |
842 | ||
843 | static void | |
844 | blt_ring_get_user_irq(struct drm_device *dev, | |
845 | struct intel_ring_buffer *ring) | |
846 | { | |
847 | /* do nothing */ | |
848 | } | |
849 | static void | |
850 | blt_ring_put_user_irq(struct drm_device *dev, | |
851 | struct intel_ring_buffer *ring) | |
852 | { | |
853 | /* do nothing */ | |
854 | } | |
855 | ||
856 | static const struct intel_ring_buffer gen6_blt_ring = { | |
857 | .name = "blt ring", | |
858 | .id = RING_BLT, | |
859 | .mmio_base = BLT_RING_BASE, | |
860 | .size = 32 * PAGE_SIZE, | |
861 | .init = init_ring_common, | |
862 | .set_tail = ring_set_tail, | |
863 | .flush = gen6_ring_flush, | |
864 | .add_request = ring_add_request, | |
865 | .get_seqno = ring_status_page_get_seqno, | |
866 | .user_irq_get = blt_ring_get_user_irq, | |
867 | .user_irq_put = blt_ring_put_user_irq, | |
868 | .dispatch_gem_execbuffer = gen6_ring_dispatch_gem_execbuffer, | |
881f47b6 XH |
869 | }; |
870 | ||
5c1143bb XH |
871 | int intel_init_render_ring_buffer(struct drm_device *dev) |
872 | { | |
873 | drm_i915_private_t *dev_priv = dev->dev_private; | |
874 | ||
875 | dev_priv->render_ring = render_ring; | |
876 | ||
877 | if (!I915_NEED_GFX_HWS(dev)) { | |
878 | dev_priv->render_ring.status_page.page_addr | |
879 | = dev_priv->status_page_dmah->vaddr; | |
880 | memset(dev_priv->render_ring.status_page.page_addr, | |
881 | 0, PAGE_SIZE); | |
882 | } | |
883 | ||
884 | return intel_init_ring_buffer(dev, &dev_priv->render_ring); | |
885 | } | |
886 | ||
887 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
888 | { | |
889 | drm_i915_private_t *dev_priv = dev->dev_private; | |
890 | ||
881f47b6 XH |
891 | if (IS_GEN6(dev)) |
892 | dev_priv->bsd_ring = gen6_bsd_ring; | |
893 | else | |
894 | dev_priv->bsd_ring = bsd_ring; | |
5c1143bb XH |
895 | |
896 | return intel_init_ring_buffer(dev, &dev_priv->bsd_ring); | |
897 | } | |
549f7365 CW |
898 | |
899 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
900 | { | |
901 | drm_i915_private_t *dev_priv = dev->dev_private; | |
902 | ||
903 | dev_priv->blt_ring = gen6_blt_ring; | |
904 | ||
905 | return intel_init_ring_buffer(dev, &dev_priv->blt_ring); | |
906 | } |