Commit | Line | Data |
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8187a2b7 ZN |
1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ | |
3 | ||
44e895a8 | 4 | #include <linux/hashtable.h> |
06fbca71 | 5 | #include "i915_gem_batch_pool.h" |
44e895a8 BV |
6 | |
7 | #define I915_CMD_HASH_ORDER 9 | |
8 | ||
4712274c OM |
9 | /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, |
10 | * but keeps the logic simple. Indeed, the whole purpose of this macro is just | |
11 | * to give some inclination as to some of the magic values used in the various | |
12 | * workarounds! | |
13 | */ | |
14 | #define CACHELINE_BYTES 64 | |
17ee950d | 15 | #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t)) |
4712274c | 16 | |
633cf8f5 VS |
17 | /* |
18 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" | |
19 | * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" | |
20 | * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" | |
21 | * | |
22 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same | |
23 | * cacheline, the Head Pointer must not be greater than the Tail | |
24 | * Pointer." | |
25 | */ | |
26 | #define I915_RING_FREE_SPACE 64 | |
27 | ||
8187a2b7 | 28 | struct intel_hw_status_page { |
4225d0f2 | 29 | u32 *page_addr; |
8187a2b7 | 30 | unsigned int gfx_addr; |
05394f39 | 31 | struct drm_i915_gem_object *obj; |
8187a2b7 ZN |
32 | }; |
33 | ||
b7287d80 BW |
34 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
35 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) | |
cae5852d | 36 | |
b7287d80 BW |
37 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
38 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) | |
cae5852d | 39 | |
b7287d80 BW |
40 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
41 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) | |
cae5852d | 42 | |
b7287d80 BW |
43 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
44 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) | |
cae5852d | 45 | |
b7287d80 BW |
46 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
47 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) | |
870e86dd | 48 | |
e9fea574 | 49 | #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base)) |
9991ae78 | 50 | #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val) |
e9fea574 | 51 | |
3e78998a BW |
52 | /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to |
53 | * do the writes, and that must have qw aligned offsets, simply pretend it's 8b. | |
54 | */ | |
55 | #define i915_semaphore_seqno_size sizeof(uint64_t) | |
56 | #define GEN8_SIGNAL_OFFSET(__ring, to) \ | |
57 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ | |
666796da | 58 | ((__ring)->id * I915_NUM_ENGINES * i915_semaphore_seqno_size) + \ |
3e78998a BW |
59 | (i915_semaphore_seqno_size * (to))) |
60 | ||
61 | #define GEN8_WAIT_OFFSET(__ring, from) \ | |
62 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ | |
666796da | 63 | ((from) * I915_NUM_ENGINES * i915_semaphore_seqno_size) + \ |
3e78998a BW |
64 | (i915_semaphore_seqno_size * (__ring)->id)) |
65 | ||
e2f80391 | 66 | #define GEN8_RING_SEMAPHORE_INIT(e) do { \ |
3e78998a BW |
67 | if (!dev_priv->semaphore_obj) { \ |
68 | break; \ | |
69 | } \ | |
e2f80391 TU |
70 | (e)->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET((e), RCS); \ |
71 | (e)->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET((e), VCS); \ | |
72 | (e)->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET((e), BCS); \ | |
73 | (e)->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET((e), VECS); \ | |
74 | (e)->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET((e), VCS2); \ | |
75 | (e)->semaphore.signal_ggtt[(e)->id] = MI_SEMAPHORE_SYNC_INVALID; \ | |
3e78998a BW |
76 | } while(0) |
77 | ||
f2f4d82f | 78 | enum intel_ring_hangcheck_action { |
da661464 | 79 | HANGCHECK_IDLE = 0, |
f2f4d82f JN |
80 | HANGCHECK_WAIT, |
81 | HANGCHECK_ACTIVE, | |
82 | HANGCHECK_KICK, | |
83 | HANGCHECK_HUNG, | |
84 | }; | |
ad8beaea | 85 | |
b6b0fac0 MK |
86 | #define HANGCHECK_SCORE_RING_HUNG 31 |
87 | ||
92cab734 | 88 | struct intel_ring_hangcheck { |
50877445 | 89 | u64 acthd; |
92cab734 | 90 | u32 seqno; |
05407ff8 | 91 | int score; |
ad8beaea | 92 | enum intel_ring_hangcheck_action action; |
4be17381 | 93 | int deadlock; |
61642ff0 | 94 | u32 instdone[I915_NUM_INSTDONE_REG]; |
92cab734 MK |
95 | }; |
96 | ||
8ee14975 OM |
97 | struct intel_ringbuffer { |
98 | struct drm_i915_gem_object *obj; | |
99 | void __iomem *virtual_start; | |
0eb973d3 | 100 | struct i915_vma *vma; |
8ee14975 | 101 | |
4a570db5 | 102 | struct intel_engine_cs *engine; |
608c1a52 | 103 | struct list_head link; |
0c7dd53b | 104 | |
8ee14975 OM |
105 | u32 head; |
106 | u32 tail; | |
107 | int space; | |
108 | int size; | |
109 | int effective_size; | |
29b1b415 JH |
110 | int reserved_size; |
111 | int reserved_tail; | |
112 | bool reserved_in_use; | |
8ee14975 OM |
113 | |
114 | /** We track the position of the requests in the ring buffer, and | |
115 | * when each is retired we increment last_retired_head as the GPU | |
116 | * must have finished processing the request and so we know we | |
117 | * can advance the ringbuffer up to that position. | |
118 | * | |
119 | * last_retired_head is set to -1 after the value is consumed so | |
120 | * we can detect new retirements. | |
121 | */ | |
122 | u32 last_retired_head; | |
123 | }; | |
124 | ||
21076372 | 125 | struct intel_context; |
361b027b | 126 | struct drm_i915_reg_table; |
21076372 | 127 | |
17ee950d AS |
128 | /* |
129 | * we use a single page to load ctx workarounds so all of these | |
130 | * values are referred in terms of dwords | |
131 | * | |
132 | * struct i915_wa_ctx_bb: | |
133 | * offset: specifies batch starting position, also helpful in case | |
134 | * if we want to have multiple batches at different offsets based on | |
135 | * some criteria. It is not a requirement at the moment but provides | |
136 | * an option for future use. | |
137 | * size: size of the batch in DWORDS | |
138 | */ | |
139 | struct i915_ctx_workarounds { | |
140 | struct i915_wa_ctx_bb { | |
141 | u32 offset; | |
142 | u32 size; | |
143 | } indirect_ctx, per_ctx; | |
144 | struct drm_i915_gem_object *obj; | |
145 | }; | |
146 | ||
a4872ba6 | 147 | struct intel_engine_cs { |
8187a2b7 | 148 | const char *name; |
117897f4 | 149 | enum intel_engine_id { |
de1add36 | 150 | RCS = 0, |
96154f2f | 151 | BCS, |
de1add36 TU |
152 | VCS, |
153 | VCS2, /* Keep instances of the same type engine together. */ | |
154 | VECS | |
9220434a | 155 | } id; |
666796da | 156 | #define I915_NUM_ENGINES 5 |
de1add36 | 157 | #define _VCS(n) (VCS + (n)) |
426960be | 158 | unsigned int exec_id; |
397097b0 | 159 | unsigned int guc_id; |
333e9fe9 | 160 | u32 mmio_base; |
8187a2b7 | 161 | struct drm_device *dev; |
8ee14975 | 162 | struct intel_ringbuffer *buffer; |
608c1a52 | 163 | struct list_head buffers; |
8187a2b7 | 164 | |
06fbca71 CW |
165 | /* |
166 | * A pool of objects to use as shadow copies of client batch buffers | |
167 | * when the command parser is enabled. Prevents the client from | |
168 | * modifying the batch contents after software parsing. | |
169 | */ | |
170 | struct i915_gem_batch_pool batch_pool; | |
171 | ||
8187a2b7 | 172 | struct intel_hw_status_page status_page; |
17ee950d | 173 | struct i915_ctx_workarounds wa_ctx; |
8187a2b7 | 174 | |
c7113cc3 | 175 | unsigned irq_refcount; /* protected by dev_priv->irq_lock */ |
6a848ccb | 176 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
581c26e8 | 177 | struct drm_i915_gem_request *trace_irq_req; |
a4872ba6 OM |
178 | bool __must_check (*irq_get)(struct intel_engine_cs *ring); |
179 | void (*irq_put)(struct intel_engine_cs *ring); | |
8187a2b7 | 180 | |
ecfe00d8 | 181 | int (*init_hw)(struct intel_engine_cs *ring); |
8187a2b7 | 182 | |
8753181e | 183 | int (*init_context)(struct drm_i915_gem_request *req); |
86d7f238 | 184 | |
a4872ba6 | 185 | void (*write_tail)(struct intel_engine_cs *ring, |
297b0c5b | 186 | u32 value); |
a84c3ae1 | 187 | int __must_check (*flush)(struct drm_i915_gem_request *req, |
b72f3acb CW |
188 | u32 invalidate_domains, |
189 | u32 flush_domains); | |
ee044a88 | 190 | int (*add_request)(struct drm_i915_gem_request *req); |
b2eadbc8 CW |
191 | /* Some chipsets are not quite as coherent as advertised and need |
192 | * an expensive kick to force a true read of the up-to-date seqno. | |
193 | * However, the up-to-date seqno is not always required and the last | |
194 | * seen value is good enough. Note that the seqno will always be | |
195 | * monotonic, even if not coherent. | |
196 | */ | |
a4872ba6 | 197 | u32 (*get_seqno)(struct intel_engine_cs *ring, |
b2eadbc8 | 198 | bool lazy_coherency); |
a4872ba6 | 199 | void (*set_seqno)(struct intel_engine_cs *ring, |
b70ec5bf | 200 | u32 seqno); |
53fddaf7 | 201 | int (*dispatch_execbuffer)(struct drm_i915_gem_request *req, |
9bcb144c | 202 | u64 offset, u32 length, |
8e004efc | 203 | unsigned dispatch_flags); |
d7d4eedd | 204 | #define I915_DISPATCH_SECURE 0x1 |
b45305fc | 205 | #define I915_DISPATCH_PINNED 0x2 |
919032ec | 206 | #define I915_DISPATCH_RS 0x4 |
a4872ba6 | 207 | void (*cleanup)(struct intel_engine_cs *ring); |
ebc348b2 | 208 | |
3e78998a BW |
209 | /* GEN8 signal/wait table - never trust comments! |
210 | * signal to signal to signal to signal to signal to | |
211 | * RCS VCS BCS VECS VCS2 | |
212 | * -------------------------------------------------------------------- | |
213 | * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) | | |
214 | * |------------------------------------------------------------------- | |
215 | * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) | | |
216 | * |------------------------------------------------------------------- | |
217 | * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) | | |
218 | * |------------------------------------------------------------------- | |
219 | * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) | | |
220 | * |------------------------------------------------------------------- | |
221 | * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) | | |
222 | * |------------------------------------------------------------------- | |
223 | * | |
224 | * Generalization: | |
225 | * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id) | |
226 | * ie. transpose of g(x, y) | |
227 | * | |
228 | * sync from sync from sync from sync from sync from | |
229 | * RCS VCS BCS VECS VCS2 | |
230 | * -------------------------------------------------------------------- | |
231 | * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) | | |
232 | * |------------------------------------------------------------------- | |
233 | * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) | | |
234 | * |------------------------------------------------------------------- | |
235 | * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) | | |
236 | * |------------------------------------------------------------------- | |
237 | * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) | | |
238 | * |------------------------------------------------------------------- | |
239 | * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) | | |
240 | * |------------------------------------------------------------------- | |
241 | * | |
242 | * Generalization: | |
243 | * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id) | |
244 | * ie. transpose of f(x, y) | |
245 | */ | |
ebc348b2 | 246 | struct { |
666796da | 247 | u32 sync_seqno[I915_NUM_ENGINES-1]; |
78325f2d | 248 | |
3e78998a BW |
249 | union { |
250 | struct { | |
251 | /* our mbox written by others */ | |
666796da | 252 | u32 wait[I915_NUM_ENGINES]; |
3e78998a | 253 | /* mboxes this ring signals to */ |
666796da | 254 | i915_reg_t signal[I915_NUM_ENGINES]; |
3e78998a | 255 | } mbox; |
666796da | 256 | u64 signal_ggtt[I915_NUM_ENGINES]; |
3e78998a | 257 | }; |
78325f2d BW |
258 | |
259 | /* AKA wait() */ | |
599d924c JH |
260 | int (*sync_to)(struct drm_i915_gem_request *to_req, |
261 | struct intel_engine_cs *from, | |
78325f2d | 262 | u32 seqno); |
f7169687 | 263 | int (*signal)(struct drm_i915_gem_request *signaller_req, |
024a43e1 BW |
264 | /* num_dwords needed by caller */ |
265 | unsigned int num_dwords); | |
ebc348b2 | 266 | } semaphore; |
ad776f8b | 267 | |
4da46e1e | 268 | /* Execlists */ |
acdd884a MT |
269 | spinlock_t execlist_lock; |
270 | struct list_head execlist_queue; | |
c86ee3a9 | 271 | struct list_head execlist_retired_req_list; |
c6a2ac71 TU |
272 | unsigned int next_context_status_buffer; |
273 | unsigned int idle_lite_restore_wa; | |
ca82580c TU |
274 | bool disable_lite_restore_wa; |
275 | u32 ctx_desc_template; | |
73d477f6 | 276 | u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */ |
c4e76638 | 277 | int (*emit_request)(struct drm_i915_gem_request *request); |
7deb4d39 | 278 | int (*emit_flush)(struct drm_i915_gem_request *request, |
4712274c OM |
279 | u32 invalidate_domains, |
280 | u32 flush_domains); | |
be795fc1 | 281 | int (*emit_bb_start)(struct drm_i915_gem_request *req, |
8e004efc | 282 | u64 offset, unsigned dispatch_flags); |
4da46e1e | 283 | |
8187a2b7 ZN |
284 | /** |
285 | * List of objects currently involved in rendering from the | |
286 | * ringbuffer. | |
287 | * | |
288 | * Includes buffers having the contents of their GPU caches | |
97b2a6a1 | 289 | * flushed, not necessarily primitives. last_read_req |
8187a2b7 ZN |
290 | * represents when the rendering involved will be completed. |
291 | * | |
292 | * A reference is held on the buffer while on this list. | |
293 | */ | |
294 | struct list_head active_list; | |
295 | ||
296 | /** | |
297 | * List of breadcrumbs associated with GPU requests currently | |
298 | * outstanding. | |
299 | */ | |
300 | struct list_head request_list; | |
301 | ||
94f7bbe1 TE |
302 | /** |
303 | * Seqno of request most recently submitted to request_list. | |
304 | * Used exclusively by hang checker to avoid grabbing lock while | |
305 | * inspecting request list. | |
306 | */ | |
307 | u32 last_submitted_seqno; | |
308 | ||
cc889e0f | 309 | bool gpu_caches_dirty; |
a56ba56c | 310 | |
8187a2b7 | 311 | wait_queue_head_t irq_queue; |
8d19215b | 312 | |
273497e5 | 313 | struct intel_context *last_context; |
40521054 | 314 | |
92cab734 MK |
315 | struct intel_ring_hangcheck hangcheck; |
316 | ||
0d1aacac CW |
317 | struct { |
318 | struct drm_i915_gem_object *obj; | |
319 | u32 gtt_offset; | |
320 | volatile u32 *cpu_page; | |
321 | } scratch; | |
351e3db2 | 322 | |
44e895a8 BV |
323 | bool needs_cmd_parser; |
324 | ||
351e3db2 | 325 | /* |
44e895a8 | 326 | * Table of commands the command parser needs to know about |
351e3db2 BV |
327 | * for this ring. |
328 | */ | |
44e895a8 | 329 | DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER); |
351e3db2 BV |
330 | |
331 | /* | |
332 | * Table of registers allowed in commands that read/write registers. | |
333 | */ | |
361b027b JJ |
334 | const struct drm_i915_reg_table *reg_tables; |
335 | int reg_table_count; | |
351e3db2 BV |
336 | |
337 | /* | |
338 | * Returns the bitmask for the length field of the specified command. | |
339 | * Return 0 for an unrecognized/invalid command. | |
340 | * | |
341 | * If the command parser finds an entry for a command in the ring's | |
342 | * cmd_tables, it gets the command's length based on the table entry. | |
343 | * If not, it calls this function to determine the per-ring length field | |
344 | * encoding for the command (i.e. certain opcode ranges use certain bits | |
345 | * to encode the command length in the header). | |
346 | */ | |
347 | u32 (*get_cmd_length_mask)(u32 cmd_header); | |
8187a2b7 ZN |
348 | }; |
349 | ||
b0366a54 | 350 | static inline bool |
117897f4 | 351 | intel_engine_initialized(struct intel_engine_cs *engine) |
b0366a54 | 352 | { |
0bc40be8 | 353 | return engine->dev != NULL; |
b0366a54 | 354 | } |
b4519513 | 355 | |
96154f2f | 356 | static inline unsigned |
666796da | 357 | intel_engine_flag(struct intel_engine_cs *engine) |
96154f2f | 358 | { |
0bc40be8 | 359 | return 1 << engine->id; |
96154f2f DV |
360 | } |
361 | ||
1ec14ad3 | 362 | static inline u32 |
0bc40be8 | 363 | intel_ring_sync_index(struct intel_engine_cs *engine, |
a4872ba6 | 364 | struct intel_engine_cs *other) |
1ec14ad3 CW |
365 | { |
366 | int idx; | |
367 | ||
368 | /* | |
ddd4dbc6 RV |
369 | * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2; |
370 | * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs; | |
371 | * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs; | |
372 | * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs; | |
373 | * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs; | |
1ec14ad3 CW |
374 | */ |
375 | ||
0bc40be8 | 376 | idx = (other - engine) - 1; |
1ec14ad3 | 377 | if (idx < 0) |
666796da | 378 | idx += I915_NUM_ENGINES; |
1ec14ad3 CW |
379 | |
380 | return idx; | |
381 | } | |
382 | ||
319404df | 383 | static inline void |
0bc40be8 | 384 | intel_flush_status_page(struct intel_engine_cs *engine, int reg) |
319404df | 385 | { |
0bc40be8 | 386 | drm_clflush_virt_range(&engine->status_page.page_addr[reg], |
319404df ID |
387 | sizeof(uint32_t)); |
388 | } | |
389 | ||
8187a2b7 | 390 | static inline u32 |
0bc40be8 | 391 | intel_read_status_page(struct intel_engine_cs *engine, |
78501eac | 392 | int reg) |
8187a2b7 | 393 | { |
4225d0f2 DV |
394 | /* Ensure that the compiler doesn't optimize away the load. */ |
395 | barrier(); | |
0bc40be8 | 396 | return engine->status_page.page_addr[reg]; |
8187a2b7 ZN |
397 | } |
398 | ||
b70ec5bf | 399 | static inline void |
0bc40be8 | 400 | intel_write_status_page(struct intel_engine_cs *engine, |
b70ec5bf MK |
401 | int reg, u32 value) |
402 | { | |
0bc40be8 | 403 | engine->status_page.page_addr[reg] = value; |
b70ec5bf MK |
404 | } |
405 | ||
e2828914 | 406 | /* |
311bd68e CW |
407 | * Reads a dword out of the status page, which is written to from the command |
408 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
409 | * MI_STORE_DATA_IMM. | |
410 | * | |
411 | * The following dwords have a reserved meaning: | |
412 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. | |
413 | * 0x04: ring 0 head pointer | |
414 | * 0x05: ring 1 head pointer (915-class) | |
415 | * 0x06: ring 2 head pointer (915-class) | |
416 | * 0x10-0x1b: Context status DWords (GM45) | |
417 | * 0x1f: Last written status offset. (GM45) | |
b07da53c | 418 | * 0x20-0x2f: Reserved (Gen6+) |
311bd68e | 419 | * |
b07da53c | 420 | * The area from dword 0x30 to 0x3ff is available for driver usage. |
311bd68e | 421 | */ |
b07da53c | 422 | #define I915_GEM_HWS_INDEX 0x30 |
7c17d377 | 423 | #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
b07da53c | 424 | #define I915_GEM_HWS_SCRATCH_INDEX 0x40 |
9a289771 | 425 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
311bd68e | 426 | |
01101fa7 CW |
427 | struct intel_ringbuffer * |
428 | intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size); | |
7ba717cf TD |
429 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, |
430 | struct intel_ringbuffer *ringbuf); | |
01101fa7 CW |
431 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf); |
432 | void intel_ringbuffer_free(struct intel_ringbuffer *ring); | |
84c2377f | 433 | |
117897f4 TU |
434 | void intel_stop_engine(struct intel_engine_cs *engine); |
435 | void intel_cleanup_engine(struct intel_engine_cs *engine); | |
96f298aa | 436 | |
6689cb2b JH |
437 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request); |
438 | ||
5fb9de1a | 439 | int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n); |
bba09b12 | 440 | int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req); |
0bc40be8 | 441 | static inline void intel_ring_emit(struct intel_engine_cs *engine, |
78501eac | 442 | u32 data) |
e898cd22 | 443 | { |
0bc40be8 | 444 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 OM |
445 | iowrite32(data, ringbuf->virtual_start + ringbuf->tail); |
446 | ringbuf->tail += 4; | |
e898cd22 | 447 | } |
0bc40be8 | 448 | static inline void intel_ring_emit_reg(struct intel_engine_cs *engine, |
f0f59a00 | 449 | i915_reg_t reg) |
f92a9162 | 450 | { |
0bc40be8 | 451 | intel_ring_emit(engine, i915_mmio_reg_offset(reg)); |
f92a9162 | 452 | } |
0bc40be8 | 453 | static inline void intel_ring_advance(struct intel_engine_cs *engine) |
09246732 | 454 | { |
0bc40be8 | 455 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 456 | ringbuf->tail &= ringbuf->size - 1; |
09246732 | 457 | } |
82e104cc | 458 | int __intel_ring_space(int head, int tail, int size); |
ebd0fd4b | 459 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf); |
82e104cc | 460 | int intel_ring_space(struct intel_ringbuffer *ringbuf); |
117897f4 | 461 | bool intel_engine_stopped(struct intel_engine_cs *engine); |
09246732 | 462 | |
666796da | 463 | int __must_check intel_engine_idle(struct intel_engine_cs *engine); |
0bc40be8 | 464 | void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno); |
4866d729 | 465 | int intel_ring_flush_all_caches(struct drm_i915_gem_request *req); |
2f20055d | 466 | int intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req); |
8187a2b7 | 467 | |
0bc40be8 TU |
468 | void intel_fini_pipe_control(struct intel_engine_cs *engine); |
469 | int intel_init_pipe_control(struct intel_engine_cs *engine); | |
9b1136d5 | 470 | |
5c1143bb XH |
471 | int intel_init_render_ring_buffer(struct drm_device *dev); |
472 | int intel_init_bsd_ring_buffer(struct drm_device *dev); | |
845f74a7 | 473 | int intel_init_bsd2_ring_buffer(struct drm_device *dev); |
549f7365 | 474 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
9a8a2213 | 475 | int intel_init_vebox_ring_buffer(struct drm_device *dev); |
8187a2b7 | 476 | |
0bc40be8 | 477 | u64 intel_ring_get_active_head(struct intel_engine_cs *engine); |
79f321b7 | 478 | |
0bc40be8 | 479 | int init_workarounds_ring(struct intel_engine_cs *engine); |
771b9a53 | 480 | |
1b5d063f | 481 | static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf) |
a71d8d94 | 482 | { |
1b5d063f | 483 | return ringbuf->tail; |
a71d8d94 CW |
484 | } |
485 | ||
29b1b415 JH |
486 | /* |
487 | * Arbitrary size for largest possible 'add request' sequence. The code paths | |
488 | * are complex and variable. Empirical measurement shows that the worst case | |
489 | * is ILK at 136 words. Reserving too much is better than reserving too little | |
490 | * as that allows for corner cases that might have been missed. So the figure | |
491 | * has been rounded up to 160 words. | |
492 | */ | |
493 | #define MIN_SPACE_FOR_ADD_REQUEST 160 | |
494 | ||
495 | /* | |
496 | * Reserve space in the ring to guarantee that the i915_add_request() call | |
497 | * will always have sufficient room to do its stuff. The request creation | |
498 | * code calls this automatically. | |
499 | */ | |
500 | void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size); | |
501 | /* Cancel the reservation, e.g. because the request is being discarded. */ | |
502 | void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf); | |
503 | /* Use the reserved space - for use by i915_add_request() only. */ | |
504 | void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf); | |
505 | /* Finish with the reserved space - for use by i915_add_request() only. */ | |
506 | void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf); | |
507 | ||
79bbcc29 JH |
508 | /* Legacy ringbuffer specific portion of reservation code: */ |
509 | int intel_ring_reserve_space(struct drm_i915_gem_request *request); | |
510 | ||
8187a2b7 | 511 | #endif /* _INTEL_RINGBUFFER_H_ */ |