[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.h

#ifndef _INTEL_RINGBUFFER_H_
#define _INTEL_RINGBUFFER_H_

#include <linux/hashtable.h>
#include "i915_gem_batch_pool.h"

#define I915_CMD_HASH_ORDER 9

/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
 * to give some inclination as to some of the magic values used in the various
 * workarounds!
 */
#define CACHELINE_BYTES 64
#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))

/*
 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
 *
 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
 * cacheline, the Head Pointer must not be greater than the Tail
 * Pointer."
 */
#define I915_RING_FREE_SPACE 64

struct  intel_hw_status_page {
	u32		*page_addr;
	unsigned int	gfx_addr;
	struct		drm_i915_gem_object *obj;
};

#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)

#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)

#define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)

#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)

#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)

#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)

/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
 */
#define i915_semaphore_seqno_size sizeof(uint64_t)
#define GEN8_SIGNAL_OFFSET(__ring, to)			     \
	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) +	\
	(i915_semaphore_seqno_size * (to)))

#define GEN8_WAIT_OFFSET(__ring, from)			     \
	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
	(i915_semaphore_seqno_size * (__ring)->id))

#define GEN8_RING_SEMAPHORE_INIT do { \
	if (!dev_priv->semaphore_obj) { \
		break; \
	} \
	ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \
	ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \
	ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \
	ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \
	ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \
	ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \
	} while(0)

enum intel_ring_hangcheck_action {
	HANGCHECK_IDLE = 0,
	HANGCHECK_WAIT,
	HANGCHECK_ACTIVE,
	HANGCHECK_ACTIVE_LOOP,
	HANGCHECK_KICK,
	HANGCHECK_HUNG,
};

#define HANGCHECK_SCORE_RING_HUNG 31

struct intel_ring_hangcheck {
	u64 acthd;
	u64 max_acthd;
	u32 seqno;
	int score;
	enum intel_ring_hangcheck_action action;
	int deadlock;
};

struct intel_ringbuffer {
	struct drm_i915_gem_object *obj;
	void __iomem *virtual_start;

	struct intel_engine_cs *ring;

	u32 head;
	u32 tail;
	int space;
	int size;
	int effective_size;
	int reserved_size;
	int reserved_tail;
	bool reserved_in_use;

	/** We track the position of the requests in the ring buffer, and
	 * when each is retired we increment last_retired_head as the GPU
	 * must have finished processing the request and so we know we
	 * can advance the ringbuffer up to that position.
	 *
	 * last_retired_head is set to -1 after the value is consumed so
	 * we can detect new retirements.
	 */
	u32 last_retired_head;
};

struct	intel_context;
struct drm_i915_reg_descriptor;

/*
 * we use a single page to load ctx workarounds so all of these
 * values are referred in terms of dwords
 *
 * struct i915_wa_ctx_bb:
 *  offset: specifies batch starting position, also helpful in case
 *    if we want to have multiple batches at different offsets based on
 *    some criteria. It is not a requirement at the moment but provides
 *    an option for future use.
 *  size: size of the batch in DWORDS
 */
struct  i915_ctx_workarounds {
	struct i915_wa_ctx_bb {
		u32 offset;
		u32 size;
	} indirect_ctx, per_ctx;
	struct drm_i915_gem_object *obj;
};

struct  intel_engine_cs {
	const char	*name;
	enum intel_ring_id {
		RCS = 0x0,
		VCS,
		BCS,
		VECS,
		VCS2
	} id;
#define I915_NUM_RINGS 5
#define LAST_USER_RING (VECS + 1)
	u32		mmio_base;
	struct		drm_device *dev;
	struct intel_ringbuffer *buffer;

	/*
	 * A pool of objects to use as shadow copies of client batch buffers
	 * when the command parser is enabled. Prevents the client from
	 * modifying the batch contents after software parsing.
	 */
	struct i915_gem_batch_pool batch_pool;

	struct intel_hw_status_page status_page;
	struct i915_ctx_workarounds wa_ctx;

	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */
	struct drm_i915_gem_request *trace_irq_req;
	bool __must_check (*irq_get)(struct intel_engine_cs *ring);
	void		(*irq_put)(struct intel_engine_cs *ring);

	int		(*init_hw)(struct intel_engine_cs *ring);

	int		(*init_context)(struct drm_i915_gem_request *req);

	void		(*write_tail)(struct intel_engine_cs *ring,
				      u32 value);
	int __must_check (*flush)(struct drm_i915_gem_request *req,
				  u32	invalidate_domains,
				  u32	flush_domains);
	int		(*add_request)(struct drm_i915_gem_request *req);
	/* Some chipsets are not quite as coherent as advertised and need
	 * an expensive kick to force a true read of the up-to-date seqno.
	 * However, the up-to-date seqno is not always required and the last
	 * seen value is good enough. Note that the seqno will always be
	 * monotonic, even if not coherent.
	 */
	u32		(*get_seqno)(struct intel_engine_cs *ring,
				     bool lazy_coherency);
	void		(*set_seqno)(struct intel_engine_cs *ring,
				     u32 seqno);
	int		(*dispatch_execbuffer)(struct drm_i915_gem_request *req,
					       u64 offset, u32 length,
					       unsigned dispatch_flags);
#define I915_DISPATCH_SECURE 0x1
#define I915_DISPATCH_PINNED 0x2
#define I915_DISPATCH_RS     0x4
	void		(*cleanup)(struct intel_engine_cs *ring);

	/* GEN8 signal/wait table - never trust comments!
	 *	  signal to	signal to    signal to   signal to      signal to
	 *	    RCS		   VCS          BCS        VECS		 VCS2
	 *      --------------------------------------------------------------------
	 *  RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
	 *	|-------------------------------------------------------------------
	 *  VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
	 *	|-------------------------------------------------------------------
	 *  BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
	 *	|-------------------------------------------------------------------
	 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) |  NOP (0x90) | VCS2 (0x98) |
	 *	|-------------------------------------------------------------------
	 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP  (0xc0) |
	 *	|-------------------------------------------------------------------
	 *
	 * Generalization:
	 *  f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
	 *  ie. transpose of g(x, y)
	 *
	 *	 sync from	sync from    sync from    sync from	sync from
	 *	    RCS		   VCS          BCS        VECS		 VCS2
	 *      --------------------------------------------------------------------
	 *  RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
	 *	|-------------------------------------------------------------------
	 *  VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
	 *	|-------------------------------------------------------------------
	 *  BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
	 *	|-------------------------------------------------------------------
	 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) |  NOP (0x90) | VCS2 (0xb8) |
	 *	|-------------------------------------------------------------------
	 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) |  NOP (0xc0) |
	 *	|-------------------------------------------------------------------
	 *
	 * Generalization:
	 *  g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
	 *  ie. transpose of f(x, y)
	 */
	struct {
		u32	sync_seqno[I915_NUM_RINGS-1];

		union {
			struct {
				/* our mbox written by others */
				u32		wait[I915_NUM_RINGS];
				/* mboxes this ring signals to */
				u32		signal[I915_NUM_RINGS];
			} mbox;
			u64		signal_ggtt[I915_NUM_RINGS];
		};

		/* AKA wait() */
		int	(*sync_to)(struct drm_i915_gem_request *to_req,
				   struct intel_engine_cs *from,
				   u32 seqno);
		int	(*signal)(struct drm_i915_gem_request *signaller_req,
				  /* num_dwords needed by caller */
				  unsigned int num_dwords);
	} semaphore;

	/* Execlists */
	spinlock_t execlist_lock;
	struct list_head execlist_queue;
	struct list_head execlist_retired_req_list;
	u8 next_context_status_buffer;
	u32             irq_keep_mask; /* bitmask for interrupts that should not be masked */
	int		(*emit_request)(struct drm_i915_gem_request *request);
	int		(*emit_flush)(struct drm_i915_gem_request *request,
				      u32 invalidate_domains,
				      u32 flush_domains);
	int		(*emit_bb_start)(struct drm_i915_gem_request *req,
					 u64 offset, unsigned dispatch_flags);

	/**
	 * List of objects currently involved in rendering from the
	 * ringbuffer.
	 *
	 * Includes buffers having the contents of their GPU caches
	 * flushed, not necessarily primitives.  last_read_req
	 * represents when the rendering involved will be completed.
	 *
	 * A reference is held on the buffer while on this list.
	 */
	struct list_head active_list;

	/**
	 * List of breadcrumbs associated with GPU requests currently
	 * outstanding.
	 */
	struct list_head request_list;

	/**
	 * Seqno of request most recently submitted to request_list.
	 * Used exclusively by hang checker to avoid grabbing lock while
	 * inspecting request list.
	 */
	u32 last_submitted_seqno;

	bool gpu_caches_dirty;

	wait_queue_head_t irq_queue;

	struct intel_context *default_context;
	struct intel_context *last_context;

	struct intel_ring_hangcheck hangcheck;

	struct {
		struct drm_i915_gem_object *obj;
		u32 gtt_offset;
		volatile u32 *cpu_page;
	} scratch;

	bool needs_cmd_parser;

	/*
	 * Table of commands the command parser needs to know about
	 * for this ring.
	 */
	DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);

	/*
	 * Table of registers allowed in commands that read/write registers.
	 */
	const struct drm_i915_reg_descriptor *reg_table;
	int reg_count;

	/*
	 * Table of registers allowed in commands that read/write registers, but
	 * only from the DRM master.
	 */
	const struct drm_i915_reg_descriptor *master_reg_table;
	int master_reg_count;

	/*
	 * Returns the bitmask for the length field of the specified command.
	 * Return 0 for an unrecognized/invalid command.
	 *
	 * If the command parser finds an entry for a command in the ring's
	 * cmd_tables, it gets the command's length based on the table entry.
	 * If not, it calls this function to determine the per-ring length field
	 * encoding for the command (i.e. certain opcode ranges use certain bits
	 * to encode the command length in the header).
	 */
	u32 (*get_cmd_length_mask)(u32 cmd_header);
};

bool intel_ring_initialized(struct intel_engine_cs *ring);

static inline unsigned
intel_ring_flag(struct intel_engine_cs *ring)
{
	return 1 << ring->id;
}

static inline u32
intel_ring_sync_index(struct intel_engine_cs *ring,
		      struct intel_engine_cs *other)
{
	int idx;

	/*
	 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
	 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
	 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
	 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
	 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
	 */

	idx = (other - ring) - 1;
	if (idx < 0)
		idx += I915_NUM_RINGS;

	return idx;
}

static inline void
intel_flush_status_page(struct intel_engine_cs *ring, int reg)
{
	drm_clflush_virt_range(&ring->status_page.page_addr[reg],
			       sizeof(uint32_t));
}

static inline u32
intel_read_status_page(struct intel_engine_cs *ring,
		       int reg)
{
	/* Ensure that the compiler doesn't optimize away the load. */
	barrier();
	return ring->status_page.page_addr[reg];
}

static inline void
intel_write_status_page(struct intel_engine_cs *ring,
			int reg, u32 value)
{
	ring->status_page.page_addr[reg] = value;
}

/**
 * Reads a dword out of the status page, which is written to from the command
 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 * MI_STORE_DATA_IMM.
 *
 * The following dwords have a reserved meaning:
 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 * 0x04: ring 0 head pointer
 * 0x05: ring 1 head pointer (915-class)
 * 0x06: ring 2 head pointer (915-class)
 * 0x10-0x1b: Context status DWords (GM45)
 * 0x1f: Last written status offset. (GM45)
 * 0x20-0x2f: Reserved (Gen6+)
 *
 * The area from dword 0x30 to 0x3ff is available for driver usage.
 */
#define I915_GEM_HWS_INDEX		0x30
#define I915_GEM_HWS_SCRATCH_INDEX	0x40
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)

struct intel_ringbuffer *
intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size);
int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
				     struct intel_ringbuffer *ringbuf);
void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
void intel_ringbuffer_free(struct intel_ringbuffer *ring);

void intel_stop_ring_buffer(struct intel_engine_cs *ring);
void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);

int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);

int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
static inline void intel_ring_emit(struct intel_engine_cs *ring,
				   u32 data)
{
	struct intel_ringbuffer *ringbuf = ring->buffer;
	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
	ringbuf->tail += 4;
}
static inline void intel_ring_advance(struct intel_engine_cs *ring)
{
	struct intel_ringbuffer *ringbuf = ring->buffer;
	ringbuf->tail &= ringbuf->size - 1;
}
int __intel_ring_space(int head, int tail, int size);
void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
int intel_ring_space(struct intel_ringbuffer *ringbuf);
bool intel_ring_stopped(struct intel_engine_cs *ring);

int __must_check intel_ring_idle(struct intel_engine_cs *ring);
void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno);
int intel_ring_flush_all_caches(struct drm_i915_gem_request *req);
int intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req);

void intel_fini_pipe_control(struct intel_engine_cs *ring);
int intel_init_pipe_control(struct intel_engine_cs *ring);

int intel_init_render_ring_buffer(struct drm_device *dev);
int intel_init_bsd_ring_buffer(struct drm_device *dev);
int intel_init_bsd2_ring_buffer(struct drm_device *dev);
int intel_init_blt_ring_buffer(struct drm_device *dev);
int intel_init_vebox_ring_buffer(struct drm_device *dev);

u64 intel_ring_get_active_head(struct intel_engine_cs *ring);

int init_workarounds_ring(struct intel_engine_cs *ring);

static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
{
	return ringbuf->tail;
}

/*
 * Arbitrary size for largest possible 'add request' sequence. The code paths
 * are complex and variable. Empirical measurement shows that the worst case
 * is ILK at 136 words. Reserving too much is better than reserving too little
 * as that allows for corner cases that might have been missed. So the figure
 * has been rounded up to 160 words.
 */
#define MIN_SPACE_FOR_ADD_REQUEST	160

/*
 * Reserve space in the ring to guarantee that the i915_add_request() call
 * will always have sufficient room to do its stuff. The request creation
 * code calls this automatically.
 */
void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size);
/* Cancel the reservation, e.g. because the request is being discarded. */
void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf);
/* Use the reserved space - for use by i915_add_request() only. */
void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf);
/* Finish with the reserved space - for use by i915_add_request() only. */
void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf);

/* Legacy ringbuffer specific portion of reservation code: */
int intel_ring_reserve_space(struct drm_i915_gem_request *request);

#endif /* _INTEL_RINGBUFFER_H_ */
Commit	Line	Data
8187a2b7 ZN	1	#ifndef _INTEL_RINGBUFFER_H_
	2	#define _INTEL_RINGBUFFER_H_
	3
44e895a8	4	#include <linux/hashtable.h>
06fbca71	5	#include "i915_gem_batch_pool.h"
44e895a8 BV	6
	7	#define I915_CMD_HASH_ORDER 9
	8
4712274c OM	9	/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
	10	* but keeps the logic simple. Indeed, the whole purpose of this macro is just
	11	* to give some inclination as to some of the magic values used in the various
	12	* workarounds!
	13	*/
	14	#define CACHELINE_BYTES 64
17ee950d	15	#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
4712274c	16
633cf8f5 VS	17	/*
	18	* Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
	19	* Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
	20	* Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
	21	*
	22	* "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
	23	* cacheline, the Head Pointer must not be greater than the Tail
	24	* Pointer."
	25	*/
	26	#define I915_RING_FREE_SPACE 64
	27
8187a2b7	28	struct intel_hw_status_page {
4225d0f2	29	u32 *page_addr;
8187a2b7	30	unsigned int gfx_addr;
05394f39	31	struct drm_i915_gem_object *obj;
8187a2b7 ZN	32	};
8187a2b7 ZN	33
b7287d80 BW	34	#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
b7287d80 BW	35	#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
cae5852d	36
b7287d80 BW	37	#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
b7287d80 BW	38	#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
cae5852d	39
b7287d80 BW	40	#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
b7287d80 BW	41	#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
cae5852d	42
b7287d80 BW	43	#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
b7287d80 BW	44	#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
cae5852d	45
b7287d80 BW	46	#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
b7287d80 BW	47	#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
870e86dd	48
e9fea574	49	#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
9991ae78	50	#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
e9fea574	51
3e78998a BW	52	/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
	53	* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
	54	*/
	55	#define i915_semaphore_seqno_size sizeof(uint64_t)
	56	#define GEN8_SIGNAL_OFFSET(__ring, to) \
	57	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	58	((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
	59	(i915_semaphore_seqno_size * (to)))
	60
	61	#define GEN8_WAIT_OFFSET(__ring, from) \
	62	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	63	((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
	64	(i915_semaphore_seqno_size * (__ring)->id))
	65
	66	#define GEN8_RING_SEMAPHORE_INIT do { \
	67	if (!dev_priv->semaphore_obj) { \
	68	break; \
	69	} \
	70	ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \
	71	ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \
	72	ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \
	73	ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \
	74	ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \
	75	ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \
	76	} while(0)
	77
f2f4d82f	78	enum intel_ring_hangcheck_action {
da661464	79	HANGCHECK_IDLE = 0,
f2f4d82f JN	80	HANGCHECK_WAIT,
f2f4d82f JN	81	HANGCHECK_ACTIVE,
f260fe7b	82	HANGCHECK_ACTIVE_LOOP,
f2f4d82f JN	83	HANGCHECK_KICK,
	84	HANGCHECK_HUNG,
	85	};
ad8beaea	86
b6b0fac0 MK	87	#define HANGCHECK_SCORE_RING_HUNG 31
b6b0fac0 MK	88
92cab734	89	struct intel_ring_hangcheck {
50877445	90	u64 acthd;
f260fe7b	91	u64 max_acthd;
92cab734	92	u32 seqno;
05407ff8	93	int score;
ad8beaea	94	enum intel_ring_hangcheck_action action;
4be17381	95	int deadlock;
92cab734 MK	96	};
92cab734 MK	97
8ee14975 OM	98	struct intel_ringbuffer {
	99	struct drm_i915_gem_object *obj;
	100	void __iomem *virtual_start;
	101
0c7dd53b DV	102	struct intel_engine_cs *ring;
0c7dd53b DV	103
8ee14975 OM	104	u32 head;
	105	u32 tail;
	106	int space;
	107	int size;
	108	int effective_size;
29b1b415 JH	109	int reserved_size;
	110	int reserved_tail;
	111	bool reserved_in_use;
8ee14975 OM	112
	113	/** We track the position of the requests in the ring buffer, and
	114	* when each is retired we increment last_retired_head as the GPU
	115	* must have finished processing the request and so we know we
	116	* can advance the ringbuffer up to that position.
	117	*
	118	* last_retired_head is set to -1 after the value is consumed so
	119	* we can detect new retirements.
	120	*/
	121	u32 last_retired_head;
	122	};
	123
21076372	124	struct intel_context;
4e86f725	125	struct drm_i915_reg_descriptor;
21076372	126
17ee950d AS	127	/*
	128	* we use a single page to load ctx workarounds so all of these
	129	* values are referred in terms of dwords
	130	*
	131	* struct i915_wa_ctx_bb:
	132	* offset: specifies batch starting position, also helpful in case
	133	* if we want to have multiple batches at different offsets based on
	134	* some criteria. It is not a requirement at the moment but provides
	135	* an option for future use.
	136	* size: size of the batch in DWORDS
	137	*/
	138	struct i915_ctx_workarounds {
	139	struct i915_wa_ctx_bb {
	140	u32 offset;
	141	u32 size;
	142	} indirect_ctx, per_ctx;
	143	struct drm_i915_gem_object *obj;
	144	};
	145
a4872ba6	146	struct intel_engine_cs {
8187a2b7	147	const char *name;
9220434a	148	enum intel_ring_id {
96154f2f DV	149	RCS = 0x0,
	150	VCS,
	151	BCS,
4a3dd19d	152	VECS,
845f74a7	153	VCS2
9220434a	154	} id;
845f74a7	155	#define I915_NUM_RINGS 5
b1a93306	156	#define LAST_USER_RING (VECS + 1)
333e9fe9	157	u32 mmio_base;
8187a2b7	158	struct drm_device *dev;
8ee14975	159	struct intel_ringbuffer *buffer;
8187a2b7	160
06fbca71 CW	161	/*
	162	* A pool of objects to use as shadow copies of client batch buffers
	163	* when the command parser is enabled. Prevents the client from
	164	* modifying the batch contents after software parsing.
	165	*/
	166	struct i915_gem_batch_pool batch_pool;
	167
8187a2b7	168	struct intel_hw_status_page status_page;
17ee950d	169	struct i915_ctx_workarounds wa_ctx;
8187a2b7	170
c7113cc3	171	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
6a848ccb	172	u32 irq_enable_mask; /* bitmask to enable ring interrupt */
581c26e8	173	struct drm_i915_gem_request *trace_irq_req;
a4872ba6 OM	174	bool __must_check (irq_get)(struct intel_engine_cs ring);
a4872ba6 OM	175	void (irq_put)(struct intel_engine_cs ring);
8187a2b7	176
ecfe00d8	177	int (init_hw)(struct intel_engine_cs ring);
8187a2b7	178
8753181e	179	int (init_context)(struct drm_i915_gem_request req);
86d7f238	180
a4872ba6	181	void (write_tail)(struct intel_engine_cs ring,
297b0c5b	182	u32 value);
a84c3ae1	183	int __must_check (flush)(struct drm_i915_gem_request req,
b72f3acb CW	184	u32 invalidate_domains,
b72f3acb CW	185	u32 flush_domains);
ee044a88	186	int (add_request)(struct drm_i915_gem_request req);
b2eadbc8 CW	187	/* Some chipsets are not quite as coherent as advertised and need
	188	* an expensive kick to force a true read of the up-to-date seqno.
	189	* However, the up-to-date seqno is not always required and the last
	190	* seen value is good enough. Note that the seqno will always be
	191	* monotonic, even if not coherent.
	192	*/
a4872ba6	193	u32 (get_seqno)(struct intel_engine_cs ring,
b2eadbc8	194	bool lazy_coherency);
a4872ba6	195	void (set_seqno)(struct intel_engine_cs ring,
b70ec5bf	196	u32 seqno);
53fddaf7	197	int (dispatch_execbuffer)(struct drm_i915_gem_request req,
9bcb144c	198	u64 offset, u32 length,
8e004efc	199	unsigned dispatch_flags);
d7d4eedd	200	#define I915_DISPATCH_SECURE 0x1
b45305fc	201	#define I915_DISPATCH_PINNED 0x2
919032ec	202	#define I915_DISPATCH_RS 0x4
a4872ba6	203	void (cleanup)(struct intel_engine_cs ring);
ebc348b2	204
3e78998a BW	205	/* GEN8 signal/wait table - never trust comments!
	206	* signal to signal to signal to signal to signal to
	207	* RCS VCS BCS VECS VCS2
	208	* --------------------------------------------------------------------
	209	* RCS \| NOP (0x00) \| VCS (0x08) \| BCS (0x10) \| VECS (0x18) \| VCS2 (0x20) \|
	210	* \|-------------------------------------------------------------------
	211	* VCS \| RCS (0x28) \| NOP (0x30) \| BCS (0x38) \| VECS (0x40) \| VCS2 (0x48) \|
	212	* \|-------------------------------------------------------------------
	213	* BCS \| RCS (0x50) \| VCS (0x58) \| NOP (0x60) \| VECS (0x68) \| VCS2 (0x70) \|
	214	* \|-------------------------------------------------------------------
	215	* VECS \| RCS (0x78) \| VCS (0x80) \| BCS (0x88) \| NOP (0x90) \| VCS2 (0x98) \|
	216	* \|-------------------------------------------------------------------
	217	* VCS2 \| RCS (0xa0) \| VCS (0xa8) \| BCS (0xb0) \| VECS (0xb8) \| NOP (0xc0) \|
	218	* \|-------------------------------------------------------------------
	219	*
	220	* Generalization:
	221	* f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
	222	* ie. transpose of g(x, y)
	223	*
	224	* sync from sync from sync from sync from sync from
	225	* RCS VCS BCS VECS VCS2
	226	* --------------------------------------------------------------------
	227	* RCS \| NOP (0x00) \| VCS (0x28) \| BCS (0x50) \| VECS (0x78) \| VCS2 (0xa0) \|
	228	* \|-------------------------------------------------------------------
	229	* VCS \| RCS (0x08) \| NOP (0x30) \| BCS (0x58) \| VECS (0x80) \| VCS2 (0xa8) \|
	230	* \|-------------------------------------------------------------------
	231	* BCS \| RCS (0x10) \| VCS (0x38) \| NOP (0x60) \| VECS (0x88) \| VCS2 (0xb0) \|
	232	* \|-------------------------------------------------------------------
	233	* VECS \| RCS (0x18) \| VCS (0x40) \| BCS (0x68) \| NOP (0x90) \| VCS2 (0xb8) \|
	234	* \|-------------------------------------------------------------------
	235	* VCS2 \| RCS (0x20) \| VCS (0x48) \| BCS (0x70) \| VECS (0x98) \| NOP (0xc0) \|
	236	* \|-------------------------------------------------------------------
	237	*
	238	* Generalization:
	239	* g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
	240	* ie. transpose of f(x, y)
	241	*/
ebc348b2 BW	242	struct {
ebc348b2 BW	243	u32 sync_seqno[I915_NUM_RINGS-1];
78325f2d	244
3e78998a BW	245	union {
	246	struct {
	247	/* our mbox written by others */
	248	u32 wait[I915_NUM_RINGS];
	249	/* mboxes this ring signals to */
	250	u32 signal[I915_NUM_RINGS];
	251	} mbox;
	252	u64 signal_ggtt[I915_NUM_RINGS];
	253	};
78325f2d BW	254
78325f2d BW	255	/* AKA wait() */
599d924c JH	256	int (sync_to)(struct drm_i915_gem_request to_req,
599d924c JH	257	struct intel_engine_cs *from,
78325f2d	258	u32 seqno);
f7169687	259	int (signal)(struct drm_i915_gem_request signaller_req,
024a43e1 BW	260	/* num_dwords needed by caller */
024a43e1 BW	261	unsigned int num_dwords);
ebc348b2	262	} semaphore;
ad776f8b	263
4da46e1e	264	/* Execlists */
acdd884a MT	265	spinlock_t execlist_lock;
acdd884a MT	266	struct list_head execlist_queue;
c86ee3a9	267	struct list_head execlist_retired_req_list;
e981e7b1	268	u8 next_context_status_buffer;
73d477f6	269	u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
c4e76638	270	int (emit_request)(struct drm_i915_gem_request request);
7deb4d39	271	int (emit_flush)(struct drm_i915_gem_request request,
4712274c OM	272	u32 invalidate_domains,
4712274c OM	273	u32 flush_domains);
be795fc1	274	int (emit_bb_start)(struct drm_i915_gem_request req,
8e004efc	275	u64 offset, unsigned dispatch_flags);
4da46e1e	276
8187a2b7 ZN	277	/**
	278	* List of objects currently involved in rendering from the
	279	* ringbuffer.
	280	*
	281	* Includes buffers having the contents of their GPU caches
97b2a6a1	282	* flushed, not necessarily primitives. last_read_req
8187a2b7 ZN	283	* represents when the rendering involved will be completed.
	284	*
	285	* A reference is held on the buffer while on this list.
	286	*/
	287	struct list_head active_list;
	288
	289	/**
	290	* List of breadcrumbs associated with GPU requests currently
	291	* outstanding.
	292	*/
	293	struct list_head request_list;
	294
94f7bbe1 TE	295	/**
	296	* Seqno of request most recently submitted to request_list.
	297	* Used exclusively by hang checker to avoid grabbing lock while
	298	* inspecting request list.
	299	*/
	300	u32 last_submitted_seqno;
	301
cc889e0f	302	bool gpu_caches_dirty;
a56ba56c	303
8187a2b7	304	wait_queue_head_t irq_queue;
8d19215b	305
273497e5 OM	306	struct intel_context *default_context;
273497e5 OM	307	struct intel_context *last_context;
40521054	308
92cab734 MK	309	struct intel_ring_hangcheck hangcheck;
92cab734 MK	310
0d1aacac CW	311	struct {
	312	struct drm_i915_gem_object *obj;
	313	u32 gtt_offset;
	314	volatile u32 *cpu_page;
	315	} scratch;
351e3db2	316
44e895a8 BV	317	bool needs_cmd_parser;
44e895a8 BV	318
351e3db2	319	/*
44e895a8	320	* Table of commands the command parser needs to know about
351e3db2 BV	321	* for this ring.
351e3db2 BV	322	*/
44e895a8	323	DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
351e3db2 BV	324
	325	/*
	326	* Table of registers allowed in commands that read/write registers.
	327	*/
4e86f725	328	const struct drm_i915_reg_descriptor *reg_table;
351e3db2 BV	329	int reg_count;
	330
	331	/*
	332	* Table of registers allowed in commands that read/write registers, but
	333	* only from the DRM master.
	334	*/
4e86f725	335	const struct drm_i915_reg_descriptor *master_reg_table;
351e3db2 BV	336	int master_reg_count;
	337
	338	/*
	339	* Returns the bitmask for the length field of the specified command.
	340	* Return 0 for an unrecognized/invalid command.
	341	*
	342	* If the command parser finds an entry for a command in the ring's
	343	* cmd_tables, it gets the command's length based on the table entry.
	344	* If not, it calls this function to determine the per-ring length field
	345	* encoding for the command (i.e. certain opcode ranges use certain bits
	346	* to encode the command length in the header).
	347	*/
	348	u32 (*get_cmd_length_mask)(u32 cmd_header);
8187a2b7 ZN	349	};
8187a2b7 ZN	350
48d82387	351	bool intel_ring_initialized(struct intel_engine_cs *ring);
b4519513	352
96154f2f	353	static inline unsigned
a4872ba6	354	intel_ring_flag(struct intel_engine_cs *ring)
96154f2f DV	355	{
	356	return 1 << ring->id;
	357	}
	358
1ec14ad3	359	static inline u32
a4872ba6 OM	360	intel_ring_sync_index(struct intel_engine_cs *ring,
a4872ba6 OM	361	struct intel_engine_cs *other)
1ec14ad3 CW	362	{
	363	int idx;
	364
	365	/*
ddd4dbc6 RV	366	* rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
	367	* vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
	368	* bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
	369	* vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
	370	* vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
1ec14ad3 CW	371	*/
	372
	373	idx = (other - ring) - 1;
	374	if (idx < 0)
	375	idx += I915_NUM_RINGS;
	376
	377	return idx;
	378	}
	379
319404df ID	380	static inline void
	381	intel_flush_status_page(struct intel_engine_cs *ring, int reg)
	382	{
	383	drm_clflush_virt_range(&ring->status_page.page_addr[reg],
	384	sizeof(uint32_t));
	385	}
	386
8187a2b7	387	static inline u32
a4872ba6	388	intel_read_status_page(struct intel_engine_cs *ring,
78501eac	389	int reg)
8187a2b7	390	{
4225d0f2 DV	391	/* Ensure that the compiler doesn't optimize away the load. */
	392	barrier();
	393	return ring->status_page.page_addr[reg];
8187a2b7 ZN	394	}
8187a2b7 ZN	395
b70ec5bf	396	static inline void
a4872ba6	397	intel_write_status_page(struct intel_engine_cs *ring,
b70ec5bf MK	398	int reg, u32 value)
	399	{
	400	ring->status_page.page_addr[reg] = value;
	401	}
	402
311bd68e CW	403	/**
	404	* Reads a dword out of the status page, which is written to from the command
	405	* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
	406	* MI_STORE_DATA_IMM.
	407	*
	408	* The following dwords have a reserved meaning:
	409	* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
	410	* 0x04: ring 0 head pointer
	411	* 0x05: ring 1 head pointer (915-class)
	412	* 0x06: ring 2 head pointer (915-class)
	413	* 0x10-0x1b: Context status DWords (GM45)
	414	* 0x1f: Last written status offset. (GM45)
b07da53c	415	* 0x20-0x2f: Reserved (Gen6+)
311bd68e	416	*
b07da53c	417	* The area from dword 0x30 to 0x3ff is available for driver usage.
311bd68e	418	*/
b07da53c TD	419	#define I915_GEM_HWS_INDEX 0x30
b07da53c TD	420	#define I915_GEM_HWS_SCRATCH_INDEX 0x40
9a289771	421	#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
311bd68e	422
01101fa7 CW	423	struct intel_ringbuffer *
01101fa7 CW	424	intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size);
7ba717cf TD	425	int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
7ba717cf TD	426	struct intel_ringbuffer *ringbuf);
01101fa7 CW	427	void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
01101fa7 CW	428	void intel_ringbuffer_free(struct intel_ringbuffer *ring);
84c2377f	429
a4872ba6 OM	430	void intel_stop_ring_buffer(struct intel_engine_cs *ring);
a4872ba6 OM	431	void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);
96f298aa	432
6689cb2b JH	433	int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
6689cb2b JH	434
5fb9de1a	435	int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
bba09b12	436	int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
a4872ba6	437	static inline void intel_ring_emit(struct intel_engine_cs *ring,
78501eac	438	u32 data)
e898cd22	439	{
93b0a4e0 OM	440	struct intel_ringbuffer *ringbuf = ring->buffer;
	441	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
	442	ringbuf->tail += 4;
e898cd22	443	}
a4872ba6	444	static inline void intel_ring_advance(struct intel_engine_cs *ring)
09246732	445	{
93b0a4e0 OM	446	struct intel_ringbuffer *ringbuf = ring->buffer;
93b0a4e0 OM	447	ringbuf->tail &= ringbuf->size - 1;
09246732	448	}
82e104cc	449	int __intel_ring_space(int head, int tail, int size);
ebd0fd4b	450	void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
82e104cc OM	451	int intel_ring_space(struct intel_ringbuffer *ringbuf);
82e104cc OM	452	bool intel_ring_stopped(struct intel_engine_cs *ring);
09246732	453
a4872ba6 OM	454	int __must_check intel_ring_idle(struct intel_engine_cs *ring);
a4872ba6 OM	455	void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno);
4866d729	456	int intel_ring_flush_all_caches(struct drm_i915_gem_request *req);
2f20055d	457	int intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req);
8187a2b7	458
9b1136d5 OM	459	void intel_fini_pipe_control(struct intel_engine_cs *ring);
	460	int intel_init_pipe_control(struct intel_engine_cs *ring);
	461
5c1143bb XH	462	int intel_init_render_ring_buffer(struct drm_device *dev);
5c1143bb XH	463	int intel_init_bsd_ring_buffer(struct drm_device *dev);
845f74a7	464	int intel_init_bsd2_ring_buffer(struct drm_device *dev);
549f7365	465	int intel_init_blt_ring_buffer(struct drm_device *dev);
9a8a2213	466	int intel_init_vebox_ring_buffer(struct drm_device *dev);
8187a2b7	467
a4872ba6	468	u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
79f321b7	469
771b9a53 MT	470	int init_workarounds_ring(struct intel_engine_cs *ring);
771b9a53 MT	471
1b5d063f	472	static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
a71d8d94	473	{
1b5d063f	474	return ringbuf->tail;
a71d8d94 CW	475	}
a71d8d94 CW	476
29b1b415 JH	477	/*
	478	* Arbitrary size for largest possible 'add request' sequence. The code paths
	479	* are complex and variable. Empirical measurement shows that the worst case
	480	* is ILK at 136 words. Reserving too much is better than reserving too little
	481	* as that allows for corner cases that might have been missed. So the figure
	482	* has been rounded up to 160 words.
	483	*/
	484	#define MIN_SPACE_FOR_ADD_REQUEST 160
	485
	486	/*
	487	* Reserve space in the ring to guarantee that the i915_add_request() call
	488	* will always have sufficient room to do its stuff. The request creation
	489	* code calls this automatically.
	490	*/
	491	void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size);
	492	/* Cancel the reservation, e.g. because the request is being discarded. */
	493	void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf);
	494	/* Use the reserved space - for use by i915_add_request() only. */
	495	void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf);
	496	/* Finish with the reserved space - for use by i915_add_request() only. */
	497	void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf);
	498
79bbcc29 JH	499	/* Legacy ringbuffer specific portion of reservation code: */
	500	int intel_ring_reserve_space(struct drm_i915_gem_request *request);
	501
8187a2b7	502	#endif /* _INTEL_RINGBUFFER_H_ */