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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945
JB		 30#include <linux/delay.h>
31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
2b8d33f7 34#include "drm_edid.h"
ea5b213a 35#include "intel_drv.h"
79e53945
JB		 36#include "i915_drm.h"
37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 50#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
14571b4c 51
79e53945 52
2e88e40b 53static const char *tv_format_names[] = {
ce6feabd
ZY		 54 "NTSC_M" , "NTSC_J" , "NTSC_443",
55 "PAL_B" , "PAL_D" , "PAL_G" ,
56 "PAL_H" , "PAL_I" , "PAL_M" ,
57 "PAL_N" , "PAL_NC" , "PAL_60" ,
58 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
59 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
60 "SECAM_60"
61};
62
63#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
64
ea5b213a
CW		 65struct intel_sdvo {
66 struct intel_encoder base;
67
f899fc64 68 struct i2c_adapter *i2c;
f9c10a9b 69 u8 slave_addr;
e2f0ba97 70
e957d772
CW		 71 struct i2c_adapter ddc;
72
e2f0ba97 73 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 74 int sdvo_reg;
79e53945 75
e2f0ba97
JB		 76 /* Active outputs controlled by this SDVO output */
77 uint16_t controlled_output;
79e53945 78
e2f0ba97
JB		 79 /*
80 * Capabilities of the SDVO device returned by
81 * i830_sdvo_get_capabilities()
82 */
79e53945 83 struct intel_sdvo_caps caps;
e2f0ba97
JB		 84
85 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 86 int pixel_clock_min, pixel_clock_max;
87
fb7a46f3 88 /*
89 * For multiple function SDVO device,
90 * this is for current attached outputs.
91 */
92 uint16_t attached_output;
93
e2f0ba97
JB		 94 /**
95 * This is set if we're going to treat the device as TV-out.
96 *
97 * While we have these nice friendly flags for output types that ought
98 * to decide this for us, the S-Video output on our HDMI+S-Video card
99 * shows up as RGB1 (VGA).
100 */
101 bool is_tv;
102
ce6feabd 103 /* This is for current tv format name */
40039750 104 int tv_format_index;
ce6feabd 105
e2f0ba97
JB		 106 /**
107 * This is set if we treat the device as HDMI, instead of DVI.
108 */
109 bool is_hdmi;
da79de97
CW		 110 bool has_hdmi_monitor;
111 bool has_hdmi_audio;
12682a97 112
7086c87f 113 /**
6c9547ff
CW		 114 * This is set if we detect output of sdvo device as LVDS and
115 * have a valid fixed mode to use with the panel.
7086c87f
ML		 116 */
117 bool is_lvds;
e2f0ba97 118
12682a97 119 /**
120 * This is sdvo fixed pannel mode pointer
121 */
122 struct drm_display_mode *sdvo_lvds_fixed_mode;
123
c751ce4f 124 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 125 uint8_t ddc_bus;
126
6c9547ff
CW		 127 /* Input timings for adjusted_mode */
128 struct intel_sdvo_dtd input_dtd;
14571b4c
ZW		 129};
130
131struct intel_sdvo_connector {
615fb93f
CW		 132 struct intel_connector base;
133
14571b4c
ZW		 134 /* Mark the type of connector */
135 uint16_t output_flag;
136
7f36e7ed
CW		 137 int force_audio;
138
14571b4c 139 /* This contains all current supported TV format */
40039750 140 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 141 int format_supported_num;
c5521706 142 struct drm_property *tv_format;
14571b4c 143
7f36e7ed
CW		 144 struct drm_property *force_audio_property;
145
b9219c5e 146 /* add the property for the SDVO-TV */
c5521706
CW		 147 struct drm_property *left;
148 struct drm_property *right;
149 struct drm_property *top;
150 struct drm_property *bottom;
151 struct drm_property *hpos;
152 struct drm_property *vpos;
153 struct drm_property *contrast;
154 struct drm_property *saturation;
155 struct drm_property *hue;
156 struct drm_property *sharpness;
157 struct drm_property *flicker_filter;
158 struct drm_property *flicker_filter_adaptive;
159 struct drm_property *flicker_filter_2d;
160 struct drm_property *tv_chroma_filter;
161 struct drm_property *tv_luma_filter;
e044218a 162 struct drm_property *dot_crawl;
b9219c5e
ZY		 163
164 /* add the property for the SDVO-TV/LVDS */
c5521706 165 struct drm_property *brightness;
b9219c5e
ZY		 166
167 /* Add variable to record current setting for the above property */
168 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 169
b9219c5e
ZY		 170 /* this is to get the range of margin.*/
171 u32 max_hscan, max_vscan;
172 u32 max_hpos, cur_hpos;
173 u32 max_vpos, cur_vpos;
174 u32 cur_brightness, max_brightness;
175 u32 cur_contrast, max_contrast;
176 u32 cur_saturation, max_saturation;
177 u32 cur_hue, max_hue;
c5521706
CW		 178 u32 cur_sharpness, max_sharpness;
179 u32 cur_flicker_filter, max_flicker_filter;
180 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
181 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
182 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
183 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 184 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 185};
186
890f3359 187static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 188{
4ef69c7a 189 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 190}
191
df0e9248
CW		 192static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
193{
194 return container_of(intel_attached_encoder(connector),
195 struct intel_sdvo, base);
196}
197
615fb93f
CW		 198static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
199{
200 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
201}
202
fb7a46f3 203static bool
ea5b213a 204intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 205static bool
206intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
207 struct intel_sdvo_connector *intel_sdvo_connector,
208 int type);
209static bool
210intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
211 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 212
79e53945
JB		 213/**
214 * Writes the SDVOB or SDVOC with the given value, but always writes both
215 * SDVOB and SDVOC to work around apparent hardware issues (according to
216 * comments in the BIOS).
217 */
ea5b213a 218static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 219{
4ef69c7a 220 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 221 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 222 u32 bval = val, cval = val;
223 int i;
224
ea5b213a
CW		 225 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
226 I915_WRITE(intel_sdvo->sdvo_reg, val);
227 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 228 return;
229 }
230
ea5b213a 231 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 232 cval = I915_READ(SDVOC);
233 } else {
234 bval = I915_READ(SDVOB);
235 }
236 /*
237 * Write the registers twice for luck. Sometimes,
238 * writing them only once doesn't appear to 'stick'.
239 * The BIOS does this too. Yay, magic
240 */
241 for (i = 0; i < 2; i++)
242 {
243 I915_WRITE(SDVOB, bval);
244 I915_READ(SDVOB);
245 I915_WRITE(SDVOC, cval);
246 I915_READ(SDVOC);
247 }
248}
249
32aad86f 250static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 251{
79e53945
JB		 252 struct i2c_msg msgs[] = {
253 {
e957d772 254 .addr = intel_sdvo->slave_addr,
79e53945
JB		 255 .flags = 0,
256 .len = 1,
e957d772 257 .buf = &addr,
79e53945
JB		 258 },
259 {
e957d772 260 .addr = intel_sdvo->slave_addr,
79e53945
JB		 261 .flags = I2C_M_RD,
262 .len = 1,
e957d772 263 .buf = ch,
79e53945
JB		 264 }
265 };
32aad86f 266 int ret;
79e53945 267
f899fc64 268 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 269 return true;
79e53945 270
8a4c47f3 271 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 272 return false;
273}
274
79e53945
JB		 275#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
276/** Mapping of command numbers to names, for debug output */
005568be 277static const struct _sdvo_cmd_name {
e2f0ba97 278 u8 cmd;
2e88e40b 279 const char *name;
79e53945
JB		 280} sdvo_cmd_names[] = {
281 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
282 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
283 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
284 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
285 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
286 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
e2f0ba97
JB		 316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
79e53945 320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
e2f0ba97
JB		 321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
c5521706 324
b9219c5e 325 /* Add the op code for SDVO enhancements */
c5521706
CW		 326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
b9219c5e
ZY		 332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
c5521706
CW		 350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
370
e2f0ba97
JB		 371 /* HDMI op code */
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 392};
393
461ed3ca 394#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
ea5b213a 395#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
79e53945 396
ea5b213a 397static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 398 const void *args, int args_len)
79e53945 399{
79e53945
JB		 400 int i;
401
8a4c47f3 402 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 403 SDVO_NAME(intel_sdvo), cmd);
79e53945 404 for (i = 0; i < args_len; i++)
342dc382 405 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 406 for (; i < 8; i++)
342dc382 407 DRM_LOG_KMS(" ");
04ad327f 408 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 409 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 410 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 411 break;
412 }
413 }
04ad327f 414 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 415 DRM_LOG_KMS("(%02X)", cmd);
416 DRM_LOG_KMS("\n");
79e53945 417}
79e53945 418
e957d772
CW		 419static const char *cmd_status_names[] = {
420 "Power on",
421 "Success",
422 "Not supported",
423 "Invalid arg",
424 "Pending",
425 "Target not specified",
426 "Scaling not supported"
427};
428
32aad86f
CW		 429static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
430 const void *args, int args_len)
79e53945 431{
e957d772
CW		 432 u8 buf[args_len*2 + 2], status;
433 struct i2c_msg msgs[args_len + 3];
434 int i, ret;
79e53945 435
ea5b213a 436 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 437
438 for (i = 0; i < args_len; i++) {
e957d772
CW		 439 msgs[i].addr = intel_sdvo->slave_addr;
440 msgs[i].flags = 0;
441 msgs[i].len = 2;
442 msgs[i].buf = buf + 2 *i;
443 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
444 buf[2*i + 1] = ((u8*)args)[i];
445 }
446 msgs[i].addr = intel_sdvo->slave_addr;
447 msgs[i].flags = 0;
448 msgs[i].len = 2;
449 msgs[i].buf = buf + 2*i;
450 buf[2*i + 0] = SDVO_I2C_OPCODE;
451 buf[2*i + 1] = cmd;
452
453 /* the following two are to read the response */
454 status = SDVO_I2C_CMD_STATUS;
455 msgs[i+1].addr = intel_sdvo->slave_addr;
456 msgs[i+1].flags = 0;
457 msgs[i+1].len = 1;
458 msgs[i+1].buf = &status;
459
460 msgs[i+2].addr = intel_sdvo->slave_addr;
461 msgs[i+2].flags = I2C_M_RD;
462 msgs[i+2].len = 1;
463 msgs[i+2].buf = &status;
464
465 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
466 if (ret < 0) {
467 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
468 return false;
469 }
470 if (ret != i+3) {
471 /* failure in I2C transfer */
472 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
473 return false;
474 }
475
476 i = 3;
477 while (status == SDVO_CMD_STATUS_PENDING && i--) {
478 if (!intel_sdvo_read_byte(intel_sdvo,
479 SDVO_I2C_CMD_STATUS,
480 &status))
32aad86f 481 return false;
79e53945 482 }
e957d772
CW		 483 if (status != SDVO_CMD_STATUS_SUCCESS) {
484 DRM_DEBUG_KMS("command returns response %s [%d]\n",
485 status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP ? cmd_status_names[status] : "???",
486 status);
487 return false;
488 }
79e53945 489
e957d772 490 return true;
79e53945
JB		 491}
492
b5c616a7
CW		 493static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
494 void *response, int response_len)
79e53945 495{
b5c616a7
CW		 496 u8 retry = 5;
497 u8 status;
33b52961 498 int i;
79e53945 499
b5c616a7
CW		 500 /*
501 * The documentation states that all commands will be
502 * processed within 15µs, and that we need only poll
503 * the status byte a maximum of 3 times in order for the
504 * command to be complete.
505 *
506 * Check 5 times in case the hardware failed to read the docs.
507 */
508 do {
509 if (!intel_sdvo_read_byte(intel_sdvo,
510 SDVO_I2C_CMD_STATUS,
511 &status))
512 return false;
513 } while (status == SDVO_CMD_STATUS_PENDING && --retry);
514
ea5b213a 515 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
79e53945 516 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 517 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 518 else
342dc382 519 DRM_LOG_KMS("(??? %d)", status);
79e53945 520
b5c616a7
CW		 521 if (status != SDVO_CMD_STATUS_SUCCESS)
522 goto log_fail;
79e53945 523
b5c616a7
CW		 524 /* Read the command response */
525 for (i = 0; i < response_len; i++) {
526 if (!intel_sdvo_read_byte(intel_sdvo,
527 SDVO_I2C_RETURN_0 + i,
528 &((u8 *)response)[i]))
529 goto log_fail;
e957d772 530 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 531 }
b5c616a7 532 DRM_LOG_KMS("\n");
b5c616a7 533 return true;
79e53945 534
b5c616a7
CW		 535log_fail:
536 DRM_LOG_KMS("\n");
537 return false;
79e53945
JB		 538}
539
b358d0a6 540static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 541{
542 if (mode->clock >= 100000)
543 return 1;
544 else if (mode->clock >= 50000)
545 return 2;
546 else
547 return 4;
548}
549
e957d772
CW		 550static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
551 u8 ddc_bus)
79e53945 552{
e957d772
CW		 553 return intel_sdvo_write_cmd(intel_sdvo,
554 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
555 &ddc_bus, 1);
79e53945
JB		 556}
557
32aad86f 558static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 559{
e957d772 560 return intel_sdvo_write_cmd(intel_sdvo, cmd, data, len);
32aad86f 561}
79e53945 562
32aad86f
CW		 563static bool
564intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
565{
566 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
567 return false;
79e53945 568
32aad86f
CW		 569 return intel_sdvo_read_response(intel_sdvo, value, len);
570}
79e53945 571
32aad86f
CW		 572static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
573{
574 struct intel_sdvo_set_target_input_args targets = {0};
575 return intel_sdvo_set_value(intel_sdvo,
576 SDVO_CMD_SET_TARGET_INPUT,
577 &targets, sizeof(targets));
79e53945
JB		 578}
579
580/**
581 * Return whether each input is trained.
582 *
583 * This function is making an assumption about the layout of the response,
584 * which should be checked against the docs.
585 */
ea5b213a 586static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 587{
588 struct intel_sdvo_get_trained_inputs_response response;
79e53945 589
32aad86f
CW		 590 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
591 &response, sizeof(response)))
79e53945
JB		 592 return false;
593
594 *input_1 = response.input0_trained;
595 *input_2 = response.input1_trained;
596 return true;
597}
598
ea5b213a 599static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 600 u16 outputs)
601{
32aad86f
CW		 602 return intel_sdvo_set_value(intel_sdvo,
603 SDVO_CMD_SET_ACTIVE_OUTPUTS,
604 &outputs, sizeof(outputs));
79e53945
JB		 605}
606
ea5b213a 607static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 608 int mode)
609{
32aad86f 610 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 611
612 switch (mode) {
613 case DRM_MODE_DPMS_ON:
614 state = SDVO_ENCODER_STATE_ON;
615 break;
616 case DRM_MODE_DPMS_STANDBY:
617 state = SDVO_ENCODER_STATE_STANDBY;
618 break;
619 case DRM_MODE_DPMS_SUSPEND:
620 state = SDVO_ENCODER_STATE_SUSPEND;
621 break;
622 case DRM_MODE_DPMS_OFF:
623 state = SDVO_ENCODER_STATE_OFF;
624 break;
625 }
626
32aad86f
CW		 627 return intel_sdvo_set_value(intel_sdvo,
628 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 629}
630
ea5b213a 631static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 632 int *clock_min,
633 int *clock_max)
634{
635 struct intel_sdvo_pixel_clock_range clocks;
79e53945 636
32aad86f
CW		 637 if (!intel_sdvo_get_value(intel_sdvo,
638 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
639 &clocks, sizeof(clocks)))
79e53945
JB		 640 return false;
641
642 /* Convert the values from units of 10 kHz to kHz. */
643 *clock_min = clocks.min * 10;
644 *clock_max = clocks.max * 10;
79e53945
JB		 645 return true;
646}
647
ea5b213a 648static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 649 u16 outputs)
650{
32aad86f
CW		 651 return intel_sdvo_set_value(intel_sdvo,
652 SDVO_CMD_SET_TARGET_OUTPUT,
653 &outputs, sizeof(outputs));
79e53945
JB		 654}
655
ea5b213a 656static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 657 struct intel_sdvo_dtd *dtd)
658{
32aad86f
CW		 659 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
660 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 661}
662
ea5b213a 663static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 664 struct intel_sdvo_dtd *dtd)
665{
ea5b213a 666 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 667 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
668}
669
ea5b213a 670static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 671 struct intel_sdvo_dtd *dtd)
672{
ea5b213a 673 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 674 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
675}
676
e2f0ba97 677static bool
ea5b213a 678intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 679 uint16_t clock,
680 uint16_t width,
681 uint16_t height)
682{
683 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 684
e642c6f1 685 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 686 args.clock = clock;
687 args.width = width;
688 args.height = height;
e642c6f1 689 args.interlace = 0;
12682a97 690
ea5b213a
CW		 691 if (intel_sdvo->is_lvds &&
692 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
693 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 694 args.scaled = 1;
695
32aad86f
CW		 696 return intel_sdvo_set_value(intel_sdvo,
697 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
698 &args, sizeof(args));
e2f0ba97
JB		 699}
700
ea5b213a 701static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 702 struct intel_sdvo_dtd *dtd)
703{
32aad86f
CW		 704 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
705 &dtd->part1, sizeof(dtd->part1)) &&
706 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
707 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 708}
79e53945 709
ea5b213a 710static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 711{
32aad86f 712 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 713}
714
e2f0ba97 715static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 716 const struct drm_display_mode *mode)
79e53945 717{
e2f0ba97
JB		 718 uint16_t width, height;
719 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
720 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 721
722 width = mode->crtc_hdisplay;
723 height = mode->crtc_vdisplay;
724
725 /* do some mode translations */
726 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
727 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
728
729 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
730 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
731
732 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
733 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
734
e2f0ba97
JB		 735 dtd->part1.clock = mode->clock / 10;
736 dtd->part1.h_active = width & 0xff;
737 dtd->part1.h_blank = h_blank_len & 0xff;
738 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 739 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 740 dtd->part1.v_active = height & 0xff;
741 dtd->part1.v_blank = v_blank_len & 0xff;
742 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 743 ((v_blank_len >> 8) & 0xf);
744
171a9e96 745 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 746 dtd->part2.h_sync_width = h_sync_len & 0xff;
747 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 748 (v_sync_len & 0xf);
e2f0ba97 749 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 750 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
751 ((v_sync_len & 0x30) >> 4);
752
e2f0ba97 753 dtd->part2.dtd_flags = 0x18;
79e53945 754 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 755 dtd->part2.dtd_flags |= 0x2;
79e53945 756 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 757 dtd->part2.dtd_flags |= 0x4;
758
759 dtd->part2.sdvo_flags = 0;
760 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
761 dtd->part2.reserved = 0;
762}
763
764static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 765 const struct intel_sdvo_dtd *dtd)
e2f0ba97 766{
e2f0ba97
JB		 767 mode->hdisplay = dtd->part1.h_active;
768 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
769 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 770 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 771 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
772 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
773 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
774 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
775
776 mode->vdisplay = dtd->part1.v_active;
777 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
778 mode->vsync_start = mode->vdisplay;
779 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 780 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 781 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
782 mode->vsync_end = mode->vsync_start +
783 (dtd->part2.v_sync_off_width & 0xf);
784 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
785 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
786 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
787
788 mode->clock = dtd->part1.clock * 10;
789
171a9e96 790 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 791 if (dtd->part2.dtd_flags & 0x2)
792 mode->flags |= DRM_MODE_FLAG_PHSYNC;
793 if (dtd->part2.dtd_flags & 0x4)
794 mode->flags |= DRM_MODE_FLAG_PVSYNC;
795}
796
e27d8538 797static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 798{
e27d8538 799 struct intel_sdvo_encode encode;
e2f0ba97 800
e27d8538
CW		 801 return intel_sdvo_get_value(intel_sdvo,
802 SDVO_CMD_GET_SUPP_ENCODE,
803 &encode, sizeof(encode));
e2f0ba97
JB		 804}
805
ea5b213a 806static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 807 uint8_t mode)
e2f0ba97 808{
32aad86f 809 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 810}
811
ea5b213a 812static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 813 uint8_t mode)
814{
32aad86f 815 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 816}
817
818#if 0
ea5b213a 819static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 820{
821 int i, j;
822 uint8_t set_buf_index[2];
823 uint8_t av_split;
824 uint8_t buf_size;
825 uint8_t buf[48];
826 uint8_t *pos;
827
32aad86f 828 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 829
830 for (i = 0; i <= av_split; i++) {
831 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 832 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 833 set_buf_index, 2);
c751ce4f
EA		 834 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
835 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 836
837 pos = buf;
838 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 839 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 840 NULL, 0);
c751ce4f 841 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 842 pos += 8;
843 }
844 }
845}
846#endif
847
3c17fe4b 848static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 849{
850 struct dip_infoframe avi_if = {
851 .type = DIP_TYPE_AVI,
3c17fe4b 852 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 853 .len = DIP_LEN_AVI,
854 };
3c17fe4b
DH		 855 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
856 uint8_t set_buf_index[2] = { 1, 0 };
857 uint64_t *data = (uint64_t *)&avi_if;
858 unsigned i;
859
860 intel_dip_infoframe_csum(&avi_if);
861
862 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX,
863 set_buf_index, 2))
864 return false;
865
866 for (i = 0; i < sizeof(avi_if); i += 8) {
867 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA,
868 data, 8))
869 return false;
870 data++;
871 }
e2f0ba97 872
3c17fe4b
DH		 873 return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE,
874 &tx_rate, 1);
e2f0ba97
JB		 875}
876
32aad86f 877static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 878{
ce6feabd 879 struct intel_sdvo_tv_format format;
40039750 880 uint32_t format_map;
ce6feabd 881
40039750 882 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 883 memset(&format, 0, sizeof(format));
32aad86f 884 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 885
32aad86f
CW		 886 BUILD_BUG_ON(sizeof(format) != 6);
887 return intel_sdvo_set_value(intel_sdvo,
888 SDVO_CMD_SET_TV_FORMAT,
889 &format, sizeof(format));
7026d4ac
ZW		 890}
891
32aad86f
CW		 892static bool
893intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
894 struct drm_display_mode *mode)
e2f0ba97 895{
32aad86f 896 struct intel_sdvo_dtd output_dtd;
79e53945 897
32aad86f
CW		 898 if (!intel_sdvo_set_target_output(intel_sdvo,
899 intel_sdvo->attached_output))
900 return false;
e2f0ba97 901
32aad86f
CW		 902 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
903 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
904 return false;
e2f0ba97 905
32aad86f
CW		 906 return true;
907}
908
909static bool
910intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
911 struct drm_display_mode *mode,
912 struct drm_display_mode *adjusted_mode)
913{
32aad86f
CW		 914 /* Reset the input timing to the screen. Assume always input 0. */
915 if (!intel_sdvo_set_target_input(intel_sdvo))
916 return false;
e2f0ba97 917
32aad86f
CW		 918 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
919 mode->clock / 10,
920 mode->hdisplay,
921 mode->vdisplay))
922 return false;
e2f0ba97 923
32aad86f 924 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
6c9547ff 925 &intel_sdvo->input_dtd))
32aad86f 926 return false;
e2f0ba97 927
6c9547ff 928 intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
79e53945 929
32aad86f 930 drm_mode_set_crtcinfo(adjusted_mode, 0);
32aad86f
CW		 931 return true;
932}
12682a97 933
32aad86f
CW		 934static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
935 struct drm_display_mode *mode,
936 struct drm_display_mode *adjusted_mode)
937{
890f3359 938 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 939 int multiplier;
12682a97 940
32aad86f
CW		 941 /* We need to construct preferred input timings based on our
942 * output timings. To do that, we have to set the output
943 * timings, even though this isn't really the right place in
944 * the sequence to do it. Oh well.
945 */
946 if (intel_sdvo->is_tv) {
947 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
948 return false;
12682a97 949
c74696b9
PR		 950 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
951 mode,
952 adjusted_mode);
ea5b213a 953 } else if (intel_sdvo->is_lvds) {
32aad86f 954 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 955 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 956 return false;
12682a97 957
c74696b9
PR		 958 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
959 mode,
960 adjusted_mode);
e2f0ba97 961 }
32aad86f
CW		 962
963 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 964 * SDVO device will factor out the multiplier during mode_set.
32aad86f 965 */
6c9547ff
CW		 966 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
967 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 968
e2f0ba97
JB		 969 return true;
970}
971
972static void intel_sdvo_mode_set(struct drm_encoder *encoder,
973 struct drm_display_mode *mode,
974 struct drm_display_mode *adjusted_mode)
975{
976 struct drm_device *dev = encoder->dev;
977 struct drm_i915_private *dev_priv = dev->dev_private;
978 struct drm_crtc *crtc = encoder->crtc;
979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 980 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 981 u32 sdvox;
e2f0ba97
JB		 982 struct intel_sdvo_in_out_map in_out;
983 struct intel_sdvo_dtd input_dtd;
6c9547ff
CW		 984 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
985 int rate;
e2f0ba97
JB		 986
987 if (!mode)
988 return;
989
990 /* First, set the input mapping for the first input to our controlled
991 * output. This is only correct if we're a single-input device, in
992 * which case the first input is the output from the appropriate SDVO
993 * channel on the motherboard. In a two-input device, the first input
994 * will be SDVOB and the second SDVOC.
995 */
ea5b213a 996 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 997 in_out.in1 = 0;
998
c74696b9
PR		 999 intel_sdvo_set_value(intel_sdvo,
1000 SDVO_CMD_SET_IN_OUT_MAP,
1001 &in_out, sizeof(in_out));
e2f0ba97 1002
6c9547ff
CW		 1003 /* Set the output timings to the screen */
1004 if (!intel_sdvo_set_target_output(intel_sdvo,
1005 intel_sdvo->attached_output))
1006 return;
e2f0ba97 1007
7026d4ac 1008 /* We have tried to get input timing in mode_fixup, and filled into
6c9547ff 1009 * adjusted_mode.
e2f0ba97 1010 */
6c9547ff
CW		 1011 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
1012 input_dtd = intel_sdvo->input_dtd;
1013 } else {
e2f0ba97 1014 /* Set the output timing to the screen */
32aad86f
CW		 1015 if (!intel_sdvo_set_target_output(intel_sdvo,
1016 intel_sdvo->attached_output))
1017 return;
1018
6c9547ff 1019 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c74696b9 1020 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
e2f0ba97 1021 }
79e53945
JB		 1022
1023 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1024 if (!intel_sdvo_set_target_input(intel_sdvo))
1025 return;
79e53945 1026
da79de97 1027 if (intel_sdvo->has_hdmi_monitor &&
3c17fe4b 1028 !intel_sdvo_set_avi_infoframe(intel_sdvo))
6c9547ff 1029 return;
7026d4ac 1030
6c9547ff
CW		 1031 if (intel_sdvo->is_tv &&
1032 !intel_sdvo_set_tv_format(intel_sdvo))
1033 return;
e2f0ba97 1034
c74696b9 1035 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
79e53945 1036
6c9547ff
CW		 1037 switch (pixel_multiplier) {
1038 default:
32aad86f
CW		 1039 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1040 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1041 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1042 }
32aad86f
CW		 1043 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1044 return;
79e53945
JB		 1045
1046 /* Set the SDVO control regs. */
a6c45cf0 1047 if (INTEL_INFO(dev)->gen >= 4) {
6c9547ff 1048 sdvox = SDVO_BORDER_ENABLE;
81a14b46
AJ		 1049 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1050 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1051 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1052 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
e2f0ba97 1053 } else {
6c9547ff 1054 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1055 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1056 case SDVOB:
1057 sdvox &= SDVOB_PRESERVE_MASK;
1058 break;
1059 case SDVOC:
1060 sdvox &= SDVOC_PRESERVE_MASK;
1061 break;
1062 }
1063 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1064 }
79e53945
JB		 1065 if (intel_crtc->pipe == 1)
1066 sdvox |= SDVO_PIPE_B_SELECT;
da79de97 1067 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1068 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1069
a6c45cf0 1070 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1071 /* done in crtc_mode_set as the dpll_md reg must be written early */
1072 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1073 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1074 } else {
6c9547ff 1075 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1076 }
1077
6c9547ff 1078 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL)
12682a97 1079 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1080 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1081}
1082
1083static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1084{
1085 struct drm_device *dev = encoder->dev;
1086 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 1087 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
9d0498a2 1088 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1089 u32 temp;
1090
1091 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1092 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1093 if (0)
ea5b213a 1094 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1095
1096 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1097 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1098 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1099 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1100 }
1101 }
1102 } else {
1103 bool input1, input2;
1104 int i;
1105 u8 status;
1106
ea5b213a 1107 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1108 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1109 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1110 for (i = 0; i < 2; i++)
9d0498a2 1111 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1112
32aad86f 1113 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1114 /* Warn if the device reported failure to sync.
1115 * A lot of SDVO devices fail to notify of sync, but it's
1116 * a given it the status is a success, we succeeded.
1117 */
1118 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1119 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1120 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1121 }
1122
1123 if (0)
ea5b213a
CW		 1124 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1125 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1126 }
1127 return;
1128}
1129
79e53945
JB		 1130static int intel_sdvo_mode_valid(struct drm_connector *connector,
1131 struct drm_display_mode *mode)
1132{
df0e9248 1133 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1134
1135 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1136 return MODE_NO_DBLESCAN;
1137
ea5b213a 1138 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1139 return MODE_CLOCK_LOW;
1140
ea5b213a 1141 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1142 return MODE_CLOCK_HIGH;
1143
8545423a 1144 if (intel_sdvo->is_lvds) {
ea5b213a 1145 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1146 return MODE_PANEL;
1147
ea5b213a 1148 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1149 return MODE_PANEL;
1150 }
1151
79e53945
JB		 1152 return MODE_OK;
1153}
1154
ea5b213a 1155static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1156{
e957d772
CW		 1157 if (!intel_sdvo_get_value(intel_sdvo,
1158 SDVO_CMD_GET_DEVICE_CAPS,
1159 caps, sizeof(*caps)))
1160 return false;
1161
1162 DRM_DEBUG_KMS("SDVO capabilities:\n"
1163 " vendor_id: %d\n"
1164 " device_id: %d\n"
1165 " device_rev_id: %d\n"
1166 " sdvo_version_major: %d\n"
1167 " sdvo_version_minor: %d\n"
1168 " sdvo_inputs_mask: %d\n"
1169 " smooth_scaling: %d\n"
1170 " sharp_scaling: %d\n"
1171 " up_scaling: %d\n"
1172 " down_scaling: %d\n"
1173 " stall_support: %d\n"
1174 " output_flags: %d\n",
1175 caps->vendor_id,
1176 caps->device_id,
1177 caps->device_rev_id,
1178 caps->sdvo_version_major,
1179 caps->sdvo_version_minor,
1180 caps->sdvo_inputs_mask,
1181 caps->smooth_scaling,
1182 caps->sharp_scaling,
1183 caps->up_scaling,
1184 caps->down_scaling,
1185 caps->stall_support,
1186 caps->output_flags);
1187
1188 return true;
79e53945
JB		 1189}
1190
d2a82a6f
ZW		 1191/* No use! */
1192#if 0
79e53945
JB		 1193struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1194{
1195 struct drm_connector *connector = NULL;
ea5b213a
CW		 1196 struct intel_sdvo *iout = NULL;
1197 struct intel_sdvo *sdvo;
79e53945
JB		 1198
1199 /* find the sdvo connector */
1200 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
ea5b213a 1201 iout = to_intel_sdvo(connector);
79e53945
JB		 1202
1203 if (iout->type != INTEL_OUTPUT_SDVO)
1204 continue;
1205
1206 sdvo = iout->dev_priv;
1207
c751ce4f 1208 if (sdvo->sdvo_reg == SDVOB && sdvoB)
79e53945
JB		 1209 return connector;
1210
c751ce4f 1211 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
79e53945
JB		 1212 return connector;
1213
1214 }
1215
1216 return NULL;
1217}
1218
1219int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1220{
1221 u8 response[2];
1222 u8 status;
ea5b213a 1223 struct intel_sdvo *intel_sdvo;
8a4c47f3 1224 DRM_DEBUG_KMS("\n");
79e53945
JB		 1225
1226 if (!connector)
1227 return 0;
1228
ea5b213a 1229 intel_sdvo = to_intel_sdvo(connector);
79e53945 1230
32aad86f
CW		 1231 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1232 &response, 2) && response[0];
79e53945
JB		 1233}
1234
1235void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1236{
1237 u8 response[2];
1238 u8 status;
ea5b213a 1239 struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
79e53945 1240
ea5b213a
CW		 1241 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1242 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945
JB		 1243
1244 if (on) {
ea5b213a
CW		 1245 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1246 status = intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1247
ea5b213a 1248 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1249 } else {
1250 response[0] = 0;
1251 response[1] = 0;
ea5b213a 1252 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1253 }
1254
ea5b213a
CW		 1255 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1256 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1257}
d2a82a6f 1258#endif
79e53945 1259
fb7a46f3 1260static bool
ea5b213a 1261intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1262{
fb7a46f3 1263 int caps = 0;
1264
ea5b213a 1265 if (intel_sdvo->caps.output_flags &
fb7a46f3 1266 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1267 caps++;
ea5b213a 1268 if (intel_sdvo->caps.output_flags &
fb7a46f3 1269 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1270 caps++;
ea5b213a 1271 if (intel_sdvo->caps.output_flags &
19e1f888 1272 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
fb7a46f3 1273 caps++;
ea5b213a 1274 if (intel_sdvo->caps.output_flags &
fb7a46f3 1275 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1276 caps++;
ea5b213a 1277 if (intel_sdvo->caps.output_flags &
fb7a46f3 1278 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1279 caps++;
1280
ea5b213a 1281 if (intel_sdvo->caps.output_flags &
fb7a46f3 1282 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1283 caps++;
1284
ea5b213a 1285 if (intel_sdvo->caps.output_flags &
fb7a46f3 1286 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1287 caps++;
1288
1289 return (caps > 1);
1290}
1291
f899fc64 1292static struct edid *
e957d772 1293intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1294{
e957d772
CW		 1295 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1296 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1297}
1298
ff482d83
CW		 1299/* Mac mini hack -- use the same DDC as the analog connector */
1300static struct edid *
1301intel_sdvo_get_analog_edid(struct drm_connector *connector)
1302{
f899fc64 1303 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1304
0c1dab89
CW		 1305 return drm_get_edid(connector,
1306 &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
ff482d83
CW		 1307}
1308
2b8d33f7 1309enum drm_connector_status
149c36a3 1310intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
9dff6af8 1311{
df0e9248 1312 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1313 enum drm_connector_status status;
1314 struct edid *edid;
9dff6af8 1315
e957d772 1316 edid = intel_sdvo_get_edid(connector);
57cdaf90 1317
ea5b213a 1318 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1319 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1320
7c3f0a27
ZY		 1321 /*
1322 * Don't use the 1 as the argument of DDC bus switch to get
1323 * the EDID. It is used for SDVO SPD ROM.
1324 */
9d1a903d 1325 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1326 intel_sdvo->ddc_bus = ddc;
1327 edid = intel_sdvo_get_edid(connector);
1328 if (edid)
7c3f0a27 1329 break;
7c3f0a27 1330 }
e957d772
CW		 1331 /*
1332 * If we found the EDID on the other bus,
1333 * assume that is the correct DDC bus.
1334 */
1335 if (edid == NULL)
1336 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1337 }
9d1a903d
CW		 1338
1339 /*
1340 * When there is no edid and no monitor is connected with VGA
1341 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1342 */
ff482d83
CW		 1343 if (edid == NULL)
1344 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1345
2f551c84 1346 status = connector_status_unknown;
9dff6af8 1347 if (edid != NULL) {
149c36a3 1348 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1349 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1350 status = connector_status_connected;
da79de97
CW		 1351 if (intel_sdvo->is_hdmi) {
1352 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1353 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1354 }
9d1a903d 1355 }
149c36a3 1356 connector->display_info.raw_edid = NULL;
9d1a903d
CW		 1357 kfree(edid);
1358 }
7f36e7ed
CW		 1359
1360 if (status == connector_status_connected) {
1361 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1362 if (intel_sdvo_connector->force_audio)
da79de97 1363 intel_sdvo->has_hdmi_audio = intel_sdvo_connector->force_audio > 0;
7f36e7ed
CW		 1364 }
1365
2b8d33f7 1366 return status;
9dff6af8
ML		 1367}
1368
7b334fcb 1369static enum drm_connector_status
930a9e28 1370intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1371{
fb7a46f3 1372 uint16_t response;
df0e9248 1373 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1374 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1375 enum drm_connector_status ret;
79e53945 1376
32aad86f 1377 if (!intel_sdvo_write_cmd(intel_sdvo,
e957d772 1378 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
32aad86f 1379 return connector_status_unknown;
ba84cd1f
CW		 1380
1381 /* add 30ms delay when the output type might be TV */
1382 if (intel_sdvo->caps.output_flags &
1383 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
d09c23de 1384 mdelay(30);
ba84cd1f 1385
32aad86f
CW		 1386 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1387 return connector_status_unknown;
79e53945 1388
e957d772
CW		 1389 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1390 response & 0xff, response >> 8,
1391 intel_sdvo_connector->output_flag);
e2f0ba97 1392
fb7a46f3 1393 if (response == 0)
79e53945 1394 return connector_status_disconnected;
fb7a46f3 1395
ea5b213a 1396 intel_sdvo->attached_output = response;
14571b4c 1397
615fb93f 1398 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1399 ret = connector_status_disconnected;
149c36a3
AJ		 1400 else if (response & SDVO_TMDS_MASK)
1401 ret = intel_sdvo_hdmi_sink_detect(connector);
14571b4c
ZW		 1402 else
1403 ret = connector_status_connected;
1404
1405 /* May update encoder flag for like clock for SDVO TV, etc.*/
1406 if (ret == connector_status_connected) {
ea5b213a
CW		 1407 intel_sdvo->is_tv = false;
1408 intel_sdvo->is_lvds = false;
1409 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1410
1411 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1412 intel_sdvo->is_tv = true;
1413 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1414 }
1415 if (response & SDVO_LVDS_MASK)
8545423a 1416 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1417 }
14571b4c
ZW		 1418
1419 return ret;
79e53945
JB		 1420}
1421
e2f0ba97 1422static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1423{
ff482d83 1424 struct edid *edid;
79e53945
JB		 1425
1426 /* set the bus switch and get the modes */
e957d772 1427 edid = intel_sdvo_get_edid(connector);
79e53945 1428
57cdaf90
KP		 1429 /*
1430 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1431 * link between analog and digital outputs. So, if the regular SDVO
1432 * DDC fails, check to see if the analog output is disconnected, in
1433 * which case we'll look there for the digital DDC data.
e2f0ba97 1434 */
f899fc64
CW		 1435 if (edid == NULL)
1436 edid = intel_sdvo_get_analog_edid(connector);
1437
ff482d83 1438 if (edid != NULL) {
0c1dab89
CW		 1439 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1440 drm_mode_connector_update_edid_property(connector, edid);
1441 drm_add_edid_modes(connector, edid);
1442 }
ff482d83
CW		 1443 connector->display_info.raw_edid = NULL;
1444 kfree(edid);
e2f0ba97 1445 }
e2f0ba97
JB		 1446}
1447
1448/*
1449 * Set of SDVO TV modes.
1450 * Note! This is in reply order (see loop in get_tv_modes).
1451 * XXX: all 60Hz refresh?
1452 */
1453struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1454 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1455 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1457 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1458 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1460 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1461 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1463 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1464 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1466 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1467 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1469 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1470 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1472 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1473 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1475 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1476 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1478 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1479 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1481 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1482 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1484 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1485 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1487 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1488 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1490 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1491 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1493 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1494 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1496 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1497 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1499 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1500 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1502 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1503 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1505 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1506 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1508 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1509 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1511};
1512
1513static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1514{
df0e9248 1515 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1516 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1517 uint32_t reply = 0, format_map = 0;
1518 int i;
e2f0ba97
JB		 1519
1520 /* Read the list of supported input resolutions for the selected TV
1521 * format.
1522 */
40039750 1523 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1524 memcpy(&tv_res, &format_map,
32aad86f 1525 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1526
32aad86f
CW		 1527 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1528 return;
ce6feabd 1529
32aad86f 1530 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1531 if (!intel_sdvo_write_cmd(intel_sdvo,
1532 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1533 &tv_res, sizeof(tv_res)))
1534 return;
1535 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1536 return;
1537
1538 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1539 if (reply & (1 << i)) {
1540 struct drm_display_mode *nmode;
1541 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1542 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1543 if (nmode)
1544 drm_mode_probed_add(connector, nmode);
1545 }
e2f0ba97
JB		 1546}
1547
7086c87f
ML		 1548static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1549{
df0e9248 1550 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1551 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1552 struct drm_display_mode *newmode;
7086c87f
ML		 1553
1554 /*
1555 * Attempt to get the mode list from DDC.
1556 * Assume that the preferred modes are
1557 * arranged in priority order.
1558 */
f899fc64 1559 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1560 if (list_empty(&connector->probed_modes) == false)
12682a97 1561 goto end;
7086c87f
ML		 1562
1563 /* Fetch modes from VBT */
1564 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1565 newmode = drm_mode_duplicate(connector->dev,
1566 dev_priv->sdvo_lvds_vbt_mode);
1567 if (newmode != NULL) {
1568 /* Guarantee the mode is preferred */
1569 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1570 DRM_MODE_TYPE_DRIVER);
1571 drm_mode_probed_add(connector, newmode);
1572 }
1573 }
12682a97 1574
1575end:
1576 list_for_each_entry(newmode, &connector->probed_modes, head) {
1577 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1578 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1579 drm_mode_duplicate(connector->dev, newmode);
6c9547ff
CW		 1580
1581 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
1582 0);
1583
8545423a 1584 intel_sdvo->is_lvds = true;
12682a97 1585 break;
1586 }
1587 }
1588
7086c87f
ML		 1589}
1590
e2f0ba97
JB		 1591static int intel_sdvo_get_modes(struct drm_connector *connector)
1592{
615fb93f 1593 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1594
615fb93f 1595 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1596 intel_sdvo_get_tv_modes(connector);
615fb93f 1597 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1598 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1599 else
1600 intel_sdvo_get_ddc_modes(connector);
1601
32aad86f 1602 return !list_empty(&connector->probed_modes);
79e53945
JB		 1603}
1604
fcc8d672
CW		 1605static void
1606intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1607{
615fb93f 1608 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1609 struct drm_device *dev = connector->dev;
1610
c5521706
CW		 1611 if (intel_sdvo_connector->left)
1612 drm_property_destroy(dev, intel_sdvo_connector->left);
1613 if (intel_sdvo_connector->right)
1614 drm_property_destroy(dev, intel_sdvo_connector->right);
1615 if (intel_sdvo_connector->top)
1616 drm_property_destroy(dev, intel_sdvo_connector->top);
1617 if (intel_sdvo_connector->bottom)
1618 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1619 if (intel_sdvo_connector->hpos)
1620 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1621 if (intel_sdvo_connector->vpos)
1622 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1623 if (intel_sdvo_connector->saturation)
1624 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1625 if (intel_sdvo_connector->contrast)
1626 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1627 if (intel_sdvo_connector->hue)
1628 drm_property_destroy(dev, intel_sdvo_connector->hue);
1629 if (intel_sdvo_connector->sharpness)
1630 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1631 if (intel_sdvo_connector->flicker_filter)
1632 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1633 if (intel_sdvo_connector->flicker_filter_2d)
1634 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1635 if (intel_sdvo_connector->flicker_filter_adaptive)
1636 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1637 if (intel_sdvo_connector->tv_luma_filter)
1638 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1639 if (intel_sdvo_connector->tv_chroma_filter)
1640 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1641 if (intel_sdvo_connector->dot_crawl)
1642 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1643 if (intel_sdvo_connector->brightness)
1644 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1645}
1646
79e53945
JB		 1647static void intel_sdvo_destroy(struct drm_connector *connector)
1648{
615fb93f 1649 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1650
c5521706 1651 if (intel_sdvo_connector->tv_format)
ce6feabd 1652 drm_property_destroy(connector->dev,
c5521706 1653 intel_sdvo_connector->tv_format);
b9219c5e 1654
d2a82a6f 1655 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1656 drm_sysfs_connector_remove(connector);
1657 drm_connector_cleanup(connector);
d2a82a6f 1658 kfree(connector);
79e53945
JB		 1659}
1660
ce6feabd
ZY		 1661static int
1662intel_sdvo_set_property(struct drm_connector *connector,
1663 struct drm_property *property,
1664 uint64_t val)
1665{
df0e9248 1666 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1667 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e 1668 uint16_t temp_value;
32aad86f
CW		 1669 uint8_t cmd;
1670 int ret;
ce6feabd
ZY		 1671
1672 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1673 if (ret)
1674 return ret;
ce6feabd 1675
7f36e7ed
CW		 1676 if (property == intel_sdvo_connector->force_audio_property) {
1677 if (val == intel_sdvo_connector->force_audio)
1678 return 0;
1679
1680 intel_sdvo_connector->force_audio = val;
1681
da79de97 1682 if (val > 0 && intel_sdvo->has_hdmi_audio)
7f36e7ed 1683 return 0;
da79de97 1684 if (val < 0 && !intel_sdvo->has_hdmi_audio)
7f36e7ed
CW		 1685 return 0;
1686
da79de97 1687 intel_sdvo->has_hdmi_audio = val > 0;
7f36e7ed
CW		 1688 goto done;
1689 }
1690
c5521706
CW		 1691#define CHECK_PROPERTY(name, NAME) \
1692 if (intel_sdvo_connector->name == property) { \
1693 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1694 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1695 cmd = SDVO_CMD_SET_##NAME; \
1696 intel_sdvo_connector->cur_##name = temp_value; \
1697 goto set_value; \
1698 }
1699
1700 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1701 if (val >= TV_FORMAT_NUM)
1702 return -EINVAL;
1703
40039750 1704 if (intel_sdvo->tv_format_index ==
615fb93f 1705 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1706 return 0;
ce6feabd 1707
40039750 1708 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1709 goto done;
32aad86f 1710 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1711 temp_value = val;
c5521706 1712 if (intel_sdvo_connector->left == property) {
b9219c5e 1713 drm_connector_property_set_value(connector,
c5521706 1714 intel_sdvo_connector->right, val);
615fb93f 1715 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1716 return 0;
b9219c5e 1717
615fb93f
CW		 1718 intel_sdvo_connector->left_margin = temp_value;
1719 intel_sdvo_connector->right_margin = temp_value;
1720 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1721 intel_sdvo_connector->left_margin;
b9219c5e 1722 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1723 goto set_value;
1724 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1725 drm_connector_property_set_value(connector,
c5521706 1726 intel_sdvo_connector->left, val);
615fb93f 1727 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1728 return 0;
b9219c5e 1729
615fb93f
CW		 1730 intel_sdvo_connector->left_margin = temp_value;
1731 intel_sdvo_connector->right_margin = temp_value;
1732 temp_value = intel_sdvo_connector->max_hscan -
1733 intel_sdvo_connector->left_margin;
b9219c5e 1734 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1735 goto set_value;
1736 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1737 drm_connector_property_set_value(connector,
c5521706 1738 intel_sdvo_connector->bottom, val);
615fb93f 1739 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1740 return 0;
b9219c5e 1741
615fb93f
CW		 1742 intel_sdvo_connector->top_margin = temp_value;
1743 intel_sdvo_connector->bottom_margin = temp_value;
1744 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1745 intel_sdvo_connector->top_margin;
b9219c5e 1746 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1747 goto set_value;
1748 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1749 drm_connector_property_set_value(connector,
c5521706 1750 intel_sdvo_connector->top, val);
615fb93f 1751 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1752 return 0;
1753
615fb93f
CW		 1754 intel_sdvo_connector->top_margin = temp_value;
1755 intel_sdvo_connector->bottom_margin = temp_value;
1756 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1757 intel_sdvo_connector->top_margin;
b9219c5e 1758 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1759 goto set_value;
1760 }
1761 CHECK_PROPERTY(hpos, HPOS)
1762 CHECK_PROPERTY(vpos, VPOS)
1763 CHECK_PROPERTY(saturation, SATURATION)
1764 CHECK_PROPERTY(contrast, CONTRAST)
1765 CHECK_PROPERTY(hue, HUE)
1766 CHECK_PROPERTY(brightness, BRIGHTNESS)
1767 CHECK_PROPERTY(sharpness, SHARPNESS)
1768 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1769 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1770 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1771 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1772 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1773 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1774 }
b9219c5e 1775
c5521706 1776 return -EINVAL; /* unknown property */
b9219c5e 1777
c5521706
CW		 1778set_value:
1779 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1780 return -EIO;
b9219c5e 1781
b9219c5e 1782
c5521706 1783done:
df0e9248
CW		 1784 if (intel_sdvo->base.base.crtc) {
1785 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1786 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1787 crtc->y, crtc->fb);
1788 }
1789
32aad86f 1790 return 0;
c5521706 1791#undef CHECK_PROPERTY
ce6feabd
ZY		 1792}
1793
79e53945
JB		 1794static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1795 .dpms = intel_sdvo_dpms,
1796 .mode_fixup = intel_sdvo_mode_fixup,
1797 .prepare = intel_encoder_prepare,
1798 .mode_set = intel_sdvo_mode_set,
1799 .commit = intel_encoder_commit,
1800};
1801
1802static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1803 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1804 .detect = intel_sdvo_detect,
1805 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1806 .set_property = intel_sdvo_set_property,
79e53945
JB		 1807 .destroy = intel_sdvo_destroy,
1808};
1809
1810static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1811 .get_modes = intel_sdvo_get_modes,
1812 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1813 .best_encoder = intel_best_encoder,
79e53945
JB		 1814};
1815
b358d0a6 1816static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1817{
890f3359 1818 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1819
ea5b213a 1820 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1821 drm_mode_destroy(encoder->dev,
ea5b213a 1822 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1823
e957d772 1824 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 1825 intel_encoder_destroy(encoder);
79e53945
JB		 1826}
1827
1828static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1829 .destroy = intel_sdvo_enc_destroy,
1830};
1831
b66d8424
CW		 1832static void
1833intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1834{
1835 uint16_t mask = 0;
1836 unsigned int num_bits;
1837
1838 /* Make a mask of outputs less than or equal to our own priority in the
1839 * list.
1840 */
1841 switch (sdvo->controlled_output) {
1842 case SDVO_OUTPUT_LVDS1:
1843 mask |= SDVO_OUTPUT_LVDS1;
1844 case SDVO_OUTPUT_LVDS0:
1845 mask |= SDVO_OUTPUT_LVDS0;
1846 case SDVO_OUTPUT_TMDS1:
1847 mask |= SDVO_OUTPUT_TMDS1;
1848 case SDVO_OUTPUT_TMDS0:
1849 mask |= SDVO_OUTPUT_TMDS0;
1850 case SDVO_OUTPUT_RGB1:
1851 mask |= SDVO_OUTPUT_RGB1;
1852 case SDVO_OUTPUT_RGB0:
1853 mask |= SDVO_OUTPUT_RGB0;
1854 break;
1855 }
1856
1857 /* Count bits to find what number we are in the priority list. */
1858 mask &= sdvo->caps.output_flags;
1859 num_bits = hweight16(mask);
1860 /* If more than 3 outputs, default to DDC bus 3 for now. */
1861 if (num_bits > 3)
1862 num_bits = 3;
1863
1864 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1865 sdvo->ddc_bus = 1 << num_bits;
1866}
79e53945 1867
e2f0ba97
JB		 1868/**
1869 * Choose the appropriate DDC bus for control bus switch command for this
1870 * SDVO output based on the controlled output.
1871 *
1872 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1873 * outputs, then LVDS outputs.
1874 */
1875static void
b1083333 1876intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1877 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1878{
b1083333 1879 struct sdvo_device_mapping *mapping;
e2f0ba97 1880
b1083333
AJ		 1881 if (IS_SDVOB(reg))
1882 mapping = &(dev_priv->sdvo_mappings[0]);
1883 else
1884 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1885
b66d8424
CW		 1886 if (mapping->initialized)
1887 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1888 else
1889 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1890}
1891
e957d772
CW		 1892static void
1893intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
1894 struct intel_sdvo *sdvo, u32 reg)
1895{
1896 struct sdvo_device_mapping *mapping;
1897 u8 pin, speed;
1898
1899 if (IS_SDVOB(reg))
1900 mapping = &dev_priv->sdvo_mappings[0];
1901 else
1902 mapping = &dev_priv->sdvo_mappings[1];
1903
1904 pin = GMBUS_PORT_DPB;
1905 speed = GMBUS_RATE_1MHZ >> 8;
1906 if (mapping->initialized) {
1907 pin = mapping->i2c_pin;
1908 speed = mapping->i2c_speed;
1909 }
1910
1911 sdvo->i2c = &dev_priv->gmbus[pin].adapter;
1912 intel_gmbus_set_speed(sdvo->i2c, speed);
1913 intel_gmbus_force_bit(sdvo->i2c, true);
1914}
1915
e2f0ba97 1916static bool
e27d8538 1917intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1918{
e27d8538
CW		 1919 int is_hdmi;
1920
1921 if (!intel_sdvo_check_supp_encode(intel_sdvo))
1922 return false;
1923
1924 if (!intel_sdvo_set_target_output(intel_sdvo,
1925 device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1))
1926 return false;
1927
1928 is_hdmi = 0;
1929 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, &is_hdmi, 1))
1930 return false;
1931
1932 return !!is_hdmi;
e2f0ba97
JB		 1933}
1934
714605e4 1935static u8
c751ce4f 1936intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 1937{
1938 struct drm_i915_private *dev_priv = dev->dev_private;
1939 struct sdvo_device_mapping *my_mapping, *other_mapping;
1940
461ed3ca 1941 if (IS_SDVOB(sdvo_reg)) {
714605e4 1942 my_mapping = &dev_priv->sdvo_mappings[0];
1943 other_mapping = &dev_priv->sdvo_mappings[1];
1944 } else {
1945 my_mapping = &dev_priv->sdvo_mappings[1];
1946 other_mapping = &dev_priv->sdvo_mappings[0];
1947 }
1948
1949 /* If the BIOS described our SDVO device, take advantage of it. */
1950 if (my_mapping->slave_addr)
1951 return my_mapping->slave_addr;
1952
1953 /* If the BIOS only described a different SDVO device, use the
1954 * address that it isn't using.
1955 */
1956 if (other_mapping->slave_addr) {
1957 if (other_mapping->slave_addr == 0x70)
1958 return 0x72;
1959 else
1960 return 0x70;
1961 }
1962
1963 /* No SDVO device info is found for another DVO port,
1964 * so use mapping assumption we had before BIOS parsing.
1965 */
461ed3ca 1966 if (IS_SDVOB(sdvo_reg))
714605e4 1967 return 0x70;
1968 else
1969 return 0x72;
1970}
1971
14571b4c 1972static void
df0e9248
CW		 1973intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
1974 struct intel_sdvo *encoder)
14571b4c 1975{
df0e9248
CW		 1976 drm_connector_init(encoder->base.base.dev,
1977 &connector->base.base,
1978 &intel_sdvo_connector_funcs,
1979 connector->base.base.connector_type);
6070a4a9 1980
df0e9248
CW		 1981 drm_connector_helper_add(&connector->base.base,
1982 &intel_sdvo_connector_helper_funcs);
14571b4c 1983
df0e9248
CW		 1984 connector->base.base.interlace_allowed = 0;
1985 connector->base.base.doublescan_allowed = 0;
1986 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 1987
df0e9248
CW		 1988 intel_connector_attach_encoder(&connector->base, &encoder->base);
1989 drm_sysfs_connector_add(&connector->base.base);
14571b4c 1990}
6070a4a9 1991
7f36e7ed
CW		 1992static void
1993intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
1994{
1995 struct drm_device *dev = connector->base.base.dev;
1996
1997 connector->force_audio_property =
1998 drm_property_create(dev, DRM_MODE_PROP_RANGE, "force_audio", 2);
1999 if (connector->force_audio_property) {
2000 connector->force_audio_property->values[0] = -1;
2001 connector->force_audio_property->values[1] = 1;
2002 drm_connector_attach_property(&connector->base.base,
2003 connector->force_audio_property, 0);
2004 }
2005}
2006
fb7a46f3 2007static bool
ea5b213a 2008intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2009{
4ef69c7a 2010 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c
ZW		 2011 struct drm_connector *connector;
2012 struct intel_connector *intel_connector;
615fb93f 2013 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2014
615fb93f
CW		 2015 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2016 if (!intel_sdvo_connector)
14571b4c
ZW		 2017 return false;
2018
14571b4c 2019 if (device == 0) {
ea5b213a 2020 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2021 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2022 } else if (device == 1) {
ea5b213a 2023 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2024 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2025 }
2026
615fb93f 2027 intel_connector = &intel_sdvo_connector->base;
14571b4c 2028 connector = &intel_connector->base;
eb1f8e4f 2029 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2030 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2031 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2032
e27d8538 2033 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2034 /* enable hdmi encoding mode if supported */
ea5b213a
CW		 2035 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
2036 intel_sdvo_set_colorimetry(intel_sdvo,
14571b4c
ZW		 2037 SDVO_COLORIMETRY_RGB256);
2038 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
da79de97
CW		 2039
2040 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
e27d8538 2041 intel_sdvo->is_hdmi = true;
14571b4c 2042 }
ea5b213a
CW		 2043 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2044 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2045
df0e9248 2046 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c
ZW		 2047
2048 return true;
2049}
2050
2051static bool
ea5b213a 2052intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2053{
4ef69c7a
CW		 2054 struct drm_encoder *encoder = &intel_sdvo->base.base;
2055 struct drm_connector *connector;
2056 struct intel_connector *intel_connector;
2057 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2058
615fb93f
CW		 2059 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2060 if (!intel_sdvo_connector)
2061 return false;
14571b4c 2062
615fb93f 2063 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2064 connector = &intel_connector->base;
2065 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2066 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2067
4ef69c7a
CW		 2068 intel_sdvo->controlled_output |= type;
2069 intel_sdvo_connector->output_flag = type;
14571b4c 2070
4ef69c7a
CW		 2071 intel_sdvo->is_tv = true;
2072 intel_sdvo->base.needs_tv_clock = true;
2073 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2074
df0e9248 2075 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2076
4ef69c7a 2077 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2078 goto err;
14571b4c 2079
4ef69c7a 2080 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2081 goto err;
14571b4c 2082
4ef69c7a 2083 return true;
32aad86f
CW		 2084
2085err:
123d5c01 2086 intel_sdvo_destroy(connector);
32aad86f 2087 return false;
14571b4c
ZW		 2088}
2089
2090static bool
ea5b213a 2091intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2092{
4ef69c7a
CW		 2093 struct drm_encoder *encoder = &intel_sdvo->base.base;
2094 struct drm_connector *connector;
2095 struct intel_connector *intel_connector;
2096 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2097
615fb93f
CW		 2098 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2099 if (!intel_sdvo_connector)
2100 return false;
14571b4c 2101
615fb93f 2102 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2103 connector = &intel_connector->base;
eb1f8e4f 2104 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2105 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2106 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2107
2108 if (device == 0) {
2109 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2110 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2111 } else if (device == 1) {
2112 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2113 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2114 }
2115
2116 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2117 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2118
df0e9248
CW		 2119 intel_sdvo_connector_init(intel_sdvo_connector,
2120 intel_sdvo);
4ef69c7a 2121 return true;
14571b4c
ZW		 2122}
2123
2124static bool
ea5b213a 2125intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2126{
4ef69c7a
CW		 2127 struct drm_encoder *encoder = &intel_sdvo->base.base;
2128 struct drm_connector *connector;
2129 struct intel_connector *intel_connector;
2130 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2131
615fb93f
CW		 2132 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2133 if (!intel_sdvo_connector)
2134 return false;
14571b4c 2135
615fb93f
CW		 2136 intel_connector = &intel_sdvo_connector->base;
2137 connector = &intel_connector->base;
4ef69c7a
CW		 2138 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2139 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2140
2141 if (device == 0) {
2142 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2143 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2144 } else if (device == 1) {
2145 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2146 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2147 }
2148
2149 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2150 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2151
df0e9248 2152 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2153 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2154 goto err;
2155
2156 return true;
2157
2158err:
123d5c01 2159 intel_sdvo_destroy(connector);
32aad86f 2160 return false;
14571b4c
ZW		 2161}
2162
2163static bool
ea5b213a 2164intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2165{
ea5b213a
CW		 2166 intel_sdvo->is_tv = false;
2167 intel_sdvo->base.needs_tv_clock = false;
2168 intel_sdvo->is_lvds = false;
fb7a46f3 2169
14571b4c 2170 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2171
14571b4c 2172 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2173 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2174 return false;
2175
2176 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2177 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2178 return false;
2179
2180 /* TV has no XXX1 function block */
a1f4b7ff 2181 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2182 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2183 return false;
2184
2185 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2186 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2187 return false;
fb7a46f3 2188
14571b4c 2189 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2190 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2191 return false;
2192
2193 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2194 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2195 return false;
2196
2197 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2198 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2199 return false;
2200
2201 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2202 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2203 return false;
fb7a46f3 2204
14571b4c 2205 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2206 unsigned char bytes[2];
2207
ea5b213a
CW		 2208 intel_sdvo->controlled_output = 0;
2209 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2210 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2211 SDVO_NAME(intel_sdvo),
51c8b407 2212 bytes[0], bytes[1]);
14571b4c 2213 return false;
fb7a46f3 2214 }
ea5b213a 2215 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
fb7a46f3 2216
14571b4c 2217 return true;
fb7a46f3 2218}
2219
32aad86f
CW		 2220static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2221 struct intel_sdvo_connector *intel_sdvo_connector,
2222 int type)
ce6feabd 2223{
4ef69c7a 2224 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2225 struct intel_sdvo_tv_format format;
2226 uint32_t format_map, i;
ce6feabd 2227
32aad86f
CW		 2228 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2229 return false;
ce6feabd 2230
32aad86f
CW		 2231 if (!intel_sdvo_get_value(intel_sdvo,
2232 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2233 &format, sizeof(format)))
2234 return false;
ce6feabd 2235
32aad86f 2236 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2237
2238 if (format_map == 0)
32aad86f 2239 return false;
ce6feabd 2240
615fb93f 2241 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2242 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2243 if (format_map & (1 << i))
2244 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2245
2246
c5521706 2247 intel_sdvo_connector->tv_format =
32aad86f
CW		 2248 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2249 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2250 if (!intel_sdvo_connector->tv_format)
fcc8d672 2251 return false;
ce6feabd 2252
615fb93f 2253 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2254 drm_property_add_enum(
c5521706 2255 intel_sdvo_connector->tv_format, i,
40039750 2256 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2257
40039750 2258 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2259 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2260 intel_sdvo_connector->tv_format, 0);
32aad86f 2261 return true;
ce6feabd
ZY		 2262
2263}
2264
c5521706
CW		 2265#define ENHANCEMENT(name, NAME) do { \
2266 if (enhancements.name) { \
2267 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2268 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2269 return false; \
2270 intel_sdvo_connector->max_##name = data_value[0]; \
2271 intel_sdvo_connector->cur_##name = response; \
2272 intel_sdvo_connector->name = \
2273 drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
2274 if (!intel_sdvo_connector->name) return false; \
2275 intel_sdvo_connector->name->values[0] = 0; \
2276 intel_sdvo_connector->name->values[1] = data_value[0]; \
2277 drm_connector_attach_property(connector, \
2278 intel_sdvo_connector->name, \
2279 intel_sdvo_connector->cur_##name); \
2280 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2281 data_value[0], data_value[1], response); \
2282 } \
2283} while(0)
2284
2285static bool
2286intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2287 struct intel_sdvo_connector *intel_sdvo_connector,
2288 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2289{
4ef69c7a 2290 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2291 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2292 uint16_t response, data_value[2];
2293
c5521706
CW		 2294 /* when horizontal overscan is supported, Add the left/right property */
2295 if (enhancements.overscan_h) {
2296 if (!intel_sdvo_get_value(intel_sdvo,
2297 SDVO_CMD_GET_MAX_OVERSCAN_H,
2298 &data_value, 4))
2299 return false;
32aad86f 2300
c5521706
CW		 2301 if (!intel_sdvo_get_value(intel_sdvo,
2302 SDVO_CMD_GET_OVERSCAN_H,
2303 &response, 2))
2304 return false;
fcc8d672 2305
c5521706
CW		 2306 intel_sdvo_connector->max_hscan = data_value[0];
2307 intel_sdvo_connector->left_margin = data_value[0] - response;
2308 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2309 intel_sdvo_connector->left =
2310 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2311 "left_margin", 2);
2312 if (!intel_sdvo_connector->left)
2313 return false;
fcc8d672 2314
c5521706
CW		 2315 intel_sdvo_connector->left->values[0] = 0;
2316 intel_sdvo_connector->left->values[1] = data_value[0];
2317 drm_connector_attach_property(connector,
2318 intel_sdvo_connector->left,
2319 intel_sdvo_connector->left_margin);
fcc8d672 2320
c5521706
CW		 2321 intel_sdvo_connector->right =
2322 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2323 "right_margin", 2);
2324 if (!intel_sdvo_connector->right)
2325 return false;
32aad86f 2326
c5521706
CW		 2327 intel_sdvo_connector->right->values[0] = 0;
2328 intel_sdvo_connector->right->values[1] = data_value[0];
2329 drm_connector_attach_property(connector,
2330 intel_sdvo_connector->right,
2331 intel_sdvo_connector->right_margin);
2332 DRM_DEBUG_KMS("h_overscan: max %d, "
2333 "default %d, current %d\n",
2334 data_value[0], data_value[1], response);
2335 }
32aad86f 2336
c5521706
CW		 2337 if (enhancements.overscan_v) {
2338 if (!intel_sdvo_get_value(intel_sdvo,
2339 SDVO_CMD_GET_MAX_OVERSCAN_V,
2340 &data_value, 4))
2341 return false;
fcc8d672 2342
c5521706
CW		 2343 if (!intel_sdvo_get_value(intel_sdvo,
2344 SDVO_CMD_GET_OVERSCAN_V,
2345 &response, 2))
2346 return false;
32aad86f 2347
c5521706
CW		 2348 intel_sdvo_connector->max_vscan = data_value[0];
2349 intel_sdvo_connector->top_margin = data_value[0] - response;
2350 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2351 intel_sdvo_connector->top =
2352 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2353 "top_margin", 2);
2354 if (!intel_sdvo_connector->top)
2355 return false;
32aad86f 2356
c5521706
CW		 2357 intel_sdvo_connector->top->values[0] = 0;
2358 intel_sdvo_connector->top->values[1] = data_value[0];
2359 drm_connector_attach_property(connector,
2360 intel_sdvo_connector->top,
2361 intel_sdvo_connector->top_margin);
fcc8d672 2362
c5521706
CW		 2363 intel_sdvo_connector->bottom =
2364 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2365 "bottom_margin", 2);
2366 if (!intel_sdvo_connector->bottom)
2367 return false;
32aad86f 2368
c5521706
CW		 2369 intel_sdvo_connector->bottom->values[0] = 0;
2370 intel_sdvo_connector->bottom->values[1] = data_value[0];
2371 drm_connector_attach_property(connector,
2372 intel_sdvo_connector->bottom,
2373 intel_sdvo_connector->bottom_margin);
2374 DRM_DEBUG_KMS("v_overscan: max %d, "
2375 "default %d, current %d\n",
2376 data_value[0], data_value[1], response);
2377 }
32aad86f 2378
c5521706
CW		 2379 ENHANCEMENT(hpos, HPOS);
2380 ENHANCEMENT(vpos, VPOS);
2381 ENHANCEMENT(saturation, SATURATION);
2382 ENHANCEMENT(contrast, CONTRAST);
2383 ENHANCEMENT(hue, HUE);
2384 ENHANCEMENT(sharpness, SHARPNESS);
2385 ENHANCEMENT(brightness, BRIGHTNESS);
2386 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2387 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2388 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2389 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2390 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2391
e044218a
CW		 2392 if (enhancements.dot_crawl) {
2393 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2394 return false;
2395
2396 intel_sdvo_connector->max_dot_crawl = 1;
2397 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2398 intel_sdvo_connector->dot_crawl =
2399 drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
2400 if (!intel_sdvo_connector->dot_crawl)
2401 return false;
2402
2403 intel_sdvo_connector->dot_crawl->values[0] = 0;
2404 intel_sdvo_connector->dot_crawl->values[1] = 1;
2405 drm_connector_attach_property(connector,
2406 intel_sdvo_connector->dot_crawl,
2407 intel_sdvo_connector->cur_dot_crawl);
2408 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2409 }
2410
c5521706
CW		 2411 return true;
2412}
32aad86f 2413
c5521706
CW		 2414static bool
2415intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2416 struct intel_sdvo_connector *intel_sdvo_connector,
2417 struct intel_sdvo_enhancements_reply enhancements)
2418{
4ef69c7a 2419 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2420 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2421 uint16_t response, data_value[2];
32aad86f 2422
c5521706 2423 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2424
c5521706
CW		 2425 return true;
2426}
2427#undef ENHANCEMENT
32aad86f 2428
c5521706
CW		 2429static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2430 struct intel_sdvo_connector *intel_sdvo_connector)
2431{
2432 union {
2433 struct intel_sdvo_enhancements_reply reply;
2434 uint16_t response;
2435 } enhancements;
32aad86f 2436
cf9a2f3a
CW		 2437 enhancements.response = 0;
2438 intel_sdvo_get_value(intel_sdvo,
2439 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2440 &enhancements, sizeof(enhancements));
c5521706
CW		 2441 if (enhancements.response == 0) {
2442 DRM_DEBUG_KMS("No enhancement is supported\n");
2443 return true;
b9219c5e 2444 }
32aad86f 2445
c5521706
CW		 2446 if (IS_TV(intel_sdvo_connector))
2447 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2448 else if(IS_LVDS(intel_sdvo_connector))
2449 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2450 else
2451 return true;
e957d772
CW		 2452}
2453
2454static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2455 struct i2c_msg *msgs,
2456 int num)
2457{
2458 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2459
e957d772
CW		 2460 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2461 return -EIO;
2462
2463 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2464}
2465
2466static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2467{
2468 struct intel_sdvo *sdvo = adapter->algo_data;
2469 return sdvo->i2c->algo->functionality(sdvo->i2c);
2470}
2471
2472static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2473 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2474 .functionality = intel_sdvo_ddc_proxy_func
2475};
2476
2477static bool
2478intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2479 struct drm_device *dev)
2480{
2481 sdvo->ddc.owner = THIS_MODULE;
2482 sdvo->ddc.class = I2C_CLASS_DDC;
2483 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2484 sdvo->ddc.dev.parent = &dev->pdev->dev;
2485 sdvo->ddc.algo_data = sdvo;
2486 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2487
2488 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2489}
2490
c751ce4f 2491bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2492{
b01f2c3a 2493 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2494 struct intel_encoder *intel_encoder;
ea5b213a 2495 struct intel_sdvo *intel_sdvo;
79e53945 2496 int i;
79e53945 2497
ea5b213a
CW		 2498 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2499 if (!intel_sdvo)
7d57382e 2500 return false;
79e53945 2501
e957d772
CW		 2502 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
2503 kfree(intel_sdvo);
2504 return false;
2505 }
2506
ea5b213a 2507 intel_sdvo->sdvo_reg = sdvo_reg;
308cd3a2 2508
ea5b213a 2509 intel_encoder = &intel_sdvo->base;
21d40d37 2510 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7
CW		 2511 /* encoder type will be decided later */
2512 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2513
e957d772
CW		 2514 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
2515 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
79e53945 2516
79e53945
JB		 2517 /* Read the regs to test if we can talk to the device */
2518 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2519 u8 byte;
2520
2521 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
8a4c47f3 2522 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
461ed3ca 2523 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
f899fc64 2524 goto err;
79e53945
JB		 2525 }
2526 }
2527
f899fc64 2528 if (IS_SDVOB(sdvo_reg))
b01f2c3a 2529 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
f899fc64 2530 else
b01f2c3a 2531 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
619ac3b7 2532
4ef69c7a 2533 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2534
af901ca1 2535 /* In default case sdvo lvds is false */
32aad86f 2536 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2537 goto err;
79e53945 2538
ea5b213a
CW		 2539 if (intel_sdvo_output_setup(intel_sdvo,
2540 intel_sdvo->caps.output_flags) != true) {
51c8b407 2541 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
461ed3ca 2542 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
f899fc64 2543 goto err;
79e53945
JB		 2544 }
2545
ea5b213a 2546 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2547
79e53945 2548 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2549 if (!intel_sdvo_set_target_input(intel_sdvo))
f899fc64 2550 goto err;
79e53945 2551
32aad86f
CW		 2552 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2553 &intel_sdvo->pixel_clock_min,
2554 &intel_sdvo->pixel_clock_max))
f899fc64 2555 goto err;
79e53945 2556
8a4c47f3 2557 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2558 "clock range %dMHz - %dMHz, "
2559 "input 1: %c, input 2: %c, "
2560 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2561 SDVO_NAME(intel_sdvo),
2562 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2563 intel_sdvo->caps.device_rev_id,
2564 intel_sdvo->pixel_clock_min / 1000,
2565 intel_sdvo->pixel_clock_max / 1000,
2566 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2567 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2568 /* check currently supported outputs */
ea5b213a 2569 intel_sdvo->caps.output_flags &
79e53945 2570 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2571 intel_sdvo->caps.output_flags &
79e53945 2572 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2573 return true;
79e53945 2574
f899fc64 2575err:
373a3cf7 2576 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2577 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2578 kfree(intel_sdvo);
79e53945 2579
7d57382e 2580 return false;
79e53945 2581}
Linux kernel - Deliverables
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