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79e53945 JB |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2007 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Eric Anholt <eric@anholt.net> | |
27 | */ | |
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
79e53945 | 30 | #include <linux/delay.h> |
2d1a8a48 | 31 | #include <linux/export.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_edid.h> | |
ea5b213a | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
79e53945 JB |
37 | #include "i915_drv.h" |
38 | #include "intel_sdvo_regs.h" | |
39 | ||
14571b4c ZW |
40 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
41 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) | |
42 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) | |
a0b1c7a5 | 43 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) |
14571b4c ZW |
44 | |
45 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ | |
0206e353 | 46 | SDVO_TV_MASK) |
14571b4c ZW |
47 | |
48 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) | |
13946743 | 49 | #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) |
14571b4c | 50 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
32aad86f | 51 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) |
52220085 | 52 | #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) |
14571b4c | 53 | |
79e53945 | 54 | |
2e88e40b | 55 | static const char *tv_format_names[] = { |
ce6feabd ZY |
56 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
57 | "PAL_B" , "PAL_D" , "PAL_G" , | |
58 | "PAL_H" , "PAL_I" , "PAL_M" , | |
59 | "PAL_N" , "PAL_NC" , "PAL_60" , | |
60 | "SECAM_B" , "SECAM_D" , "SECAM_G" , | |
61 | "SECAM_K" , "SECAM_K1", "SECAM_L" , | |
62 | "SECAM_60" | |
63 | }; | |
64 | ||
65 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) | |
66 | ||
ea5b213a CW |
67 | struct intel_sdvo { |
68 | struct intel_encoder base; | |
69 | ||
f899fc64 | 70 | struct i2c_adapter *i2c; |
f9c10a9b | 71 | u8 slave_addr; |
e2f0ba97 | 72 | |
e957d772 CW |
73 | struct i2c_adapter ddc; |
74 | ||
e2f0ba97 | 75 | /* Register for the SDVO device: SDVOB or SDVOC */ |
eef4eacb | 76 | uint32_t sdvo_reg; |
79e53945 | 77 | |
e2f0ba97 JB |
78 | /* Active outputs controlled by this SDVO output */ |
79 | uint16_t controlled_output; | |
79e53945 | 80 | |
e2f0ba97 JB |
81 | /* |
82 | * Capabilities of the SDVO device returned by | |
19d415a2 | 83 | * intel_sdvo_get_capabilities() |
e2f0ba97 | 84 | */ |
79e53945 | 85 | struct intel_sdvo_caps caps; |
e2f0ba97 JB |
86 | |
87 | /* Pixel clock limitations reported by the SDVO device, in kHz */ | |
79e53945 JB |
88 | int pixel_clock_min, pixel_clock_max; |
89 | ||
fb7a46f3 | 90 | /* |
91 | * For multiple function SDVO device, | |
92 | * this is for current attached outputs. | |
93 | */ | |
94 | uint16_t attached_output; | |
95 | ||
cc68c81a SF |
96 | /* |
97 | * Hotplug activation bits for this device | |
98 | */ | |
5fa7ac9c | 99 | uint16_t hotplug_active; |
cc68c81a | 100 | |
e953fd7b CW |
101 | /** |
102 | * This is used to select the color range of RBG outputs in HDMI mode. | |
103 | * It is only valid when using TMDS encoding and 8 bit per color mode. | |
104 | */ | |
105 | uint32_t color_range; | |
55bc60db | 106 | bool color_range_auto; |
e953fd7b | 107 | |
e2f0ba97 JB |
108 | /** |
109 | * This is set if we're going to treat the device as TV-out. | |
110 | * | |
111 | * While we have these nice friendly flags for output types that ought | |
112 | * to decide this for us, the S-Video output on our HDMI+S-Video card | |
113 | * shows up as RGB1 (VGA). | |
114 | */ | |
115 | bool is_tv; | |
116 | ||
eef4eacb DV |
117 | /* On different gens SDVOB is at different places. */ |
118 | bool is_sdvob; | |
119 | ||
ce6feabd | 120 | /* This is for current tv format name */ |
40039750 | 121 | int tv_format_index; |
ce6feabd | 122 | |
e2f0ba97 JB |
123 | /** |
124 | * This is set if we treat the device as HDMI, instead of DVI. | |
125 | */ | |
126 | bool is_hdmi; | |
da79de97 CW |
127 | bool has_hdmi_monitor; |
128 | bool has_hdmi_audio; | |
abedc077 | 129 | bool rgb_quant_range_selectable; |
12682a97 | 130 | |
7086c87f | 131 | /** |
6c9547ff CW |
132 | * This is set if we detect output of sdvo device as LVDS and |
133 | * have a valid fixed mode to use with the panel. | |
7086c87f ML |
134 | */ |
135 | bool is_lvds; | |
e2f0ba97 | 136 | |
12682a97 | 137 | /** |
138 | * This is sdvo fixed pannel mode pointer | |
139 | */ | |
140 | struct drm_display_mode *sdvo_lvds_fixed_mode; | |
141 | ||
c751ce4f | 142 | /* DDC bus used by this SDVO encoder */ |
e2f0ba97 | 143 | uint8_t ddc_bus; |
e751823d EE |
144 | |
145 | /* | |
146 | * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd | |
147 | */ | |
148 | uint8_t dtd_sdvo_flags; | |
14571b4c ZW |
149 | }; |
150 | ||
151 | struct intel_sdvo_connector { | |
615fb93f CW |
152 | struct intel_connector base; |
153 | ||
14571b4c ZW |
154 | /* Mark the type of connector */ |
155 | uint16_t output_flag; | |
156 | ||
c3e5f67b | 157 | enum hdmi_force_audio force_audio; |
7f36e7ed | 158 | |
14571b4c | 159 | /* This contains all current supported TV format */ |
40039750 | 160 | u8 tv_format_supported[TV_FORMAT_NUM]; |
14571b4c | 161 | int format_supported_num; |
c5521706 | 162 | struct drm_property *tv_format; |
14571b4c | 163 | |
b9219c5e | 164 | /* add the property for the SDVO-TV */ |
c5521706 CW |
165 | struct drm_property *left; |
166 | struct drm_property *right; | |
167 | struct drm_property *top; | |
168 | struct drm_property *bottom; | |
169 | struct drm_property *hpos; | |
170 | struct drm_property *vpos; | |
171 | struct drm_property *contrast; | |
172 | struct drm_property *saturation; | |
173 | struct drm_property *hue; | |
174 | struct drm_property *sharpness; | |
175 | struct drm_property *flicker_filter; | |
176 | struct drm_property *flicker_filter_adaptive; | |
177 | struct drm_property *flicker_filter_2d; | |
178 | struct drm_property *tv_chroma_filter; | |
179 | struct drm_property *tv_luma_filter; | |
e044218a | 180 | struct drm_property *dot_crawl; |
b9219c5e ZY |
181 | |
182 | /* add the property for the SDVO-TV/LVDS */ | |
c5521706 | 183 | struct drm_property *brightness; |
b9219c5e ZY |
184 | |
185 | /* Add variable to record current setting for the above property */ | |
186 | u32 left_margin, right_margin, top_margin, bottom_margin; | |
c5521706 | 187 | |
b9219c5e ZY |
188 | /* this is to get the range of margin.*/ |
189 | u32 max_hscan, max_vscan; | |
190 | u32 max_hpos, cur_hpos; | |
191 | u32 max_vpos, cur_vpos; | |
192 | u32 cur_brightness, max_brightness; | |
193 | u32 cur_contrast, max_contrast; | |
194 | u32 cur_saturation, max_saturation; | |
195 | u32 cur_hue, max_hue; | |
c5521706 CW |
196 | u32 cur_sharpness, max_sharpness; |
197 | u32 cur_flicker_filter, max_flicker_filter; | |
198 | u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; | |
199 | u32 cur_flicker_filter_2d, max_flicker_filter_2d; | |
200 | u32 cur_tv_chroma_filter, max_tv_chroma_filter; | |
201 | u32 cur_tv_luma_filter, max_tv_luma_filter; | |
e044218a | 202 | u32 cur_dot_crawl, max_dot_crawl; |
79e53945 JB |
203 | }; |
204 | ||
8aca63aa | 205 | static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) |
ea5b213a | 206 | { |
8aca63aa | 207 | return container_of(encoder, struct intel_sdvo, base); |
ea5b213a CW |
208 | } |
209 | ||
df0e9248 CW |
210 | static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) |
211 | { | |
8aca63aa | 212 | return to_sdvo(intel_attached_encoder(connector)); |
df0e9248 CW |
213 | } |
214 | ||
615fb93f CW |
215 | static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) |
216 | { | |
217 | return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); | |
218 | } | |
219 | ||
fb7a46f3 | 220 | static bool |
ea5b213a | 221 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); |
32aad86f CW |
222 | static bool |
223 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, | |
224 | struct intel_sdvo_connector *intel_sdvo_connector, | |
225 | int type); | |
226 | static bool | |
227 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, | |
228 | struct intel_sdvo_connector *intel_sdvo_connector); | |
fb7a46f3 | 229 | |
79e53945 JB |
230 | /** |
231 | * Writes the SDVOB or SDVOC with the given value, but always writes both | |
232 | * SDVOB and SDVOC to work around apparent hardware issues (according to | |
233 | * comments in the BIOS). | |
234 | */ | |
ea5b213a | 235 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
79e53945 | 236 | { |
4ef69c7a | 237 | struct drm_device *dev = intel_sdvo->base.base.dev; |
79e53945 | 238 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
239 | u32 bval = val, cval = val; |
240 | int i; | |
241 | ||
ea5b213a CW |
242 | if (intel_sdvo->sdvo_reg == PCH_SDVOB) { |
243 | I915_WRITE(intel_sdvo->sdvo_reg, val); | |
244 | I915_READ(intel_sdvo->sdvo_reg); | |
461ed3ca ZY |
245 | return; |
246 | } | |
247 | ||
e2debe91 PZ |
248 | if (intel_sdvo->sdvo_reg == GEN3_SDVOB) |
249 | cval = I915_READ(GEN3_SDVOC); | |
250 | else | |
251 | bval = I915_READ(GEN3_SDVOB); | |
252 | ||
79e53945 JB |
253 | /* |
254 | * Write the registers twice for luck. Sometimes, | |
255 | * writing them only once doesn't appear to 'stick'. | |
256 | * The BIOS does this too. Yay, magic | |
257 | */ | |
258 | for (i = 0; i < 2; i++) | |
259 | { | |
e2debe91 PZ |
260 | I915_WRITE(GEN3_SDVOB, bval); |
261 | I915_READ(GEN3_SDVOB); | |
262 | I915_WRITE(GEN3_SDVOC, cval); | |
263 | I915_READ(GEN3_SDVOC); | |
79e53945 JB |
264 | } |
265 | } | |
266 | ||
32aad86f | 267 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) |
79e53945 | 268 | { |
79e53945 JB |
269 | struct i2c_msg msgs[] = { |
270 | { | |
e957d772 | 271 | .addr = intel_sdvo->slave_addr, |
79e53945 JB |
272 | .flags = 0, |
273 | .len = 1, | |
e957d772 | 274 | .buf = &addr, |
79e53945 JB |
275 | }, |
276 | { | |
e957d772 | 277 | .addr = intel_sdvo->slave_addr, |
79e53945 JB |
278 | .flags = I2C_M_RD, |
279 | .len = 1, | |
e957d772 | 280 | .buf = ch, |
79e53945 JB |
281 | } |
282 | }; | |
32aad86f | 283 | int ret; |
79e53945 | 284 | |
f899fc64 | 285 | if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) |
79e53945 | 286 | return true; |
79e53945 | 287 | |
8a4c47f3 | 288 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
79e53945 JB |
289 | return false; |
290 | } | |
291 | ||
79e53945 JB |
292 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
293 | /** Mapping of command numbers to names, for debug output */ | |
005568be | 294 | static const struct _sdvo_cmd_name { |
e2f0ba97 | 295 | u8 cmd; |
2e88e40b | 296 | const char *name; |
79e53945 | 297 | } sdvo_cmd_names[] = { |
0206e353 AJ |
298 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
299 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), | |
300 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), | |
301 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), | |
302 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), | |
303 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), | |
304 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), | |
305 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), | |
306 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), | |
307 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), | |
308 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), | |
309 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), | |
310 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), | |
311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), | |
312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), | |
313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), | |
314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), | |
315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), | |
317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), | |
319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), | |
320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), | |
321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), | |
322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), | |
323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), | |
324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), | |
325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), | |
326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), | |
327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), | |
328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), | |
329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), | |
330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), | |
331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), | |
332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), | |
333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), | |
334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), | |
335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), | |
336 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), | |
337 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), | |
338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), | |
339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), | |
340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), | |
341 | ||
342 | /* Add the op code for SDVO enhancements */ | |
343 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), | |
344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), | |
345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), | |
346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), | |
347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), | |
348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), | |
349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), | |
350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), | |
351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), | |
352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), | |
353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), | |
354 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), | |
355 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), | |
356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), | |
357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), | |
358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), | |
359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), | |
360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), | |
361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), | |
362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), | |
363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), | |
364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), | |
365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), | |
366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), | |
367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), | |
368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), | |
369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), | |
370 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), | |
371 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), | |
372 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), | |
373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), | |
374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), | |
375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), | |
376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), | |
377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), | |
378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), | |
379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), | |
380 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), | |
381 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), | |
382 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), | |
383 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), | |
384 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), | |
385 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), | |
386 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), | |
387 | ||
388 | /* HDMI op code */ | |
389 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), | |
390 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), | |
391 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), | |
392 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), | |
393 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), | |
394 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), | |
395 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), | |
396 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), | |
397 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), | |
398 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), | |
399 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), | |
400 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), | |
401 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), | |
402 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), | |
403 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), | |
404 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), | |
405 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), | |
406 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), | |
407 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), | |
408 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), | |
79e53945 JB |
409 | }; |
410 | ||
eef4eacb | 411 | #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC") |
79e53945 | 412 | |
ea5b213a | 413 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
32aad86f | 414 | const void *args, int args_len) |
79e53945 | 415 | { |
79e53945 JB |
416 | int i; |
417 | ||
8a4c47f3 | 418 | DRM_DEBUG_KMS("%s: W: %02X ", |
ea5b213a | 419 | SDVO_NAME(intel_sdvo), cmd); |
79e53945 | 420 | for (i = 0; i < args_len; i++) |
342dc382 | 421 | DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); |
79e53945 | 422 | for (; i < 8; i++) |
342dc382 | 423 | DRM_LOG_KMS(" "); |
04ad327f | 424 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { |
79e53945 | 425 | if (cmd == sdvo_cmd_names[i].cmd) { |
342dc382 | 426 | DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); |
79e53945 JB |
427 | break; |
428 | } | |
429 | } | |
04ad327f | 430 | if (i == ARRAY_SIZE(sdvo_cmd_names)) |
342dc382 | 431 | DRM_LOG_KMS("(%02X)", cmd); |
432 | DRM_LOG_KMS("\n"); | |
79e53945 | 433 | } |
79e53945 | 434 | |
e957d772 CW |
435 | static const char *cmd_status_names[] = { |
436 | "Power on", | |
437 | "Success", | |
438 | "Not supported", | |
439 | "Invalid arg", | |
440 | "Pending", | |
441 | "Target not specified", | |
442 | "Scaling not supported" | |
443 | }; | |
444 | ||
32aad86f CW |
445 | static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
446 | const void *args, int args_len) | |
79e53945 | 447 | { |
3bf3f452 BW |
448 | u8 *buf, status; |
449 | struct i2c_msg *msgs; | |
450 | int i, ret = true; | |
451 | ||
0274df3e | 452 | /* Would be simpler to allocate both in one go ? */ |
5c67eeb6 | 453 | buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); |
3bf3f452 BW |
454 | if (!buf) |
455 | return false; | |
456 | ||
457 | msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); | |
0274df3e AC |
458 | if (!msgs) { |
459 | kfree(buf); | |
3bf3f452 | 460 | return false; |
0274df3e | 461 | } |
79e53945 | 462 | |
ea5b213a | 463 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
79e53945 JB |
464 | |
465 | for (i = 0; i < args_len; i++) { | |
e957d772 CW |
466 | msgs[i].addr = intel_sdvo->slave_addr; |
467 | msgs[i].flags = 0; | |
468 | msgs[i].len = 2; | |
469 | msgs[i].buf = buf + 2 *i; | |
470 | buf[2*i + 0] = SDVO_I2C_ARG_0 - i; | |
471 | buf[2*i + 1] = ((u8*)args)[i]; | |
472 | } | |
473 | msgs[i].addr = intel_sdvo->slave_addr; | |
474 | msgs[i].flags = 0; | |
475 | msgs[i].len = 2; | |
476 | msgs[i].buf = buf + 2*i; | |
477 | buf[2*i + 0] = SDVO_I2C_OPCODE; | |
478 | buf[2*i + 1] = cmd; | |
479 | ||
480 | /* the following two are to read the response */ | |
481 | status = SDVO_I2C_CMD_STATUS; | |
482 | msgs[i+1].addr = intel_sdvo->slave_addr; | |
483 | msgs[i+1].flags = 0; | |
484 | msgs[i+1].len = 1; | |
485 | msgs[i+1].buf = &status; | |
486 | ||
487 | msgs[i+2].addr = intel_sdvo->slave_addr; | |
488 | msgs[i+2].flags = I2C_M_RD; | |
489 | msgs[i+2].len = 1; | |
490 | msgs[i+2].buf = &status; | |
491 | ||
492 | ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); | |
493 | if (ret < 0) { | |
494 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); | |
3bf3f452 BW |
495 | ret = false; |
496 | goto out; | |
e957d772 CW |
497 | } |
498 | if (ret != i+3) { | |
499 | /* failure in I2C transfer */ | |
500 | DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); | |
3bf3f452 | 501 | ret = false; |
e957d772 CW |
502 | } |
503 | ||
3bf3f452 BW |
504 | out: |
505 | kfree(msgs); | |
506 | kfree(buf); | |
507 | return ret; | |
79e53945 JB |
508 | } |
509 | ||
b5c616a7 CW |
510 | static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
511 | void *response, int response_len) | |
79e53945 | 512 | { |
fc37381c | 513 | u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ |
b5c616a7 | 514 | u8 status; |
33b52961 | 515 | int i; |
79e53945 | 516 | |
d121a5d2 CW |
517 | DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo)); |
518 | ||
b5c616a7 CW |
519 | /* |
520 | * The documentation states that all commands will be | |
521 | * processed within 15µs, and that we need only poll | |
522 | * the status byte a maximum of 3 times in order for the | |
523 | * command to be complete. | |
524 | * | |
525 | * Check 5 times in case the hardware failed to read the docs. | |
fc37381c CW |
526 | * |
527 | * Also beware that the first response by many devices is to | |
528 | * reply PENDING and stall for time. TVs are notorious for | |
529 | * requiring longer than specified to complete their replies. | |
530 | * Originally (in the DDX long ago), the delay was only ever 15ms | |
531 | * with an additional delay of 30ms applied for TVs added later after | |
532 | * many experiments. To accommodate both sets of delays, we do a | |
533 | * sequence of slow checks if the device is falling behind and fails | |
534 | * to reply within 5*15µs. | |
b5c616a7 | 535 | */ |
d121a5d2 CW |
536 | if (!intel_sdvo_read_byte(intel_sdvo, |
537 | SDVO_I2C_CMD_STATUS, | |
538 | &status)) | |
539 | goto log_fail; | |
540 | ||
1ad87e72 GC |
541 | while ((status == SDVO_CMD_STATUS_PENDING || |
542 | status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { | |
fc37381c CW |
543 | if (retry < 10) |
544 | msleep(15); | |
545 | else | |
546 | udelay(15); | |
547 | ||
b5c616a7 CW |
548 | if (!intel_sdvo_read_byte(intel_sdvo, |
549 | SDVO_I2C_CMD_STATUS, | |
550 | &status)) | |
d121a5d2 CW |
551 | goto log_fail; |
552 | } | |
b5c616a7 | 553 | |
79e53945 | 554 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
342dc382 | 555 | DRM_LOG_KMS("(%s)", cmd_status_names[status]); |
79e53945 | 556 | else |
342dc382 | 557 | DRM_LOG_KMS("(??? %d)", status); |
79e53945 | 558 | |
b5c616a7 CW |
559 | if (status != SDVO_CMD_STATUS_SUCCESS) |
560 | goto log_fail; | |
79e53945 | 561 | |
b5c616a7 CW |
562 | /* Read the command response */ |
563 | for (i = 0; i < response_len; i++) { | |
564 | if (!intel_sdvo_read_byte(intel_sdvo, | |
565 | SDVO_I2C_RETURN_0 + i, | |
566 | &((u8 *)response)[i])) | |
567 | goto log_fail; | |
e957d772 | 568 | DRM_LOG_KMS(" %02X", ((u8 *)response)[i]); |
b5c616a7 | 569 | } |
b5c616a7 | 570 | DRM_LOG_KMS("\n"); |
b5c616a7 | 571 | return true; |
79e53945 | 572 | |
b5c616a7 | 573 | log_fail: |
d121a5d2 | 574 | DRM_LOG_KMS("... failed\n"); |
b5c616a7 | 575 | return false; |
79e53945 JB |
576 | } |
577 | ||
b358d0a6 | 578 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) |
79e53945 JB |
579 | { |
580 | if (mode->clock >= 100000) | |
581 | return 1; | |
582 | else if (mode->clock >= 50000) | |
583 | return 2; | |
584 | else | |
585 | return 4; | |
586 | } | |
587 | ||
e957d772 CW |
588 | static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
589 | u8 ddc_bus) | |
79e53945 | 590 | { |
d121a5d2 | 591 | /* This must be the immediately preceding write before the i2c xfer */ |
e957d772 CW |
592 | return intel_sdvo_write_cmd(intel_sdvo, |
593 | SDVO_CMD_SET_CONTROL_BUS_SWITCH, | |
594 | &ddc_bus, 1); | |
79e53945 JB |
595 | } |
596 | ||
32aad86f | 597 | static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) |
79e53945 | 598 | { |
d121a5d2 CW |
599 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) |
600 | return false; | |
601 | ||
602 | return intel_sdvo_read_response(intel_sdvo, NULL, 0); | |
32aad86f | 603 | } |
79e53945 | 604 | |
32aad86f CW |
605 | static bool |
606 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) | |
607 | { | |
608 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) | |
609 | return false; | |
79e53945 | 610 | |
32aad86f CW |
611 | return intel_sdvo_read_response(intel_sdvo, value, len); |
612 | } | |
79e53945 | 613 | |
32aad86f CW |
614 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) |
615 | { | |
616 | struct intel_sdvo_set_target_input_args targets = {0}; | |
617 | return intel_sdvo_set_value(intel_sdvo, | |
618 | SDVO_CMD_SET_TARGET_INPUT, | |
619 | &targets, sizeof(targets)); | |
79e53945 JB |
620 | } |
621 | ||
622 | /** | |
623 | * Return whether each input is trained. | |
624 | * | |
625 | * This function is making an assumption about the layout of the response, | |
626 | * which should be checked against the docs. | |
627 | */ | |
ea5b213a | 628 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) |
79e53945 JB |
629 | { |
630 | struct intel_sdvo_get_trained_inputs_response response; | |
79e53945 | 631 | |
1a3665c8 | 632 | BUILD_BUG_ON(sizeof(response) != 1); |
32aad86f CW |
633 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, |
634 | &response, sizeof(response))) | |
79e53945 JB |
635 | return false; |
636 | ||
637 | *input_1 = response.input0_trained; | |
638 | *input_2 = response.input1_trained; | |
639 | return true; | |
640 | } | |
641 | ||
ea5b213a | 642 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
643 | u16 outputs) |
644 | { | |
32aad86f CW |
645 | return intel_sdvo_set_value(intel_sdvo, |
646 | SDVO_CMD_SET_ACTIVE_OUTPUTS, | |
647 | &outputs, sizeof(outputs)); | |
79e53945 JB |
648 | } |
649 | ||
4ac41f47 DV |
650 | static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, |
651 | u16 *outputs) | |
652 | { | |
653 | return intel_sdvo_get_value(intel_sdvo, | |
654 | SDVO_CMD_GET_ACTIVE_OUTPUTS, | |
655 | outputs, sizeof(*outputs)); | |
656 | } | |
657 | ||
ea5b213a | 658 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
659 | int mode) |
660 | { | |
32aad86f | 661 | u8 state = SDVO_ENCODER_STATE_ON; |
79e53945 JB |
662 | |
663 | switch (mode) { | |
664 | case DRM_MODE_DPMS_ON: | |
665 | state = SDVO_ENCODER_STATE_ON; | |
666 | break; | |
667 | case DRM_MODE_DPMS_STANDBY: | |
668 | state = SDVO_ENCODER_STATE_STANDBY; | |
669 | break; | |
670 | case DRM_MODE_DPMS_SUSPEND: | |
671 | state = SDVO_ENCODER_STATE_SUSPEND; | |
672 | break; | |
673 | case DRM_MODE_DPMS_OFF: | |
674 | state = SDVO_ENCODER_STATE_OFF; | |
675 | break; | |
676 | } | |
677 | ||
32aad86f CW |
678 | return intel_sdvo_set_value(intel_sdvo, |
679 | SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); | |
79e53945 JB |
680 | } |
681 | ||
ea5b213a | 682 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
683 | int *clock_min, |
684 | int *clock_max) | |
685 | { | |
686 | struct intel_sdvo_pixel_clock_range clocks; | |
79e53945 | 687 | |
1a3665c8 | 688 | BUILD_BUG_ON(sizeof(clocks) != 4); |
32aad86f CW |
689 | if (!intel_sdvo_get_value(intel_sdvo, |
690 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, | |
691 | &clocks, sizeof(clocks))) | |
79e53945 JB |
692 | return false; |
693 | ||
694 | /* Convert the values from units of 10 kHz to kHz. */ | |
695 | *clock_min = clocks.min * 10; | |
696 | *clock_max = clocks.max * 10; | |
79e53945 JB |
697 | return true; |
698 | } | |
699 | ||
ea5b213a | 700 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
701 | u16 outputs) |
702 | { | |
32aad86f CW |
703 | return intel_sdvo_set_value(intel_sdvo, |
704 | SDVO_CMD_SET_TARGET_OUTPUT, | |
705 | &outputs, sizeof(outputs)); | |
79e53945 JB |
706 | } |
707 | ||
ea5b213a | 708 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
79e53945 JB |
709 | struct intel_sdvo_dtd *dtd) |
710 | { | |
32aad86f CW |
711 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
712 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); | |
79e53945 JB |
713 | } |
714 | ||
045ac3b5 JB |
715 | static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
716 | struct intel_sdvo_dtd *dtd) | |
717 | { | |
718 | return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && | |
719 | intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); | |
720 | } | |
721 | ||
ea5b213a | 722 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
723 | struct intel_sdvo_dtd *dtd) |
724 | { | |
ea5b213a | 725 | return intel_sdvo_set_timing(intel_sdvo, |
79e53945 JB |
726 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
727 | } | |
728 | ||
ea5b213a | 729 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
730 | struct intel_sdvo_dtd *dtd) |
731 | { | |
ea5b213a | 732 | return intel_sdvo_set_timing(intel_sdvo, |
79e53945 JB |
733 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
734 | } | |
735 | ||
045ac3b5 JB |
736 | static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, |
737 | struct intel_sdvo_dtd *dtd) | |
738 | { | |
739 | return intel_sdvo_get_timing(intel_sdvo, | |
740 | SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); | |
741 | } | |
742 | ||
e2f0ba97 | 743 | static bool |
ea5b213a | 744 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
745 | uint16_t clock, |
746 | uint16_t width, | |
747 | uint16_t height) | |
748 | { | |
749 | struct intel_sdvo_preferred_input_timing_args args; | |
e2f0ba97 | 750 | |
e642c6f1 | 751 | memset(&args, 0, sizeof(args)); |
e2f0ba97 JB |
752 | args.clock = clock; |
753 | args.width = width; | |
754 | args.height = height; | |
e642c6f1 | 755 | args.interlace = 0; |
12682a97 | 756 | |
ea5b213a CW |
757 | if (intel_sdvo->is_lvds && |
758 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || | |
759 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) | |
12682a97 | 760 | args.scaled = 1; |
761 | ||
32aad86f CW |
762 | return intel_sdvo_set_value(intel_sdvo, |
763 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, | |
764 | &args, sizeof(args)); | |
e2f0ba97 JB |
765 | } |
766 | ||
ea5b213a | 767 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
768 | struct intel_sdvo_dtd *dtd) |
769 | { | |
1a3665c8 CW |
770 | BUILD_BUG_ON(sizeof(dtd->part1) != 8); |
771 | BUILD_BUG_ON(sizeof(dtd->part2) != 8); | |
32aad86f CW |
772 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
773 | &dtd->part1, sizeof(dtd->part1)) && | |
774 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, | |
775 | &dtd->part2, sizeof(dtd->part2)); | |
e2f0ba97 | 776 | } |
79e53945 | 777 | |
ea5b213a | 778 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
79e53945 | 779 | { |
32aad86f | 780 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
79e53945 JB |
781 | } |
782 | ||
e2f0ba97 | 783 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
32aad86f | 784 | const struct drm_display_mode *mode) |
79e53945 | 785 | { |
e2f0ba97 JB |
786 | uint16_t width, height; |
787 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; | |
788 | uint16_t h_sync_offset, v_sync_offset; | |
6651819b | 789 | int mode_clock; |
79e53945 | 790 | |
1c4a814e DV |
791 | memset(dtd, 0, sizeof(*dtd)); |
792 | ||
c6ebd4c0 DV |
793 | width = mode->hdisplay; |
794 | height = mode->vdisplay; | |
79e53945 JB |
795 | |
796 | /* do some mode translations */ | |
c6ebd4c0 DV |
797 | h_blank_len = mode->htotal - mode->hdisplay; |
798 | h_sync_len = mode->hsync_end - mode->hsync_start; | |
79e53945 | 799 | |
c6ebd4c0 DV |
800 | v_blank_len = mode->vtotal - mode->vdisplay; |
801 | v_sync_len = mode->vsync_end - mode->vsync_start; | |
79e53945 | 802 | |
c6ebd4c0 DV |
803 | h_sync_offset = mode->hsync_start - mode->hdisplay; |
804 | v_sync_offset = mode->vsync_start - mode->vdisplay; | |
79e53945 | 805 | |
6651819b | 806 | mode_clock = mode->clock; |
6651819b DV |
807 | mode_clock /= 10; |
808 | dtd->part1.clock = mode_clock; | |
809 | ||
e2f0ba97 JB |
810 | dtd->part1.h_active = width & 0xff; |
811 | dtd->part1.h_blank = h_blank_len & 0xff; | |
812 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | | |
79e53945 | 813 | ((h_blank_len >> 8) & 0xf); |
e2f0ba97 JB |
814 | dtd->part1.v_active = height & 0xff; |
815 | dtd->part1.v_blank = v_blank_len & 0xff; | |
816 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | | |
79e53945 JB |
817 | ((v_blank_len >> 8) & 0xf); |
818 | ||
171a9e96 | 819 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
e2f0ba97 JB |
820 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
821 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | | |
79e53945 | 822 | (v_sync_len & 0xf); |
e2f0ba97 | 823 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
79e53945 JB |
824 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
825 | ((v_sync_len & 0x30) >> 4); | |
826 | ||
e2f0ba97 | 827 | dtd->part2.dtd_flags = 0x18; |
59d92bfa DV |
828 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
829 | dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; | |
79e53945 | 830 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
59d92bfa | 831 | dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; |
79e53945 | 832 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
59d92bfa | 833 | dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; |
e2f0ba97 | 834 | |
e2f0ba97 | 835 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; |
e2f0ba97 JB |
836 | } |
837 | ||
1c4a814e | 838 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, |
32aad86f | 839 | const struct intel_sdvo_dtd *dtd) |
e2f0ba97 | 840 | { |
1c4a814e DV |
841 | struct drm_display_mode mode = {}; |
842 | ||
843 | mode.hdisplay = dtd->part1.h_active; | |
844 | mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; | |
845 | mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; | |
846 | mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; | |
847 | mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; | |
848 | mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; | |
849 | mode.htotal = mode.hdisplay + dtd->part1.h_blank; | |
850 | mode.htotal += (dtd->part1.h_high & 0xf) << 8; | |
851 | ||
852 | mode.vdisplay = dtd->part1.v_active; | |
853 | mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; | |
854 | mode.vsync_start = mode.vdisplay; | |
855 | mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; | |
856 | mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; | |
857 | mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; | |
858 | mode.vsync_end = mode.vsync_start + | |
e2f0ba97 | 859 | (dtd->part2.v_sync_off_width & 0xf); |
1c4a814e DV |
860 | mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; |
861 | mode.vtotal = mode.vdisplay + dtd->part1.v_blank; | |
862 | mode.vtotal += (dtd->part1.v_high & 0xf) << 8; | |
e2f0ba97 | 863 | |
1c4a814e | 864 | mode.clock = dtd->part1.clock * 10; |
e2f0ba97 | 865 | |
59d92bfa | 866 | if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) |
1c4a814e | 867 | mode.flags |= DRM_MODE_FLAG_INTERLACE; |
59d92bfa | 868 | if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) |
1c4a814e | 869 | mode.flags |= DRM_MODE_FLAG_PHSYNC; |
3cea210f | 870 | else |
1c4a814e | 871 | mode.flags |= DRM_MODE_FLAG_NHSYNC; |
59d92bfa | 872 | if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) |
1c4a814e | 873 | mode.flags |= DRM_MODE_FLAG_PVSYNC; |
3cea210f | 874 | else |
1c4a814e DV |
875 | mode.flags |= DRM_MODE_FLAG_NVSYNC; |
876 | ||
877 | drm_mode_set_crtcinfo(&mode, 0); | |
878 | ||
879 | drm_mode_copy(pmode, &mode); | |
e2f0ba97 JB |
880 | } |
881 | ||
e27d8538 | 882 | static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) |
e2f0ba97 | 883 | { |
e27d8538 | 884 | struct intel_sdvo_encode encode; |
e2f0ba97 | 885 | |
1a3665c8 | 886 | BUILD_BUG_ON(sizeof(encode) != 2); |
e27d8538 CW |
887 | return intel_sdvo_get_value(intel_sdvo, |
888 | SDVO_CMD_GET_SUPP_ENCODE, | |
889 | &encode, sizeof(encode)); | |
e2f0ba97 JB |
890 | } |
891 | ||
ea5b213a | 892 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
c751ce4f | 893 | uint8_t mode) |
e2f0ba97 | 894 | { |
32aad86f | 895 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); |
e2f0ba97 JB |
896 | } |
897 | ||
ea5b213a | 898 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
899 | uint8_t mode) |
900 | { | |
32aad86f | 901 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
e2f0ba97 JB |
902 | } |
903 | ||
904 | #if 0 | |
ea5b213a | 905 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
e2f0ba97 JB |
906 | { |
907 | int i, j; | |
908 | uint8_t set_buf_index[2]; | |
909 | uint8_t av_split; | |
910 | uint8_t buf_size; | |
911 | uint8_t buf[48]; | |
912 | uint8_t *pos; | |
913 | ||
32aad86f | 914 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); |
e2f0ba97 JB |
915 | |
916 | for (i = 0; i <= av_split; i++) { | |
917 | set_buf_index[0] = i; set_buf_index[1] = 0; | |
c751ce4f | 918 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
e2f0ba97 | 919 | set_buf_index, 2); |
c751ce4f EA |
920 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
921 | intel_sdvo_read_response(encoder, &buf_size, 1); | |
e2f0ba97 JB |
922 | |
923 | pos = buf; | |
924 | for (j = 0; j <= buf_size; j += 8) { | |
c751ce4f | 925 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
e2f0ba97 | 926 | NULL, 0); |
c751ce4f | 927 | intel_sdvo_read_response(encoder, pos, 8); |
e2f0ba97 JB |
928 | pos += 8; |
929 | } | |
930 | } | |
931 | } | |
932 | #endif | |
933 | ||
b6e0e543 DV |
934 | static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, |
935 | unsigned if_index, uint8_t tx_rate, | |
936 | uint8_t *data, unsigned length) | |
937 | { | |
938 | uint8_t set_buf_index[2] = { if_index, 0 }; | |
939 | uint8_t hbuf_size, tmp[8]; | |
940 | int i; | |
941 | ||
942 | if (!intel_sdvo_set_value(intel_sdvo, | |
943 | SDVO_CMD_SET_HBUF_INDEX, | |
944 | set_buf_index, 2)) | |
945 | return false; | |
946 | ||
947 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, | |
948 | &hbuf_size, 1)) | |
949 | return false; | |
950 | ||
951 | /* Buffer size is 0 based, hooray! */ | |
952 | hbuf_size++; | |
953 | ||
954 | DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", | |
955 | if_index, length, hbuf_size); | |
956 | ||
957 | for (i = 0; i < hbuf_size; i += 8) { | |
958 | memset(tmp, 0, 8); | |
959 | if (i < length) | |
960 | memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); | |
961 | ||
962 | if (!intel_sdvo_set_value(intel_sdvo, | |
963 | SDVO_CMD_SET_HBUF_DATA, | |
964 | tmp, 8)) | |
965 | return false; | |
966 | } | |
967 | ||
968 | return intel_sdvo_set_value(intel_sdvo, | |
969 | SDVO_CMD_SET_HBUF_TXRATE, | |
970 | &tx_rate, 1); | |
971 | } | |
972 | ||
abedc077 VS |
973 | static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, |
974 | const struct drm_display_mode *adjusted_mode) | |
e2f0ba97 | 975 | { |
15dcd350 DL |
976 | uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; |
977 | struct drm_crtc *crtc = intel_sdvo->base.base.crtc; | |
978 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
979 | union hdmi_infoframe frame; | |
980 | int ret; | |
981 | ssize_t len; | |
982 | ||
983 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, | |
984 | adjusted_mode); | |
985 | if (ret < 0) { | |
986 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
987 | return false; | |
988 | } | |
3c17fe4b | 989 | |
abedc077 | 990 | if (intel_sdvo->rgb_quant_range_selectable) { |
50f3b016 | 991 | if (intel_crtc->config.limited_color_range) |
15dcd350 DL |
992 | frame.avi.quantization_range = |
993 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 994 | else |
15dcd350 DL |
995 | frame.avi.quantization_range = |
996 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
997 | } |
998 | ||
15dcd350 DL |
999 | len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data)); |
1000 | if (len < 0) | |
1001 | return false; | |
81014b9d | 1002 | |
b6e0e543 DV |
1003 | return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, |
1004 | SDVO_HBUF_TX_VSYNC, | |
1005 | sdvo_data, sizeof(sdvo_data)); | |
e2f0ba97 JB |
1006 | } |
1007 | ||
32aad86f | 1008 | static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) |
7026d4ac | 1009 | { |
ce6feabd | 1010 | struct intel_sdvo_tv_format format; |
40039750 | 1011 | uint32_t format_map; |
ce6feabd | 1012 | |
40039750 | 1013 | format_map = 1 << intel_sdvo->tv_format_index; |
ce6feabd | 1014 | memset(&format, 0, sizeof(format)); |
32aad86f | 1015 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); |
ce6feabd | 1016 | |
32aad86f CW |
1017 | BUILD_BUG_ON(sizeof(format) != 6); |
1018 | return intel_sdvo_set_value(intel_sdvo, | |
1019 | SDVO_CMD_SET_TV_FORMAT, | |
1020 | &format, sizeof(format)); | |
7026d4ac ZW |
1021 | } |
1022 | ||
32aad86f CW |
1023 | static bool |
1024 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, | |
e811f5ae | 1025 | const struct drm_display_mode *mode) |
e2f0ba97 | 1026 | { |
32aad86f | 1027 | struct intel_sdvo_dtd output_dtd; |
79e53945 | 1028 | |
32aad86f CW |
1029 | if (!intel_sdvo_set_target_output(intel_sdvo, |
1030 | intel_sdvo->attached_output)) | |
1031 | return false; | |
e2f0ba97 | 1032 | |
32aad86f CW |
1033 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
1034 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) | |
1035 | return false; | |
e2f0ba97 | 1036 | |
32aad86f CW |
1037 | return true; |
1038 | } | |
1039 | ||
c9a29698 DV |
1040 | /* Asks the sdvo controller for the preferred input mode given the output mode. |
1041 | * Unfortunately we have to set up the full output mode to do that. */ | |
32aad86f | 1042 | static bool |
c9a29698 | 1043 | intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, |
e811f5ae | 1044 | const struct drm_display_mode *mode, |
c9a29698 | 1045 | struct drm_display_mode *adjusted_mode) |
32aad86f | 1046 | { |
c9a29698 DV |
1047 | struct intel_sdvo_dtd input_dtd; |
1048 | ||
32aad86f CW |
1049 | /* Reset the input timing to the screen. Assume always input 0. */ |
1050 | if (!intel_sdvo_set_target_input(intel_sdvo)) | |
1051 | return false; | |
e2f0ba97 | 1052 | |
32aad86f CW |
1053 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, |
1054 | mode->clock / 10, | |
1055 | mode->hdisplay, | |
1056 | mode->vdisplay)) | |
1057 | return false; | |
e2f0ba97 | 1058 | |
32aad86f | 1059 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, |
c9a29698 | 1060 | &input_dtd)) |
32aad86f | 1061 | return false; |
e2f0ba97 | 1062 | |
c9a29698 | 1063 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); |
e751823d | 1064 | intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; |
79e53945 | 1065 | |
32aad86f CW |
1066 | return true; |
1067 | } | |
12682a97 | 1068 | |
70484559 DV |
1069 | static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config) |
1070 | { | |
3c52f4eb | 1071 | unsigned dotclock = pipe_config->port_clock; |
70484559 DV |
1072 | struct dpll *clock = &pipe_config->dpll; |
1073 | ||
1074 | /* SDVO TV has fixed PLL values depend on its clock range, | |
1075 | this mirrors vbios setting. */ | |
1076 | if (dotclock >= 100000 && dotclock < 140500) { | |
1077 | clock->p1 = 2; | |
1078 | clock->p2 = 10; | |
1079 | clock->n = 3; | |
1080 | clock->m1 = 16; | |
1081 | clock->m2 = 8; | |
1082 | } else if (dotclock >= 140500 && dotclock <= 200000) { | |
1083 | clock->p1 = 1; | |
1084 | clock->p2 = 10; | |
1085 | clock->n = 6; | |
1086 | clock->m1 = 12; | |
1087 | clock->m2 = 8; | |
1088 | } else { | |
1089 | WARN(1, "SDVO TV clock out of range: %i\n", dotclock); | |
1090 | } | |
1091 | ||
1092 | pipe_config->clock_set = true; | |
1093 | } | |
1094 | ||
6cc5f341 DV |
1095 | static bool intel_sdvo_compute_config(struct intel_encoder *encoder, |
1096 | struct intel_crtc_config *pipe_config) | |
32aad86f | 1097 | { |
8aca63aa | 1098 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
6cc5f341 DV |
1099 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
1100 | struct drm_display_mode *mode = &pipe_config->requested_mode; | |
12682a97 | 1101 | |
5d2d38dd DV |
1102 | DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); |
1103 | pipe_config->pipe_bpp = 8*3; | |
1104 | ||
5bfe2ac0 DV |
1105 | if (HAS_PCH_SPLIT(encoder->base.dev)) |
1106 | pipe_config->has_pch_encoder = true; | |
1107 | ||
32aad86f CW |
1108 | /* We need to construct preferred input timings based on our |
1109 | * output timings. To do that, we have to set the output | |
1110 | * timings, even though this isn't really the right place in | |
1111 | * the sequence to do it. Oh well. | |
1112 | */ | |
1113 | if (intel_sdvo->is_tv) { | |
1114 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) | |
1115 | return false; | |
12682a97 | 1116 | |
c9a29698 DV |
1117 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
1118 | mode, | |
1119 | adjusted_mode); | |
09ede541 | 1120 | pipe_config->sdvo_tv_clock = true; |
ea5b213a | 1121 | } else if (intel_sdvo->is_lvds) { |
32aad86f | 1122 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, |
6c9547ff | 1123 | intel_sdvo->sdvo_lvds_fixed_mode)) |
e2f0ba97 | 1124 | return false; |
12682a97 | 1125 | |
c9a29698 DV |
1126 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
1127 | mode, | |
1128 | adjusted_mode); | |
e2f0ba97 | 1129 | } |
32aad86f CW |
1130 | |
1131 | /* Make the CRTC code factor in the SDVO pixel multiplier. The | |
6c9547ff | 1132 | * SDVO device will factor out the multiplier during mode_set. |
32aad86f | 1133 | */ |
6cc5f341 DV |
1134 | pipe_config->pixel_multiplier = |
1135 | intel_sdvo_get_pixel_multiplier(adjusted_mode); | |
32aad86f | 1136 | |
55bc60db VS |
1137 | if (intel_sdvo->color_range_auto) { |
1138 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
4f3a8bc7 PZ |
1139 | /* FIXME: This bit is only valid when using TMDS encoding and 8 |
1140 | * bit per color mode. */ | |
55bc60db | 1141 | if (intel_sdvo->has_hdmi_monitor && |
18316c8c | 1142 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 1143 | intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1144 | else |
1145 | intel_sdvo->color_range = 0; | |
1146 | } | |
1147 | ||
3685a8f3 | 1148 | if (intel_sdvo->color_range) |
50f3b016 | 1149 | pipe_config->limited_color_range = true; |
3685a8f3 | 1150 | |
70484559 DV |
1151 | /* Clock computation needs to happen after pixel multiplier. */ |
1152 | if (intel_sdvo->is_tv) | |
1153 | i9xx_adjust_sdvo_tv_clock(pipe_config); | |
1154 | ||
e2f0ba97 JB |
1155 | return true; |
1156 | } | |
1157 | ||
6cc5f341 | 1158 | static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder) |
e2f0ba97 | 1159 | { |
6cc5f341 | 1160 | struct drm_device *dev = intel_encoder->base.dev; |
e2f0ba97 | 1161 | struct drm_i915_private *dev_priv = dev->dev_private; |
eeb47937 | 1162 | struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); |
6cc5f341 | 1163 | struct drm_display_mode *adjusted_mode = |
eeb47937 DV |
1164 | &crtc->config.adjusted_mode; |
1165 | struct drm_display_mode *mode = &crtc->config.requested_mode; | |
8aca63aa | 1166 | struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); |
6c9547ff | 1167 | u32 sdvox; |
e2f0ba97 | 1168 | struct intel_sdvo_in_out_map in_out; |
6651819b | 1169 | struct intel_sdvo_dtd input_dtd, output_dtd; |
6c9547ff | 1170 | int rate; |
e2f0ba97 JB |
1171 | |
1172 | if (!mode) | |
1173 | return; | |
1174 | ||
1175 | /* First, set the input mapping for the first input to our controlled | |
1176 | * output. This is only correct if we're a single-input device, in | |
1177 | * which case the first input is the output from the appropriate SDVO | |
1178 | * channel on the motherboard. In a two-input device, the first input | |
1179 | * will be SDVOB and the second SDVOC. | |
1180 | */ | |
ea5b213a | 1181 | in_out.in0 = intel_sdvo->attached_output; |
e2f0ba97 JB |
1182 | in_out.in1 = 0; |
1183 | ||
c74696b9 PR |
1184 | intel_sdvo_set_value(intel_sdvo, |
1185 | SDVO_CMD_SET_IN_OUT_MAP, | |
1186 | &in_out, sizeof(in_out)); | |
e2f0ba97 | 1187 | |
6c9547ff CW |
1188 | /* Set the output timings to the screen */ |
1189 | if (!intel_sdvo_set_target_output(intel_sdvo, | |
1190 | intel_sdvo->attached_output)) | |
1191 | return; | |
e2f0ba97 | 1192 | |
6651819b DV |
1193 | /* lvds has a special fixed output timing. */ |
1194 | if (intel_sdvo->is_lvds) | |
1195 | intel_sdvo_get_dtd_from_mode(&output_dtd, | |
1196 | intel_sdvo->sdvo_lvds_fixed_mode); | |
1197 | else | |
1198 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); | |
c8d4bb54 DV |
1199 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
1200 | DRM_INFO("Setting output timings on %s failed\n", | |
1201 | SDVO_NAME(intel_sdvo)); | |
79e53945 JB |
1202 | |
1203 | /* Set the input timing to the screen. Assume always input 0. */ | |
32aad86f CW |
1204 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
1205 | return; | |
79e53945 | 1206 | |
97aaf910 CW |
1207 | if (intel_sdvo->has_hdmi_monitor) { |
1208 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); | |
1209 | intel_sdvo_set_colorimetry(intel_sdvo, | |
1210 | SDVO_COLORIMETRY_RGB256); | |
abedc077 | 1211 | intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); |
97aaf910 CW |
1212 | } else |
1213 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); | |
7026d4ac | 1214 | |
6c9547ff CW |
1215 | if (intel_sdvo->is_tv && |
1216 | !intel_sdvo_set_tv_format(intel_sdvo)) | |
1217 | return; | |
e2f0ba97 | 1218 | |
6651819b | 1219 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
eeb47937 | 1220 | |
e751823d EE |
1221 | if (intel_sdvo->is_tv || intel_sdvo->is_lvds) |
1222 | input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; | |
c8d4bb54 DV |
1223 | if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) |
1224 | DRM_INFO("Setting input timings on %s failed\n", | |
1225 | SDVO_NAME(intel_sdvo)); | |
79e53945 | 1226 | |
eeb47937 | 1227 | switch (crtc->config.pixel_multiplier) { |
6c9547ff | 1228 | default: |
ef1b460d | 1229 | WARN(1, "unknown pixel mutlipler specified\n"); |
32aad86f CW |
1230 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; |
1231 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; | |
1232 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; | |
79e53945 | 1233 | } |
32aad86f CW |
1234 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) |
1235 | return; | |
79e53945 JB |
1236 | |
1237 | /* Set the SDVO control regs. */ | |
a6c45cf0 | 1238 | if (INTEL_INFO(dev)->gen >= 4) { |
ba68e086 PZ |
1239 | /* The real mode polarity is set by the SDVO commands, using |
1240 | * struct intel_sdvo_dtd. */ | |
1241 | sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; | |
3685a8f3 | 1242 | if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi) |
e953fd7b | 1243 | sdvox |= intel_sdvo->color_range; |
6714afb1 CW |
1244 | if (INTEL_INFO(dev)->gen < 5) |
1245 | sdvox |= SDVO_BORDER_ENABLE; | |
e2f0ba97 | 1246 | } else { |
6c9547ff | 1247 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
ea5b213a | 1248 | switch (intel_sdvo->sdvo_reg) { |
e2debe91 | 1249 | case GEN3_SDVOB: |
e2f0ba97 JB |
1250 | sdvox &= SDVOB_PRESERVE_MASK; |
1251 | break; | |
e2debe91 | 1252 | case GEN3_SDVOC: |
e2f0ba97 JB |
1253 | sdvox &= SDVOC_PRESERVE_MASK; |
1254 | break; | |
1255 | } | |
1256 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; | |
1257 | } | |
3573c410 PZ |
1258 | |
1259 | if (INTEL_PCH_TYPE(dev) >= PCH_CPT) | |
eeb47937 | 1260 | sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
3573c410 | 1261 | else |
eeb47937 | 1262 | sdvox |= SDVO_PIPE_SEL(crtc->pipe); |
3573c410 | 1263 | |
da79de97 | 1264 | if (intel_sdvo->has_hdmi_audio) |
6c9547ff | 1265 | sdvox |= SDVO_AUDIO_ENABLE; |
79e53945 | 1266 | |
a6c45cf0 | 1267 | if (INTEL_INFO(dev)->gen >= 4) { |
e2f0ba97 JB |
1268 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
1269 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { | |
1270 | /* done in crtc_mode_set as it lives inside the dpll register */ | |
79e53945 | 1271 | } else { |
eeb47937 | 1272 | sdvox |= (crtc->config.pixel_multiplier - 1) |
6cc5f341 | 1273 | << SDVO_PORT_MULTIPLY_SHIFT; |
79e53945 JB |
1274 | } |
1275 | ||
6714afb1 CW |
1276 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && |
1277 | INTEL_INFO(dev)->gen < 5) | |
12682a97 | 1278 | sdvox |= SDVO_STALL_SELECT; |
ea5b213a | 1279 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
79e53945 JB |
1280 | } |
1281 | ||
4ac41f47 | 1282 | static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) |
79e53945 | 1283 | { |
4ac41f47 DV |
1284 | struct intel_sdvo_connector *intel_sdvo_connector = |
1285 | to_intel_sdvo_connector(&connector->base); | |
1286 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); | |
2f28c50b | 1287 | u16 active_outputs = 0; |
4ac41f47 DV |
1288 | |
1289 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); | |
1290 | ||
1291 | if (active_outputs & intel_sdvo_connector->output_flag) | |
1292 | return true; | |
1293 | else | |
1294 | return false; | |
1295 | } | |
1296 | ||
1297 | static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, | |
1298 | enum pipe *pipe) | |
1299 | { | |
1300 | struct drm_device *dev = encoder->base.dev; | |
79e53945 | 1301 | struct drm_i915_private *dev_priv = dev->dev_private; |
8aca63aa | 1302 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
2f28c50b | 1303 | u16 active_outputs = 0; |
4ac41f47 DV |
1304 | u32 tmp; |
1305 | ||
1306 | tmp = I915_READ(intel_sdvo->sdvo_reg); | |
7a7d1fb7 | 1307 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); |
4ac41f47 | 1308 | |
7a7d1fb7 | 1309 | if (!(tmp & SDVO_ENABLE) && (active_outputs == 0)) |
4ac41f47 DV |
1310 | return false; |
1311 | ||
1312 | if (HAS_PCH_CPT(dev)) | |
1313 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
1314 | else | |
1315 | *pipe = PORT_TO_PIPE(tmp); | |
1316 | ||
1317 | return true; | |
1318 | } | |
1319 | ||
045ac3b5 JB |
1320 | static void intel_sdvo_get_config(struct intel_encoder *encoder, |
1321 | struct intel_crtc_config *pipe_config) | |
1322 | { | |
6c49f241 DV |
1323 | struct drm_device *dev = encoder->base.dev; |
1324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8aca63aa | 1325 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
045ac3b5 | 1326 | struct intel_sdvo_dtd dtd; |
6c49f241 | 1327 | int encoder_pixel_multiplier = 0; |
18442d08 | 1328 | int dotclock; |
6c49f241 DV |
1329 | u32 flags = 0, sdvox; |
1330 | u8 val; | |
045ac3b5 JB |
1331 | bool ret; |
1332 | ||
1333 | ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); | |
1334 | if (!ret) { | |
bb760063 DV |
1335 | /* Some sdvo encoders are not spec compliant and don't |
1336 | * implement the mandatory get_timings function. */ | |
045ac3b5 | 1337 | DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); |
bb760063 DV |
1338 | pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; |
1339 | } else { | |
1340 | if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) | |
1341 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1342 | else | |
1343 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 1344 | |
bb760063 DV |
1345 | if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) |
1346 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1347 | else | |
1348 | flags |= DRM_MODE_FLAG_NVSYNC; | |
045ac3b5 JB |
1349 | } |
1350 | ||
045ac3b5 | 1351 | pipe_config->adjusted_mode.flags |= flags; |
045ac3b5 | 1352 | |
fdafa9e2 DV |
1353 | /* |
1354 | * pixel multiplier readout is tricky: Only on i915g/gm it is stored in | |
1355 | * the sdvo port register, on all other platforms it is part of the dpll | |
1356 | * state. Since the general pipe state readout happens before the | |
1357 | * encoder->get_config we so already have a valid pixel multplier on all | |
1358 | * other platfroms. | |
1359 | */ | |
6c49f241 DV |
1360 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
1361 | sdvox = I915_READ(intel_sdvo->sdvo_reg); | |
1362 | pipe_config->pixel_multiplier = | |
1363 | ((sdvox & SDVO_PORT_MULTIPLY_MASK) | |
1364 | >> SDVO_PORT_MULTIPLY_SHIFT) + 1; | |
1365 | } | |
045ac3b5 | 1366 | |
18442d08 VS |
1367 | dotclock = pipe_config->port_clock / pipe_config->pixel_multiplier; |
1368 | ||
1369 | if (HAS_PCH_SPLIT(dev)) | |
1370 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
1371 | ||
1372 | pipe_config->adjusted_mode.clock = dotclock; | |
1373 | ||
6c49f241 | 1374 | /* Cross check the port pixel multiplier with the sdvo encoder state. */ |
53b91408 DL |
1375 | if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, |
1376 | &val, 1)) { | |
1377 | switch (val) { | |
1378 | case SDVO_CLOCK_RATE_MULT_1X: | |
1379 | encoder_pixel_multiplier = 1; | |
1380 | break; | |
1381 | case SDVO_CLOCK_RATE_MULT_2X: | |
1382 | encoder_pixel_multiplier = 2; | |
1383 | break; | |
1384 | case SDVO_CLOCK_RATE_MULT_4X: | |
1385 | encoder_pixel_multiplier = 4; | |
1386 | break; | |
1387 | } | |
6c49f241 | 1388 | } |
fdafa9e2 | 1389 | |
6c49f241 DV |
1390 | WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, |
1391 | "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", | |
1392 | pipe_config->pixel_multiplier, encoder_pixel_multiplier); | |
045ac3b5 JB |
1393 | } |
1394 | ||
ce22c320 DV |
1395 | static void intel_disable_sdvo(struct intel_encoder *encoder) |
1396 | { | |
1397 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
8aca63aa | 1398 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
ce22c320 DV |
1399 | u32 temp; |
1400 | ||
1401 | intel_sdvo_set_active_outputs(intel_sdvo, 0); | |
1402 | if (0) | |
1403 | intel_sdvo_set_encoder_power_state(intel_sdvo, | |
1404 | DRM_MODE_DPMS_OFF); | |
1405 | ||
1406 | temp = I915_READ(intel_sdvo->sdvo_reg); | |
1407 | if ((temp & SDVO_ENABLE) != 0) { | |
776ca7cf CW |
1408 | /* HW workaround for IBX, we need to move the port to |
1409 | * transcoder A before disabling it. */ | |
1410 | if (HAS_PCH_IBX(encoder->base.dev)) { | |
1411 | struct drm_crtc *crtc = encoder->base.crtc; | |
1412 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
1413 | ||
1414 | if (temp & SDVO_PIPE_B_SELECT) { | |
1415 | temp &= ~SDVO_PIPE_B_SELECT; | |
1416 | I915_WRITE(intel_sdvo->sdvo_reg, temp); | |
1417 | POSTING_READ(intel_sdvo->sdvo_reg); | |
1418 | ||
1419 | /* Again we need to write this twice. */ | |
1420 | I915_WRITE(intel_sdvo->sdvo_reg, temp); | |
1421 | POSTING_READ(intel_sdvo->sdvo_reg); | |
1422 | ||
1423 | /* Transcoder selection bits only update | |
1424 | * effectively on vblank. */ | |
1425 | if (crtc) | |
1426 | intel_wait_for_vblank(encoder->base.dev, pipe); | |
1427 | else | |
1428 | msleep(50); | |
1429 | } | |
1430 | } | |
1431 | ||
ce22c320 DV |
1432 | intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); |
1433 | } | |
1434 | } | |
1435 | ||
1436 | static void intel_enable_sdvo(struct intel_encoder *encoder) | |
1437 | { | |
1438 | struct drm_device *dev = encoder->base.dev; | |
1439 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8aca63aa | 1440 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
ce22c320 | 1441 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
79e53945 | 1442 | u32 temp; |
ce22c320 DV |
1443 | bool input1, input2; |
1444 | int i; | |
1445 | u8 status; | |
1446 | ||
1447 | temp = I915_READ(intel_sdvo->sdvo_reg); | |
776ca7cf CW |
1448 | if ((temp & SDVO_ENABLE) == 0) { |
1449 | /* HW workaround for IBX, we need to move the port | |
dc0fa718 PZ |
1450 | * to transcoder A before disabling it, so restore it here. */ |
1451 | if (HAS_PCH_IBX(dev)) | |
1452 | temp |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
776ca7cf | 1453 | |
ce22c320 | 1454 | intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); |
776ca7cf | 1455 | } |
ce22c320 DV |
1456 | for (i = 0; i < 2; i++) |
1457 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1458 | ||
1459 | status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); | |
1460 | /* Warn if the device reported failure to sync. | |
1461 | * A lot of SDVO devices fail to notify of sync, but it's | |
1462 | * a given it the status is a success, we succeeded. | |
1463 | */ | |
1464 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { | |
1465 | DRM_DEBUG_KMS("First %s output reported failure to " | |
1466 | "sync\n", SDVO_NAME(intel_sdvo)); | |
1467 | } | |
1468 | ||
1469 | if (0) | |
1470 | intel_sdvo_set_encoder_power_state(intel_sdvo, | |
1471 | DRM_MODE_DPMS_ON); | |
1472 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); | |
1473 | } | |
1474 | ||
6b1c087b | 1475 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
b2cabb0e | 1476 | static void intel_sdvo_dpms(struct drm_connector *connector, int mode) |
79e53945 | 1477 | { |
b2cabb0e DV |
1478 | struct drm_crtc *crtc; |
1479 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); | |
1480 | ||
1481 | /* dvo supports only 2 dpms states. */ | |
1482 | if (mode != DRM_MODE_DPMS_ON) | |
1483 | mode = DRM_MODE_DPMS_OFF; | |
1484 | ||
1485 | if (mode == connector->dpms) | |
1486 | return; | |
1487 | ||
1488 | connector->dpms = mode; | |
1489 | ||
1490 | /* Only need to change hw state when actually enabled */ | |
1491 | crtc = intel_sdvo->base.base.crtc; | |
1492 | if (!crtc) { | |
1493 | intel_sdvo->base.connectors_active = false; | |
1494 | return; | |
1495 | } | |
79e53945 | 1496 | |
6b1c087b JN |
1497 | /* We set active outputs manually below in case pipe dpms doesn't change |
1498 | * due to cloning. */ | |
79e53945 | 1499 | if (mode != DRM_MODE_DPMS_ON) { |
ea5b213a | 1500 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
79e53945 | 1501 | if (0) |
ea5b213a | 1502 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
79e53945 | 1503 | |
b2cabb0e DV |
1504 | intel_sdvo->base.connectors_active = false; |
1505 | ||
1506 | intel_crtc_update_dpms(crtc); | |
79e53945 | 1507 | } else { |
b2cabb0e DV |
1508 | intel_sdvo->base.connectors_active = true; |
1509 | ||
1510 | intel_crtc_update_dpms(crtc); | |
79e53945 JB |
1511 | |
1512 | if (0) | |
ea5b213a CW |
1513 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
1514 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); | |
79e53945 | 1515 | } |
0a91ca29 | 1516 | |
b980514c | 1517 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
1518 | } |
1519 | ||
79e53945 JB |
1520 | static int intel_sdvo_mode_valid(struct drm_connector *connector, |
1521 | struct drm_display_mode *mode) | |
1522 | { | |
df0e9248 | 1523 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
79e53945 JB |
1524 | |
1525 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1526 | return MODE_NO_DBLESCAN; | |
1527 | ||
ea5b213a | 1528 | if (intel_sdvo->pixel_clock_min > mode->clock) |
79e53945 JB |
1529 | return MODE_CLOCK_LOW; |
1530 | ||
ea5b213a | 1531 | if (intel_sdvo->pixel_clock_max < mode->clock) |
79e53945 JB |
1532 | return MODE_CLOCK_HIGH; |
1533 | ||
8545423a | 1534 | if (intel_sdvo->is_lvds) { |
ea5b213a | 1535 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) |
12682a97 | 1536 | return MODE_PANEL; |
1537 | ||
ea5b213a | 1538 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) |
12682a97 | 1539 | return MODE_PANEL; |
1540 | } | |
1541 | ||
79e53945 JB |
1542 | return MODE_OK; |
1543 | } | |
1544 | ||
ea5b213a | 1545 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
79e53945 | 1546 | { |
1a3665c8 | 1547 | BUILD_BUG_ON(sizeof(*caps) != 8); |
e957d772 CW |
1548 | if (!intel_sdvo_get_value(intel_sdvo, |
1549 | SDVO_CMD_GET_DEVICE_CAPS, | |
1550 | caps, sizeof(*caps))) | |
1551 | return false; | |
1552 | ||
1553 | DRM_DEBUG_KMS("SDVO capabilities:\n" | |
1554 | " vendor_id: %d\n" | |
1555 | " device_id: %d\n" | |
1556 | " device_rev_id: %d\n" | |
1557 | " sdvo_version_major: %d\n" | |
1558 | " sdvo_version_minor: %d\n" | |
1559 | " sdvo_inputs_mask: %d\n" | |
1560 | " smooth_scaling: %d\n" | |
1561 | " sharp_scaling: %d\n" | |
1562 | " up_scaling: %d\n" | |
1563 | " down_scaling: %d\n" | |
1564 | " stall_support: %d\n" | |
1565 | " output_flags: %d\n", | |
1566 | caps->vendor_id, | |
1567 | caps->device_id, | |
1568 | caps->device_rev_id, | |
1569 | caps->sdvo_version_major, | |
1570 | caps->sdvo_version_minor, | |
1571 | caps->sdvo_inputs_mask, | |
1572 | caps->smooth_scaling, | |
1573 | caps->sharp_scaling, | |
1574 | caps->up_scaling, | |
1575 | caps->down_scaling, | |
1576 | caps->stall_support, | |
1577 | caps->output_flags); | |
1578 | ||
1579 | return true; | |
79e53945 JB |
1580 | } |
1581 | ||
5fa7ac9c | 1582 | static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) |
79e53945 | 1583 | { |
768b107e | 1584 | struct drm_device *dev = intel_sdvo->base.base.dev; |
5fa7ac9c | 1585 | uint16_t hotplug; |
79e53945 | 1586 | |
768b107e DV |
1587 | /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise |
1588 | * on the line. */ | |
1589 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
5fa7ac9c | 1590 | return 0; |
768b107e | 1591 | |
5fa7ac9c JN |
1592 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, |
1593 | &hotplug, sizeof(hotplug))) | |
1594 | return 0; | |
768b107e | 1595 | |
5fa7ac9c | 1596 | return hotplug; |
79e53945 JB |
1597 | } |
1598 | ||
cc68c81a | 1599 | static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) |
79e53945 | 1600 | { |
8aca63aa | 1601 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
79e53945 | 1602 | |
5fa7ac9c JN |
1603 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, |
1604 | &intel_sdvo->hotplug_active, 2); | |
79e53945 JB |
1605 | } |
1606 | ||
fb7a46f3 | 1607 | static bool |
ea5b213a | 1608 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
fb7a46f3 | 1609 | { |
bc65212c | 1610 | /* Is there more than one type of output? */ |
2294488d | 1611 | return hweight16(intel_sdvo->caps.output_flags) > 1; |
fb7a46f3 | 1612 | } |
1613 | ||
f899fc64 | 1614 | static struct edid * |
e957d772 | 1615 | intel_sdvo_get_edid(struct drm_connector *connector) |
f899fc64 | 1616 | { |
e957d772 CW |
1617 | struct intel_sdvo *sdvo = intel_attached_sdvo(connector); |
1618 | return drm_get_edid(connector, &sdvo->ddc); | |
f899fc64 CW |
1619 | } |
1620 | ||
ff482d83 CW |
1621 | /* Mac mini hack -- use the same DDC as the analog connector */ |
1622 | static struct edid * | |
1623 | intel_sdvo_get_analog_edid(struct drm_connector *connector) | |
1624 | { | |
f899fc64 | 1625 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
ff482d83 | 1626 | |
0c1dab89 | 1627 | return drm_get_edid(connector, |
3bd7d909 | 1628 | intel_gmbus_get_adapter(dev_priv, |
41aa3448 | 1629 | dev_priv->vbt.crt_ddc_pin)); |
ff482d83 CW |
1630 | } |
1631 | ||
c43b5634 | 1632 | static enum drm_connector_status |
8bf38485 | 1633 | intel_sdvo_tmds_sink_detect(struct drm_connector *connector) |
9dff6af8 | 1634 | { |
df0e9248 | 1635 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
9d1a903d CW |
1636 | enum drm_connector_status status; |
1637 | struct edid *edid; | |
9dff6af8 | 1638 | |
e957d772 | 1639 | edid = intel_sdvo_get_edid(connector); |
57cdaf90 | 1640 | |
ea5b213a | 1641 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
e957d772 | 1642 | u8 ddc, saved_ddc = intel_sdvo->ddc_bus; |
9d1a903d | 1643 | |
7c3f0a27 ZY |
1644 | /* |
1645 | * Don't use the 1 as the argument of DDC bus switch to get | |
1646 | * the EDID. It is used for SDVO SPD ROM. | |
1647 | */ | |
9d1a903d | 1648 | for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { |
e957d772 CW |
1649 | intel_sdvo->ddc_bus = ddc; |
1650 | edid = intel_sdvo_get_edid(connector); | |
1651 | if (edid) | |
7c3f0a27 | 1652 | break; |
7c3f0a27 | 1653 | } |
e957d772 CW |
1654 | /* |
1655 | * If we found the EDID on the other bus, | |
1656 | * assume that is the correct DDC bus. | |
1657 | */ | |
1658 | if (edid == NULL) | |
1659 | intel_sdvo->ddc_bus = saved_ddc; | |
7c3f0a27 | 1660 | } |
9d1a903d CW |
1661 | |
1662 | /* | |
1663 | * When there is no edid and no monitor is connected with VGA | |
1664 | * port, try to use the CRT ddc to read the EDID for DVI-connector. | |
57cdaf90 | 1665 | */ |
ff482d83 CW |
1666 | if (edid == NULL) |
1667 | edid = intel_sdvo_get_analog_edid(connector); | |
149c36a3 | 1668 | |
2f551c84 | 1669 | status = connector_status_unknown; |
9dff6af8 | 1670 | if (edid != NULL) { |
149c36a3 | 1671 | /* DDC bus is shared, match EDID to connector type */ |
9d1a903d CW |
1672 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
1673 | status = connector_status_connected; | |
da79de97 CW |
1674 | if (intel_sdvo->is_hdmi) { |
1675 | intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); | |
1676 | intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); | |
abedc077 VS |
1677 | intel_sdvo->rgb_quant_range_selectable = |
1678 | drm_rgb_quant_range_selectable(edid); | |
da79de97 | 1679 | } |
13946743 CW |
1680 | } else |
1681 | status = connector_status_disconnected; | |
9d1a903d CW |
1682 | kfree(edid); |
1683 | } | |
7f36e7ed CW |
1684 | |
1685 | if (status == connector_status_connected) { | |
1686 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); | |
c3e5f67b DV |
1687 | if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) |
1688 | intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); | |
7f36e7ed CW |
1689 | } |
1690 | ||
2b8d33f7 | 1691 | return status; |
9dff6af8 ML |
1692 | } |
1693 | ||
52220085 CW |
1694 | static bool |
1695 | intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, | |
1696 | struct edid *edid) | |
1697 | { | |
1698 | bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); | |
1699 | bool connector_is_digital = !!IS_DIGITAL(sdvo); | |
1700 | ||
1701 | DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", | |
1702 | connector_is_digital, monitor_is_digital); | |
1703 | return connector_is_digital == monitor_is_digital; | |
1704 | } | |
1705 | ||
7b334fcb | 1706 | static enum drm_connector_status |
930a9e28 | 1707 | intel_sdvo_detect(struct drm_connector *connector, bool force) |
79e53945 | 1708 | { |
fb7a46f3 | 1709 | uint16_t response; |
df0e9248 | 1710 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
615fb93f | 1711 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
14571b4c | 1712 | enum drm_connector_status ret; |
79e53945 | 1713 | |
164c8598 CW |
1714 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1715 | connector->base.id, drm_get_connector_name(connector)); | |
1716 | ||
fc37381c CW |
1717 | if (!intel_sdvo_get_value(intel_sdvo, |
1718 | SDVO_CMD_GET_ATTACHED_DISPLAYS, | |
1719 | &response, 2)) | |
32aad86f | 1720 | return connector_status_unknown; |
79e53945 | 1721 | |
e957d772 CW |
1722 | DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", |
1723 | response & 0xff, response >> 8, | |
1724 | intel_sdvo_connector->output_flag); | |
e2f0ba97 | 1725 | |
fb7a46f3 | 1726 | if (response == 0) |
79e53945 | 1727 | return connector_status_disconnected; |
fb7a46f3 | 1728 | |
ea5b213a | 1729 | intel_sdvo->attached_output = response; |
14571b4c | 1730 | |
97aaf910 CW |
1731 | intel_sdvo->has_hdmi_monitor = false; |
1732 | intel_sdvo->has_hdmi_audio = false; | |
abedc077 | 1733 | intel_sdvo->rgb_quant_range_selectable = false; |
97aaf910 | 1734 | |
615fb93f | 1735 | if ((intel_sdvo_connector->output_flag & response) == 0) |
14571b4c | 1736 | ret = connector_status_disconnected; |
13946743 | 1737 | else if (IS_TMDS(intel_sdvo_connector)) |
8bf38485 | 1738 | ret = intel_sdvo_tmds_sink_detect(connector); |
13946743 CW |
1739 | else { |
1740 | struct edid *edid; | |
1741 | ||
1742 | /* if we have an edid check it matches the connection */ | |
1743 | edid = intel_sdvo_get_edid(connector); | |
1744 | if (edid == NULL) | |
1745 | edid = intel_sdvo_get_analog_edid(connector); | |
1746 | if (edid != NULL) { | |
52220085 CW |
1747 | if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, |
1748 | edid)) | |
13946743 | 1749 | ret = connector_status_connected; |
52220085 CW |
1750 | else |
1751 | ret = connector_status_disconnected; | |
1752 | ||
13946743 CW |
1753 | kfree(edid); |
1754 | } else | |
1755 | ret = connector_status_connected; | |
1756 | } | |
14571b4c ZW |
1757 | |
1758 | /* May update encoder flag for like clock for SDVO TV, etc.*/ | |
1759 | if (ret == connector_status_connected) { | |
ea5b213a CW |
1760 | intel_sdvo->is_tv = false; |
1761 | intel_sdvo->is_lvds = false; | |
14571b4c | 1762 | |
09ede541 | 1763 | if (response & SDVO_TV_MASK) |
ea5b213a | 1764 | intel_sdvo->is_tv = true; |
14571b4c | 1765 | if (response & SDVO_LVDS_MASK) |
8545423a | 1766 | intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; |
fb7a46f3 | 1767 | } |
14571b4c ZW |
1768 | |
1769 | return ret; | |
79e53945 JB |
1770 | } |
1771 | ||
e2f0ba97 | 1772 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
79e53945 | 1773 | { |
ff482d83 | 1774 | struct edid *edid; |
79e53945 JB |
1775 | |
1776 | /* set the bus switch and get the modes */ | |
e957d772 | 1777 | edid = intel_sdvo_get_edid(connector); |
79e53945 | 1778 | |
57cdaf90 KP |
1779 | /* |
1780 | * Mac mini hack. On this device, the DVI-I connector shares one DDC | |
1781 | * link between analog and digital outputs. So, if the regular SDVO | |
1782 | * DDC fails, check to see if the analog output is disconnected, in | |
1783 | * which case we'll look there for the digital DDC data. | |
e2f0ba97 | 1784 | */ |
f899fc64 CW |
1785 | if (edid == NULL) |
1786 | edid = intel_sdvo_get_analog_edid(connector); | |
1787 | ||
ff482d83 | 1788 | if (edid != NULL) { |
52220085 CW |
1789 | if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), |
1790 | edid)) { | |
0c1dab89 CW |
1791 | drm_mode_connector_update_edid_property(connector, edid); |
1792 | drm_add_edid_modes(connector, edid); | |
1793 | } | |
13946743 | 1794 | |
ff482d83 | 1795 | kfree(edid); |
e2f0ba97 | 1796 | } |
e2f0ba97 JB |
1797 | } |
1798 | ||
1799 | /* | |
1800 | * Set of SDVO TV modes. | |
1801 | * Note! This is in reply order (see loop in get_tv_modes). | |
1802 | * XXX: all 60Hz refresh? | |
1803 | */ | |
b1f559ec | 1804 | static const struct drm_display_mode sdvo_tv_modes[] = { |
7026d4ac ZW |
1805 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
1806 | 416, 0, 200, 201, 232, 233, 0, | |
e2f0ba97 | 1807 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1808 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
1809 | 416, 0, 240, 241, 272, 273, 0, | |
e2f0ba97 | 1810 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1811 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
1812 | 496, 0, 300, 301, 332, 333, 0, | |
e2f0ba97 | 1813 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1814 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
1815 | 736, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1816 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1817 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
1818 | 736, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1819 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1820 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
1821 | 736, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1822 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1823 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
1824 | 800, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1825 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1826 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
1827 | 800, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1828 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1829 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
1830 | 816, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1831 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1832 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
1833 | 816, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1834 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1835 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
1836 | 816, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1837 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1838 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
1839 | 816, 0, 540, 541, 572, 573, 0, | |
e2f0ba97 | 1840 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1841 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
1842 | 816, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1843 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1844 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
1845 | 864, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1846 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1847 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
1848 | 896, 0, 600, 601, 632, 633, 0, | |
e2f0ba97 | 1849 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1850 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
1851 | 928, 0, 624, 625, 656, 657, 0, | |
e2f0ba97 | 1852 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1853 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
1854 | 1016, 0, 766, 767, 798, 799, 0, | |
e2f0ba97 | 1855 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1856 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
1857 | 1120, 0, 768, 769, 800, 801, 0, | |
e2f0ba97 | 1858 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1859 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
1860 | 1376, 0, 1024, 1025, 1056, 1057, 0, | |
e2f0ba97 JB |
1861 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1862 | }; | |
1863 | ||
1864 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) | |
1865 | { | |
df0e9248 | 1866 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
7026d4ac | 1867 | struct intel_sdvo_sdtv_resolution_request tv_res; |
ce6feabd ZY |
1868 | uint32_t reply = 0, format_map = 0; |
1869 | int i; | |
e2f0ba97 JB |
1870 | |
1871 | /* Read the list of supported input resolutions for the selected TV | |
1872 | * format. | |
1873 | */ | |
40039750 | 1874 | format_map = 1 << intel_sdvo->tv_format_index; |
ce6feabd | 1875 | memcpy(&tv_res, &format_map, |
32aad86f | 1876 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); |
ce6feabd | 1877 | |
32aad86f CW |
1878 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) |
1879 | return; | |
ce6feabd | 1880 | |
32aad86f | 1881 | BUILD_BUG_ON(sizeof(tv_res) != 3); |
e957d772 CW |
1882 | if (!intel_sdvo_write_cmd(intel_sdvo, |
1883 | SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, | |
32aad86f CW |
1884 | &tv_res, sizeof(tv_res))) |
1885 | return; | |
1886 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) | |
e2f0ba97 JB |
1887 | return; |
1888 | ||
1889 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) | |
7026d4ac ZW |
1890 | if (reply & (1 << i)) { |
1891 | struct drm_display_mode *nmode; | |
1892 | nmode = drm_mode_duplicate(connector->dev, | |
32aad86f | 1893 | &sdvo_tv_modes[i]); |
7026d4ac ZW |
1894 | if (nmode) |
1895 | drm_mode_probed_add(connector, nmode); | |
1896 | } | |
e2f0ba97 JB |
1897 | } |
1898 | ||
7086c87f ML |
1899 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
1900 | { | |
df0e9248 | 1901 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
7086c87f | 1902 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
12682a97 | 1903 | struct drm_display_mode *newmode; |
7086c87f ML |
1904 | |
1905 | /* | |
c3456fb3 | 1906 | * Fetch modes from VBT. For SDVO prefer the VBT mode since some |
4300a0f8 | 1907 | * SDVO->LVDS transcoders can't cope with the EDID mode. |
7086c87f | 1908 | */ |
41aa3448 | 1909 | if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { |
7086c87f | 1910 | newmode = drm_mode_duplicate(connector->dev, |
41aa3448 | 1911 | dev_priv->vbt.sdvo_lvds_vbt_mode); |
7086c87f ML |
1912 | if (newmode != NULL) { |
1913 | /* Guarantee the mode is preferred */ | |
1914 | newmode->type = (DRM_MODE_TYPE_PREFERRED | | |
1915 | DRM_MODE_TYPE_DRIVER); | |
1916 | drm_mode_probed_add(connector, newmode); | |
1917 | } | |
1918 | } | |
12682a97 | 1919 | |
4300a0f8 DA |
1920 | /* |
1921 | * Attempt to get the mode list from DDC. | |
1922 | * Assume that the preferred modes are | |
1923 | * arranged in priority order. | |
1924 | */ | |
1925 | intel_ddc_get_modes(connector, &intel_sdvo->ddc); | |
1926 | ||
12682a97 | 1927 | list_for_each_entry(newmode, &connector->probed_modes, head) { |
1928 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
ea5b213a | 1929 | intel_sdvo->sdvo_lvds_fixed_mode = |
12682a97 | 1930 | drm_mode_duplicate(connector->dev, newmode); |
6c9547ff | 1931 | |
8545423a | 1932 | intel_sdvo->is_lvds = true; |
12682a97 | 1933 | break; |
1934 | } | |
1935 | } | |
1936 | ||
7086c87f ML |
1937 | } |
1938 | ||
e2f0ba97 JB |
1939 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
1940 | { | |
615fb93f | 1941 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
e2f0ba97 | 1942 | |
615fb93f | 1943 | if (IS_TV(intel_sdvo_connector)) |
e2f0ba97 | 1944 | intel_sdvo_get_tv_modes(connector); |
615fb93f | 1945 | else if (IS_LVDS(intel_sdvo_connector)) |
7086c87f | 1946 | intel_sdvo_get_lvds_modes(connector); |
e2f0ba97 JB |
1947 | else |
1948 | intel_sdvo_get_ddc_modes(connector); | |
1949 | ||
32aad86f | 1950 | return !list_empty(&connector->probed_modes); |
79e53945 JB |
1951 | } |
1952 | ||
fcc8d672 CW |
1953 | static void |
1954 | intel_sdvo_destroy_enhance_property(struct drm_connector *connector) | |
b9219c5e | 1955 | { |
615fb93f | 1956 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
b9219c5e ZY |
1957 | struct drm_device *dev = connector->dev; |
1958 | ||
c5521706 CW |
1959 | if (intel_sdvo_connector->left) |
1960 | drm_property_destroy(dev, intel_sdvo_connector->left); | |
1961 | if (intel_sdvo_connector->right) | |
1962 | drm_property_destroy(dev, intel_sdvo_connector->right); | |
1963 | if (intel_sdvo_connector->top) | |
1964 | drm_property_destroy(dev, intel_sdvo_connector->top); | |
1965 | if (intel_sdvo_connector->bottom) | |
1966 | drm_property_destroy(dev, intel_sdvo_connector->bottom); | |
1967 | if (intel_sdvo_connector->hpos) | |
1968 | drm_property_destroy(dev, intel_sdvo_connector->hpos); | |
1969 | if (intel_sdvo_connector->vpos) | |
1970 | drm_property_destroy(dev, intel_sdvo_connector->vpos); | |
1971 | if (intel_sdvo_connector->saturation) | |
1972 | drm_property_destroy(dev, intel_sdvo_connector->saturation); | |
1973 | if (intel_sdvo_connector->contrast) | |
1974 | drm_property_destroy(dev, intel_sdvo_connector->contrast); | |
1975 | if (intel_sdvo_connector->hue) | |
1976 | drm_property_destroy(dev, intel_sdvo_connector->hue); | |
1977 | if (intel_sdvo_connector->sharpness) | |
1978 | drm_property_destroy(dev, intel_sdvo_connector->sharpness); | |
1979 | if (intel_sdvo_connector->flicker_filter) | |
1980 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter); | |
1981 | if (intel_sdvo_connector->flicker_filter_2d) | |
1982 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d); | |
1983 | if (intel_sdvo_connector->flicker_filter_adaptive) | |
1984 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive); | |
1985 | if (intel_sdvo_connector->tv_luma_filter) | |
1986 | drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter); | |
1987 | if (intel_sdvo_connector->tv_chroma_filter) | |
1988 | drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter); | |
e044218a CW |
1989 | if (intel_sdvo_connector->dot_crawl) |
1990 | drm_property_destroy(dev, intel_sdvo_connector->dot_crawl); | |
c5521706 CW |
1991 | if (intel_sdvo_connector->brightness) |
1992 | drm_property_destroy(dev, intel_sdvo_connector->brightness); | |
b9219c5e ZY |
1993 | } |
1994 | ||
79e53945 JB |
1995 | static void intel_sdvo_destroy(struct drm_connector *connector) |
1996 | { | |
615fb93f | 1997 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
79e53945 | 1998 | |
c5521706 | 1999 | if (intel_sdvo_connector->tv_format) |
ce6feabd | 2000 | drm_property_destroy(connector->dev, |
c5521706 | 2001 | intel_sdvo_connector->tv_format); |
b9219c5e | 2002 | |
d2a82a6f | 2003 | intel_sdvo_destroy_enhance_property(connector); |
79e53945 JB |
2004 | drm_sysfs_connector_remove(connector); |
2005 | drm_connector_cleanup(connector); | |
4b745b1e | 2006 | kfree(intel_sdvo_connector); |
79e53945 JB |
2007 | } |
2008 | ||
1aad7ac0 CW |
2009 | static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) |
2010 | { | |
2011 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); | |
2012 | struct edid *edid; | |
2013 | bool has_audio = false; | |
2014 | ||
2015 | if (!intel_sdvo->is_hdmi) | |
2016 | return false; | |
2017 | ||
2018 | edid = intel_sdvo_get_edid(connector); | |
2019 | if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) | |
2020 | has_audio = drm_detect_monitor_audio(edid); | |
38ab8a20 | 2021 | kfree(edid); |
1aad7ac0 CW |
2022 | |
2023 | return has_audio; | |
2024 | } | |
2025 | ||
ce6feabd ZY |
2026 | static int |
2027 | intel_sdvo_set_property(struct drm_connector *connector, | |
2028 | struct drm_property *property, | |
2029 | uint64_t val) | |
2030 | { | |
df0e9248 | 2031 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
615fb93f | 2032 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
e953fd7b | 2033 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
b9219c5e | 2034 | uint16_t temp_value; |
32aad86f CW |
2035 | uint8_t cmd; |
2036 | int ret; | |
ce6feabd | 2037 | |
662595df | 2038 | ret = drm_object_property_set_value(&connector->base, property, val); |
32aad86f CW |
2039 | if (ret) |
2040 | return ret; | |
ce6feabd | 2041 | |
3f43c48d | 2042 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
2043 | int i = val; |
2044 | bool has_audio; | |
2045 | ||
2046 | if (i == intel_sdvo_connector->force_audio) | |
7f36e7ed CW |
2047 | return 0; |
2048 | ||
1aad7ac0 | 2049 | intel_sdvo_connector->force_audio = i; |
7f36e7ed | 2050 | |
c3e5f67b | 2051 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
2052 | has_audio = intel_sdvo_detect_hdmi_audio(connector); |
2053 | else | |
c3e5f67b | 2054 | has_audio = (i == HDMI_AUDIO_ON); |
7f36e7ed | 2055 | |
1aad7ac0 | 2056 | if (has_audio == intel_sdvo->has_hdmi_audio) |
7f36e7ed | 2057 | return 0; |
7f36e7ed | 2058 | |
1aad7ac0 | 2059 | intel_sdvo->has_hdmi_audio = has_audio; |
7f36e7ed CW |
2060 | goto done; |
2061 | } | |
2062 | ||
e953fd7b | 2063 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
2064 | bool old_auto = intel_sdvo->color_range_auto; |
2065 | uint32_t old_range = intel_sdvo->color_range; | |
2066 | ||
55bc60db VS |
2067 | switch (val) { |
2068 | case INTEL_BROADCAST_RGB_AUTO: | |
2069 | intel_sdvo->color_range_auto = true; | |
2070 | break; | |
2071 | case INTEL_BROADCAST_RGB_FULL: | |
2072 | intel_sdvo->color_range_auto = false; | |
2073 | intel_sdvo->color_range = 0; | |
2074 | break; | |
2075 | case INTEL_BROADCAST_RGB_LIMITED: | |
2076 | intel_sdvo->color_range_auto = false; | |
4f3a8bc7 PZ |
2077 | /* FIXME: this bit is only valid when using TMDS |
2078 | * encoding and 8 bit per color mode. */ | |
2079 | intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; | |
55bc60db VS |
2080 | break; |
2081 | default: | |
2082 | return -EINVAL; | |
2083 | } | |
ae4edb80 DV |
2084 | |
2085 | if (old_auto == intel_sdvo->color_range_auto && | |
2086 | old_range == intel_sdvo->color_range) | |
2087 | return 0; | |
2088 | ||
7f36e7ed CW |
2089 | goto done; |
2090 | } | |
2091 | ||
c5521706 CW |
2092 | #define CHECK_PROPERTY(name, NAME) \ |
2093 | if (intel_sdvo_connector->name == property) { \ | |
2094 | if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ | |
2095 | if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ | |
2096 | cmd = SDVO_CMD_SET_##NAME; \ | |
2097 | intel_sdvo_connector->cur_##name = temp_value; \ | |
2098 | goto set_value; \ | |
2099 | } | |
2100 | ||
2101 | if (property == intel_sdvo_connector->tv_format) { | |
32aad86f CW |
2102 | if (val >= TV_FORMAT_NUM) |
2103 | return -EINVAL; | |
2104 | ||
40039750 | 2105 | if (intel_sdvo->tv_format_index == |
615fb93f | 2106 | intel_sdvo_connector->tv_format_supported[val]) |
32aad86f | 2107 | return 0; |
ce6feabd | 2108 | |
40039750 | 2109 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; |
c5521706 | 2110 | goto done; |
32aad86f | 2111 | } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { |
b9219c5e | 2112 | temp_value = val; |
c5521706 | 2113 | if (intel_sdvo_connector->left == property) { |
662595df | 2114 | drm_object_property_set_value(&connector->base, |
c5521706 | 2115 | intel_sdvo_connector->right, val); |
615fb93f | 2116 | if (intel_sdvo_connector->left_margin == temp_value) |
32aad86f | 2117 | return 0; |
b9219c5e | 2118 | |
615fb93f CW |
2119 | intel_sdvo_connector->left_margin = temp_value; |
2120 | intel_sdvo_connector->right_margin = temp_value; | |
2121 | temp_value = intel_sdvo_connector->max_hscan - | |
c5521706 | 2122 | intel_sdvo_connector->left_margin; |
b9219c5e | 2123 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
c5521706 CW |
2124 | goto set_value; |
2125 | } else if (intel_sdvo_connector->right == property) { | |
662595df | 2126 | drm_object_property_set_value(&connector->base, |
c5521706 | 2127 | intel_sdvo_connector->left, val); |
615fb93f | 2128 | if (intel_sdvo_connector->right_margin == temp_value) |
32aad86f | 2129 | return 0; |
b9219c5e | 2130 | |
615fb93f CW |
2131 | intel_sdvo_connector->left_margin = temp_value; |
2132 | intel_sdvo_connector->right_margin = temp_value; | |
2133 | temp_value = intel_sdvo_connector->max_hscan - | |
2134 | intel_sdvo_connector->left_margin; | |
b9219c5e | 2135 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
c5521706 CW |
2136 | goto set_value; |
2137 | } else if (intel_sdvo_connector->top == property) { | |
662595df | 2138 | drm_object_property_set_value(&connector->base, |
c5521706 | 2139 | intel_sdvo_connector->bottom, val); |
615fb93f | 2140 | if (intel_sdvo_connector->top_margin == temp_value) |
32aad86f | 2141 | return 0; |
b9219c5e | 2142 | |
615fb93f CW |
2143 | intel_sdvo_connector->top_margin = temp_value; |
2144 | intel_sdvo_connector->bottom_margin = temp_value; | |
2145 | temp_value = intel_sdvo_connector->max_vscan - | |
c5521706 | 2146 | intel_sdvo_connector->top_margin; |
b9219c5e | 2147 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
c5521706 CW |
2148 | goto set_value; |
2149 | } else if (intel_sdvo_connector->bottom == property) { | |
662595df | 2150 | drm_object_property_set_value(&connector->base, |
c5521706 | 2151 | intel_sdvo_connector->top, val); |
615fb93f | 2152 | if (intel_sdvo_connector->bottom_margin == temp_value) |
32aad86f CW |
2153 | return 0; |
2154 | ||
615fb93f CW |
2155 | intel_sdvo_connector->top_margin = temp_value; |
2156 | intel_sdvo_connector->bottom_margin = temp_value; | |
2157 | temp_value = intel_sdvo_connector->max_vscan - | |
c5521706 | 2158 | intel_sdvo_connector->top_margin; |
b9219c5e | 2159 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
c5521706 CW |
2160 | goto set_value; |
2161 | } | |
2162 | CHECK_PROPERTY(hpos, HPOS) | |
2163 | CHECK_PROPERTY(vpos, VPOS) | |
2164 | CHECK_PROPERTY(saturation, SATURATION) | |
2165 | CHECK_PROPERTY(contrast, CONTRAST) | |
2166 | CHECK_PROPERTY(hue, HUE) | |
2167 | CHECK_PROPERTY(brightness, BRIGHTNESS) | |
2168 | CHECK_PROPERTY(sharpness, SHARPNESS) | |
2169 | CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) | |
2170 | CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) | |
2171 | CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) | |
2172 | CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) | |
2173 | CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) | |
e044218a | 2174 | CHECK_PROPERTY(dot_crawl, DOT_CRAWL) |
c5521706 | 2175 | } |
b9219c5e | 2176 | |
c5521706 | 2177 | return -EINVAL; /* unknown property */ |
b9219c5e | 2178 | |
c5521706 CW |
2179 | set_value: |
2180 | if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) | |
2181 | return -EIO; | |
b9219c5e | 2182 | |
b9219c5e | 2183 | |
c5521706 | 2184 | done: |
c0c36b94 CW |
2185 | if (intel_sdvo->base.base.crtc) |
2186 | intel_crtc_restore_mode(intel_sdvo->base.base.crtc); | |
c5521706 | 2187 | |
32aad86f | 2188 | return 0; |
c5521706 | 2189 | #undef CHECK_PROPERTY |
ce6feabd ZY |
2190 | } |
2191 | ||
79e53945 | 2192 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
b2cabb0e | 2193 | .dpms = intel_sdvo_dpms, |
79e53945 JB |
2194 | .detect = intel_sdvo_detect, |
2195 | .fill_modes = drm_helper_probe_single_connector_modes, | |
ce6feabd | 2196 | .set_property = intel_sdvo_set_property, |
79e53945 JB |
2197 | .destroy = intel_sdvo_destroy, |
2198 | }; | |
2199 | ||
2200 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { | |
2201 | .get_modes = intel_sdvo_get_modes, | |
2202 | .mode_valid = intel_sdvo_mode_valid, | |
df0e9248 | 2203 | .best_encoder = intel_best_encoder, |
79e53945 JB |
2204 | }; |
2205 | ||
b358d0a6 | 2206 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
79e53945 | 2207 | { |
8aca63aa | 2208 | struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); |
d2a82a6f | 2209 | |
ea5b213a | 2210 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) |
d2a82a6f | 2211 | drm_mode_destroy(encoder->dev, |
ea5b213a | 2212 | intel_sdvo->sdvo_lvds_fixed_mode); |
d2a82a6f | 2213 | |
e957d772 | 2214 | i2c_del_adapter(&intel_sdvo->ddc); |
ea5b213a | 2215 | intel_encoder_destroy(encoder); |
79e53945 JB |
2216 | } |
2217 | ||
2218 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { | |
2219 | .destroy = intel_sdvo_enc_destroy, | |
2220 | }; | |
2221 | ||
b66d8424 CW |
2222 | static void |
2223 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) | |
2224 | { | |
2225 | uint16_t mask = 0; | |
2226 | unsigned int num_bits; | |
2227 | ||
2228 | /* Make a mask of outputs less than or equal to our own priority in the | |
2229 | * list. | |
2230 | */ | |
2231 | switch (sdvo->controlled_output) { | |
2232 | case SDVO_OUTPUT_LVDS1: | |
2233 | mask |= SDVO_OUTPUT_LVDS1; | |
2234 | case SDVO_OUTPUT_LVDS0: | |
2235 | mask |= SDVO_OUTPUT_LVDS0; | |
2236 | case SDVO_OUTPUT_TMDS1: | |
2237 | mask |= SDVO_OUTPUT_TMDS1; | |
2238 | case SDVO_OUTPUT_TMDS0: | |
2239 | mask |= SDVO_OUTPUT_TMDS0; | |
2240 | case SDVO_OUTPUT_RGB1: | |
2241 | mask |= SDVO_OUTPUT_RGB1; | |
2242 | case SDVO_OUTPUT_RGB0: | |
2243 | mask |= SDVO_OUTPUT_RGB0; | |
2244 | break; | |
2245 | } | |
2246 | ||
2247 | /* Count bits to find what number we are in the priority list. */ | |
2248 | mask &= sdvo->caps.output_flags; | |
2249 | num_bits = hweight16(mask); | |
2250 | /* If more than 3 outputs, default to DDC bus 3 for now. */ | |
2251 | if (num_bits > 3) | |
2252 | num_bits = 3; | |
2253 | ||
2254 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ | |
2255 | sdvo->ddc_bus = 1 << num_bits; | |
2256 | } | |
79e53945 | 2257 | |
e2f0ba97 JB |
2258 | /** |
2259 | * Choose the appropriate DDC bus for control bus switch command for this | |
2260 | * SDVO output based on the controlled output. | |
2261 | * | |
2262 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS | |
2263 | * outputs, then LVDS outputs. | |
2264 | */ | |
2265 | static void | |
b1083333 | 2266 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, |
ea5b213a | 2267 | struct intel_sdvo *sdvo, u32 reg) |
e2f0ba97 | 2268 | { |
b1083333 | 2269 | struct sdvo_device_mapping *mapping; |
e2f0ba97 | 2270 | |
eef4eacb | 2271 | if (sdvo->is_sdvob) |
b1083333 AJ |
2272 | mapping = &(dev_priv->sdvo_mappings[0]); |
2273 | else | |
2274 | mapping = &(dev_priv->sdvo_mappings[1]); | |
e2f0ba97 | 2275 | |
b66d8424 CW |
2276 | if (mapping->initialized) |
2277 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); | |
2278 | else | |
2279 | intel_sdvo_guess_ddc_bus(sdvo); | |
e2f0ba97 JB |
2280 | } |
2281 | ||
e957d772 CW |
2282 | static void |
2283 | intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, | |
2284 | struct intel_sdvo *sdvo, u32 reg) | |
2285 | { | |
2286 | struct sdvo_device_mapping *mapping; | |
46eb3036 | 2287 | u8 pin; |
e957d772 | 2288 | |
eef4eacb | 2289 | if (sdvo->is_sdvob) |
e957d772 CW |
2290 | mapping = &dev_priv->sdvo_mappings[0]; |
2291 | else | |
2292 | mapping = &dev_priv->sdvo_mappings[1]; | |
2293 | ||
6cb1612a | 2294 | if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin)) |
e957d772 | 2295 | pin = mapping->i2c_pin; |
6cb1612a JN |
2296 | else |
2297 | pin = GMBUS_PORT_DPB; | |
e957d772 | 2298 | |
6cb1612a JN |
2299 | sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); |
2300 | ||
2301 | /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow | |
2302 | * our code totally fails once we start using gmbus. Hence fall back to | |
2303 | * bit banging for now. */ | |
2304 | intel_gmbus_force_bit(sdvo->i2c, true); | |
e957d772 CW |
2305 | } |
2306 | ||
fbfcc4f3 JN |
2307 | /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ |
2308 | static void | |
2309 | intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) | |
2310 | { | |
2311 | intel_gmbus_force_bit(sdvo->i2c, false); | |
e957d772 CW |
2312 | } |
2313 | ||
e2f0ba97 | 2314 | static bool |
e27d8538 | 2315 | intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) |
e2f0ba97 | 2316 | { |
97aaf910 | 2317 | return intel_sdvo_check_supp_encode(intel_sdvo); |
e2f0ba97 JB |
2318 | } |
2319 | ||
714605e4 | 2320 | static u8 |
eef4eacb | 2321 | intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) |
714605e4 | 2322 | { |
2323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2324 | struct sdvo_device_mapping *my_mapping, *other_mapping; | |
2325 | ||
eef4eacb | 2326 | if (sdvo->is_sdvob) { |
714605e4 | 2327 | my_mapping = &dev_priv->sdvo_mappings[0]; |
2328 | other_mapping = &dev_priv->sdvo_mappings[1]; | |
2329 | } else { | |
2330 | my_mapping = &dev_priv->sdvo_mappings[1]; | |
2331 | other_mapping = &dev_priv->sdvo_mappings[0]; | |
2332 | } | |
2333 | ||
2334 | /* If the BIOS described our SDVO device, take advantage of it. */ | |
2335 | if (my_mapping->slave_addr) | |
2336 | return my_mapping->slave_addr; | |
2337 | ||
2338 | /* If the BIOS only described a different SDVO device, use the | |
2339 | * address that it isn't using. | |
2340 | */ | |
2341 | if (other_mapping->slave_addr) { | |
2342 | if (other_mapping->slave_addr == 0x70) | |
2343 | return 0x72; | |
2344 | else | |
2345 | return 0x70; | |
2346 | } | |
2347 | ||
2348 | /* No SDVO device info is found for another DVO port, | |
2349 | * so use mapping assumption we had before BIOS parsing. | |
2350 | */ | |
eef4eacb | 2351 | if (sdvo->is_sdvob) |
714605e4 | 2352 | return 0x70; |
2353 | else | |
2354 | return 0x72; | |
2355 | } | |
2356 | ||
14571b4c | 2357 | static void |
df0e9248 CW |
2358 | intel_sdvo_connector_init(struct intel_sdvo_connector *connector, |
2359 | struct intel_sdvo *encoder) | |
14571b4c | 2360 | { |
df0e9248 CW |
2361 | drm_connector_init(encoder->base.base.dev, |
2362 | &connector->base.base, | |
2363 | &intel_sdvo_connector_funcs, | |
2364 | connector->base.base.connector_type); | |
6070a4a9 | 2365 | |
df0e9248 CW |
2366 | drm_connector_helper_add(&connector->base.base, |
2367 | &intel_sdvo_connector_helper_funcs); | |
14571b4c | 2368 | |
8f4839e2 | 2369 | connector->base.base.interlace_allowed = 1; |
df0e9248 CW |
2370 | connector->base.base.doublescan_allowed = 0; |
2371 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; | |
4ac41f47 | 2372 | connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; |
14571b4c | 2373 | |
df0e9248 CW |
2374 | intel_connector_attach_encoder(&connector->base, &encoder->base); |
2375 | drm_sysfs_connector_add(&connector->base.base); | |
14571b4c | 2376 | } |
6070a4a9 | 2377 | |
7f36e7ed | 2378 | static void |
55bc60db VS |
2379 | intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, |
2380 | struct intel_sdvo_connector *connector) | |
7f36e7ed CW |
2381 | { |
2382 | struct drm_device *dev = connector->base.base.dev; | |
2383 | ||
3f43c48d | 2384 | intel_attach_force_audio_property(&connector->base.base); |
55bc60db | 2385 | if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { |
e953fd7b | 2386 | intel_attach_broadcast_rgb_property(&connector->base.base); |
55bc60db VS |
2387 | intel_sdvo->color_range_auto = true; |
2388 | } | |
7f36e7ed CW |
2389 | } |
2390 | ||
fb7a46f3 | 2391 | static bool |
ea5b213a | 2392 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
fb7a46f3 | 2393 | { |
4ef69c7a | 2394 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
14571b4c | 2395 | struct drm_connector *connector; |
cc68c81a | 2396 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
14571b4c | 2397 | struct intel_connector *intel_connector; |
615fb93f | 2398 | struct intel_sdvo_connector *intel_sdvo_connector; |
14571b4c | 2399 | |
b14c5679 | 2400 | intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); |
615fb93f | 2401 | if (!intel_sdvo_connector) |
14571b4c ZW |
2402 | return false; |
2403 | ||
14571b4c | 2404 | if (device == 0) { |
ea5b213a | 2405 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; |
615fb93f | 2406 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
14571b4c | 2407 | } else if (device == 1) { |
ea5b213a | 2408 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; |
615fb93f | 2409 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
14571b4c ZW |
2410 | } |
2411 | ||
615fb93f | 2412 | intel_connector = &intel_sdvo_connector->base; |
14571b4c | 2413 | connector = &intel_connector->base; |
5fa7ac9c JN |
2414 | if (intel_sdvo_get_hotplug_support(intel_sdvo) & |
2415 | intel_sdvo_connector->output_flag) { | |
5fa7ac9c | 2416 | intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; |
cc68c81a SF |
2417 | /* Some SDVO devices have one-shot hotplug interrupts. |
2418 | * Ensure that they get re-enabled when an interrupt happens. | |
2419 | */ | |
2420 | intel_encoder->hot_plug = intel_sdvo_enable_hotplug; | |
2421 | intel_sdvo_enable_hotplug(intel_encoder); | |
5fa7ac9c | 2422 | } else { |
821450c6 | 2423 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; |
5fa7ac9c | 2424 | } |
14571b4c ZW |
2425 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
2426 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; | |
2427 | ||
e27d8538 | 2428 | if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { |
14571b4c | 2429 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
e27d8538 | 2430 | intel_sdvo->is_hdmi = true; |
14571b4c | 2431 | } |
14571b4c | 2432 | |
df0e9248 | 2433 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
f797d221 | 2434 | if (intel_sdvo->is_hdmi) |
55bc60db | 2435 | intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); |
14571b4c ZW |
2436 | |
2437 | return true; | |
2438 | } | |
2439 | ||
2440 | static bool | |
ea5b213a | 2441 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
14571b4c | 2442 | { |
4ef69c7a CW |
2443 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2444 | struct drm_connector *connector; | |
2445 | struct intel_connector *intel_connector; | |
2446 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2447 | |
b14c5679 | 2448 | intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); |
615fb93f CW |
2449 | if (!intel_sdvo_connector) |
2450 | return false; | |
14571b4c | 2451 | |
615fb93f | 2452 | intel_connector = &intel_sdvo_connector->base; |
4ef69c7a CW |
2453 | connector = &intel_connector->base; |
2454 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; | |
2455 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; | |
14571b4c | 2456 | |
4ef69c7a CW |
2457 | intel_sdvo->controlled_output |= type; |
2458 | intel_sdvo_connector->output_flag = type; | |
14571b4c | 2459 | |
4ef69c7a | 2460 | intel_sdvo->is_tv = true; |
14571b4c | 2461 | |
df0e9248 | 2462 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
14571b4c | 2463 | |
4ef69c7a | 2464 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) |
32aad86f | 2465 | goto err; |
14571b4c | 2466 | |
4ef69c7a | 2467 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
32aad86f | 2468 | goto err; |
14571b4c | 2469 | |
4ef69c7a | 2470 | return true; |
32aad86f CW |
2471 | |
2472 | err: | |
123d5c01 | 2473 | intel_sdvo_destroy(connector); |
32aad86f | 2474 | return false; |
14571b4c ZW |
2475 | } |
2476 | ||
2477 | static bool | |
ea5b213a | 2478 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
14571b4c | 2479 | { |
4ef69c7a CW |
2480 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2481 | struct drm_connector *connector; | |
2482 | struct intel_connector *intel_connector; | |
2483 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2484 | |
b14c5679 | 2485 | intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); |
615fb93f CW |
2486 | if (!intel_sdvo_connector) |
2487 | return false; | |
14571b4c | 2488 | |
615fb93f | 2489 | intel_connector = &intel_sdvo_connector->base; |
4ef69c7a | 2490 | connector = &intel_connector->base; |
821450c6 | 2491 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
4ef69c7a CW |
2492 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
2493 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; | |
2494 | ||
2495 | if (device == 0) { | |
2496 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; | |
2497 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; | |
2498 | } else if (device == 1) { | |
2499 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; | |
2500 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; | |
2501 | } | |
2502 | ||
df0e9248 CW |
2503 | intel_sdvo_connector_init(intel_sdvo_connector, |
2504 | intel_sdvo); | |
4ef69c7a | 2505 | return true; |
14571b4c ZW |
2506 | } |
2507 | ||
2508 | static bool | |
ea5b213a | 2509 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
14571b4c | 2510 | { |
4ef69c7a CW |
2511 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2512 | struct drm_connector *connector; | |
2513 | struct intel_connector *intel_connector; | |
2514 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2515 | |
b14c5679 | 2516 | intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); |
615fb93f CW |
2517 | if (!intel_sdvo_connector) |
2518 | return false; | |
14571b4c | 2519 | |
615fb93f CW |
2520 | intel_connector = &intel_sdvo_connector->base; |
2521 | connector = &intel_connector->base; | |
4ef69c7a CW |
2522 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
2523 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; | |
2524 | ||
2525 | if (device == 0) { | |
2526 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; | |
2527 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; | |
2528 | } else if (device == 1) { | |
2529 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; | |
2530 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; | |
2531 | } | |
2532 | ||
df0e9248 | 2533 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
4ef69c7a | 2534 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
32aad86f CW |
2535 | goto err; |
2536 | ||
2537 | return true; | |
2538 | ||
2539 | err: | |
123d5c01 | 2540 | intel_sdvo_destroy(connector); |
32aad86f | 2541 | return false; |
14571b4c ZW |
2542 | } |
2543 | ||
2544 | static bool | |
ea5b213a | 2545 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) |
14571b4c | 2546 | { |
ea5b213a | 2547 | intel_sdvo->is_tv = false; |
ea5b213a | 2548 | intel_sdvo->is_lvds = false; |
fb7a46f3 | 2549 | |
14571b4c | 2550 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
fb7a46f3 | 2551 | |
14571b4c | 2552 | if (flags & SDVO_OUTPUT_TMDS0) |
ea5b213a | 2553 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
14571b4c ZW |
2554 | return false; |
2555 | ||
2556 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) | |
ea5b213a | 2557 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
14571b4c ZW |
2558 | return false; |
2559 | ||
2560 | /* TV has no XXX1 function block */ | |
a1f4b7ff | 2561 | if (flags & SDVO_OUTPUT_SVID0) |
ea5b213a | 2562 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) |
14571b4c ZW |
2563 | return false; |
2564 | ||
2565 | if (flags & SDVO_OUTPUT_CVBS0) | |
ea5b213a | 2566 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) |
14571b4c | 2567 | return false; |
fb7a46f3 | 2568 | |
a0b1c7a5 CW |
2569 | if (flags & SDVO_OUTPUT_YPRPB0) |
2570 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) | |
2571 | return false; | |
2572 | ||
14571b4c | 2573 | if (flags & SDVO_OUTPUT_RGB0) |
ea5b213a | 2574 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
14571b4c ZW |
2575 | return false; |
2576 | ||
2577 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) | |
ea5b213a | 2578 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
14571b4c ZW |
2579 | return false; |
2580 | ||
2581 | if (flags & SDVO_OUTPUT_LVDS0) | |
ea5b213a | 2582 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
14571b4c ZW |
2583 | return false; |
2584 | ||
2585 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) | |
ea5b213a | 2586 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
14571b4c | 2587 | return false; |
fb7a46f3 | 2588 | |
14571b4c | 2589 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
fb7a46f3 | 2590 | unsigned char bytes[2]; |
2591 | ||
ea5b213a CW |
2592 | intel_sdvo->controlled_output = 0; |
2593 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); | |
51c8b407 | 2594 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
ea5b213a | 2595 | SDVO_NAME(intel_sdvo), |
51c8b407 | 2596 | bytes[0], bytes[1]); |
14571b4c | 2597 | return false; |
fb7a46f3 | 2598 | } |
27f8227b | 2599 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
fb7a46f3 | 2600 | |
14571b4c | 2601 | return true; |
fb7a46f3 | 2602 | } |
2603 | ||
d0ddfbd3 JN |
2604 | static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) |
2605 | { | |
2606 | struct drm_device *dev = intel_sdvo->base.base.dev; | |
2607 | struct drm_connector *connector, *tmp; | |
2608 | ||
2609 | list_for_each_entry_safe(connector, tmp, | |
2610 | &dev->mode_config.connector_list, head) { | |
2611 | if (intel_attached_encoder(connector) == &intel_sdvo->base) | |
2612 | intel_sdvo_destroy(connector); | |
2613 | } | |
2614 | } | |
2615 | ||
32aad86f CW |
2616 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
2617 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2618 | int type) | |
ce6feabd | 2619 | { |
4ef69c7a | 2620 | struct drm_device *dev = intel_sdvo->base.base.dev; |
ce6feabd ZY |
2621 | struct intel_sdvo_tv_format format; |
2622 | uint32_t format_map, i; | |
ce6feabd | 2623 | |
32aad86f CW |
2624 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) |
2625 | return false; | |
ce6feabd | 2626 | |
1a3665c8 | 2627 | BUILD_BUG_ON(sizeof(format) != 6); |
32aad86f CW |
2628 | if (!intel_sdvo_get_value(intel_sdvo, |
2629 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, | |
2630 | &format, sizeof(format))) | |
2631 | return false; | |
ce6feabd | 2632 | |
32aad86f | 2633 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); |
ce6feabd ZY |
2634 | |
2635 | if (format_map == 0) | |
32aad86f | 2636 | return false; |
ce6feabd | 2637 | |
615fb93f | 2638 | intel_sdvo_connector->format_supported_num = 0; |
ce6feabd | 2639 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
40039750 CW |
2640 | if (format_map & (1 << i)) |
2641 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; | |
ce6feabd ZY |
2642 | |
2643 | ||
c5521706 | 2644 | intel_sdvo_connector->tv_format = |
32aad86f CW |
2645 | drm_property_create(dev, DRM_MODE_PROP_ENUM, |
2646 | "mode", intel_sdvo_connector->format_supported_num); | |
c5521706 | 2647 | if (!intel_sdvo_connector->tv_format) |
fcc8d672 | 2648 | return false; |
ce6feabd | 2649 | |
615fb93f | 2650 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
ce6feabd | 2651 | drm_property_add_enum( |
c5521706 | 2652 | intel_sdvo_connector->tv_format, i, |
40039750 | 2653 | i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); |
ce6feabd | 2654 | |
40039750 | 2655 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; |
662595df | 2656 | drm_object_attach_property(&intel_sdvo_connector->base.base.base, |
c5521706 | 2657 | intel_sdvo_connector->tv_format, 0); |
32aad86f | 2658 | return true; |
ce6feabd ZY |
2659 | |
2660 | } | |
2661 | ||
c5521706 CW |
2662 | #define ENHANCEMENT(name, NAME) do { \ |
2663 | if (enhancements.name) { \ | |
2664 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ | |
2665 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ | |
2666 | return false; \ | |
2667 | intel_sdvo_connector->max_##name = data_value[0]; \ | |
2668 | intel_sdvo_connector->cur_##name = response; \ | |
2669 | intel_sdvo_connector->name = \ | |
d9bc3c02 | 2670 | drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ |
c5521706 | 2671 | if (!intel_sdvo_connector->name) return false; \ |
662595df | 2672 | drm_object_attach_property(&connector->base, \ |
c5521706 CW |
2673 | intel_sdvo_connector->name, \ |
2674 | intel_sdvo_connector->cur_##name); \ | |
2675 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ | |
2676 | data_value[0], data_value[1], response); \ | |
2677 | } \ | |
0206e353 | 2678 | } while (0) |
c5521706 CW |
2679 | |
2680 | static bool | |
2681 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, | |
2682 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2683 | struct intel_sdvo_enhancements_reply enhancements) | |
b9219c5e | 2684 | { |
4ef69c7a | 2685 | struct drm_device *dev = intel_sdvo->base.base.dev; |
32aad86f | 2686 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
b9219c5e ZY |
2687 | uint16_t response, data_value[2]; |
2688 | ||
c5521706 CW |
2689 | /* when horizontal overscan is supported, Add the left/right property */ |
2690 | if (enhancements.overscan_h) { | |
2691 | if (!intel_sdvo_get_value(intel_sdvo, | |
2692 | SDVO_CMD_GET_MAX_OVERSCAN_H, | |
2693 | &data_value, 4)) | |
2694 | return false; | |
32aad86f | 2695 | |
c5521706 CW |
2696 | if (!intel_sdvo_get_value(intel_sdvo, |
2697 | SDVO_CMD_GET_OVERSCAN_H, | |
2698 | &response, 2)) | |
2699 | return false; | |
fcc8d672 | 2700 | |
c5521706 CW |
2701 | intel_sdvo_connector->max_hscan = data_value[0]; |
2702 | intel_sdvo_connector->left_margin = data_value[0] - response; | |
2703 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; | |
2704 | intel_sdvo_connector->left = | |
d9bc3c02 | 2705 | drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); |
c5521706 CW |
2706 | if (!intel_sdvo_connector->left) |
2707 | return false; | |
fcc8d672 | 2708 | |
662595df | 2709 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2710 | intel_sdvo_connector->left, |
2711 | intel_sdvo_connector->left_margin); | |
fcc8d672 | 2712 | |
c5521706 | 2713 | intel_sdvo_connector->right = |
d9bc3c02 | 2714 | drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); |
c5521706 CW |
2715 | if (!intel_sdvo_connector->right) |
2716 | return false; | |
32aad86f | 2717 | |
662595df | 2718 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2719 | intel_sdvo_connector->right, |
2720 | intel_sdvo_connector->right_margin); | |
2721 | DRM_DEBUG_KMS("h_overscan: max %d, " | |
2722 | "default %d, current %d\n", | |
2723 | data_value[0], data_value[1], response); | |
2724 | } | |
32aad86f | 2725 | |
c5521706 CW |
2726 | if (enhancements.overscan_v) { |
2727 | if (!intel_sdvo_get_value(intel_sdvo, | |
2728 | SDVO_CMD_GET_MAX_OVERSCAN_V, | |
2729 | &data_value, 4)) | |
2730 | return false; | |
fcc8d672 | 2731 | |
c5521706 CW |
2732 | if (!intel_sdvo_get_value(intel_sdvo, |
2733 | SDVO_CMD_GET_OVERSCAN_V, | |
2734 | &response, 2)) | |
2735 | return false; | |
32aad86f | 2736 | |
c5521706 CW |
2737 | intel_sdvo_connector->max_vscan = data_value[0]; |
2738 | intel_sdvo_connector->top_margin = data_value[0] - response; | |
2739 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; | |
2740 | intel_sdvo_connector->top = | |
d9bc3c02 SH |
2741 | drm_property_create_range(dev, 0, |
2742 | "top_margin", 0, data_value[0]); | |
c5521706 CW |
2743 | if (!intel_sdvo_connector->top) |
2744 | return false; | |
32aad86f | 2745 | |
662595df | 2746 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2747 | intel_sdvo_connector->top, |
2748 | intel_sdvo_connector->top_margin); | |
fcc8d672 | 2749 | |
c5521706 | 2750 | intel_sdvo_connector->bottom = |
d9bc3c02 SH |
2751 | drm_property_create_range(dev, 0, |
2752 | "bottom_margin", 0, data_value[0]); | |
c5521706 CW |
2753 | if (!intel_sdvo_connector->bottom) |
2754 | return false; | |
32aad86f | 2755 | |
662595df | 2756 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2757 | intel_sdvo_connector->bottom, |
2758 | intel_sdvo_connector->bottom_margin); | |
2759 | DRM_DEBUG_KMS("v_overscan: max %d, " | |
2760 | "default %d, current %d\n", | |
2761 | data_value[0], data_value[1], response); | |
2762 | } | |
32aad86f | 2763 | |
c5521706 CW |
2764 | ENHANCEMENT(hpos, HPOS); |
2765 | ENHANCEMENT(vpos, VPOS); | |
2766 | ENHANCEMENT(saturation, SATURATION); | |
2767 | ENHANCEMENT(contrast, CONTRAST); | |
2768 | ENHANCEMENT(hue, HUE); | |
2769 | ENHANCEMENT(sharpness, SHARPNESS); | |
2770 | ENHANCEMENT(brightness, BRIGHTNESS); | |
2771 | ENHANCEMENT(flicker_filter, FLICKER_FILTER); | |
2772 | ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); | |
2773 | ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); | |
2774 | ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); | |
2775 | ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); | |
fcc8d672 | 2776 | |
e044218a CW |
2777 | if (enhancements.dot_crawl) { |
2778 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) | |
2779 | return false; | |
2780 | ||
2781 | intel_sdvo_connector->max_dot_crawl = 1; | |
2782 | intel_sdvo_connector->cur_dot_crawl = response & 0x1; | |
2783 | intel_sdvo_connector->dot_crawl = | |
d9bc3c02 | 2784 | drm_property_create_range(dev, 0, "dot_crawl", 0, 1); |
e044218a CW |
2785 | if (!intel_sdvo_connector->dot_crawl) |
2786 | return false; | |
2787 | ||
662595df | 2788 | drm_object_attach_property(&connector->base, |
e044218a CW |
2789 | intel_sdvo_connector->dot_crawl, |
2790 | intel_sdvo_connector->cur_dot_crawl); | |
2791 | DRM_DEBUG_KMS("dot crawl: current %d\n", response); | |
2792 | } | |
2793 | ||
c5521706 CW |
2794 | return true; |
2795 | } | |
32aad86f | 2796 | |
c5521706 CW |
2797 | static bool |
2798 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, | |
2799 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2800 | struct intel_sdvo_enhancements_reply enhancements) | |
2801 | { | |
4ef69c7a | 2802 | struct drm_device *dev = intel_sdvo->base.base.dev; |
c5521706 CW |
2803 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
2804 | uint16_t response, data_value[2]; | |
32aad86f | 2805 | |
c5521706 | 2806 | ENHANCEMENT(brightness, BRIGHTNESS); |
fcc8d672 | 2807 | |
c5521706 CW |
2808 | return true; |
2809 | } | |
2810 | #undef ENHANCEMENT | |
32aad86f | 2811 | |
c5521706 CW |
2812 | static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
2813 | struct intel_sdvo_connector *intel_sdvo_connector) | |
2814 | { | |
2815 | union { | |
2816 | struct intel_sdvo_enhancements_reply reply; | |
2817 | uint16_t response; | |
2818 | } enhancements; | |
32aad86f | 2819 | |
1a3665c8 CW |
2820 | BUILD_BUG_ON(sizeof(enhancements) != 2); |
2821 | ||
cf9a2f3a CW |
2822 | enhancements.response = 0; |
2823 | intel_sdvo_get_value(intel_sdvo, | |
2824 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, | |
2825 | &enhancements, sizeof(enhancements)); | |
c5521706 CW |
2826 | if (enhancements.response == 0) { |
2827 | DRM_DEBUG_KMS("No enhancement is supported\n"); | |
2828 | return true; | |
b9219c5e | 2829 | } |
32aad86f | 2830 | |
c5521706 CW |
2831 | if (IS_TV(intel_sdvo_connector)) |
2832 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); | |
0206e353 | 2833 | else if (IS_LVDS(intel_sdvo_connector)) |
c5521706 CW |
2834 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
2835 | else | |
2836 | return true; | |
e957d772 CW |
2837 | } |
2838 | ||
2839 | static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, | |
2840 | struct i2c_msg *msgs, | |
2841 | int num) | |
2842 | { | |
2843 | struct intel_sdvo *sdvo = adapter->algo_data; | |
fcc8d672 | 2844 | |
e957d772 CW |
2845 | if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) |
2846 | return -EIO; | |
2847 | ||
2848 | return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); | |
2849 | } | |
2850 | ||
2851 | static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) | |
2852 | { | |
2853 | struct intel_sdvo *sdvo = adapter->algo_data; | |
2854 | return sdvo->i2c->algo->functionality(sdvo->i2c); | |
2855 | } | |
2856 | ||
2857 | static const struct i2c_algorithm intel_sdvo_ddc_proxy = { | |
2858 | .master_xfer = intel_sdvo_ddc_proxy_xfer, | |
2859 | .functionality = intel_sdvo_ddc_proxy_func | |
2860 | }; | |
2861 | ||
2862 | static bool | |
2863 | intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, | |
2864 | struct drm_device *dev) | |
2865 | { | |
2866 | sdvo->ddc.owner = THIS_MODULE; | |
2867 | sdvo->ddc.class = I2C_CLASS_DDC; | |
2868 | snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); | |
2869 | sdvo->ddc.dev.parent = &dev->pdev->dev; | |
2870 | sdvo->ddc.algo_data = sdvo; | |
2871 | sdvo->ddc.algo = &intel_sdvo_ddc_proxy; | |
2872 | ||
2873 | return i2c_add_adapter(&sdvo->ddc) == 0; | |
b9219c5e ZY |
2874 | } |
2875 | ||
eef4eacb | 2876 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) |
79e53945 | 2877 | { |
b01f2c3a | 2878 | struct drm_i915_private *dev_priv = dev->dev_private; |
21d40d37 | 2879 | struct intel_encoder *intel_encoder; |
ea5b213a | 2880 | struct intel_sdvo *intel_sdvo; |
79e53945 | 2881 | int i; |
b14c5679 | 2882 | intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); |
ea5b213a | 2883 | if (!intel_sdvo) |
7d57382e | 2884 | return false; |
79e53945 | 2885 | |
56184e3d | 2886 | intel_sdvo->sdvo_reg = sdvo_reg; |
eef4eacb DV |
2887 | intel_sdvo->is_sdvob = is_sdvob; |
2888 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; | |
56184e3d | 2889 | intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg); |
fbfcc4f3 JN |
2890 | if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) |
2891 | goto err_i2c_bus; | |
e957d772 | 2892 | |
56184e3d | 2893 | /* encoder type will be decided later */ |
ea5b213a | 2894 | intel_encoder = &intel_sdvo->base; |
21d40d37 | 2895 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
373a3cf7 | 2896 | drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); |
79e53945 | 2897 | |
79e53945 JB |
2898 | /* Read the regs to test if we can talk to the device */ |
2899 | for (i = 0; i < 0x40; i++) { | |
f899fc64 CW |
2900 | u8 byte; |
2901 | ||
2902 | if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { | |
eef4eacb DV |
2903 | DRM_DEBUG_KMS("No SDVO device found on %s\n", |
2904 | SDVO_NAME(intel_sdvo)); | |
f899fc64 | 2905 | goto err; |
79e53945 JB |
2906 | } |
2907 | } | |
2908 | ||
6cc5f341 | 2909 | intel_encoder->compute_config = intel_sdvo_compute_config; |
ce22c320 | 2910 | intel_encoder->disable = intel_disable_sdvo; |
6cc5f341 | 2911 | intel_encoder->mode_set = intel_sdvo_mode_set; |
ce22c320 | 2912 | intel_encoder->enable = intel_enable_sdvo; |
4ac41f47 | 2913 | intel_encoder->get_hw_state = intel_sdvo_get_hw_state; |
045ac3b5 | 2914 | intel_encoder->get_config = intel_sdvo_get_config; |
ce22c320 | 2915 | |
af901ca1 | 2916 | /* In default case sdvo lvds is false */ |
32aad86f | 2917 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) |
f899fc64 | 2918 | goto err; |
79e53945 | 2919 | |
ea5b213a CW |
2920 | if (intel_sdvo_output_setup(intel_sdvo, |
2921 | intel_sdvo->caps.output_flags) != true) { | |
eef4eacb DV |
2922 | DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", |
2923 | SDVO_NAME(intel_sdvo)); | |
d0ddfbd3 JN |
2924 | /* Output_setup can leave behind connectors! */ |
2925 | goto err_output; | |
79e53945 JB |
2926 | } |
2927 | ||
7ba220ce CW |
2928 | /* Only enable the hotplug irq if we need it, to work around noisy |
2929 | * hotplug lines. | |
2930 | */ | |
2931 | if (intel_sdvo->hotplug_active) { | |
2932 | intel_encoder->hpd_pin = | |
2933 | intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C; | |
2934 | } | |
2935 | ||
e506d6fd DV |
2936 | /* |
2937 | * Cloning SDVO with anything is often impossible, since the SDVO | |
2938 | * encoder can request a special input timing mode. And even if that's | |
2939 | * not the case we have evidence that cloning a plain unscaled mode with | |
2940 | * VGA doesn't really work. Furthermore the cloning flags are way too | |
2941 | * simplistic anyway to express such constraints, so just give up on | |
2942 | * cloning for SDVO encoders. | |
2943 | */ | |
2944 | intel_sdvo->base.cloneable = false; | |
2945 | ||
ea5b213a | 2946 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); |
e2f0ba97 | 2947 | |
79e53945 | 2948 | /* Set the input timing to the screen. Assume always input 0. */ |
32aad86f | 2949 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
d0ddfbd3 | 2950 | goto err_output; |
79e53945 | 2951 | |
32aad86f CW |
2952 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
2953 | &intel_sdvo->pixel_clock_min, | |
2954 | &intel_sdvo->pixel_clock_max)) | |
d0ddfbd3 | 2955 | goto err_output; |
79e53945 | 2956 | |
8a4c47f3 | 2957 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
342dc382 | 2958 | "clock range %dMHz - %dMHz, " |
2959 | "input 1: %c, input 2: %c, " | |
2960 | "output 1: %c, output 2: %c\n", | |
ea5b213a CW |
2961 | SDVO_NAME(intel_sdvo), |
2962 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, | |
2963 | intel_sdvo->caps.device_rev_id, | |
2964 | intel_sdvo->pixel_clock_min / 1000, | |
2965 | intel_sdvo->pixel_clock_max / 1000, | |
2966 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', | |
2967 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', | |
342dc382 | 2968 | /* check currently supported outputs */ |
ea5b213a | 2969 | intel_sdvo->caps.output_flags & |
79e53945 | 2970 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
ea5b213a | 2971 | intel_sdvo->caps.output_flags & |
79e53945 | 2972 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
7d57382e | 2973 | return true; |
79e53945 | 2974 | |
d0ddfbd3 JN |
2975 | err_output: |
2976 | intel_sdvo_output_cleanup(intel_sdvo); | |
2977 | ||
f899fc64 | 2978 | err: |
373a3cf7 | 2979 | drm_encoder_cleanup(&intel_encoder->base); |
e957d772 | 2980 | i2c_del_adapter(&intel_sdvo->ddc); |
fbfcc4f3 JN |
2981 | err_i2c_bus: |
2982 | intel_sdvo_unselect_i2c_bus(intel_sdvo); | |
ea5b213a | 2983 | kfree(intel_sdvo); |
79e53945 | 2984 | |
7d57382e | 2985 | return false; |
79e53945 | 2986 | } |