Commit | Line | Data |
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907b28c5 CW |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "i915_drv.h" | |
25 | #include "intel_drv.h" | |
26 | ||
27 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 | |
28 | ||
6af5d92f CW |
29 | #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__)) |
30 | #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__)) | |
31 | ||
32 | #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) | |
33 | #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__)) | |
34 | ||
35 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
36 | #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__)) | |
37 | ||
38 | #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__)) | |
39 | #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__)) | |
40 | ||
41 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) | |
42 | ||
b2ec142c PZ |
43 | static void |
44 | assert_device_not_suspended(struct drm_i915_private *dev_priv) | |
45 | { | |
46 | WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended, | |
47 | "Device suspended\n"); | |
48 | } | |
6af5d92f | 49 | |
907b28c5 CW |
50 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
51 | { | |
52 | u32 gt_thread_status_mask; | |
53 | ||
54 | if (IS_HASWELL(dev_priv->dev)) | |
55 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; | |
56 | else | |
57 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; | |
58 | ||
59 | /* w/a for a sporadic read returning 0 by waiting for the GT | |
60 | * thread to wake up. | |
61 | */ | |
6af5d92f | 62 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) |
907b28c5 CW |
63 | DRM_ERROR("GT thread status wait timed out\n"); |
64 | } | |
65 | ||
66 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) | |
67 | { | |
6af5d92f CW |
68 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
69 | /* something from same cacheline, but !FORCEWAKE */ | |
70 | __raw_posting_read(dev_priv, ECOBUS); | |
907b28c5 CW |
71 | } |
72 | ||
c8d9a590 D |
73 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, |
74 | int fw_engine) | |
907b28c5 | 75 | { |
6af5d92f | 76 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, |
907b28c5 CW |
77 | FORCEWAKE_ACK_TIMEOUT_MS)) |
78 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); | |
79 | ||
6af5d92f CW |
80 | __raw_i915_write32(dev_priv, FORCEWAKE, 1); |
81 | /* something from same cacheline, but !FORCEWAKE */ | |
82 | __raw_posting_read(dev_priv, ECOBUS); | |
907b28c5 | 83 | |
6af5d92f | 84 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1), |
907b28c5 CW |
85 | FORCEWAKE_ACK_TIMEOUT_MS)) |
86 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); | |
87 | ||
88 | /* WaRsForcewakeWaitTC0:snb */ | |
89 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
90 | } | |
91 | ||
92 | static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) | |
93 | { | |
6af5d92f | 94 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); |
907b28c5 | 95 | /* something from same cacheline, but !FORCEWAKE_MT */ |
6af5d92f | 96 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 CW |
97 | } |
98 | ||
c8d9a590 D |
99 | static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv, |
100 | int fw_engine) | |
907b28c5 CW |
101 | { |
102 | u32 forcewake_ack; | |
103 | ||
ab2aa47e | 104 | if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev)) |
907b28c5 CW |
105 | forcewake_ack = FORCEWAKE_ACK_HSW; |
106 | else | |
107 | forcewake_ack = FORCEWAKE_MT_ACK; | |
108 | ||
6af5d92f | 109 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0, |
907b28c5 CW |
110 | FORCEWAKE_ACK_TIMEOUT_MS)) |
111 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); | |
112 | ||
6af5d92f CW |
113 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
114 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
907b28c5 | 115 | /* something from same cacheline, but !FORCEWAKE_MT */ |
6af5d92f | 116 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 | 117 | |
6af5d92f | 118 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), |
907b28c5 CW |
119 | FORCEWAKE_ACK_TIMEOUT_MS)) |
120 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); | |
121 | ||
122 | /* WaRsForcewakeWaitTC0:ivb,hsw */ | |
0f161f70 BW |
123 | if (INTEL_INFO(dev_priv->dev)->gen < 8) |
124 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
907b28c5 CW |
125 | } |
126 | ||
127 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) | |
128 | { | |
129 | u32 gtfifodbg; | |
6af5d92f CW |
130 | |
131 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); | |
90f256b5 VS |
132 | if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) |
133 | __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); | |
907b28c5 CW |
134 | } |
135 | ||
c8d9a590 D |
136 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, |
137 | int fw_engine) | |
907b28c5 | 138 | { |
6af5d92f | 139 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
907b28c5 | 140 | /* something from same cacheline, but !FORCEWAKE */ |
6af5d92f | 141 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 CW |
142 | gen6_gt_check_fifodbg(dev_priv); |
143 | } | |
144 | ||
c8d9a590 D |
145 | static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv, |
146 | int fw_engine) | |
907b28c5 | 147 | { |
6af5d92f CW |
148 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
149 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
907b28c5 | 150 | /* something from same cacheline, but !FORCEWAKE_MT */ |
6af5d92f | 151 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 CW |
152 | gen6_gt_check_fifodbg(dev_priv); |
153 | } | |
154 | ||
155 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) | |
156 | { | |
157 | int ret = 0; | |
158 | ||
5135d64b D |
159 | /* On VLV, FIFO will be shared by both SW and HW. |
160 | * So, we need to read the FREE_ENTRIES everytime */ | |
161 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
162 | dev_priv->uncore.fifo_count = | |
163 | __raw_i915_read32(dev_priv, GTFIFOCTL) & | |
164 | GT_FIFO_FREE_ENTRIES_MASK; | |
165 | ||
907b28c5 CW |
166 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
167 | int loop = 500; | |
46520e2b | 168 | u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
907b28c5 CW |
169 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
170 | udelay(10); | |
46520e2b | 171 | fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
907b28c5 CW |
172 | } |
173 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) | |
174 | ++ret; | |
175 | dev_priv->uncore.fifo_count = fifo; | |
176 | } | |
177 | dev_priv->uncore.fifo_count--; | |
178 | ||
179 | return ret; | |
180 | } | |
181 | ||
182 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) | |
183 | { | |
6af5d92f CW |
184 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
185 | _MASKED_BIT_DISABLE(0xffff)); | |
907b28c5 | 186 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
6af5d92f | 187 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
907b28c5 CW |
188 | } |
189 | ||
940aece4 D |
190 | static void __vlv_force_wake_get(struct drm_i915_private *dev_priv, |
191 | int fw_engine) | |
907b28c5 | 192 | { |
940aece4 D |
193 | /* Check for Render Engine */ |
194 | if (FORCEWAKE_RENDER & fw_engine) { | |
195 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
196 | FORCEWAKE_ACK_VLV) & | |
197 | FORCEWAKE_KERNEL) == 0, | |
198 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
199 | DRM_ERROR("Timed out: Render forcewake old ack to clear.\n"); | |
200 | ||
201 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, | |
202 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
203 | ||
204 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
205 | FORCEWAKE_ACK_VLV) & | |
206 | FORCEWAKE_KERNEL), | |
207 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
208 | DRM_ERROR("Timed out: waiting for Render to ack.\n"); | |
209 | } | |
907b28c5 | 210 | |
940aece4 D |
211 | /* Check for Media Engine */ |
212 | if (FORCEWAKE_MEDIA & fw_engine) { | |
213 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
214 | FORCEWAKE_ACK_MEDIA_VLV) & | |
215 | FORCEWAKE_KERNEL) == 0, | |
216 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
217 | DRM_ERROR("Timed out: Media forcewake old ack to clear.\n"); | |
218 | ||
219 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, | |
220 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
221 | ||
222 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
223 | FORCEWAKE_ACK_MEDIA_VLV) & | |
224 | FORCEWAKE_KERNEL), | |
225 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
226 | DRM_ERROR("Timed out: waiting for media to ack.\n"); | |
227 | } | |
907b28c5 CW |
228 | |
229 | /* WaRsForcewakeWaitTC0:vlv */ | |
230 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
940aece4 | 231 | |
907b28c5 CW |
232 | } |
233 | ||
940aece4 D |
234 | static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, |
235 | int fw_engine) | |
907b28c5 | 236 | { |
940aece4 D |
237 | |
238 | /* Check for Render Engine */ | |
239 | if (FORCEWAKE_RENDER & fw_engine) | |
240 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, | |
241 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
242 | ||
243 | ||
244 | /* Check for Media Engine */ | |
245 | if (FORCEWAKE_MEDIA & fw_engine) | |
246 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, | |
247 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
248 | ||
907b28c5 CW |
249 | /* The below doubles as a POSTING_READ */ |
250 | gen6_gt_check_fifodbg(dev_priv); | |
940aece4 D |
251 | |
252 | } | |
253 | ||
254 | void vlv_force_wake_get(struct drm_i915_private *dev_priv, | |
255 | int fw_engine) | |
256 | { | |
257 | unsigned long irqflags; | |
258 | ||
259 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
6fe72865 VS |
260 | |
261 | if (fw_engine & FORCEWAKE_RENDER && | |
262 | dev_priv->uncore.fw_rendercount++ != 0) | |
263 | fw_engine &= ~FORCEWAKE_RENDER; | |
264 | if (fw_engine & FORCEWAKE_MEDIA && | |
265 | dev_priv->uncore.fw_mediacount++ != 0) | |
266 | fw_engine &= ~FORCEWAKE_MEDIA; | |
267 | ||
268 | if (fw_engine) | |
269 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine); | |
940aece4 D |
270 | |
271 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
272 | } | |
273 | ||
274 | void vlv_force_wake_put(struct drm_i915_private *dev_priv, | |
275 | int fw_engine) | |
276 | { | |
277 | unsigned long irqflags; | |
278 | ||
279 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
280 | ||
6fe72865 VS |
281 | if (fw_engine & FORCEWAKE_RENDER && |
282 | --dev_priv->uncore.fw_rendercount != 0) | |
283 | fw_engine &= ~FORCEWAKE_RENDER; | |
284 | if (fw_engine & FORCEWAKE_MEDIA && | |
285 | --dev_priv->uncore.fw_mediacount != 0) | |
286 | fw_engine &= ~FORCEWAKE_MEDIA; | |
940aece4 | 287 | |
6fe72865 VS |
288 | if (fw_engine) |
289 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine); | |
940aece4 D |
290 | |
291 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
907b28c5 CW |
292 | } |
293 | ||
8232644c | 294 | static void gen6_force_wake_timer(unsigned long arg) |
aec347ab | 295 | { |
8232644c | 296 | struct drm_i915_private *dev_priv = (void *)arg; |
aec347ab CW |
297 | unsigned long irqflags; |
298 | ||
b2ec142c PZ |
299 | assert_device_not_suspended(dev_priv); |
300 | ||
aec347ab CW |
301 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
302 | if (--dev_priv->uncore.forcewake_count == 0) | |
c8d9a590 | 303 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
aec347ab | 304 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
6d88064e PZ |
305 | |
306 | intel_runtime_pm_put(dev_priv); | |
aec347ab CW |
307 | } |
308 | ||
ef46e0d2 DV |
309 | static void intel_uncore_forcewake_reset(struct drm_device *dev) |
310 | { | |
311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
312 | ||
0a089e33 | 313 | if (IS_VALLEYVIEW(dev)) |
ef46e0d2 | 314 | vlv_force_wake_reset(dev_priv); |
0a089e33 | 315 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
ef46e0d2 | 316 | __gen6_gt_force_wake_reset(dev_priv); |
0a089e33 MK |
317 | |
318 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_GEN8(dev)) | |
319 | __gen6_gt_force_wake_mt_reset(dev_priv); | |
ef46e0d2 DV |
320 | } |
321 | ||
907b28c5 CW |
322 | void intel_uncore_early_sanitize(struct drm_device *dev) |
323 | { | |
324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
325 | ||
326 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) | |
6af5d92f | 327 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
18ce3994 BW |
328 | |
329 | if (IS_HASWELL(dev) && | |
330 | (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) { | |
331 | /* The docs do not explain exactly how the calculation can be | |
332 | * made. It is somewhat guessable, but for now, it's always | |
333 | * 128MB. | |
334 | * NB: We can't write IDICR yet because we do not have gt funcs | |
335 | * set up */ | |
336 | dev_priv->ellc_size = 128; | |
337 | DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); | |
338 | } | |
907b28c5 | 339 | |
97058870 VS |
340 | /* clear out old GT FIFO errors */ |
341 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
342 | __raw_i915_write32(dev_priv, GTFIFODBG, | |
343 | __raw_i915_read32(dev_priv, GTFIFODBG)); | |
344 | ||
ef46e0d2 | 345 | intel_uncore_forcewake_reset(dev); |
521198a2 MK |
346 | } |
347 | ||
348 | void intel_uncore_sanitize(struct drm_device *dev) | |
349 | { | |
02f4c9e0 CML |
350 | struct drm_i915_private *dev_priv = dev->dev_private; |
351 | u32 reg_val; | |
352 | ||
907b28c5 CW |
353 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
354 | intel_disable_gt_powersave(dev); | |
02f4c9e0 CML |
355 | |
356 | /* Turn off power gate, require especially for the BIOS less system */ | |
357 | if (IS_VALLEYVIEW(dev)) { | |
358 | ||
359 | mutex_lock(&dev_priv->rps.hw_lock); | |
360 | reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS); | |
361 | ||
362 | if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT)) | |
363 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0); | |
364 | ||
365 | mutex_unlock(&dev_priv->rps.hw_lock); | |
366 | ||
367 | } | |
907b28c5 CW |
368 | } |
369 | ||
370 | /* | |
371 | * Generally this is called implicitly by the register read function. However, | |
372 | * if some sequence requires the GT to not power down then this function should | |
373 | * be called at the beginning of the sequence followed by a call to | |
374 | * gen6_gt_force_wake_put() at the end of the sequence. | |
375 | */ | |
c8d9a590 | 376 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
907b28c5 CW |
377 | { |
378 | unsigned long irqflags; | |
379 | ||
ab484f8f BW |
380 | if (!dev_priv->uncore.funcs.force_wake_get) |
381 | return; | |
382 | ||
c8c8fb33 PZ |
383 | intel_runtime_pm_get(dev_priv); |
384 | ||
940aece4 D |
385 | /* Redirect to VLV specific routine */ |
386 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
387 | return vlv_force_wake_get(dev_priv, fw_engine); | |
388 | ||
907b28c5 CW |
389 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
390 | if (dev_priv->uncore.forcewake_count++ == 0) | |
c8d9a590 | 391 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); |
907b28c5 CW |
392 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
393 | } | |
394 | ||
395 | /* | |
396 | * see gen6_gt_force_wake_get() | |
397 | */ | |
c8d9a590 | 398 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
907b28c5 CW |
399 | { |
400 | unsigned long irqflags; | |
6d88064e | 401 | bool delayed = false; |
907b28c5 | 402 | |
ab484f8f BW |
403 | if (!dev_priv->uncore.funcs.force_wake_put) |
404 | return; | |
405 | ||
940aece4 | 406 | /* Redirect to VLV specific routine */ |
6d88064e PZ |
407 | if (IS_VALLEYVIEW(dev_priv->dev)) { |
408 | vlv_force_wake_put(dev_priv, fw_engine); | |
409 | goto out; | |
410 | } | |
940aece4 D |
411 | |
412 | ||
907b28c5 | 413 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
aec347ab CW |
414 | if (--dev_priv->uncore.forcewake_count == 0) { |
415 | dev_priv->uncore.forcewake_count++; | |
6d88064e | 416 | delayed = true; |
8232644c CW |
417 | mod_timer_pinned(&dev_priv->uncore.force_wake_timer, |
418 | jiffies + 1); | |
aec347ab | 419 | } |
907b28c5 | 420 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
c8c8fb33 | 421 | |
6d88064e PZ |
422 | out: |
423 | if (!delayed) | |
424 | intel_runtime_pm_put(dev_priv); | |
907b28c5 CW |
425 | } |
426 | ||
e998c40f PZ |
427 | void assert_force_wake_inactive(struct drm_i915_private *dev_priv) |
428 | { | |
429 | if (!dev_priv->uncore.funcs.force_wake_get) | |
430 | return; | |
431 | ||
432 | WARN_ON(dev_priv->uncore.forcewake_count > 0); | |
433 | } | |
434 | ||
907b28c5 CW |
435 | /* We give fast paths for the really cool registers */ |
436 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | |
ab484f8f | 437 | ((reg) < 0x40000 && (reg) != FORCEWAKE) |
907b28c5 CW |
438 | |
439 | static void | |
440 | ilk_dummy_write(struct drm_i915_private *dev_priv) | |
441 | { | |
442 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up | |
443 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
444 | * hence harmless to write 0 into. */ | |
6af5d92f | 445 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
907b28c5 CW |
446 | } |
447 | ||
448 | static void | |
449 | hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) | |
450 | { | |
ab484f8f | 451 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
907b28c5 CW |
452 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", |
453 | reg); | |
6af5d92f | 454 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
455 | } |
456 | } | |
457 | ||
458 | static void | |
459 | hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) | |
460 | { | |
ab484f8f | 461 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
907b28c5 | 462 | DRM_ERROR("Unclaimed write to %x\n", reg); |
6af5d92f | 463 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
464 | } |
465 | } | |
466 | ||
5d738795 BW |
467 | #define REG_READ_HEADER(x) \ |
468 | unsigned long irqflags; \ | |
469 | u##x val = 0; \ | |
6f0ea9e2 | 470 | assert_device_not_suspended(dev_priv); \ |
5d738795 BW |
471 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
472 | ||
473 | #define REG_READ_FOOTER \ | |
474 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
475 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ | |
476 | return val | |
477 | ||
3967018e | 478 | #define __gen4_read(x) \ |
0b274481 | 479 | static u##x \ |
3967018e BW |
480 | gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
481 | REG_READ_HEADER(x); \ | |
482 | val = __raw_i915_read##x(dev_priv, reg); \ | |
483 | REG_READ_FOOTER; \ | |
484 | } | |
485 | ||
486 | #define __gen5_read(x) \ | |
487 | static u##x \ | |
488 | gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
489 | REG_READ_HEADER(x); \ | |
490 | ilk_dummy_write(dev_priv); \ | |
491 | val = __raw_i915_read##x(dev_priv, reg); \ | |
492 | REG_READ_FOOTER; \ | |
493 | } | |
494 | ||
495 | #define __gen6_read(x) \ | |
496 | static u##x \ | |
497 | gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
5d738795 | 498 | REG_READ_HEADER(x); \ |
8232644c CW |
499 | if (dev_priv->uncore.forcewake_count == 0 && \ |
500 | NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
501 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ | |
502 | FORCEWAKE_ALL); \ | |
503 | dev_priv->uncore.forcewake_count++; \ | |
504 | mod_timer_pinned(&dev_priv->uncore.force_wake_timer, \ | |
505 | jiffies + 1); \ | |
907b28c5 | 506 | } \ |
8232644c | 507 | val = __raw_i915_read##x(dev_priv, reg); \ |
5d738795 | 508 | REG_READ_FOOTER; \ |
907b28c5 CW |
509 | } |
510 | ||
940aece4 D |
511 | #define __vlv_read(x) \ |
512 | static u##x \ | |
513 | vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
514 | unsigned fwengine = 0; \ | |
940aece4 | 515 | REG_READ_HEADER(x); \ |
6fe72865 VS |
516 | if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \ |
517 | if (dev_priv->uncore.fw_rendercount == 0) \ | |
518 | fwengine = FORCEWAKE_RENDER; \ | |
519 | } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \ | |
520 | if (dev_priv->uncore.fw_mediacount == 0) \ | |
521 | fwengine = FORCEWAKE_MEDIA; \ | |
940aece4 | 522 | } \ |
6fe72865 VS |
523 | if (fwengine) \ |
524 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ | |
525 | val = __raw_i915_read##x(dev_priv, reg); \ | |
526 | if (fwengine) \ | |
527 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ | |
940aece4 D |
528 | REG_READ_FOOTER; \ |
529 | } | |
530 | ||
531 | ||
532 | __vlv_read(8) | |
533 | __vlv_read(16) | |
534 | __vlv_read(32) | |
535 | __vlv_read(64) | |
3967018e BW |
536 | __gen6_read(8) |
537 | __gen6_read(16) | |
538 | __gen6_read(32) | |
539 | __gen6_read(64) | |
540 | __gen5_read(8) | |
541 | __gen5_read(16) | |
542 | __gen5_read(32) | |
543 | __gen5_read(64) | |
544 | __gen4_read(8) | |
545 | __gen4_read(16) | |
546 | __gen4_read(32) | |
547 | __gen4_read(64) | |
548 | ||
940aece4 | 549 | #undef __vlv_read |
3967018e BW |
550 | #undef __gen6_read |
551 | #undef __gen5_read | |
552 | #undef __gen4_read | |
5d738795 BW |
553 | #undef REG_READ_FOOTER |
554 | #undef REG_READ_HEADER | |
555 | ||
556 | #define REG_WRITE_HEADER \ | |
557 | unsigned long irqflags; \ | |
558 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
6f0ea9e2 | 559 | assert_device_not_suspended(dev_priv); \ |
5d738795 | 560 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
907b28c5 | 561 | |
0d965301 VS |
562 | #define REG_WRITE_FOOTER \ |
563 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) | |
564 | ||
4032ef43 | 565 | #define __gen4_write(x) \ |
0b274481 | 566 | static void \ |
4032ef43 BW |
567 | gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
568 | REG_WRITE_HEADER; \ | |
569 | __raw_i915_write##x(dev_priv, reg, val); \ | |
0d965301 | 570 | REG_WRITE_FOOTER; \ |
4032ef43 BW |
571 | } |
572 | ||
573 | #define __gen5_write(x) \ | |
574 | static void \ | |
575 | gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
576 | REG_WRITE_HEADER; \ | |
577 | ilk_dummy_write(dev_priv); \ | |
578 | __raw_i915_write##x(dev_priv, reg, val); \ | |
0d965301 | 579 | REG_WRITE_FOOTER; \ |
4032ef43 BW |
580 | } |
581 | ||
582 | #define __gen6_write(x) \ | |
583 | static void \ | |
584 | gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
585 | u32 __fifo_ret = 0; \ | |
586 | REG_WRITE_HEADER; \ | |
587 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
588 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ | |
589 | } \ | |
590 | __raw_i915_write##x(dev_priv, reg, val); \ | |
591 | if (unlikely(__fifo_ret)) { \ | |
592 | gen6_gt_check_fifodbg(dev_priv); \ | |
593 | } \ | |
0d965301 | 594 | REG_WRITE_FOOTER; \ |
4032ef43 BW |
595 | } |
596 | ||
597 | #define __hsw_write(x) \ | |
598 | static void \ | |
599 | hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
907b28c5 | 600 | u32 __fifo_ret = 0; \ |
5d738795 | 601 | REG_WRITE_HEADER; \ |
907b28c5 CW |
602 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
603 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ | |
604 | } \ | |
907b28c5 | 605 | hsw_unclaimed_reg_clear(dev_priv, reg); \ |
6af5d92f | 606 | __raw_i915_write##x(dev_priv, reg, val); \ |
907b28c5 CW |
607 | if (unlikely(__fifo_ret)) { \ |
608 | gen6_gt_check_fifodbg(dev_priv); \ | |
609 | } \ | |
610 | hsw_unclaimed_reg_check(dev_priv, reg); \ | |
0d965301 | 611 | REG_WRITE_FOOTER; \ |
907b28c5 | 612 | } |
3967018e | 613 | |
ab2aa47e BW |
614 | static const u32 gen8_shadowed_regs[] = { |
615 | FORCEWAKE_MT, | |
616 | GEN6_RPNSWREQ, | |
617 | GEN6_RC_VIDEO_FREQ, | |
618 | RING_TAIL(RENDER_RING_BASE), | |
619 | RING_TAIL(GEN6_BSD_RING_BASE), | |
620 | RING_TAIL(VEBOX_RING_BASE), | |
621 | RING_TAIL(BLT_RING_BASE), | |
622 | /* TODO: Other registers are not yet used */ | |
623 | }; | |
624 | ||
625 | static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg) | |
626 | { | |
627 | int i; | |
628 | for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) | |
629 | if (reg == gen8_shadowed_regs[i]) | |
630 | return true; | |
631 | ||
632 | return false; | |
633 | } | |
634 | ||
635 | #define __gen8_write(x) \ | |
636 | static void \ | |
637 | gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
ab2aa47e | 638 | REG_WRITE_HEADER; \ |
e9dbd2b2 MK |
639 | if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \ |
640 | if (dev_priv->uncore.forcewake_count == 0) \ | |
641 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ | |
642 | FORCEWAKE_ALL); \ | |
643 | __raw_i915_write##x(dev_priv, reg, val); \ | |
644 | if (dev_priv->uncore.forcewake_count == 0) \ | |
645 | dev_priv->uncore.funcs.force_wake_put(dev_priv, \ | |
646 | FORCEWAKE_ALL); \ | |
647 | } else { \ | |
648 | __raw_i915_write##x(dev_priv, reg, val); \ | |
ab2aa47e | 649 | } \ |
0d965301 | 650 | REG_WRITE_FOOTER; \ |
ab2aa47e BW |
651 | } |
652 | ||
653 | __gen8_write(8) | |
654 | __gen8_write(16) | |
655 | __gen8_write(32) | |
656 | __gen8_write(64) | |
4032ef43 BW |
657 | __hsw_write(8) |
658 | __hsw_write(16) | |
659 | __hsw_write(32) | |
660 | __hsw_write(64) | |
661 | __gen6_write(8) | |
662 | __gen6_write(16) | |
663 | __gen6_write(32) | |
664 | __gen6_write(64) | |
665 | __gen5_write(8) | |
666 | __gen5_write(16) | |
667 | __gen5_write(32) | |
668 | __gen5_write(64) | |
669 | __gen4_write(8) | |
670 | __gen4_write(16) | |
671 | __gen4_write(32) | |
672 | __gen4_write(64) | |
673 | ||
ab2aa47e | 674 | #undef __gen8_write |
4032ef43 BW |
675 | #undef __hsw_write |
676 | #undef __gen6_write | |
677 | #undef __gen5_write | |
678 | #undef __gen4_write | |
0d965301 | 679 | #undef REG_WRITE_FOOTER |
5d738795 | 680 | #undef REG_WRITE_HEADER |
907b28c5 | 681 | |
0b274481 BW |
682 | void intel_uncore_init(struct drm_device *dev) |
683 | { | |
684 | struct drm_i915_private *dev_priv = dev->dev_private; | |
685 | ||
8232644c CW |
686 | setup_timer(&dev_priv->uncore.force_wake_timer, |
687 | gen6_force_wake_timer, (unsigned long)dev_priv); | |
0b274481 BW |
688 | |
689 | if (IS_VALLEYVIEW(dev)) { | |
940aece4 D |
690 | dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; |
691 | dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; | |
43d1b647 | 692 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
0b274481 BW |
693 | dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get; |
694 | dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put; | |
695 | } else if (IS_IVYBRIDGE(dev)) { | |
696 | u32 ecobus; | |
697 | ||
698 | /* IVB configs may use multi-threaded forcewake */ | |
699 | ||
700 | /* A small trick here - if the bios hasn't configured | |
701 | * MT forcewake, and if the device is in RC6, then | |
702 | * force_wake_mt_get will not wake the device and the | |
703 | * ECOBUS read will return zero. Which will be | |
704 | * (correctly) interpreted by the test below as MT | |
705 | * forcewake being disabled. | |
706 | */ | |
707 | mutex_lock(&dev->struct_mutex); | |
c8d9a590 | 708 | __gen6_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL); |
0b274481 | 709 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
c8d9a590 | 710 | __gen6_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL); |
0b274481 BW |
711 | mutex_unlock(&dev->struct_mutex); |
712 | ||
713 | if (ecobus & FORCEWAKE_MT_ENABLE) { | |
714 | dev_priv->uncore.funcs.force_wake_get = | |
715 | __gen6_gt_force_wake_mt_get; | |
716 | dev_priv->uncore.funcs.force_wake_put = | |
717 | __gen6_gt_force_wake_mt_put; | |
718 | } else { | |
719 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); | |
720 | DRM_INFO("when using vblank-synced partial screen updates.\n"); | |
721 | dev_priv->uncore.funcs.force_wake_get = | |
722 | __gen6_gt_force_wake_get; | |
723 | dev_priv->uncore.funcs.force_wake_put = | |
724 | __gen6_gt_force_wake_put; | |
725 | } | |
726 | } else if (IS_GEN6(dev)) { | |
727 | dev_priv->uncore.funcs.force_wake_get = | |
728 | __gen6_gt_force_wake_get; | |
729 | dev_priv->uncore.funcs.force_wake_put = | |
730 | __gen6_gt_force_wake_put; | |
731 | } | |
732 | ||
3967018e | 733 | switch (INTEL_INFO(dev)->gen) { |
ab2aa47e BW |
734 | default: |
735 | dev_priv->uncore.funcs.mmio_writeb = gen8_write8; | |
736 | dev_priv->uncore.funcs.mmio_writew = gen8_write16; | |
737 | dev_priv->uncore.funcs.mmio_writel = gen8_write32; | |
738 | dev_priv->uncore.funcs.mmio_writeq = gen8_write64; | |
739 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; | |
740 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; | |
741 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; | |
742 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; | |
743 | break; | |
3967018e BW |
744 | case 7: |
745 | case 6: | |
4032ef43 BW |
746 | if (IS_HASWELL(dev)) { |
747 | dev_priv->uncore.funcs.mmio_writeb = hsw_write8; | |
748 | dev_priv->uncore.funcs.mmio_writew = hsw_write16; | |
749 | dev_priv->uncore.funcs.mmio_writel = hsw_write32; | |
750 | dev_priv->uncore.funcs.mmio_writeq = hsw_write64; | |
751 | } else { | |
752 | dev_priv->uncore.funcs.mmio_writeb = gen6_write8; | |
753 | dev_priv->uncore.funcs.mmio_writew = gen6_write16; | |
754 | dev_priv->uncore.funcs.mmio_writel = gen6_write32; | |
755 | dev_priv->uncore.funcs.mmio_writeq = gen6_write64; | |
756 | } | |
940aece4 D |
757 | |
758 | if (IS_VALLEYVIEW(dev)) { | |
759 | dev_priv->uncore.funcs.mmio_readb = vlv_read8; | |
760 | dev_priv->uncore.funcs.mmio_readw = vlv_read16; | |
761 | dev_priv->uncore.funcs.mmio_readl = vlv_read32; | |
762 | dev_priv->uncore.funcs.mmio_readq = vlv_read64; | |
763 | } else { | |
764 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; | |
765 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; | |
766 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; | |
767 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; | |
768 | } | |
3967018e BW |
769 | break; |
770 | case 5: | |
4032ef43 BW |
771 | dev_priv->uncore.funcs.mmio_writeb = gen5_write8; |
772 | dev_priv->uncore.funcs.mmio_writew = gen5_write16; | |
773 | dev_priv->uncore.funcs.mmio_writel = gen5_write32; | |
774 | dev_priv->uncore.funcs.mmio_writeq = gen5_write64; | |
3967018e BW |
775 | dev_priv->uncore.funcs.mmio_readb = gen5_read8; |
776 | dev_priv->uncore.funcs.mmio_readw = gen5_read16; | |
777 | dev_priv->uncore.funcs.mmio_readl = gen5_read32; | |
778 | dev_priv->uncore.funcs.mmio_readq = gen5_read64; | |
779 | break; | |
780 | case 4: | |
781 | case 3: | |
782 | case 2: | |
4032ef43 BW |
783 | dev_priv->uncore.funcs.mmio_writeb = gen4_write8; |
784 | dev_priv->uncore.funcs.mmio_writew = gen4_write16; | |
785 | dev_priv->uncore.funcs.mmio_writel = gen4_write32; | |
786 | dev_priv->uncore.funcs.mmio_writeq = gen4_write64; | |
3967018e BW |
787 | dev_priv->uncore.funcs.mmio_readb = gen4_read8; |
788 | dev_priv->uncore.funcs.mmio_readw = gen4_read16; | |
789 | dev_priv->uncore.funcs.mmio_readl = gen4_read32; | |
790 | dev_priv->uncore.funcs.mmio_readq = gen4_read64; | |
791 | break; | |
792 | } | |
0b274481 BW |
793 | } |
794 | ||
795 | void intel_uncore_fini(struct drm_device *dev) | |
796 | { | |
797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
798 | ||
8232644c | 799 | del_timer_sync(&dev_priv->uncore.force_wake_timer); |
0b274481 BW |
800 | |
801 | /* Paranoia: make sure we have disabled everything before we exit. */ | |
802 | intel_uncore_sanitize(dev); | |
8232644c | 803 | intel_uncore_forcewake_reset(dev); |
0b274481 BW |
804 | } |
805 | ||
907b28c5 CW |
806 | static const struct register_whitelist { |
807 | uint64_t offset; | |
808 | uint32_t size; | |
809 | uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ | |
810 | } whitelist[] = { | |
43181011 | 811 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0x1F0 }, |
907b28c5 CW |
812 | }; |
813 | ||
814 | int i915_reg_read_ioctl(struct drm_device *dev, | |
815 | void *data, struct drm_file *file) | |
816 | { | |
817 | struct drm_i915_private *dev_priv = dev->dev_private; | |
818 | struct drm_i915_reg_read *reg = data; | |
819 | struct register_whitelist const *entry = whitelist; | |
820 | int i; | |
821 | ||
822 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { | |
823 | if (entry->offset == reg->offset && | |
824 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) | |
825 | break; | |
826 | } | |
827 | ||
828 | if (i == ARRAY_SIZE(whitelist)) | |
829 | return -EINVAL; | |
830 | ||
831 | switch (entry->size) { | |
832 | case 8: | |
833 | reg->val = I915_READ64(reg->offset); | |
834 | break; | |
835 | case 4: | |
836 | reg->val = I915_READ(reg->offset); | |
837 | break; | |
838 | case 2: | |
839 | reg->val = I915_READ16(reg->offset); | |
840 | break; | |
841 | case 1: | |
842 | reg->val = I915_READ8(reg->offset); | |
843 | break; | |
844 | default: | |
845 | WARN_ON(1); | |
846 | return -EINVAL; | |
847 | } | |
848 | ||
849 | return 0; | |
850 | } | |
851 | ||
b6359918 MK |
852 | int i915_get_reset_stats_ioctl(struct drm_device *dev, |
853 | void *data, struct drm_file *file) | |
854 | { | |
855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
856 | struct drm_i915_reset_stats *args = data; | |
857 | struct i915_ctx_hang_stats *hs; | |
41bde553 | 858 | struct i915_hw_context *ctx; |
b6359918 MK |
859 | int ret; |
860 | ||
661df041 MK |
861 | if (args->flags || args->pad) |
862 | return -EINVAL; | |
863 | ||
b6359918 MK |
864 | if (args->ctx_id == DEFAULT_CONTEXT_ID && !capable(CAP_SYS_ADMIN)) |
865 | return -EPERM; | |
866 | ||
867 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
868 | if (ret) | |
869 | return ret; | |
870 | ||
41bde553 BW |
871 | ctx = i915_gem_context_get(file->driver_priv, args->ctx_id); |
872 | if (IS_ERR(ctx)) { | |
b6359918 | 873 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 874 | return PTR_ERR(ctx); |
b6359918 | 875 | } |
41bde553 | 876 | hs = &ctx->hang_stats; |
b6359918 MK |
877 | |
878 | if (capable(CAP_SYS_ADMIN)) | |
879 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); | |
880 | else | |
881 | args->reset_count = 0; | |
882 | ||
883 | args->batch_active = hs->batch_active; | |
884 | args->batch_pending = hs->batch_pending; | |
885 | ||
886 | mutex_unlock(&dev->struct_mutex); | |
887 | ||
888 | return 0; | |
889 | } | |
890 | ||
907b28c5 CW |
891 | static int i965_reset_complete(struct drm_device *dev) |
892 | { | |
893 | u8 gdrst; | |
894 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); | |
895 | return (gdrst & GRDOM_RESET_ENABLE) == 0; | |
896 | } | |
897 | ||
898 | static int i965_do_reset(struct drm_device *dev) | |
899 | { | |
900 | int ret; | |
901 | ||
902 | /* | |
903 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
904 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
905 | * triggers the reset; when done, the hardware will clear it. | |
906 | */ | |
907 | pci_write_config_byte(dev->pdev, I965_GDRST, | |
908 | GRDOM_RENDER | GRDOM_RESET_ENABLE); | |
909 | ret = wait_for(i965_reset_complete(dev), 500); | |
910 | if (ret) | |
911 | return ret; | |
912 | ||
913 | /* We can't reset render&media without also resetting display ... */ | |
914 | pci_write_config_byte(dev->pdev, I965_GDRST, | |
915 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); | |
916 | ||
917 | ret = wait_for(i965_reset_complete(dev), 500); | |
918 | if (ret) | |
919 | return ret; | |
920 | ||
921 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); | |
922 | ||
923 | return 0; | |
924 | } | |
925 | ||
926 | static int ironlake_do_reset(struct drm_device *dev) | |
927 | { | |
928 | struct drm_i915_private *dev_priv = dev->dev_private; | |
929 | u32 gdrst; | |
930 | int ret; | |
931 | ||
932 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
933 | gdrst &= ~GRDOM_MASK; | |
934 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, | |
935 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); | |
936 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
937 | if (ret) | |
938 | return ret; | |
939 | ||
940 | /* We can't reset render&media without also resetting display ... */ | |
941 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
942 | gdrst &= ~GRDOM_MASK; | |
943 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, | |
944 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); | |
945 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
946 | } | |
947 | ||
948 | static int gen6_do_reset(struct drm_device *dev) | |
949 | { | |
950 | struct drm_i915_private *dev_priv = dev->dev_private; | |
951 | int ret; | |
952 | unsigned long irqflags; | |
953 | ||
954 | /* Hold uncore.lock across reset to prevent any register access | |
955 | * with forcewake not set correctly | |
956 | */ | |
957 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
958 | ||
959 | /* Reset the chip */ | |
960 | ||
961 | /* GEN6_GDRST is not in the gt power well, no need to check | |
962 | * for fifo space for the write or forcewake the chip for | |
963 | * the read | |
964 | */ | |
6af5d92f | 965 | __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); |
907b28c5 CW |
966 | |
967 | /* Spin waiting for the device to ack the reset request */ | |
6af5d92f | 968 | ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
907b28c5 | 969 | |
521198a2 MK |
970 | intel_uncore_forcewake_reset(dev); |
971 | ||
907b28c5 | 972 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ |
ee7fa12c VS |
973 | if (IS_VALLEYVIEW(dev)) { |
974 | if (dev_priv->uncore.fw_rendercount) | |
975 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_RENDER); | |
976 | else | |
977 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_RENDER); | |
978 | ||
979 | if (dev_priv->uncore.fw_mediacount) | |
980 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_MEDIA); | |
981 | else | |
982 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_MEDIA); | |
983 | } else { | |
984 | if (dev_priv->uncore.forcewake_count) | |
985 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); | |
986 | else | |
987 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); | |
988 | } | |
907b28c5 CW |
989 | |
990 | /* Restore fifo count */ | |
46520e2b | 991 | dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
907b28c5 CW |
992 | |
993 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
994 | return ret; | |
995 | } | |
996 | ||
997 | int intel_gpu_reset(struct drm_device *dev) | |
998 | { | |
999 | switch (INTEL_INFO(dev)->gen) { | |
935e8de9 | 1000 | case 8: |
907b28c5 CW |
1001 | case 7: |
1002 | case 6: return gen6_do_reset(dev); | |
1003 | case 5: return ironlake_do_reset(dev); | |
1004 | case 4: return i965_do_reset(dev); | |
907b28c5 CW |
1005 | default: return -ENODEV; |
1006 | } | |
1007 | } | |
1008 | ||
907b28c5 CW |
1009 | void intel_uncore_check_errors(struct drm_device *dev) |
1010 | { | |
1011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1012 | ||
1013 | if (HAS_FPGA_DBG_UNCLAIMED(dev) && | |
6af5d92f | 1014 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
907b28c5 | 1015 | DRM_ERROR("Unclaimed register before interrupt\n"); |
6af5d92f | 1016 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
1017 | } |
1018 | } |