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907b28c5 CW |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "i915_drv.h" | |
25 | #include "intel_drv.h" | |
26 | ||
27 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 | |
28 | ||
6af5d92f CW |
29 | #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__)) |
30 | #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__)) | |
31 | ||
32 | #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) | |
33 | #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__)) | |
34 | ||
35 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
36 | #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__)) | |
37 | ||
38 | #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__)) | |
39 | #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__)) | |
40 | ||
41 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) | |
42 | ||
43 | ||
907b28c5 CW |
44 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
45 | { | |
46 | u32 gt_thread_status_mask; | |
47 | ||
48 | if (IS_HASWELL(dev_priv->dev)) | |
49 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; | |
50 | else | |
51 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; | |
52 | ||
53 | /* w/a for a sporadic read returning 0 by waiting for the GT | |
54 | * thread to wake up. | |
55 | */ | |
6af5d92f | 56 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) |
907b28c5 CW |
57 | DRM_ERROR("GT thread status wait timed out\n"); |
58 | } | |
59 | ||
60 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) | |
61 | { | |
6af5d92f CW |
62 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
63 | /* something from same cacheline, but !FORCEWAKE */ | |
64 | __raw_posting_read(dev_priv, ECOBUS); | |
907b28c5 CW |
65 | } |
66 | ||
67 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) | |
68 | { | |
6af5d92f | 69 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, |
907b28c5 CW |
70 | FORCEWAKE_ACK_TIMEOUT_MS)) |
71 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); | |
72 | ||
6af5d92f CW |
73 | __raw_i915_write32(dev_priv, FORCEWAKE, 1); |
74 | /* something from same cacheline, but !FORCEWAKE */ | |
75 | __raw_posting_read(dev_priv, ECOBUS); | |
907b28c5 | 76 | |
6af5d92f | 77 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1), |
907b28c5 CW |
78 | FORCEWAKE_ACK_TIMEOUT_MS)) |
79 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); | |
80 | ||
81 | /* WaRsForcewakeWaitTC0:snb */ | |
82 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
83 | } | |
84 | ||
85 | static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) | |
86 | { | |
6af5d92f | 87 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); |
907b28c5 | 88 | /* something from same cacheline, but !FORCEWAKE_MT */ |
6af5d92f | 89 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 CW |
90 | } |
91 | ||
92 | static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) | |
93 | { | |
94 | u32 forcewake_ack; | |
95 | ||
ab2aa47e | 96 | if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev)) |
907b28c5 CW |
97 | forcewake_ack = FORCEWAKE_ACK_HSW; |
98 | else | |
99 | forcewake_ack = FORCEWAKE_MT_ACK; | |
100 | ||
6af5d92f | 101 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0, |
907b28c5 CW |
102 | FORCEWAKE_ACK_TIMEOUT_MS)) |
103 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); | |
104 | ||
6af5d92f CW |
105 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
106 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
907b28c5 | 107 | /* something from same cacheline, but !FORCEWAKE_MT */ |
6af5d92f | 108 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 | 109 | |
6af5d92f | 110 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), |
907b28c5 CW |
111 | FORCEWAKE_ACK_TIMEOUT_MS)) |
112 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); | |
113 | ||
114 | /* WaRsForcewakeWaitTC0:ivb,hsw */ | |
0f161f70 BW |
115 | if (INTEL_INFO(dev_priv->dev)->gen < 8) |
116 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
907b28c5 CW |
117 | } |
118 | ||
119 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) | |
120 | { | |
121 | u32 gtfifodbg; | |
6af5d92f CW |
122 | |
123 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); | |
907b28c5 CW |
124 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, |
125 | "MMIO read or write has been dropped %x\n", gtfifodbg)) | |
6af5d92f | 126 | __raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); |
907b28c5 CW |
127 | } |
128 | ||
129 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) | |
130 | { | |
6af5d92f | 131 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
907b28c5 | 132 | /* something from same cacheline, but !FORCEWAKE */ |
6af5d92f | 133 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 CW |
134 | gen6_gt_check_fifodbg(dev_priv); |
135 | } | |
136 | ||
137 | static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) | |
138 | { | |
6af5d92f CW |
139 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
140 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
907b28c5 | 141 | /* something from same cacheline, but !FORCEWAKE_MT */ |
6af5d92f | 142 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 CW |
143 | gen6_gt_check_fifodbg(dev_priv); |
144 | } | |
145 | ||
146 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) | |
147 | { | |
148 | int ret = 0; | |
149 | ||
150 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { | |
151 | int loop = 500; | |
6af5d92f | 152 | u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); |
907b28c5 CW |
153 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
154 | udelay(10); | |
6af5d92f | 155 | fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); |
907b28c5 CW |
156 | } |
157 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) | |
158 | ++ret; | |
159 | dev_priv->uncore.fifo_count = fifo; | |
160 | } | |
161 | dev_priv->uncore.fifo_count--; | |
162 | ||
163 | return ret; | |
164 | } | |
165 | ||
166 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) | |
167 | { | |
6af5d92f CW |
168 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
169 | _MASKED_BIT_DISABLE(0xffff)); | |
907b28c5 | 170 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
6af5d92f | 171 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
907b28c5 CW |
172 | } |
173 | ||
174 | static void vlv_force_wake_get(struct drm_i915_private *dev_priv) | |
175 | { | |
6af5d92f | 176 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0, |
907b28c5 CW |
177 | FORCEWAKE_ACK_TIMEOUT_MS)) |
178 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); | |
179 | ||
6af5d92f CW |
180 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
181 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
182 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, | |
907b28c5 CW |
183 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
184 | ||
6af5d92f | 185 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL), |
907b28c5 CW |
186 | FORCEWAKE_ACK_TIMEOUT_MS)) |
187 | DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n"); | |
188 | ||
6af5d92f | 189 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_MEDIA_VLV) & |
907b28c5 CW |
190 | FORCEWAKE_KERNEL), |
191 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
192 | DRM_ERROR("Timed out waiting for media to ack forcewake request.\n"); | |
193 | ||
194 | /* WaRsForcewakeWaitTC0:vlv */ | |
195 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
196 | } | |
197 | ||
198 | static void vlv_force_wake_put(struct drm_i915_private *dev_priv) | |
199 | { | |
6af5d92f CW |
200 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
201 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
202 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, | |
907b28c5 CW |
203 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
204 | /* The below doubles as a POSTING_READ */ | |
205 | gen6_gt_check_fifodbg(dev_priv); | |
206 | } | |
207 | ||
aec347ab CW |
208 | static void gen6_force_wake_work(struct work_struct *work) |
209 | { | |
210 | struct drm_i915_private *dev_priv = | |
211 | container_of(work, typeof(*dev_priv), uncore.force_wake_work.work); | |
212 | unsigned long irqflags; | |
213 | ||
214 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
215 | if (--dev_priv->uncore.forcewake_count == 0) | |
216 | dev_priv->uncore.funcs.force_wake_put(dev_priv); | |
217 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
218 | } | |
219 | ||
907b28c5 CW |
220 | void intel_uncore_early_sanitize(struct drm_device *dev) |
221 | { | |
222 | struct drm_i915_private *dev_priv = dev->dev_private; | |
223 | ||
224 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) | |
6af5d92f | 225 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
18ce3994 BW |
226 | |
227 | if (IS_HASWELL(dev) && | |
228 | (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) { | |
229 | /* The docs do not explain exactly how the calculation can be | |
230 | * made. It is somewhat guessable, but for now, it's always | |
231 | * 128MB. | |
232 | * NB: We can't write IDICR yet because we do not have gt funcs | |
233 | * set up */ | |
234 | dev_priv->ellc_size = 128; | |
235 | DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); | |
236 | } | |
907b28c5 CW |
237 | } |
238 | ||
521198a2 | 239 | static void intel_uncore_forcewake_reset(struct drm_device *dev) |
907b28c5 CW |
240 | { |
241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
242 | ||
243 | if (IS_VALLEYVIEW(dev)) { | |
244 | vlv_force_wake_reset(dev_priv); | |
245 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
246 | __gen6_gt_force_wake_reset(dev_priv); | |
247 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
248 | __gen6_gt_force_wake_mt_reset(dev_priv); | |
249 | } | |
521198a2 MK |
250 | } |
251 | ||
252 | void intel_uncore_sanitize(struct drm_device *dev) | |
253 | { | |
02f4c9e0 CML |
254 | struct drm_i915_private *dev_priv = dev->dev_private; |
255 | u32 reg_val; | |
256 | ||
521198a2 | 257 | intel_uncore_forcewake_reset(dev); |
907b28c5 CW |
258 | |
259 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ | |
260 | intel_disable_gt_powersave(dev); | |
02f4c9e0 CML |
261 | |
262 | /* Turn off power gate, require especially for the BIOS less system */ | |
263 | if (IS_VALLEYVIEW(dev)) { | |
264 | ||
265 | mutex_lock(&dev_priv->rps.hw_lock); | |
266 | reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS); | |
267 | ||
268 | if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT)) | |
269 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0); | |
270 | ||
271 | mutex_unlock(&dev_priv->rps.hw_lock); | |
272 | ||
273 | } | |
907b28c5 CW |
274 | } |
275 | ||
276 | /* | |
277 | * Generally this is called implicitly by the register read function. However, | |
278 | * if some sequence requires the GT to not power down then this function should | |
279 | * be called at the beginning of the sequence followed by a call to | |
280 | * gen6_gt_force_wake_put() at the end of the sequence. | |
281 | */ | |
282 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) | |
283 | { | |
284 | unsigned long irqflags; | |
285 | ||
ab484f8f BW |
286 | if (!dev_priv->uncore.funcs.force_wake_get) |
287 | return; | |
288 | ||
907b28c5 CW |
289 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
290 | if (dev_priv->uncore.forcewake_count++ == 0) | |
291 | dev_priv->uncore.funcs.force_wake_get(dev_priv); | |
292 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
293 | } | |
294 | ||
295 | /* | |
296 | * see gen6_gt_force_wake_get() | |
297 | */ | |
298 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) | |
299 | { | |
300 | unsigned long irqflags; | |
301 | ||
ab484f8f BW |
302 | if (!dev_priv->uncore.funcs.force_wake_put) |
303 | return; | |
304 | ||
907b28c5 | 305 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
aec347ab CW |
306 | if (--dev_priv->uncore.forcewake_count == 0) { |
307 | dev_priv->uncore.forcewake_count++; | |
308 | mod_delayed_work(dev_priv->wq, | |
309 | &dev_priv->uncore.force_wake_work, | |
310 | 1); | |
311 | } | |
907b28c5 CW |
312 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
313 | } | |
314 | ||
315 | /* We give fast paths for the really cool registers */ | |
316 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | |
ab484f8f | 317 | ((reg) < 0x40000 && (reg) != FORCEWAKE) |
907b28c5 CW |
318 | |
319 | static void | |
320 | ilk_dummy_write(struct drm_i915_private *dev_priv) | |
321 | { | |
322 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up | |
323 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
324 | * hence harmless to write 0 into. */ | |
6af5d92f | 325 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
907b28c5 CW |
326 | } |
327 | ||
328 | static void | |
329 | hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) | |
330 | { | |
ab484f8f | 331 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
907b28c5 CW |
332 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", |
333 | reg); | |
6af5d92f | 334 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
335 | } |
336 | } | |
337 | ||
338 | static void | |
339 | hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) | |
340 | { | |
ab484f8f | 341 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
907b28c5 | 342 | DRM_ERROR("Unclaimed write to %x\n", reg); |
6af5d92f | 343 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
344 | } |
345 | } | |
346 | ||
5d738795 BW |
347 | #define REG_READ_HEADER(x) \ |
348 | unsigned long irqflags; \ | |
349 | u##x val = 0; \ | |
350 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) | |
351 | ||
352 | #define REG_READ_FOOTER \ | |
353 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
354 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ | |
355 | return val | |
356 | ||
3967018e | 357 | #define __gen4_read(x) \ |
0b274481 | 358 | static u##x \ |
3967018e BW |
359 | gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
360 | REG_READ_HEADER(x); \ | |
361 | val = __raw_i915_read##x(dev_priv, reg); \ | |
362 | REG_READ_FOOTER; \ | |
363 | } | |
364 | ||
365 | #define __gen5_read(x) \ | |
366 | static u##x \ | |
367 | gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
368 | REG_READ_HEADER(x); \ | |
369 | ilk_dummy_write(dev_priv); \ | |
370 | val = __raw_i915_read##x(dev_priv, reg); \ | |
371 | REG_READ_FOOTER; \ | |
372 | } | |
373 | ||
374 | #define __gen6_read(x) \ | |
375 | static u##x \ | |
376 | gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
5d738795 | 377 | REG_READ_HEADER(x); \ |
907b28c5 CW |
378 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
379 | if (dev_priv->uncore.forcewake_count == 0) \ | |
380 | dev_priv->uncore.funcs.force_wake_get(dev_priv); \ | |
6af5d92f | 381 | val = __raw_i915_read##x(dev_priv, reg); \ |
907b28c5 CW |
382 | if (dev_priv->uncore.forcewake_count == 0) \ |
383 | dev_priv->uncore.funcs.force_wake_put(dev_priv); \ | |
384 | } else { \ | |
6af5d92f | 385 | val = __raw_i915_read##x(dev_priv, reg); \ |
907b28c5 | 386 | } \ |
5d738795 | 387 | REG_READ_FOOTER; \ |
907b28c5 CW |
388 | } |
389 | ||
3967018e BW |
390 | __gen6_read(8) |
391 | __gen6_read(16) | |
392 | __gen6_read(32) | |
393 | __gen6_read(64) | |
394 | __gen5_read(8) | |
395 | __gen5_read(16) | |
396 | __gen5_read(32) | |
397 | __gen5_read(64) | |
398 | __gen4_read(8) | |
399 | __gen4_read(16) | |
400 | __gen4_read(32) | |
401 | __gen4_read(64) | |
402 | ||
403 | #undef __gen6_read | |
404 | #undef __gen5_read | |
405 | #undef __gen4_read | |
5d738795 BW |
406 | #undef REG_READ_FOOTER |
407 | #undef REG_READ_HEADER | |
408 | ||
409 | #define REG_WRITE_HEADER \ | |
410 | unsigned long irqflags; \ | |
411 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
412 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) | |
907b28c5 | 413 | |
4032ef43 | 414 | #define __gen4_write(x) \ |
0b274481 | 415 | static void \ |
4032ef43 BW |
416 | gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
417 | REG_WRITE_HEADER; \ | |
418 | __raw_i915_write##x(dev_priv, reg, val); \ | |
419 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
420 | } | |
421 | ||
422 | #define __gen5_write(x) \ | |
423 | static void \ | |
424 | gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
425 | REG_WRITE_HEADER; \ | |
426 | ilk_dummy_write(dev_priv); \ | |
427 | __raw_i915_write##x(dev_priv, reg, val); \ | |
428 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
429 | } | |
430 | ||
431 | #define __gen6_write(x) \ | |
432 | static void \ | |
433 | gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
434 | u32 __fifo_ret = 0; \ | |
435 | REG_WRITE_HEADER; \ | |
436 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
437 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ | |
438 | } \ | |
439 | __raw_i915_write##x(dev_priv, reg, val); \ | |
440 | if (unlikely(__fifo_ret)) { \ | |
441 | gen6_gt_check_fifodbg(dev_priv); \ | |
442 | } \ | |
443 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
444 | } | |
445 | ||
446 | #define __hsw_write(x) \ | |
447 | static void \ | |
448 | hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
907b28c5 | 449 | u32 __fifo_ret = 0; \ |
5d738795 | 450 | REG_WRITE_HEADER; \ |
907b28c5 CW |
451 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
452 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ | |
453 | } \ | |
907b28c5 | 454 | hsw_unclaimed_reg_clear(dev_priv, reg); \ |
6af5d92f | 455 | __raw_i915_write##x(dev_priv, reg, val); \ |
907b28c5 CW |
456 | if (unlikely(__fifo_ret)) { \ |
457 | gen6_gt_check_fifodbg(dev_priv); \ | |
458 | } \ | |
459 | hsw_unclaimed_reg_check(dev_priv, reg); \ | |
460 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
461 | } | |
3967018e | 462 | |
ab2aa47e BW |
463 | static const u32 gen8_shadowed_regs[] = { |
464 | FORCEWAKE_MT, | |
465 | GEN6_RPNSWREQ, | |
466 | GEN6_RC_VIDEO_FREQ, | |
467 | RING_TAIL(RENDER_RING_BASE), | |
468 | RING_TAIL(GEN6_BSD_RING_BASE), | |
469 | RING_TAIL(VEBOX_RING_BASE), | |
470 | RING_TAIL(BLT_RING_BASE), | |
471 | /* TODO: Other registers are not yet used */ | |
472 | }; | |
473 | ||
474 | static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg) | |
475 | { | |
476 | int i; | |
477 | for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) | |
478 | if (reg == gen8_shadowed_regs[i]) | |
479 | return true; | |
480 | ||
481 | return false; | |
482 | } | |
483 | ||
484 | #define __gen8_write(x) \ | |
485 | static void \ | |
486 | gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
487 | bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \ | |
488 | REG_WRITE_HEADER; \ | |
489 | if (__needs_put) { \ | |
490 | dev_priv->uncore.funcs.force_wake_get(dev_priv); \ | |
491 | } \ | |
492 | __raw_i915_write##x(dev_priv, reg, val); \ | |
493 | if (__needs_put) { \ | |
494 | dev_priv->uncore.funcs.force_wake_put(dev_priv); \ | |
495 | } \ | |
496 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
497 | } | |
498 | ||
499 | __gen8_write(8) | |
500 | __gen8_write(16) | |
501 | __gen8_write(32) | |
502 | __gen8_write(64) | |
4032ef43 BW |
503 | __hsw_write(8) |
504 | __hsw_write(16) | |
505 | __hsw_write(32) | |
506 | __hsw_write(64) | |
507 | __gen6_write(8) | |
508 | __gen6_write(16) | |
509 | __gen6_write(32) | |
510 | __gen6_write(64) | |
511 | __gen5_write(8) | |
512 | __gen5_write(16) | |
513 | __gen5_write(32) | |
514 | __gen5_write(64) | |
515 | __gen4_write(8) | |
516 | __gen4_write(16) | |
517 | __gen4_write(32) | |
518 | __gen4_write(64) | |
519 | ||
ab2aa47e | 520 | #undef __gen8_write |
4032ef43 BW |
521 | #undef __hsw_write |
522 | #undef __gen6_write | |
523 | #undef __gen5_write | |
524 | #undef __gen4_write | |
5d738795 | 525 | #undef REG_WRITE_HEADER |
907b28c5 | 526 | |
0b274481 BW |
527 | void intel_uncore_init(struct drm_device *dev) |
528 | { | |
529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
530 | ||
531 | INIT_DELAYED_WORK(&dev_priv->uncore.force_wake_work, | |
532 | gen6_force_wake_work); | |
533 | ||
534 | if (IS_VALLEYVIEW(dev)) { | |
535 | dev_priv->uncore.funcs.force_wake_get = vlv_force_wake_get; | |
536 | dev_priv->uncore.funcs.force_wake_put = vlv_force_wake_put; | |
43d1b647 | 537 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
0b274481 BW |
538 | dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get; |
539 | dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put; | |
540 | } else if (IS_IVYBRIDGE(dev)) { | |
541 | u32 ecobus; | |
542 | ||
543 | /* IVB configs may use multi-threaded forcewake */ | |
544 | ||
545 | /* A small trick here - if the bios hasn't configured | |
546 | * MT forcewake, and if the device is in RC6, then | |
547 | * force_wake_mt_get will not wake the device and the | |
548 | * ECOBUS read will return zero. Which will be | |
549 | * (correctly) interpreted by the test below as MT | |
550 | * forcewake being disabled. | |
551 | */ | |
552 | mutex_lock(&dev->struct_mutex); | |
553 | __gen6_gt_force_wake_mt_get(dev_priv); | |
554 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); | |
555 | __gen6_gt_force_wake_mt_put(dev_priv); | |
556 | mutex_unlock(&dev->struct_mutex); | |
557 | ||
558 | if (ecobus & FORCEWAKE_MT_ENABLE) { | |
559 | dev_priv->uncore.funcs.force_wake_get = | |
560 | __gen6_gt_force_wake_mt_get; | |
561 | dev_priv->uncore.funcs.force_wake_put = | |
562 | __gen6_gt_force_wake_mt_put; | |
563 | } else { | |
564 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); | |
565 | DRM_INFO("when using vblank-synced partial screen updates.\n"); | |
566 | dev_priv->uncore.funcs.force_wake_get = | |
567 | __gen6_gt_force_wake_get; | |
568 | dev_priv->uncore.funcs.force_wake_put = | |
569 | __gen6_gt_force_wake_put; | |
570 | } | |
571 | } else if (IS_GEN6(dev)) { | |
572 | dev_priv->uncore.funcs.force_wake_get = | |
573 | __gen6_gt_force_wake_get; | |
574 | dev_priv->uncore.funcs.force_wake_put = | |
575 | __gen6_gt_force_wake_put; | |
576 | } | |
577 | ||
3967018e | 578 | switch (INTEL_INFO(dev)->gen) { |
ab2aa47e BW |
579 | default: |
580 | dev_priv->uncore.funcs.mmio_writeb = gen8_write8; | |
581 | dev_priv->uncore.funcs.mmio_writew = gen8_write16; | |
582 | dev_priv->uncore.funcs.mmio_writel = gen8_write32; | |
583 | dev_priv->uncore.funcs.mmio_writeq = gen8_write64; | |
584 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; | |
585 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; | |
586 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; | |
587 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; | |
588 | break; | |
3967018e BW |
589 | case 7: |
590 | case 6: | |
4032ef43 BW |
591 | if (IS_HASWELL(dev)) { |
592 | dev_priv->uncore.funcs.mmio_writeb = hsw_write8; | |
593 | dev_priv->uncore.funcs.mmio_writew = hsw_write16; | |
594 | dev_priv->uncore.funcs.mmio_writel = hsw_write32; | |
595 | dev_priv->uncore.funcs.mmio_writeq = hsw_write64; | |
596 | } else { | |
597 | dev_priv->uncore.funcs.mmio_writeb = gen6_write8; | |
598 | dev_priv->uncore.funcs.mmio_writew = gen6_write16; | |
599 | dev_priv->uncore.funcs.mmio_writel = gen6_write32; | |
600 | dev_priv->uncore.funcs.mmio_writeq = gen6_write64; | |
601 | } | |
3967018e BW |
602 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; |
603 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; | |
604 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; | |
605 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; | |
606 | break; | |
607 | case 5: | |
4032ef43 BW |
608 | dev_priv->uncore.funcs.mmio_writeb = gen5_write8; |
609 | dev_priv->uncore.funcs.mmio_writew = gen5_write16; | |
610 | dev_priv->uncore.funcs.mmio_writel = gen5_write32; | |
611 | dev_priv->uncore.funcs.mmio_writeq = gen5_write64; | |
3967018e BW |
612 | dev_priv->uncore.funcs.mmio_readb = gen5_read8; |
613 | dev_priv->uncore.funcs.mmio_readw = gen5_read16; | |
614 | dev_priv->uncore.funcs.mmio_readl = gen5_read32; | |
615 | dev_priv->uncore.funcs.mmio_readq = gen5_read64; | |
616 | break; | |
617 | case 4: | |
618 | case 3: | |
619 | case 2: | |
4032ef43 BW |
620 | dev_priv->uncore.funcs.mmio_writeb = gen4_write8; |
621 | dev_priv->uncore.funcs.mmio_writew = gen4_write16; | |
622 | dev_priv->uncore.funcs.mmio_writel = gen4_write32; | |
623 | dev_priv->uncore.funcs.mmio_writeq = gen4_write64; | |
3967018e BW |
624 | dev_priv->uncore.funcs.mmio_readb = gen4_read8; |
625 | dev_priv->uncore.funcs.mmio_readw = gen4_read16; | |
626 | dev_priv->uncore.funcs.mmio_readl = gen4_read32; | |
627 | dev_priv->uncore.funcs.mmio_readq = gen4_read64; | |
628 | break; | |
629 | } | |
0b274481 BW |
630 | } |
631 | ||
632 | void intel_uncore_fini(struct drm_device *dev) | |
633 | { | |
634 | struct drm_i915_private *dev_priv = dev->dev_private; | |
635 | ||
636 | flush_delayed_work(&dev_priv->uncore.force_wake_work); | |
637 | ||
638 | /* Paranoia: make sure we have disabled everything before we exit. */ | |
639 | intel_uncore_sanitize(dev); | |
640 | } | |
641 | ||
907b28c5 CW |
642 | static const struct register_whitelist { |
643 | uint64_t offset; | |
644 | uint32_t size; | |
645 | uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ | |
646 | } whitelist[] = { | |
647 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 }, | |
648 | }; | |
649 | ||
650 | int i915_reg_read_ioctl(struct drm_device *dev, | |
651 | void *data, struct drm_file *file) | |
652 | { | |
653 | struct drm_i915_private *dev_priv = dev->dev_private; | |
654 | struct drm_i915_reg_read *reg = data; | |
655 | struct register_whitelist const *entry = whitelist; | |
656 | int i; | |
657 | ||
658 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { | |
659 | if (entry->offset == reg->offset && | |
660 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) | |
661 | break; | |
662 | } | |
663 | ||
664 | if (i == ARRAY_SIZE(whitelist)) | |
665 | return -EINVAL; | |
666 | ||
667 | switch (entry->size) { | |
668 | case 8: | |
669 | reg->val = I915_READ64(reg->offset); | |
670 | break; | |
671 | case 4: | |
672 | reg->val = I915_READ(reg->offset); | |
673 | break; | |
674 | case 2: | |
675 | reg->val = I915_READ16(reg->offset); | |
676 | break; | |
677 | case 1: | |
678 | reg->val = I915_READ8(reg->offset); | |
679 | break; | |
680 | default: | |
681 | WARN_ON(1); | |
682 | return -EINVAL; | |
683 | } | |
684 | ||
685 | return 0; | |
686 | } | |
687 | ||
907b28c5 CW |
688 | static int i965_reset_complete(struct drm_device *dev) |
689 | { | |
690 | u8 gdrst; | |
691 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); | |
692 | return (gdrst & GRDOM_RESET_ENABLE) == 0; | |
693 | } | |
694 | ||
695 | static int i965_do_reset(struct drm_device *dev) | |
696 | { | |
697 | int ret; | |
698 | ||
699 | /* | |
700 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
701 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
702 | * triggers the reset; when done, the hardware will clear it. | |
703 | */ | |
704 | pci_write_config_byte(dev->pdev, I965_GDRST, | |
705 | GRDOM_RENDER | GRDOM_RESET_ENABLE); | |
706 | ret = wait_for(i965_reset_complete(dev), 500); | |
707 | if (ret) | |
708 | return ret; | |
709 | ||
710 | /* We can't reset render&media without also resetting display ... */ | |
711 | pci_write_config_byte(dev->pdev, I965_GDRST, | |
712 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); | |
713 | ||
714 | ret = wait_for(i965_reset_complete(dev), 500); | |
715 | if (ret) | |
716 | return ret; | |
717 | ||
718 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
723 | static int ironlake_do_reset(struct drm_device *dev) | |
724 | { | |
725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
726 | u32 gdrst; | |
727 | int ret; | |
728 | ||
729 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
730 | gdrst &= ~GRDOM_MASK; | |
731 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, | |
732 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); | |
733 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
734 | if (ret) | |
735 | return ret; | |
736 | ||
737 | /* We can't reset render&media without also resetting display ... */ | |
738 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
739 | gdrst &= ~GRDOM_MASK; | |
740 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, | |
741 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); | |
742 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
743 | } | |
744 | ||
745 | static int gen6_do_reset(struct drm_device *dev) | |
746 | { | |
747 | struct drm_i915_private *dev_priv = dev->dev_private; | |
748 | int ret; | |
749 | unsigned long irqflags; | |
750 | ||
751 | /* Hold uncore.lock across reset to prevent any register access | |
752 | * with forcewake not set correctly | |
753 | */ | |
754 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
755 | ||
756 | /* Reset the chip */ | |
757 | ||
758 | /* GEN6_GDRST is not in the gt power well, no need to check | |
759 | * for fifo space for the write or forcewake the chip for | |
760 | * the read | |
761 | */ | |
6af5d92f | 762 | __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); |
907b28c5 CW |
763 | |
764 | /* Spin waiting for the device to ack the reset request */ | |
6af5d92f | 765 | ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
907b28c5 | 766 | |
521198a2 MK |
767 | intel_uncore_forcewake_reset(dev); |
768 | ||
907b28c5 CW |
769 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ |
770 | if (dev_priv->uncore.forcewake_count) | |
771 | dev_priv->uncore.funcs.force_wake_get(dev_priv); | |
772 | else | |
773 | dev_priv->uncore.funcs.force_wake_put(dev_priv); | |
774 | ||
775 | /* Restore fifo count */ | |
6af5d92f | 776 | dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); |
907b28c5 CW |
777 | |
778 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
779 | return ret; | |
780 | } | |
781 | ||
782 | int intel_gpu_reset(struct drm_device *dev) | |
783 | { | |
784 | switch (INTEL_INFO(dev)->gen) { | |
785 | case 7: | |
786 | case 6: return gen6_do_reset(dev); | |
787 | case 5: return ironlake_do_reset(dev); | |
788 | case 4: return i965_do_reset(dev); | |
907b28c5 CW |
789 | default: return -ENODEV; |
790 | } | |
791 | } | |
792 | ||
793 | void intel_uncore_clear_errors(struct drm_device *dev) | |
794 | { | |
795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
796 | ||
6af5d92f | 797 | /* XXX needs spinlock around caller's grouping */ |
907b28c5 | 798 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) |
6af5d92f | 799 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
800 | } |
801 | ||
802 | void intel_uncore_check_errors(struct drm_device *dev) | |
803 | { | |
804 | struct drm_i915_private *dev_priv = dev->dev_private; | |
805 | ||
806 | if (HAS_FPGA_DBG_UNCLAIMED(dev) && | |
6af5d92f | 807 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
907b28c5 | 808 | DRM_ERROR("Unclaimed register before interrupt\n"); |
6af5d92f | 809 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
810 | } |
811 | } |