Commit | Line | Data |
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907b28c5 CW |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "i915_drv.h" | |
25 | #include "intel_drv.h" | |
cf9d2890 | 26 | #include "i915_vgpu.h" |
907b28c5 | 27 | |
6daccb0b CW |
28 | #include <linux/pm_runtime.h> |
29 | ||
83e33372 | 30 | #define FORCEWAKE_ACK_TIMEOUT_MS 50 |
907b28c5 | 31 | |
75aa3f63 | 32 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__)) |
6af5d92f | 33 | |
05a2fb15 MK |
34 | static const char * const forcewake_domain_names[] = { |
35 | "render", | |
36 | "blitter", | |
37 | "media", | |
38 | }; | |
39 | ||
40 | const char * | |
48c1026a | 41 | intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) |
05a2fb15 | 42 | { |
53abb679 | 43 | BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT); |
05a2fb15 MK |
44 | |
45 | if (id >= 0 && id < FW_DOMAIN_ID_COUNT) | |
46 | return forcewake_domain_names[id]; | |
47 | ||
48 | WARN_ON(id); | |
49 | ||
50 | return "unknown"; | |
51 | } | |
52 | ||
05a2fb15 MK |
53 | static inline void |
54 | fw_domain_reset(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 55 | { |
f0f59a00 | 56 | WARN_ON(!i915_mmio_reg_valid(d->reg_set)); |
05a2fb15 | 57 | __raw_i915_write32(d->i915, d->reg_set, d->val_reset); |
907b28c5 CW |
58 | } |
59 | ||
05a2fb15 MK |
60 | static inline void |
61 | fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 62 | { |
a57a4a67 TU |
63 | d->wake_count++; |
64 | hrtimer_start_range_ns(&d->timer, | |
65 | ktime_set(0, NSEC_PER_MSEC), | |
66 | NSEC_PER_MSEC, | |
67 | HRTIMER_MODE_REL); | |
907b28c5 CW |
68 | } |
69 | ||
05a2fb15 MK |
70 | static inline void |
71 | fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 72 | { |
05a2fb15 MK |
73 | if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) & |
74 | FORCEWAKE_KERNEL) == 0, | |
907b28c5 | 75 | FORCEWAKE_ACK_TIMEOUT_MS)) |
05a2fb15 MK |
76 | DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n", |
77 | intel_uncore_forcewake_domain_to_str(d->id)); | |
78 | } | |
907b28c5 | 79 | |
05a2fb15 MK |
80 | static inline void |
81 | fw_domain_get(const struct intel_uncore_forcewake_domain *d) | |
82 | { | |
83 | __raw_i915_write32(d->i915, d->reg_set, d->val_set); | |
84 | } | |
907b28c5 | 85 | |
05a2fb15 MK |
86 | static inline void |
87 | fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d) | |
88 | { | |
89 | if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) & | |
90 | FORCEWAKE_KERNEL), | |
907b28c5 | 91 | FORCEWAKE_ACK_TIMEOUT_MS)) |
05a2fb15 MK |
92 | DRM_ERROR("%s: timed out waiting for forcewake ack request.\n", |
93 | intel_uncore_forcewake_domain_to_str(d->id)); | |
94 | } | |
907b28c5 | 95 | |
05a2fb15 MK |
96 | static inline void |
97 | fw_domain_put(const struct intel_uncore_forcewake_domain *d) | |
98 | { | |
99 | __raw_i915_write32(d->i915, d->reg_set, d->val_clear); | |
907b28c5 CW |
100 | } |
101 | ||
05a2fb15 MK |
102 | static inline void |
103 | fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 104 | { |
05a2fb15 | 105 | /* something from same cacheline, but not from the set register */ |
f0f59a00 | 106 | if (i915_mmio_reg_valid(d->reg_post)) |
05a2fb15 | 107 | __raw_posting_read(d->i915, d->reg_post); |
907b28c5 CW |
108 | } |
109 | ||
05a2fb15 | 110 | static void |
48c1026a | 111 | fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
907b28c5 | 112 | { |
05a2fb15 | 113 | struct intel_uncore_forcewake_domain *d; |
48c1026a | 114 | enum forcewake_domain_id id; |
907b28c5 | 115 | |
05a2fb15 MK |
116 | for_each_fw_domain_mask(d, fw_domains, dev_priv, id) { |
117 | fw_domain_wait_ack_clear(d); | |
118 | fw_domain_get(d); | |
05a2fb15 MK |
119 | fw_domain_wait_ack(d); |
120 | } | |
121 | } | |
907b28c5 | 122 | |
05a2fb15 | 123 | static void |
48c1026a | 124 | fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
05a2fb15 MK |
125 | { |
126 | struct intel_uncore_forcewake_domain *d; | |
48c1026a | 127 | enum forcewake_domain_id id; |
907b28c5 | 128 | |
05a2fb15 MK |
129 | for_each_fw_domain_mask(d, fw_domains, dev_priv, id) { |
130 | fw_domain_put(d); | |
131 | fw_domain_posting_read(d); | |
132 | } | |
133 | } | |
907b28c5 | 134 | |
05a2fb15 MK |
135 | static void |
136 | fw_domains_posting_read(struct drm_i915_private *dev_priv) | |
137 | { | |
138 | struct intel_uncore_forcewake_domain *d; | |
48c1026a | 139 | enum forcewake_domain_id id; |
05a2fb15 MK |
140 | |
141 | /* No need to do for all, just do for first found */ | |
142 | for_each_fw_domain(d, dev_priv, id) { | |
143 | fw_domain_posting_read(d); | |
144 | break; | |
145 | } | |
146 | } | |
147 | ||
148 | static void | |
48c1026a | 149 | fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
05a2fb15 MK |
150 | { |
151 | struct intel_uncore_forcewake_domain *d; | |
48c1026a | 152 | enum forcewake_domain_id id; |
05a2fb15 | 153 | |
3225b2f9 MK |
154 | if (dev_priv->uncore.fw_domains == 0) |
155 | return; | |
f9b3927a | 156 | |
05a2fb15 MK |
157 | for_each_fw_domain_mask(d, fw_domains, dev_priv, id) |
158 | fw_domain_reset(d); | |
159 | ||
160 | fw_domains_posting_read(dev_priv); | |
161 | } | |
162 | ||
163 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) | |
164 | { | |
165 | /* w/a for a sporadic read returning 0 by waiting for the GT | |
166 | * thread to wake up. | |
167 | */ | |
168 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & | |
169 | GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500)) | |
170 | DRM_ERROR("GT thread status wait timed out\n"); | |
171 | } | |
172 | ||
173 | static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv, | |
48c1026a | 174 | enum forcewake_domains fw_domains) |
05a2fb15 MK |
175 | { |
176 | fw_domains_get(dev_priv, fw_domains); | |
907b28c5 | 177 | |
05a2fb15 | 178 | /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ |
c549f738 | 179 | __gen6_gt_wait_for_thread_c0(dev_priv); |
907b28c5 CW |
180 | } |
181 | ||
182 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) | |
183 | { | |
184 | u32 gtfifodbg; | |
6af5d92f CW |
185 | |
186 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); | |
90f256b5 VS |
187 | if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) |
188 | __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); | |
907b28c5 CW |
189 | } |
190 | ||
05a2fb15 | 191 | static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv, |
48c1026a | 192 | enum forcewake_domains fw_domains) |
907b28c5 | 193 | { |
05a2fb15 | 194 | fw_domains_put(dev_priv, fw_domains); |
907b28c5 CW |
195 | gen6_gt_check_fifodbg(dev_priv); |
196 | } | |
197 | ||
c32e3788 DG |
198 | static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) |
199 | { | |
200 | u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); | |
201 | ||
202 | return count & GT_FIFO_FREE_ENTRIES_MASK; | |
203 | } | |
204 | ||
907b28c5 CW |
205 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
206 | { | |
207 | int ret = 0; | |
208 | ||
5135d64b D |
209 | /* On VLV, FIFO will be shared by both SW and HW. |
210 | * So, we need to read the FREE_ENTRIES everytime */ | |
2d1fe073 | 211 | if (IS_VALLEYVIEW(dev_priv)) |
c32e3788 | 212 | dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); |
5135d64b | 213 | |
907b28c5 CW |
214 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
215 | int loop = 500; | |
c32e3788 DG |
216 | u32 fifo = fifo_free_entries(dev_priv); |
217 | ||
907b28c5 CW |
218 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
219 | udelay(10); | |
c32e3788 | 220 | fifo = fifo_free_entries(dev_priv); |
907b28c5 CW |
221 | } |
222 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) | |
223 | ++ret; | |
224 | dev_priv->uncore.fifo_count = fifo; | |
225 | } | |
226 | dev_priv->uncore.fifo_count--; | |
227 | ||
228 | return ret; | |
229 | } | |
230 | ||
a57a4a67 TU |
231 | static enum hrtimer_restart |
232 | intel_uncore_fw_release_timer(struct hrtimer *timer) | |
38cff0b1 | 233 | { |
a57a4a67 TU |
234 | struct intel_uncore_forcewake_domain *domain = |
235 | container_of(timer, struct intel_uncore_forcewake_domain, timer); | |
b2cff0db | 236 | unsigned long irqflags; |
38cff0b1 | 237 | |
da5827c3 | 238 | assert_rpm_device_not_suspended(domain->i915); |
38cff0b1 | 239 | |
b2cff0db CW |
240 | spin_lock_irqsave(&domain->i915->uncore.lock, irqflags); |
241 | if (WARN_ON(domain->wake_count == 0)) | |
242 | domain->wake_count++; | |
243 | ||
244 | if (--domain->wake_count == 0) | |
245 | domain->i915->uncore.funcs.force_wake_put(domain->i915, | |
246 | 1 << domain->id); | |
247 | ||
248 | spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags); | |
a57a4a67 TU |
249 | |
250 | return HRTIMER_NORESTART; | |
38cff0b1 ZW |
251 | } |
252 | ||
b2cff0db | 253 | void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) |
38cff0b1 | 254 | { |
b2cff0db | 255 | struct drm_i915_private *dev_priv = dev->dev_private; |
48c1026a | 256 | unsigned long irqflags; |
b2cff0db | 257 | struct intel_uncore_forcewake_domain *domain; |
48c1026a MK |
258 | int retry_count = 100; |
259 | enum forcewake_domain_id id; | |
260 | enum forcewake_domains fw = 0, active_domains; | |
38cff0b1 | 261 | |
b2cff0db CW |
262 | /* Hold uncore.lock across reset to prevent any register access |
263 | * with forcewake not set correctly. Wait until all pending | |
264 | * timers are run before holding. | |
265 | */ | |
266 | while (1) { | |
267 | active_domains = 0; | |
38cff0b1 | 268 | |
b2cff0db | 269 | for_each_fw_domain(domain, dev_priv, id) { |
a57a4a67 | 270 | if (hrtimer_cancel(&domain->timer) == 0) |
b2cff0db | 271 | continue; |
38cff0b1 | 272 | |
a57a4a67 | 273 | intel_uncore_fw_release_timer(&domain->timer); |
b2cff0db | 274 | } |
aec347ab | 275 | |
b2cff0db | 276 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
b2ec142c | 277 | |
b2cff0db | 278 | for_each_fw_domain(domain, dev_priv, id) { |
a57a4a67 | 279 | if (hrtimer_active(&domain->timer)) |
b2cff0db CW |
280 | active_domains |= (1 << id); |
281 | } | |
3123fcaf | 282 | |
b2cff0db CW |
283 | if (active_domains == 0) |
284 | break; | |
aec347ab | 285 | |
b2cff0db CW |
286 | if (--retry_count == 0) { |
287 | DRM_ERROR("Timed out waiting for forcewake timers to finish\n"); | |
288 | break; | |
289 | } | |
0294ae7b | 290 | |
b2cff0db CW |
291 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
292 | cond_resched(); | |
293 | } | |
0294ae7b | 294 | |
b2cff0db CW |
295 | WARN_ON(active_domains); |
296 | ||
297 | for_each_fw_domain(domain, dev_priv, id) | |
298 | if (domain->wake_count) | |
299 | fw |= 1 << id; | |
300 | ||
301 | if (fw) | |
302 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fw); | |
ef46e0d2 | 303 | |
05a2fb15 | 304 | fw_domains_reset(dev_priv, FORCEWAKE_ALL); |
38cff0b1 | 305 | |
0294ae7b | 306 | if (restore) { /* If reset with a user forcewake, try to restore */ |
0294ae7b CW |
307 | if (fw) |
308 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); | |
309 | ||
310 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
311 | dev_priv->uncore.fifo_count = | |
c32e3788 | 312 | fifo_free_entries(dev_priv); |
0294ae7b CW |
313 | } |
314 | ||
b2cff0db | 315 | if (!restore) |
59bad947 | 316 | assert_forcewakes_inactive(dev_priv); |
b2cff0db | 317 | |
0294ae7b | 318 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
ef46e0d2 DV |
319 | } |
320 | ||
f9b3927a | 321 | static void intel_uncore_ellc_detect(struct drm_device *dev) |
907b28c5 CW |
322 | { |
323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
324 | ||
e25dca86 DL |
325 | if ((IS_HASWELL(dev) || IS_BROADWELL(dev) || |
326 | INTEL_INFO(dev)->gen >= 9) && | |
2db59d53 | 327 | (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) { |
18ce3994 BW |
328 | /* The docs do not explain exactly how the calculation can be |
329 | * made. It is somewhat guessable, but for now, it's always | |
330 | * 128MB. | |
331 | * NB: We can't write IDICR yet because we do not have gt funcs | |
332 | * set up */ | |
333 | dev_priv->ellc_size = 128; | |
334 | DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); | |
335 | } | |
f9b3927a MK |
336 | } |
337 | ||
8a47eb19 | 338 | static bool |
8ac3e1bb | 339 | fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) |
8a47eb19 MK |
340 | { |
341 | u32 dbg; | |
342 | ||
8a47eb19 MK |
343 | dbg = __raw_i915_read32(dev_priv, FPGA_DBG); |
344 | if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) | |
345 | return false; | |
346 | ||
347 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); | |
348 | ||
349 | return true; | |
350 | } | |
351 | ||
8ac3e1bb MK |
352 | static bool |
353 | vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) | |
354 | { | |
355 | u32 cer; | |
356 | ||
357 | cer = __raw_i915_read32(dev_priv, CLAIM_ER); | |
358 | if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK)))) | |
359 | return false; | |
360 | ||
361 | __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR); | |
362 | ||
363 | return true; | |
364 | } | |
365 | ||
366 | static bool | |
367 | check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) | |
368 | { | |
369 | if (HAS_FPGA_DBG_UNCLAIMED(dev_priv)) | |
370 | return fpga_check_for_unclaimed_mmio(dev_priv); | |
371 | ||
372 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
373 | return vlv_check_for_unclaimed_mmio(dev_priv); | |
374 | ||
375 | return false; | |
376 | } | |
377 | ||
f9b3927a MK |
378 | static void __intel_uncore_early_sanitize(struct drm_device *dev, |
379 | bool restore_forcewake) | |
380 | { | |
381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
382 | ||
8a47eb19 MK |
383 | /* clear out unclaimed reg detection bit */ |
384 | if (check_for_unclaimed_mmio(dev_priv)) | |
385 | DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n"); | |
907b28c5 | 386 | |
97058870 VS |
387 | /* clear out old GT FIFO errors */ |
388 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
389 | __raw_i915_write32(dev_priv, GTFIFODBG, | |
390 | __raw_i915_read32(dev_priv, GTFIFODBG)); | |
391 | ||
a04f90a3 D |
392 | /* WaDisableShadowRegForCpd:chv */ |
393 | if (IS_CHERRYVIEW(dev)) { | |
394 | __raw_i915_write32(dev_priv, GTFIFOCTL, | |
395 | __raw_i915_read32(dev_priv, GTFIFOCTL) | | |
396 | GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | | |
397 | GT_FIFO_CTL_RC6_POLICY_STALL); | |
398 | } | |
399 | ||
10018603 | 400 | intel_uncore_forcewake_reset(dev, restore_forcewake); |
521198a2 MK |
401 | } |
402 | ||
ed493883 ID |
403 | void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake) |
404 | { | |
405 | __intel_uncore_early_sanitize(dev, restore_forcewake); | |
406 | i915_check_and_clear_faults(dev); | |
407 | } | |
408 | ||
521198a2 MK |
409 | void intel_uncore_sanitize(struct drm_device *dev) |
410 | { | |
274008e8 SAK |
411 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); |
412 | ||
907b28c5 CW |
413 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
414 | intel_disable_gt_powersave(dev); | |
415 | } | |
416 | ||
a6111f7b CW |
417 | static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
418 | enum forcewake_domains fw_domains) | |
419 | { | |
420 | struct intel_uncore_forcewake_domain *domain; | |
421 | enum forcewake_domain_id id; | |
422 | ||
423 | if (!dev_priv->uncore.funcs.force_wake_get) | |
424 | return; | |
425 | ||
426 | fw_domains &= dev_priv->uncore.fw_domains; | |
427 | ||
428 | for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { | |
429 | if (domain->wake_count++) | |
430 | fw_domains &= ~(1 << id); | |
431 | } | |
432 | ||
433 | if (fw_domains) | |
434 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); | |
435 | } | |
436 | ||
59bad947 MK |
437 | /** |
438 | * intel_uncore_forcewake_get - grab forcewake domain references | |
439 | * @dev_priv: i915 device instance | |
440 | * @fw_domains: forcewake domains to get reference on | |
441 | * | |
442 | * This function can be used get GT's forcewake domain references. | |
443 | * Normal register access will handle the forcewake domains automatically. | |
444 | * However if some sequence requires the GT to not power down a particular | |
445 | * forcewake domains this function should be called at the beginning of the | |
446 | * sequence. And subsequently the reference should be dropped by symmetric | |
447 | * call to intel_unforce_forcewake_put(). Usually caller wants all the domains | |
448 | * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. | |
907b28c5 | 449 | */ |
59bad947 | 450 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 451 | enum forcewake_domains fw_domains) |
907b28c5 CW |
452 | { |
453 | unsigned long irqflags; | |
454 | ||
ab484f8f BW |
455 | if (!dev_priv->uncore.funcs.force_wake_get) |
456 | return; | |
457 | ||
c9b8846a | 458 | assert_rpm_wakelock_held(dev_priv); |
c8c8fb33 | 459 | |
6daccb0b | 460 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
a6111f7b | 461 | __intel_uncore_forcewake_get(dev_priv, fw_domains); |
907b28c5 CW |
462 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
463 | } | |
464 | ||
59bad947 | 465 | /** |
a6111f7b | 466 | * intel_uncore_forcewake_get__locked - grab forcewake domain references |
59bad947 | 467 | * @dev_priv: i915 device instance |
a6111f7b | 468 | * @fw_domains: forcewake domains to get reference on |
59bad947 | 469 | * |
a6111f7b CW |
470 | * See intel_uncore_forcewake_get(). This variant places the onus |
471 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
907b28c5 | 472 | */ |
a6111f7b CW |
473 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, |
474 | enum forcewake_domains fw_domains) | |
475 | { | |
476 | assert_spin_locked(&dev_priv->uncore.lock); | |
477 | ||
478 | if (!dev_priv->uncore.funcs.force_wake_get) | |
479 | return; | |
480 | ||
481 | __intel_uncore_forcewake_get(dev_priv, fw_domains); | |
482 | } | |
483 | ||
484 | static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, | |
485 | enum forcewake_domains fw_domains) | |
907b28c5 | 486 | { |
b2cff0db | 487 | struct intel_uncore_forcewake_domain *domain; |
48c1026a | 488 | enum forcewake_domain_id id; |
907b28c5 | 489 | |
ab484f8f BW |
490 | if (!dev_priv->uncore.funcs.force_wake_put) |
491 | return; | |
492 | ||
b2cff0db CW |
493 | fw_domains &= dev_priv->uncore.fw_domains; |
494 | ||
b2cff0db CW |
495 | for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { |
496 | if (WARN_ON(domain->wake_count == 0)) | |
497 | continue; | |
498 | ||
499 | if (--domain->wake_count) | |
500 | continue; | |
501 | ||
05a2fb15 | 502 | fw_domain_arm_timer(domain); |
aec347ab | 503 | } |
a6111f7b | 504 | } |
dc9fb09c | 505 | |
a6111f7b CW |
506 | /** |
507 | * intel_uncore_forcewake_put - release a forcewake domain reference | |
508 | * @dev_priv: i915 device instance | |
509 | * @fw_domains: forcewake domains to put references | |
510 | * | |
511 | * This function drops the device-level forcewakes for specified | |
512 | * domains obtained by intel_uncore_forcewake_get(). | |
513 | */ | |
514 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, | |
515 | enum forcewake_domains fw_domains) | |
516 | { | |
517 | unsigned long irqflags; | |
518 | ||
519 | if (!dev_priv->uncore.funcs.force_wake_put) | |
520 | return; | |
521 | ||
522 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
523 | __intel_uncore_forcewake_put(dev_priv, fw_domains); | |
907b28c5 CW |
524 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
525 | } | |
526 | ||
a6111f7b CW |
527 | /** |
528 | * intel_uncore_forcewake_put__locked - grab forcewake domain references | |
529 | * @dev_priv: i915 device instance | |
530 | * @fw_domains: forcewake domains to get reference on | |
531 | * | |
532 | * See intel_uncore_forcewake_put(). This variant places the onus | |
533 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
534 | */ | |
535 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
536 | enum forcewake_domains fw_domains) | |
537 | { | |
538 | assert_spin_locked(&dev_priv->uncore.lock); | |
539 | ||
540 | if (!dev_priv->uncore.funcs.force_wake_put) | |
541 | return; | |
542 | ||
543 | __intel_uncore_forcewake_put(dev_priv, fw_domains); | |
544 | } | |
545 | ||
59bad947 | 546 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv) |
e998c40f | 547 | { |
b2cff0db | 548 | struct intel_uncore_forcewake_domain *domain; |
48c1026a | 549 | enum forcewake_domain_id id; |
b2cff0db | 550 | |
e998c40f PZ |
551 | if (!dev_priv->uncore.funcs.force_wake_get) |
552 | return; | |
553 | ||
05a2fb15 | 554 | for_each_fw_domain(domain, dev_priv, id) |
b2cff0db | 555 | WARN_ON(domain->wake_count); |
e998c40f PZ |
556 | } |
557 | ||
907b28c5 | 558 | /* We give fast paths for the really cool registers */ |
40181697 | 559 | #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000) |
907b28c5 | 560 | |
1938e59a | 561 | #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end)) |
38fb6a40 | 562 | |
1938e59a D |
563 | #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ |
564 | (REG_RANGE((reg), 0x2000, 0x4000) || \ | |
565 | REG_RANGE((reg), 0x5000, 0x8000) || \ | |
566 | REG_RANGE((reg), 0xB000, 0x12000) || \ | |
567 | REG_RANGE((reg), 0x2E000, 0x30000)) | |
568 | ||
569 | #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \ | |
570 | (REG_RANGE((reg), 0x12000, 0x14000) || \ | |
571 | REG_RANGE((reg), 0x22000, 0x24000) || \ | |
572 | REG_RANGE((reg), 0x30000, 0x40000)) | |
573 | ||
574 | #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \ | |
575 | (REG_RANGE((reg), 0x2000, 0x4000) || \ | |
db5ff4ac | 576 | REG_RANGE((reg), 0x5200, 0x8000) || \ |
1938e59a | 577 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
db5ff4ac | 578 | REG_RANGE((reg), 0xB000, 0xB480) || \ |
1938e59a D |
579 | REG_RANGE((reg), 0xE000, 0xE800)) |
580 | ||
581 | #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \ | |
582 | (REG_RANGE((reg), 0x8800, 0x8900) || \ | |
583 | REG_RANGE((reg), 0xD000, 0xD800) || \ | |
584 | REG_RANGE((reg), 0x12000, 0x14000) || \ | |
585 | REG_RANGE((reg), 0x1A000, 0x1C000) || \ | |
586 | REG_RANGE((reg), 0x1E800, 0x1EA00) || \ | |
db5ff4ac | 587 | REG_RANGE((reg), 0x30000, 0x38000)) |
1938e59a D |
588 | |
589 | #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \ | |
590 | (REG_RANGE((reg), 0x4000, 0x5000) || \ | |
591 | REG_RANGE((reg), 0x8000, 0x8300) || \ | |
592 | REG_RANGE((reg), 0x8500, 0x8600) || \ | |
593 | REG_RANGE((reg), 0x9000, 0xB000) || \ | |
db5ff4ac | 594 | REG_RANGE((reg), 0xF000, 0x10000)) |
38fb6a40 | 595 | |
4597a88a | 596 | #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \ |
8ee558d8 | 597 | REG_RANGE((reg), 0xB00, 0x2000) |
4597a88a ZW |
598 | |
599 | #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \ | |
8ee558d8 AG |
600 | (REG_RANGE((reg), 0x2000, 0x2700) || \ |
601 | REG_RANGE((reg), 0x3000, 0x4000) || \ | |
4597a88a | 602 | REG_RANGE((reg), 0x5200, 0x8000) || \ |
8ee558d8 | 603 | REG_RANGE((reg), 0x8140, 0x8160) || \ |
4597a88a ZW |
604 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
605 | REG_RANGE((reg), 0x8C00, 0x8D00) || \ | |
606 | REG_RANGE((reg), 0xB000, 0xB480) || \ | |
8ee558d8 AG |
607 | REG_RANGE((reg), 0xE000, 0xE900) || \ |
608 | REG_RANGE((reg), 0x24400, 0x24800)) | |
4597a88a ZW |
609 | |
610 | #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \ | |
8ee558d8 AG |
611 | (REG_RANGE((reg), 0x8130, 0x8140) || \ |
612 | REG_RANGE((reg), 0x8800, 0x8A00) || \ | |
4597a88a ZW |
613 | REG_RANGE((reg), 0xD000, 0xD800) || \ |
614 | REG_RANGE((reg), 0x12000, 0x14000) || \ | |
615 | REG_RANGE((reg), 0x1A000, 0x1EA00) || \ | |
616 | REG_RANGE((reg), 0x30000, 0x40000)) | |
617 | ||
618 | #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \ | |
619 | REG_RANGE((reg), 0x9400, 0x9800) | |
620 | ||
621 | #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \ | |
0c8bfe52 | 622 | ((reg) < 0x40000 && \ |
4597a88a ZW |
623 | !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \ |
624 | !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \ | |
625 | !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \ | |
626 | !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) | |
627 | ||
907b28c5 CW |
628 | static void |
629 | ilk_dummy_write(struct drm_i915_private *dev_priv) | |
630 | { | |
631 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up | |
632 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
633 | * hence harmless to write 0 into. */ | |
6af5d92f | 634 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
907b28c5 CW |
635 | } |
636 | ||
637 | static void | |
9c053501 MK |
638 | __unclaimed_reg_debug(struct drm_i915_private *dev_priv, |
639 | const i915_reg_t reg, | |
640 | const bool read, | |
641 | const bool before) | |
907b28c5 | 642 | { |
c81eeea6 MK |
643 | /* XXX. We limit the auto arming traces for mmio |
644 | * debugs on these platforms. There are just too many | |
645 | * revealed by these and CI/Bat suffers from the noise. | |
646 | * Please fix and then re-enable the automatic traces. | |
647 | */ | |
648 | if (i915.mmio_debug < 2 && | |
649 | (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) | |
650 | return; | |
651 | ||
4bd0a25d MK |
652 | if (WARN(check_for_unclaimed_mmio(dev_priv), |
653 | "Unclaimed register detected %s %s register 0x%x\n", | |
654 | before ? "before" : "after", | |
655 | read ? "reading" : "writing to", | |
656 | i915_mmio_reg_offset(reg))) | |
48572edd | 657 | i915.mmio_debug--; /* Only report the first N failures */ |
907b28c5 CW |
658 | } |
659 | ||
9c053501 MK |
660 | static inline void |
661 | unclaimed_reg_debug(struct drm_i915_private *dev_priv, | |
662 | const i915_reg_t reg, | |
663 | const bool read, | |
664 | const bool before) | |
665 | { | |
666 | if (likely(!i915.mmio_debug)) | |
667 | return; | |
668 | ||
669 | __unclaimed_reg_debug(dev_priv, reg, read, before); | |
670 | } | |
671 | ||
51f67885 | 672 | #define GEN2_READ_HEADER(x) \ |
5d738795 | 673 | u##x val = 0; \ |
da5827c3 | 674 | assert_rpm_wakelock_held(dev_priv); |
5d738795 | 675 | |
51f67885 | 676 | #define GEN2_READ_FOOTER \ |
5d738795 BW |
677 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
678 | return val | |
679 | ||
51f67885 | 680 | #define __gen2_read(x) \ |
0b274481 | 681 | static u##x \ |
f0f59a00 | 682 | gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
51f67885 | 683 | GEN2_READ_HEADER(x); \ |
3967018e | 684 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 685 | GEN2_READ_FOOTER; \ |
3967018e BW |
686 | } |
687 | ||
688 | #define __gen5_read(x) \ | |
689 | static u##x \ | |
f0f59a00 | 690 | gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
51f67885 | 691 | GEN2_READ_HEADER(x); \ |
3967018e BW |
692 | ilk_dummy_write(dev_priv); \ |
693 | val = __raw_i915_read##x(dev_priv, reg); \ | |
51f67885 | 694 | GEN2_READ_FOOTER; \ |
3967018e BW |
695 | } |
696 | ||
51f67885 CW |
697 | __gen5_read(8) |
698 | __gen5_read(16) | |
699 | __gen5_read(32) | |
700 | __gen5_read(64) | |
701 | __gen2_read(8) | |
702 | __gen2_read(16) | |
703 | __gen2_read(32) | |
704 | __gen2_read(64) | |
705 | ||
706 | #undef __gen5_read | |
707 | #undef __gen2_read | |
708 | ||
709 | #undef GEN2_READ_FOOTER | |
710 | #undef GEN2_READ_HEADER | |
711 | ||
712 | #define GEN6_READ_HEADER(x) \ | |
f0f59a00 | 713 | u32 offset = i915_mmio_reg_offset(reg); \ |
51f67885 CW |
714 | unsigned long irqflags; \ |
715 | u##x val = 0; \ | |
da5827c3 | 716 | assert_rpm_wakelock_held(dev_priv); \ |
9c053501 MK |
717 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ |
718 | unclaimed_reg_debug(dev_priv, reg, true, true) | |
51f67885 CW |
719 | |
720 | #define GEN6_READ_FOOTER \ | |
9c053501 | 721 | unclaimed_reg_debug(dev_priv, reg, true, false); \ |
51f67885 CW |
722 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
723 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ | |
724 | return val | |
725 | ||
b208ba8e CW |
726 | static inline void __force_wake_auto(struct drm_i915_private *dev_priv, |
727 | enum forcewake_domains fw_domains) | |
b2cff0db CW |
728 | { |
729 | struct intel_uncore_forcewake_domain *domain; | |
48c1026a | 730 | enum forcewake_domain_id id; |
b2cff0db CW |
731 | |
732 | if (WARN_ON(!fw_domains)) | |
733 | return; | |
734 | ||
735 | /* Ideally GCC would be constant-fold and eliminate this loop */ | |
05a2fb15 | 736 | for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { |
b2cff0db | 737 | if (domain->wake_count) { |
05a2fb15 | 738 | fw_domains &= ~(1 << id); |
b2cff0db CW |
739 | continue; |
740 | } | |
741 | ||
05a2fb15 | 742 | fw_domain_arm_timer(domain); |
b2cff0db CW |
743 | } |
744 | ||
745 | if (fw_domains) | |
746 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); | |
747 | } | |
748 | ||
3967018e BW |
749 | #define __gen6_read(x) \ |
750 | static u##x \ | |
f0f59a00 | 751 | gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
51f67885 | 752 | GEN6_READ_HEADER(x); \ |
0670c5a6 | 753 | if (NEEDS_FORCE_WAKE(offset)) \ |
b208ba8e | 754 | __force_wake_auto(dev_priv, FORCEWAKE_RENDER); \ |
dc9fb09c | 755 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 756 | GEN6_READ_FOOTER; \ |
907b28c5 CW |
757 | } |
758 | ||
940aece4 D |
759 | #define __vlv_read(x) \ |
760 | static u##x \ | |
f0f59a00 | 761 | vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
6a42d0f4 | 762 | enum forcewake_domains fw_engine = 0; \ |
51f67885 | 763 | GEN6_READ_HEADER(x); \ |
0670c5a6 | 764 | if (!NEEDS_FORCE_WAKE(offset)) \ |
e97d8fbe | 765 | fw_engine = 0; \ |
0670c5a6 | 766 | else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \ |
6a42d0f4 | 767 | fw_engine = FORCEWAKE_RENDER; \ |
0670c5a6 | 768 | else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \ |
6a42d0f4 VS |
769 | fw_engine = FORCEWAKE_MEDIA; \ |
770 | if (fw_engine) \ | |
b208ba8e | 771 | __force_wake_auto(dev_priv, fw_engine); \ |
6fe72865 | 772 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 773 | GEN6_READ_FOOTER; \ |
940aece4 D |
774 | } |
775 | ||
1938e59a D |
776 | #define __chv_read(x) \ |
777 | static u##x \ | |
f0f59a00 | 778 | chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
6a42d0f4 | 779 | enum forcewake_domains fw_engine = 0; \ |
51f67885 | 780 | GEN6_READ_HEADER(x); \ |
0670c5a6 | 781 | if (!NEEDS_FORCE_WAKE(offset)) \ |
e97d8fbe | 782 | fw_engine = 0; \ |
0670c5a6 | 783 | else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \ |
6a42d0f4 | 784 | fw_engine = FORCEWAKE_RENDER; \ |
0670c5a6 | 785 | else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \ |
6a42d0f4 | 786 | fw_engine = FORCEWAKE_MEDIA; \ |
0670c5a6 | 787 | else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \ |
6a42d0f4 VS |
788 | fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ |
789 | if (fw_engine) \ | |
b208ba8e | 790 | __force_wake_auto(dev_priv, fw_engine); \ |
1938e59a | 791 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 792 | GEN6_READ_FOOTER; \ |
1938e59a | 793 | } |
940aece4 | 794 | |
ded17493 | 795 | #define SKL_NEEDS_FORCE_WAKE(reg) \ |
0c8bfe52 | 796 | ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg)) |
4597a88a ZW |
797 | |
798 | #define __gen9_read(x) \ | |
799 | static u##x \ | |
f0f59a00 | 800 | gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
48c1026a | 801 | enum forcewake_domains fw_engine; \ |
51f67885 | 802 | GEN6_READ_HEADER(x); \ |
0670c5a6 | 803 | if (!SKL_NEEDS_FORCE_WAKE(offset)) \ |
b2cff0db | 804 | fw_engine = 0; \ |
0670c5a6 | 805 | else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \ |
b2cff0db | 806 | fw_engine = FORCEWAKE_RENDER; \ |
0670c5a6 | 807 | else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \ |
b2cff0db | 808 | fw_engine = FORCEWAKE_MEDIA; \ |
0670c5a6 | 809 | else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \ |
b2cff0db CW |
810 | fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ |
811 | else \ | |
812 | fw_engine = FORCEWAKE_BLITTER; \ | |
813 | if (fw_engine) \ | |
b208ba8e | 814 | __force_wake_auto(dev_priv, fw_engine); \ |
b2cff0db | 815 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 816 | GEN6_READ_FOOTER; \ |
4597a88a ZW |
817 | } |
818 | ||
819 | __gen9_read(8) | |
820 | __gen9_read(16) | |
821 | __gen9_read(32) | |
822 | __gen9_read(64) | |
1938e59a D |
823 | __chv_read(8) |
824 | __chv_read(16) | |
825 | __chv_read(32) | |
826 | __chv_read(64) | |
940aece4 D |
827 | __vlv_read(8) |
828 | __vlv_read(16) | |
829 | __vlv_read(32) | |
830 | __vlv_read(64) | |
3967018e BW |
831 | __gen6_read(8) |
832 | __gen6_read(16) | |
833 | __gen6_read(32) | |
834 | __gen6_read(64) | |
3967018e | 835 | |
4597a88a | 836 | #undef __gen9_read |
1938e59a | 837 | #undef __chv_read |
940aece4 | 838 | #undef __vlv_read |
3967018e | 839 | #undef __gen6_read |
51f67885 CW |
840 | #undef GEN6_READ_FOOTER |
841 | #undef GEN6_READ_HEADER | |
5d738795 | 842 | |
8a74db7a VS |
843 | #define VGPU_READ_HEADER(x) \ |
844 | unsigned long irqflags; \ | |
845 | u##x val = 0; \ | |
da5827c3 | 846 | assert_rpm_device_not_suspended(dev_priv); \ |
8a74db7a VS |
847 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
848 | ||
849 | #define VGPU_READ_FOOTER \ | |
850 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
851 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ | |
852 | return val | |
853 | ||
854 | #define __vgpu_read(x) \ | |
855 | static u##x \ | |
f0f59a00 | 856 | vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
8a74db7a VS |
857 | VGPU_READ_HEADER(x); \ |
858 | val = __raw_i915_read##x(dev_priv, reg); \ | |
859 | VGPU_READ_FOOTER; \ | |
860 | } | |
861 | ||
862 | __vgpu_read(8) | |
863 | __vgpu_read(16) | |
864 | __vgpu_read(32) | |
865 | __vgpu_read(64) | |
866 | ||
867 | #undef __vgpu_read | |
868 | #undef VGPU_READ_FOOTER | |
869 | #undef VGPU_READ_HEADER | |
870 | ||
51f67885 | 871 | #define GEN2_WRITE_HEADER \ |
5d738795 | 872 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
da5827c3 | 873 | assert_rpm_wakelock_held(dev_priv); \ |
907b28c5 | 874 | |
51f67885 | 875 | #define GEN2_WRITE_FOOTER |
0d965301 | 876 | |
51f67885 | 877 | #define __gen2_write(x) \ |
0b274481 | 878 | static void \ |
f0f59a00 | 879 | gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 880 | GEN2_WRITE_HEADER; \ |
4032ef43 | 881 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 882 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
883 | } |
884 | ||
885 | #define __gen5_write(x) \ | |
886 | static void \ | |
f0f59a00 | 887 | gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 888 | GEN2_WRITE_HEADER; \ |
4032ef43 BW |
889 | ilk_dummy_write(dev_priv); \ |
890 | __raw_i915_write##x(dev_priv, reg, val); \ | |
51f67885 | 891 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
892 | } |
893 | ||
51f67885 CW |
894 | __gen5_write(8) |
895 | __gen5_write(16) | |
896 | __gen5_write(32) | |
897 | __gen5_write(64) | |
898 | __gen2_write(8) | |
899 | __gen2_write(16) | |
900 | __gen2_write(32) | |
901 | __gen2_write(64) | |
902 | ||
903 | #undef __gen5_write | |
904 | #undef __gen2_write | |
905 | ||
906 | #undef GEN2_WRITE_FOOTER | |
907 | #undef GEN2_WRITE_HEADER | |
908 | ||
909 | #define GEN6_WRITE_HEADER \ | |
f0f59a00 | 910 | u32 offset = i915_mmio_reg_offset(reg); \ |
51f67885 CW |
911 | unsigned long irqflags; \ |
912 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
da5827c3 | 913 | assert_rpm_wakelock_held(dev_priv); \ |
9c053501 MK |
914 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ |
915 | unclaimed_reg_debug(dev_priv, reg, false, true) | |
51f67885 CW |
916 | |
917 | #define GEN6_WRITE_FOOTER \ | |
9c053501 | 918 | unclaimed_reg_debug(dev_priv, reg, false, false); \ |
51f67885 CW |
919 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) |
920 | ||
4032ef43 BW |
921 | #define __gen6_write(x) \ |
922 | static void \ | |
f0f59a00 | 923 | gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
4032ef43 | 924 | u32 __fifo_ret = 0; \ |
51f67885 | 925 | GEN6_WRITE_HEADER; \ |
0670c5a6 | 926 | if (NEEDS_FORCE_WAKE(offset)) { \ |
4032ef43 BW |
927 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
928 | } \ | |
929 | __raw_i915_write##x(dev_priv, reg, val); \ | |
930 | if (unlikely(__fifo_ret)) { \ | |
931 | gen6_gt_check_fifodbg(dev_priv); \ | |
932 | } \ | |
51f67885 | 933 | GEN6_WRITE_FOOTER; \ |
4032ef43 BW |
934 | } |
935 | ||
936 | #define __hsw_write(x) \ | |
937 | static void \ | |
f0f59a00 | 938 | hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
907b28c5 | 939 | u32 __fifo_ret = 0; \ |
51f67885 | 940 | GEN6_WRITE_HEADER; \ |
0670c5a6 | 941 | if (NEEDS_FORCE_WAKE(offset)) { \ |
907b28c5 CW |
942 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
943 | } \ | |
6af5d92f | 944 | __raw_i915_write##x(dev_priv, reg, val); \ |
907b28c5 CW |
945 | if (unlikely(__fifo_ret)) { \ |
946 | gen6_gt_check_fifodbg(dev_priv); \ | |
947 | } \ | |
51f67885 | 948 | GEN6_WRITE_FOOTER; \ |
907b28c5 | 949 | } |
3967018e | 950 | |
f0f59a00 | 951 | static const i915_reg_t gen8_shadowed_regs[] = { |
ab2aa47e BW |
952 | FORCEWAKE_MT, |
953 | GEN6_RPNSWREQ, | |
954 | GEN6_RC_VIDEO_FREQ, | |
955 | RING_TAIL(RENDER_RING_BASE), | |
956 | RING_TAIL(GEN6_BSD_RING_BASE), | |
957 | RING_TAIL(VEBOX_RING_BASE), | |
958 | RING_TAIL(BLT_RING_BASE), | |
959 | /* TODO: Other registers are not yet used */ | |
960 | }; | |
961 | ||
f0f59a00 VS |
962 | static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, |
963 | i915_reg_t reg) | |
ab2aa47e BW |
964 | { |
965 | int i; | |
966 | for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) | |
f0f59a00 | 967 | if (i915_mmio_reg_equal(reg, gen8_shadowed_regs[i])) |
ab2aa47e BW |
968 | return true; |
969 | ||
970 | return false; | |
971 | } | |
972 | ||
973 | #define __gen8_write(x) \ | |
974 | static void \ | |
f0f59a00 | 975 | gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 976 | GEN6_WRITE_HEADER; \ |
0670c5a6 | 977 | if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(dev_priv, reg)) \ |
b208ba8e | 978 | __force_wake_auto(dev_priv, FORCEWAKE_RENDER); \ |
b2cff0db | 979 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 980 | GEN6_WRITE_FOOTER; \ |
ab2aa47e BW |
981 | } |
982 | ||
1938e59a D |
983 | #define __chv_write(x) \ |
984 | static void \ | |
f0f59a00 | 985 | chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
6a42d0f4 | 986 | enum forcewake_domains fw_engine = 0; \ |
51f67885 | 987 | GEN6_WRITE_HEADER; \ |
0670c5a6 | 988 | if (!NEEDS_FORCE_WAKE(offset) || \ |
e97d8fbe | 989 | is_gen8_shadowed(dev_priv, reg)) \ |
6a42d0f4 | 990 | fw_engine = 0; \ |
0670c5a6 | 991 | else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \ |
6a42d0f4 | 992 | fw_engine = FORCEWAKE_RENDER; \ |
0670c5a6 | 993 | else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \ |
6a42d0f4 | 994 | fw_engine = FORCEWAKE_MEDIA; \ |
0670c5a6 | 995 | else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \ |
6a42d0f4 VS |
996 | fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ |
997 | if (fw_engine) \ | |
b208ba8e | 998 | __force_wake_auto(dev_priv, fw_engine); \ |
1938e59a | 999 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 1000 | GEN6_WRITE_FOOTER; \ |
1938e59a D |
1001 | } |
1002 | ||
f0f59a00 | 1003 | static const i915_reg_t gen9_shadowed_regs[] = { |
7c859007 ZW |
1004 | RING_TAIL(RENDER_RING_BASE), |
1005 | RING_TAIL(GEN6_BSD_RING_BASE), | |
1006 | RING_TAIL(VEBOX_RING_BASE), | |
1007 | RING_TAIL(BLT_RING_BASE), | |
1008 | FORCEWAKE_BLITTER_GEN9, | |
1009 | FORCEWAKE_RENDER_GEN9, | |
1010 | FORCEWAKE_MEDIA_GEN9, | |
1011 | GEN6_RPNSWREQ, | |
1012 | GEN6_RC_VIDEO_FREQ, | |
1013 | /* TODO: Other registers are not yet used */ | |
1014 | }; | |
1015 | ||
f0f59a00 VS |
1016 | static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, |
1017 | i915_reg_t reg) | |
7c859007 ZW |
1018 | { |
1019 | int i; | |
1020 | for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++) | |
f0f59a00 | 1021 | if (i915_mmio_reg_equal(reg, gen9_shadowed_regs[i])) |
7c859007 ZW |
1022 | return true; |
1023 | ||
1024 | return false; | |
1025 | } | |
1026 | ||
4597a88a ZW |
1027 | #define __gen9_write(x) \ |
1028 | static void \ | |
f0f59a00 | 1029 | gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \ |
4597a88a | 1030 | bool trace) { \ |
48c1026a | 1031 | enum forcewake_domains fw_engine; \ |
51f67885 | 1032 | GEN6_WRITE_HEADER; \ |
0670c5a6 | 1033 | if (!SKL_NEEDS_FORCE_WAKE(offset) || \ |
b2cff0db CW |
1034 | is_gen9_shadowed(dev_priv, reg)) \ |
1035 | fw_engine = 0; \ | |
0670c5a6 | 1036 | else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \ |
b2cff0db | 1037 | fw_engine = FORCEWAKE_RENDER; \ |
0670c5a6 | 1038 | else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \ |
b2cff0db | 1039 | fw_engine = FORCEWAKE_MEDIA; \ |
0670c5a6 | 1040 | else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \ |
b2cff0db CW |
1041 | fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ |
1042 | else \ | |
1043 | fw_engine = FORCEWAKE_BLITTER; \ | |
1044 | if (fw_engine) \ | |
b208ba8e | 1045 | __force_wake_auto(dev_priv, fw_engine); \ |
b2cff0db | 1046 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 1047 | GEN6_WRITE_FOOTER; \ |
4597a88a ZW |
1048 | } |
1049 | ||
1050 | __gen9_write(8) | |
1051 | __gen9_write(16) | |
1052 | __gen9_write(32) | |
1053 | __gen9_write(64) | |
1938e59a D |
1054 | __chv_write(8) |
1055 | __chv_write(16) | |
1056 | __chv_write(32) | |
1057 | __chv_write(64) | |
ab2aa47e BW |
1058 | __gen8_write(8) |
1059 | __gen8_write(16) | |
1060 | __gen8_write(32) | |
1061 | __gen8_write(64) | |
4032ef43 BW |
1062 | __hsw_write(8) |
1063 | __hsw_write(16) | |
1064 | __hsw_write(32) | |
1065 | __hsw_write(64) | |
1066 | __gen6_write(8) | |
1067 | __gen6_write(16) | |
1068 | __gen6_write(32) | |
1069 | __gen6_write(64) | |
4032ef43 | 1070 | |
4597a88a | 1071 | #undef __gen9_write |
1938e59a | 1072 | #undef __chv_write |
ab2aa47e | 1073 | #undef __gen8_write |
4032ef43 BW |
1074 | #undef __hsw_write |
1075 | #undef __gen6_write | |
51f67885 CW |
1076 | #undef GEN6_WRITE_FOOTER |
1077 | #undef GEN6_WRITE_HEADER | |
907b28c5 | 1078 | |
8a74db7a VS |
1079 | #define VGPU_WRITE_HEADER \ |
1080 | unsigned long irqflags; \ | |
1081 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
da5827c3 | 1082 | assert_rpm_device_not_suspended(dev_priv); \ |
8a74db7a VS |
1083 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
1084 | ||
1085 | #define VGPU_WRITE_FOOTER \ | |
1086 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) | |
1087 | ||
1088 | #define __vgpu_write(x) \ | |
1089 | static void vgpu_write##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 1090 | i915_reg_t reg, u##x val, bool trace) { \ |
8a74db7a VS |
1091 | VGPU_WRITE_HEADER; \ |
1092 | __raw_i915_write##x(dev_priv, reg, val); \ | |
1093 | VGPU_WRITE_FOOTER; \ | |
1094 | } | |
1095 | ||
1096 | __vgpu_write(8) | |
1097 | __vgpu_write(16) | |
1098 | __vgpu_write(32) | |
1099 | __vgpu_write(64) | |
1100 | ||
1101 | #undef __vgpu_write | |
1102 | #undef VGPU_WRITE_FOOTER | |
1103 | #undef VGPU_WRITE_HEADER | |
1104 | ||
43d942a7 YZ |
1105 | #define ASSIGN_WRITE_MMIO_VFUNCS(x) \ |
1106 | do { \ | |
1107 | dev_priv->uncore.funcs.mmio_writeb = x##_write8; \ | |
1108 | dev_priv->uncore.funcs.mmio_writew = x##_write16; \ | |
1109 | dev_priv->uncore.funcs.mmio_writel = x##_write32; \ | |
1110 | dev_priv->uncore.funcs.mmio_writeq = x##_write64; \ | |
1111 | } while (0) | |
1112 | ||
1113 | #define ASSIGN_READ_MMIO_VFUNCS(x) \ | |
1114 | do { \ | |
1115 | dev_priv->uncore.funcs.mmio_readb = x##_read8; \ | |
1116 | dev_priv->uncore.funcs.mmio_readw = x##_read16; \ | |
1117 | dev_priv->uncore.funcs.mmio_readl = x##_read32; \ | |
1118 | dev_priv->uncore.funcs.mmio_readq = x##_read64; \ | |
1119 | } while (0) | |
1120 | ||
05a2fb15 MK |
1121 | |
1122 | static void fw_domain_init(struct drm_i915_private *dev_priv, | |
48c1026a | 1123 | enum forcewake_domain_id domain_id, |
f0f59a00 VS |
1124 | i915_reg_t reg_set, |
1125 | i915_reg_t reg_ack) | |
05a2fb15 MK |
1126 | { |
1127 | struct intel_uncore_forcewake_domain *d; | |
1128 | ||
1129 | if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT)) | |
1130 | return; | |
1131 | ||
1132 | d = &dev_priv->uncore.fw_domain[domain_id]; | |
1133 | ||
1134 | WARN_ON(d->wake_count); | |
1135 | ||
1136 | d->wake_count = 0; | |
1137 | d->reg_set = reg_set; | |
1138 | d->reg_ack = reg_ack; | |
1139 | ||
1140 | if (IS_GEN6(dev_priv)) { | |
1141 | d->val_reset = 0; | |
1142 | d->val_set = FORCEWAKE_KERNEL; | |
1143 | d->val_clear = 0; | |
1144 | } else { | |
8543747c | 1145 | /* WaRsClearFWBitsAtReset:bdw,skl */ |
05a2fb15 MK |
1146 | d->val_reset = _MASKED_BIT_DISABLE(0xffff); |
1147 | d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL); | |
1148 | d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL); | |
1149 | } | |
1150 | ||
666a4537 | 1151 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
05a2fb15 MK |
1152 | d->reg_post = FORCEWAKE_ACK_VLV; |
1153 | else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) | |
1154 | d->reg_post = ECOBUS; | |
05a2fb15 MK |
1155 | |
1156 | d->i915 = dev_priv; | |
1157 | d->id = domain_id; | |
1158 | ||
a57a4a67 TU |
1159 | hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); |
1160 | d->timer.function = intel_uncore_fw_release_timer; | |
05a2fb15 MK |
1161 | |
1162 | dev_priv->uncore.fw_domains |= (1 << domain_id); | |
f9b3927a MK |
1163 | |
1164 | fw_domain_reset(d); | |
05a2fb15 MK |
1165 | } |
1166 | ||
f9b3927a | 1167 | static void intel_uncore_fw_domains_init(struct drm_device *dev) |
0b274481 BW |
1168 | { |
1169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b274481 | 1170 | |
2d1fe073 | 1171 | if (INTEL_INFO(dev_priv)->gen <= 5) |
3225b2f9 MK |
1172 | return; |
1173 | ||
38cff0b1 | 1174 | if (IS_GEN9(dev)) { |
05a2fb15 MK |
1175 | dev_priv->uncore.funcs.force_wake_get = fw_domains_get; |
1176 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
1177 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | |
1178 | FORCEWAKE_RENDER_GEN9, | |
1179 | FORCEWAKE_ACK_RENDER_GEN9); | |
1180 | fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER, | |
1181 | FORCEWAKE_BLITTER_GEN9, | |
1182 | FORCEWAKE_ACK_BLITTER_GEN9); | |
1183 | fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, | |
1184 | FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); | |
666a4537 | 1185 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
05a2fb15 | 1186 | dev_priv->uncore.funcs.force_wake_get = fw_domains_get; |
756c349d MK |
1187 | if (!IS_CHERRYVIEW(dev)) |
1188 | dev_priv->uncore.funcs.force_wake_put = | |
1189 | fw_domains_put_with_fifo; | |
1190 | else | |
1191 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
05a2fb15 MK |
1192 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1193 | FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); | |
1194 | fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, | |
1195 | FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); | |
f98cd096 | 1196 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
05a2fb15 MK |
1197 | dev_priv->uncore.funcs.force_wake_get = |
1198 | fw_domains_get_with_thread_status; | |
1199 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
1200 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | |
1201 | FORCEWAKE_MT, FORCEWAKE_ACK_HSW); | |
0b274481 BW |
1202 | } else if (IS_IVYBRIDGE(dev)) { |
1203 | u32 ecobus; | |
1204 | ||
1205 | /* IVB configs may use multi-threaded forcewake */ | |
1206 | ||
1207 | /* A small trick here - if the bios hasn't configured | |
1208 | * MT forcewake, and if the device is in RC6, then | |
1209 | * force_wake_mt_get will not wake the device and the | |
1210 | * ECOBUS read will return zero. Which will be | |
1211 | * (correctly) interpreted by the test below as MT | |
1212 | * forcewake being disabled. | |
1213 | */ | |
05a2fb15 MK |
1214 | dev_priv->uncore.funcs.force_wake_get = |
1215 | fw_domains_get_with_thread_status; | |
1216 | dev_priv->uncore.funcs.force_wake_put = | |
1217 | fw_domains_put_with_fifo; | |
1218 | ||
f9b3927a MK |
1219 | /* We need to init first for ECOBUS access and then |
1220 | * determine later if we want to reinit, in case of MT access is | |
6ea2556f MK |
1221 | * not working. In this stage we don't know which flavour this |
1222 | * ivb is, so it is better to reset also the gen6 fw registers | |
1223 | * before the ecobus check. | |
f9b3927a | 1224 | */ |
6ea2556f MK |
1225 | |
1226 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); | |
1227 | __raw_posting_read(dev_priv, ECOBUS); | |
1228 | ||
05a2fb15 MK |
1229 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1230 | FORCEWAKE_MT, FORCEWAKE_MT_ACK); | |
f9b3927a | 1231 | |
0b274481 | 1232 | mutex_lock(&dev->struct_mutex); |
05a2fb15 | 1233 | fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL); |
0b274481 | 1234 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
05a2fb15 | 1235 | fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL); |
0b274481 BW |
1236 | mutex_unlock(&dev->struct_mutex); |
1237 | ||
05a2fb15 | 1238 | if (!(ecobus & FORCEWAKE_MT_ENABLE)) { |
0b274481 BW |
1239 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); |
1240 | DRM_INFO("when using vblank-synced partial screen updates.\n"); | |
05a2fb15 MK |
1241 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1242 | FORCEWAKE, FORCEWAKE_ACK); | |
0b274481 BW |
1243 | } |
1244 | } else if (IS_GEN6(dev)) { | |
1245 | dev_priv->uncore.funcs.force_wake_get = | |
05a2fb15 | 1246 | fw_domains_get_with_thread_status; |
0b274481 | 1247 | dev_priv->uncore.funcs.force_wake_put = |
05a2fb15 MK |
1248 | fw_domains_put_with_fifo; |
1249 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | |
1250 | FORCEWAKE, FORCEWAKE_ACK); | |
0b274481 | 1251 | } |
3225b2f9 MK |
1252 | |
1253 | /* All future platforms are expected to require complex power gating */ | |
1254 | WARN_ON(dev_priv->uncore.fw_domains == 0); | |
f9b3927a MK |
1255 | } |
1256 | ||
1257 | void intel_uncore_init(struct drm_device *dev) | |
1258 | { | |
1259 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1260 | ||
cf9d2890 YZ |
1261 | i915_check_vgpu(dev); |
1262 | ||
f9b3927a MK |
1263 | intel_uncore_ellc_detect(dev); |
1264 | intel_uncore_fw_domains_init(dev); | |
1265 | __intel_uncore_early_sanitize(dev, false); | |
0b274481 | 1266 | |
75714940 MK |
1267 | dev_priv->uncore.unclaimed_mmio_check = 1; |
1268 | ||
3967018e | 1269 | switch (INTEL_INFO(dev)->gen) { |
ab2aa47e | 1270 | default: |
4597a88a ZW |
1271 | case 9: |
1272 | ASSIGN_WRITE_MMIO_VFUNCS(gen9); | |
1273 | ASSIGN_READ_MMIO_VFUNCS(gen9); | |
1274 | break; | |
1275 | case 8: | |
1938e59a | 1276 | if (IS_CHERRYVIEW(dev)) { |
43d942a7 YZ |
1277 | ASSIGN_WRITE_MMIO_VFUNCS(chv); |
1278 | ASSIGN_READ_MMIO_VFUNCS(chv); | |
1938e59a D |
1279 | |
1280 | } else { | |
43d942a7 YZ |
1281 | ASSIGN_WRITE_MMIO_VFUNCS(gen8); |
1282 | ASSIGN_READ_MMIO_VFUNCS(gen6); | |
1938e59a | 1283 | } |
ab2aa47e | 1284 | break; |
3967018e BW |
1285 | case 7: |
1286 | case 6: | |
4032ef43 | 1287 | if (IS_HASWELL(dev)) { |
43d942a7 | 1288 | ASSIGN_WRITE_MMIO_VFUNCS(hsw); |
4032ef43 | 1289 | } else { |
43d942a7 | 1290 | ASSIGN_WRITE_MMIO_VFUNCS(gen6); |
4032ef43 | 1291 | } |
940aece4 D |
1292 | |
1293 | if (IS_VALLEYVIEW(dev)) { | |
43d942a7 | 1294 | ASSIGN_READ_MMIO_VFUNCS(vlv); |
940aece4 | 1295 | } else { |
43d942a7 | 1296 | ASSIGN_READ_MMIO_VFUNCS(gen6); |
940aece4 | 1297 | } |
3967018e BW |
1298 | break; |
1299 | case 5: | |
43d942a7 YZ |
1300 | ASSIGN_WRITE_MMIO_VFUNCS(gen5); |
1301 | ASSIGN_READ_MMIO_VFUNCS(gen5); | |
3967018e BW |
1302 | break; |
1303 | case 4: | |
1304 | case 3: | |
1305 | case 2: | |
51f67885 CW |
1306 | ASSIGN_WRITE_MMIO_VFUNCS(gen2); |
1307 | ASSIGN_READ_MMIO_VFUNCS(gen2); | |
3967018e BW |
1308 | break; |
1309 | } | |
ed493883 | 1310 | |
3be0bf5a YZ |
1311 | if (intel_vgpu_active(dev)) { |
1312 | ASSIGN_WRITE_MMIO_VFUNCS(vgpu); | |
1313 | ASSIGN_READ_MMIO_VFUNCS(vgpu); | |
1314 | } | |
1315 | ||
ed493883 | 1316 | i915_check_and_clear_faults(dev); |
0b274481 | 1317 | } |
43d942a7 YZ |
1318 | #undef ASSIGN_WRITE_MMIO_VFUNCS |
1319 | #undef ASSIGN_READ_MMIO_VFUNCS | |
0b274481 BW |
1320 | |
1321 | void intel_uncore_fini(struct drm_device *dev) | |
1322 | { | |
0b274481 BW |
1323 | /* Paranoia: make sure we have disabled everything before we exit. */ |
1324 | intel_uncore_sanitize(dev); | |
0294ae7b | 1325 | intel_uncore_forcewake_reset(dev, false); |
0b274481 BW |
1326 | } |
1327 | ||
af76ae44 DL |
1328 | #define GEN_RANGE(l, h) GENMASK(h, l) |
1329 | ||
907b28c5 | 1330 | static const struct register_whitelist { |
f0f59a00 | 1331 | i915_reg_t offset_ldw, offset_udw; |
907b28c5 | 1332 | uint32_t size; |
af76ae44 DL |
1333 | /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
1334 | uint32_t gen_bitmask; | |
907b28c5 | 1335 | } whitelist[] = { |
8697600b VS |
1336 | { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), |
1337 | .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE), | |
1338 | .size = 8, .gen_bitmask = GEN_RANGE(4, 9) }, | |
907b28c5 CW |
1339 | }; |
1340 | ||
1341 | int i915_reg_read_ioctl(struct drm_device *dev, | |
1342 | void *data, struct drm_file *file) | |
1343 | { | |
1344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1345 | struct drm_i915_reg_read *reg = data; | |
1346 | struct register_whitelist const *entry = whitelist; | |
648a9bc5 | 1347 | unsigned size; |
f0f59a00 | 1348 | i915_reg_t offset_ldw, offset_udw; |
cf67c70f | 1349 | int i, ret = 0; |
907b28c5 CW |
1350 | |
1351 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { | |
f0f59a00 | 1352 | if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) && |
907b28c5 CW |
1353 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) |
1354 | break; | |
1355 | } | |
1356 | ||
1357 | if (i == ARRAY_SIZE(whitelist)) | |
1358 | return -EINVAL; | |
1359 | ||
648a9bc5 CW |
1360 | /* We use the low bits to encode extra flags as the register should |
1361 | * be naturally aligned (and those that are not so aligned merely | |
1362 | * limit the available flags for that register). | |
1363 | */ | |
8697600b VS |
1364 | offset_ldw = entry->offset_ldw; |
1365 | offset_udw = entry->offset_udw; | |
648a9bc5 | 1366 | size = entry->size; |
f0f59a00 | 1367 | size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw); |
648a9bc5 | 1368 | |
cf67c70f PZ |
1369 | intel_runtime_pm_get(dev_priv); |
1370 | ||
648a9bc5 CW |
1371 | switch (size) { |
1372 | case 8 | 1: | |
8697600b | 1373 | reg->val = I915_READ64_2x32(offset_ldw, offset_udw); |
648a9bc5 | 1374 | break; |
907b28c5 | 1375 | case 8: |
8697600b | 1376 | reg->val = I915_READ64(offset_ldw); |
907b28c5 CW |
1377 | break; |
1378 | case 4: | |
8697600b | 1379 | reg->val = I915_READ(offset_ldw); |
907b28c5 CW |
1380 | break; |
1381 | case 2: | |
8697600b | 1382 | reg->val = I915_READ16(offset_ldw); |
907b28c5 CW |
1383 | break; |
1384 | case 1: | |
8697600b | 1385 | reg->val = I915_READ8(offset_ldw); |
907b28c5 CW |
1386 | break; |
1387 | default: | |
cf67c70f PZ |
1388 | ret = -EINVAL; |
1389 | goto out; | |
907b28c5 CW |
1390 | } |
1391 | ||
cf67c70f PZ |
1392 | out: |
1393 | intel_runtime_pm_put(dev_priv); | |
1394 | return ret; | |
907b28c5 CW |
1395 | } |
1396 | ||
b6359918 MK |
1397 | int i915_get_reset_stats_ioctl(struct drm_device *dev, |
1398 | void *data, struct drm_file *file) | |
1399 | { | |
1400 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1401 | struct drm_i915_reset_stats *args = data; | |
1402 | struct i915_ctx_hang_stats *hs; | |
273497e5 | 1403 | struct intel_context *ctx; |
b6359918 MK |
1404 | int ret; |
1405 | ||
661df041 MK |
1406 | if (args->flags || args->pad) |
1407 | return -EINVAL; | |
1408 | ||
821d66dd | 1409 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN)) |
b6359918 MK |
1410 | return -EPERM; |
1411 | ||
1412 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1413 | if (ret) | |
1414 | return ret; | |
1415 | ||
41bde553 BW |
1416 | ctx = i915_gem_context_get(file->driver_priv, args->ctx_id); |
1417 | if (IS_ERR(ctx)) { | |
b6359918 | 1418 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1419 | return PTR_ERR(ctx); |
b6359918 | 1420 | } |
41bde553 | 1421 | hs = &ctx->hang_stats; |
b6359918 MK |
1422 | |
1423 | if (capable(CAP_SYS_ADMIN)) | |
1424 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); | |
1425 | else | |
1426 | args->reset_count = 0; | |
1427 | ||
1428 | args->batch_active = hs->batch_active; | |
1429 | args->batch_pending = hs->batch_pending; | |
1430 | ||
1431 | mutex_unlock(&dev->struct_mutex); | |
1432 | ||
1433 | return 0; | |
1434 | } | |
1435 | ||
59ea9054 | 1436 | static int i915_reset_complete(struct drm_device *dev) |
907b28c5 CW |
1437 | { |
1438 | u8 gdrst; | |
59ea9054 | 1439 | pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); |
73bbf6bd | 1440 | return (gdrst & GRDOM_RESET_STATUS) == 0; |
907b28c5 CW |
1441 | } |
1442 | ||
ee4b6faf | 1443 | static int i915_do_reset(struct drm_device *dev, unsigned engine_mask) |
907b28c5 | 1444 | { |
73bbf6bd | 1445 | /* assert reset for at least 20 usec */ |
59ea9054 | 1446 | pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
73bbf6bd | 1447 | udelay(20); |
59ea9054 | 1448 | pci_write_config_byte(dev->pdev, I915_GDRST, 0); |
907b28c5 | 1449 | |
59ea9054 | 1450 | return wait_for(i915_reset_complete(dev), 500); |
73bbf6bd VS |
1451 | } |
1452 | ||
1453 | static int g4x_reset_complete(struct drm_device *dev) | |
1454 | { | |
1455 | u8 gdrst; | |
59ea9054 | 1456 | pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); |
73bbf6bd | 1457 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
907b28c5 CW |
1458 | } |
1459 | ||
ee4b6faf | 1460 | static int g33_do_reset(struct drm_device *dev, unsigned engine_mask) |
408d4b9e | 1461 | { |
408d4b9e VS |
1462 | pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
1463 | return wait_for(g4x_reset_complete(dev), 500); | |
1464 | } | |
1465 | ||
ee4b6faf | 1466 | static int g4x_do_reset(struct drm_device *dev, unsigned engine_mask) |
fa4f53c4 VS |
1467 | { |
1468 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1469 | int ret; | |
1470 | ||
59ea9054 | 1471 | pci_write_config_byte(dev->pdev, I915_GDRST, |
fa4f53c4 | 1472 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
73bbf6bd | 1473 | ret = wait_for(g4x_reset_complete(dev), 500); |
fa4f53c4 VS |
1474 | if (ret) |
1475 | return ret; | |
1476 | ||
1477 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ | |
1478 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); | |
1479 | POSTING_READ(VDECCLK_GATE_D); | |
1480 | ||
59ea9054 | 1481 | pci_write_config_byte(dev->pdev, I915_GDRST, |
fa4f53c4 | 1482 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
73bbf6bd | 1483 | ret = wait_for(g4x_reset_complete(dev), 500); |
fa4f53c4 VS |
1484 | if (ret) |
1485 | return ret; | |
1486 | ||
1487 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ | |
1488 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); | |
1489 | POSTING_READ(VDECCLK_GATE_D); | |
1490 | ||
59ea9054 | 1491 | pci_write_config_byte(dev->pdev, I915_GDRST, 0); |
fa4f53c4 VS |
1492 | |
1493 | return 0; | |
1494 | } | |
1495 | ||
ee4b6faf | 1496 | static int ironlake_do_reset(struct drm_device *dev, unsigned engine_mask) |
907b28c5 CW |
1497 | { |
1498 | struct drm_i915_private *dev_priv = dev->dev_private; | |
907b28c5 CW |
1499 | int ret; |
1500 | ||
c039b7f2 | 1501 | I915_WRITE(ILK_GDSR, |
0f08ffd6 | 1502 | ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE); |
c039b7f2 | 1503 | ret = wait_for((I915_READ(ILK_GDSR) & |
b3a3f03d | 1504 | ILK_GRDOM_RESET_ENABLE) == 0, 500); |
907b28c5 CW |
1505 | if (ret) |
1506 | return ret; | |
1507 | ||
c039b7f2 | 1508 | I915_WRITE(ILK_GDSR, |
0f08ffd6 | 1509 | ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE); |
c039b7f2 | 1510 | ret = wait_for((I915_READ(ILK_GDSR) & |
9aa7250f VS |
1511 | ILK_GRDOM_RESET_ENABLE) == 0, 500); |
1512 | if (ret) | |
1513 | return ret; | |
1514 | ||
c039b7f2 | 1515 | I915_WRITE(ILK_GDSR, 0); |
9aa7250f VS |
1516 | |
1517 | return 0; | |
907b28c5 CW |
1518 | } |
1519 | ||
ee4b6faf MK |
1520 | /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */ |
1521 | static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv, | |
1522 | u32 hw_domain_mask) | |
907b28c5 | 1523 | { |
ee4b6faf | 1524 | int ret; |
907b28c5 CW |
1525 | |
1526 | /* GEN6_GDRST is not in the gt power well, no need to check | |
1527 | * for fifo space for the write or forcewake the chip for | |
1528 | * the read | |
1529 | */ | |
ee4b6faf | 1530 | __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask); |
907b28c5 | 1531 | |
ee4b6faf MK |
1532 | #define ACKED ((__raw_i915_read32(dev_priv, GEN6_GDRST) & hw_domain_mask) == 0) |
1533 | /* Spin waiting for the device to ack the reset requests */ | |
1534 | ret = wait_for(ACKED, 500); | |
1535 | #undef ACKED | |
1536 | ||
1537 | return ret; | |
1538 | } | |
1539 | ||
1540 | /** | |
1541 | * gen6_reset_engines - reset individual engines | |
1542 | * @dev: DRM device | |
1543 | * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset | |
1544 | * | |
1545 | * This function will reset the individual engines that are set in engine_mask. | |
1546 | * If you provide ALL_ENGINES as mask, full global domain reset will be issued. | |
1547 | * | |
1548 | * Note: It is responsibility of the caller to handle the difference between | |
1549 | * asking full domain reset versus reset for all available individual engines. | |
1550 | * | |
1551 | * Returns 0 on success, nonzero on error. | |
1552 | */ | |
1553 | static int gen6_reset_engines(struct drm_device *dev, unsigned engine_mask) | |
1554 | { | |
1555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1556 | struct intel_engine_cs *engine; | |
1557 | const u32 hw_engine_mask[I915_NUM_ENGINES] = { | |
1558 | [RCS] = GEN6_GRDOM_RENDER, | |
1559 | [BCS] = GEN6_GRDOM_BLT, | |
1560 | [VCS] = GEN6_GRDOM_MEDIA, | |
1561 | [VCS2] = GEN8_GRDOM_MEDIA2, | |
1562 | [VECS] = GEN6_GRDOM_VECS, | |
1563 | }; | |
1564 | u32 hw_mask; | |
1565 | int ret; | |
1566 | ||
1567 | if (engine_mask == ALL_ENGINES) { | |
1568 | hw_mask = GEN6_GRDOM_FULL; | |
1569 | } else { | |
1570 | hw_mask = 0; | |
1571 | for_each_engine_masked(engine, dev_priv, engine_mask) | |
1572 | hw_mask |= hw_engine_mask[engine->id]; | |
1573 | } | |
1574 | ||
1575 | ret = gen6_hw_domain_reset(dev_priv, hw_mask); | |
907b28c5 | 1576 | |
0294ae7b | 1577 | intel_uncore_forcewake_reset(dev, true); |
5babf0fc | 1578 | |
907b28c5 CW |
1579 | return ret; |
1580 | } | |
1581 | ||
d431440c TE |
1582 | static int wait_for_register_fw(struct drm_i915_private *dev_priv, |
1583 | i915_reg_t reg, | |
1584 | const u32 mask, | |
1585 | const u32 value, | |
1586 | const unsigned long timeout_ms) | |
7fd2d269 | 1587 | { |
d431440c TE |
1588 | return wait_for((I915_READ_FW(reg) & mask) == value, timeout_ms); |
1589 | } | |
1590 | ||
1591 | static int gen8_request_engine_reset(struct intel_engine_cs *engine) | |
1592 | { | |
1593 | int ret; | |
1594 | struct drm_i915_private *dev_priv = engine->dev->dev_private; | |
1595 | ||
1596 | I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base), | |
1597 | _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)); | |
1598 | ||
1599 | ret = wait_for_register_fw(dev_priv, | |
1600 | RING_RESET_CTL(engine->mmio_base), | |
1601 | RESET_CTL_READY_TO_RESET, | |
1602 | RESET_CTL_READY_TO_RESET, | |
1603 | 700); | |
1604 | if (ret) | |
1605 | DRM_ERROR("%s: reset request timeout\n", engine->name); | |
1606 | ||
1607 | return ret; | |
1608 | } | |
1609 | ||
1610 | static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine) | |
1611 | { | |
1612 | struct drm_i915_private *dev_priv = engine->dev->dev_private; | |
1613 | ||
1614 | I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base), | |
1615 | _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)); | |
7fd2d269 MK |
1616 | } |
1617 | ||
ee4b6faf | 1618 | static int gen8_reset_engines(struct drm_device *dev, unsigned engine_mask) |
7fd2d269 MK |
1619 | { |
1620 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1621 | struct intel_engine_cs *engine; | |
7fd2d269 | 1622 | |
ee4b6faf | 1623 | for_each_engine_masked(engine, dev_priv, engine_mask) |
d431440c | 1624 | if (gen8_request_engine_reset(engine)) |
7fd2d269 | 1625 | goto not_ready; |
7fd2d269 | 1626 | |
ee4b6faf | 1627 | return gen6_reset_engines(dev, engine_mask); |
7fd2d269 MK |
1628 | |
1629 | not_ready: | |
ee4b6faf | 1630 | for_each_engine_masked(engine, dev_priv, engine_mask) |
d431440c | 1631 | gen8_unrequest_engine_reset(engine); |
7fd2d269 MK |
1632 | |
1633 | return -EIO; | |
1634 | } | |
1635 | ||
ee4b6faf MK |
1636 | static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *, |
1637 | unsigned engine_mask) | |
907b28c5 | 1638 | { |
b1330fbb CW |
1639 | if (!i915.reset) |
1640 | return NULL; | |
1641 | ||
7fd2d269 | 1642 | if (INTEL_INFO(dev)->gen >= 8) |
ee4b6faf | 1643 | return gen8_reset_engines; |
7fd2d269 | 1644 | else if (INTEL_INFO(dev)->gen >= 6) |
ee4b6faf | 1645 | return gen6_reset_engines; |
542c184f | 1646 | else if (IS_GEN5(dev)) |
49e4d842 | 1647 | return ironlake_do_reset; |
542c184f | 1648 | else if (IS_G4X(dev)) |
49e4d842 | 1649 | return g4x_do_reset; |
408d4b9e | 1650 | else if (IS_G33(dev)) |
49e4d842 | 1651 | return g33_do_reset; |
408d4b9e | 1652 | else if (INTEL_INFO(dev)->gen >= 3) |
49e4d842 | 1653 | return i915_do_reset; |
542c184f | 1654 | else |
49e4d842 CW |
1655 | return NULL; |
1656 | } | |
1657 | ||
ee4b6faf | 1658 | int intel_gpu_reset(struct drm_device *dev, unsigned engine_mask) |
49e4d842 | 1659 | { |
99106bc1 | 1660 | struct drm_i915_private *dev_priv = to_i915(dev); |
ee4b6faf | 1661 | int (*reset)(struct drm_device *, unsigned); |
99106bc1 | 1662 | int ret; |
49e4d842 CW |
1663 | |
1664 | reset = intel_get_gpu_reset(dev); | |
1665 | if (reset == NULL) | |
542c184f | 1666 | return -ENODEV; |
49e4d842 | 1667 | |
99106bc1 MK |
1668 | /* If the power well sleeps during the reset, the reset |
1669 | * request may be dropped and never completes (causing -EIO). | |
1670 | */ | |
1671 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
ee4b6faf | 1672 | ret = reset(dev, engine_mask); |
99106bc1 MK |
1673 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
1674 | ||
1675 | return ret; | |
49e4d842 CW |
1676 | } |
1677 | ||
1678 | bool intel_has_gpu_reset(struct drm_device *dev) | |
1679 | { | |
1680 | return intel_get_gpu_reset(dev) != NULL; | |
907b28c5 CW |
1681 | } |
1682 | ||
6b332fa2 AS |
1683 | int intel_guc_reset(struct drm_i915_private *dev_priv) |
1684 | { | |
1685 | int ret; | |
1686 | unsigned long irqflags; | |
1687 | ||
1688 | if (!i915.enable_guc_submission) | |
1689 | return -EINVAL; | |
1690 | ||
1691 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
1692 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
1693 | ||
1694 | ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC); | |
1695 | ||
1696 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
1697 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
1698 | ||
1699 | return ret; | |
1700 | } | |
1701 | ||
fc97618b | 1702 | bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv) |
907b28c5 | 1703 | { |
fc97618b | 1704 | return check_for_unclaimed_mmio(dev_priv); |
907b28c5 | 1705 | } |
75714940 | 1706 | |
bc3b9346 | 1707 | bool |
75714940 MK |
1708 | intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv) |
1709 | { | |
1710 | if (unlikely(i915.mmio_debug || | |
1711 | dev_priv->uncore.unclaimed_mmio_check <= 0)) | |
bc3b9346 | 1712 | return false; |
75714940 MK |
1713 | |
1714 | if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) { | |
1715 | DRM_DEBUG("Unclaimed register detected, " | |
1716 | "enabling oneshot unclaimed register reporting. " | |
1717 | "Please use i915.mmio_debug=N for more information.\n"); | |
1718 | i915.mmio_debug++; | |
1719 | dev_priv->uncore.unclaimed_mmio_check--; | |
bc3b9346 | 1720 | return true; |
75714940 | 1721 | } |
bc3b9346 MK |
1722 | |
1723 | return false; | |
75714940 | 1724 | } |