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drm/imx: imx-ldb: reset display clock input when disabling LVDS
[deliverable/linux.git] / drivers / gpu / drm / imx / imx-ldb.c
CommitLineData
ac4c1a9b
SH		 1/*
2 * i.MX drm driver - LVDS display bridge
3 *
4 * Copyright (C) 2012 Sascha Hauer, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
ac4c1a9b
SH		 14 */
15
16#include <linux/module.h>
17#include <linux/clk.h>
17b5001b 18#include <linux/component.h>
ac4c1a9b
SH		 19#include <drm/drmP.h>
20#include <drm/drm_fb_helper.h>
21#include <drm/drm_crtc_helper.h>
751e2676 22#include <drm/drm_panel.h>
ac4c1a9b
SH		 23#include <linux/mfd/syscon.h>
24#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
ac4c1a9b 25#include <linux/of_device.h>
751e2676 26#include <linux/of_graph.h>
ac4c1a9b
SH		 27#include <video/of_videomode.h>
28#include <linux/regmap.h>
29#include <linux/videodev2.h>
30
31#include "imx-drm.h"
32
33#define DRIVER_NAME "imx-ldb"
34
35#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
36#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
37#define LDB_CH0_MODE_EN_MASK (3 << 0)
38#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
39#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
40#define LDB_CH1_MODE_EN_MASK (3 << 2)
41#define LDB_SPLIT_MODE_EN (1 << 4)
42#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
43#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
44#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
45#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
46#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
47#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
48#define LDB_BGREF_RMODE_INT (1 << 15)
49
50#define con_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, connector)
51#define enc_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, encoder)
52
53struct imx_ldb;
54
55struct imx_ldb_channel {
56 struct imx_ldb *ldb;
57 struct drm_connector connector;
ac4c1a9b 58 struct drm_encoder encoder;
751e2676 59 struct drm_panel *panel;
1b3f7675 60 struct device_node *child;
ac4c1a9b
SH		 61 int chno;
62 void *edid;
63 int edid_len;
64 struct drm_display_mode mode;
65 int mode_valid;
66};
67
68struct bus_mux {
69 int reg;
70 int shift;
71 int mask;
72};
73
74struct imx_ldb {
75 struct regmap *regmap;
76 struct device *dev;
77 struct imx_ldb_channel channel[2];
78 struct clk *clk[2]; /* our own clock */
79 struct clk *clk_sel[4]; /* parent of display clock */
3973aff0 80 struct clk *clk_parent[4]; /* original parent of clk_sel */
ac4c1a9b
SH		 81 struct clk *clk_pll[2]; /* upstream clock we can adjust */
82 u32 ldb_ctrl;
83 const struct bus_mux *lvds_mux;
84};
85
86static enum drm_connector_status imx_ldb_connector_detect(
87 struct drm_connector *connector, bool force)
88{
89 return connector_status_connected;
90}
91
ac4c1a9b
SH		 92static int imx_ldb_connector_get_modes(struct drm_connector *connector)
93{
94 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
95 int num_modes = 0;
96
751e2676
PZ		 97 if (imx_ldb_ch->panel && imx_ldb_ch->panel->funcs &&
98 imx_ldb_ch->panel->funcs->get_modes) {
99 num_modes = imx_ldb_ch->panel->funcs->get_modes(imx_ldb_ch->panel);
100 if (num_modes > 0)
101 return num_modes;
102 }
103
ac4c1a9b
SH		 104 if (imx_ldb_ch->edid) {
105 drm_mode_connector_update_edid_property(connector,
106 imx_ldb_ch->edid);
107 num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
108 }
109
110 if (imx_ldb_ch->mode_valid) {
111 struct drm_display_mode *mode;
112
113 mode = drm_mode_create(connector->dev);
9f9b036f
FE		 114 if (!mode)
115 return -EINVAL;
ac4c1a9b
SH		 116 drm_mode_copy(mode, &imx_ldb_ch->mode);
117 mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
118 drm_mode_probed_add(connector, mode);
119 num_modes++;
120 }
121
122 return num_modes;
123}
124
ac4c1a9b
SH		 125static struct drm_encoder *imx_ldb_connector_best_encoder(
126 struct drm_connector *connector)
127{
128 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
129
130 return &imx_ldb_ch->encoder;
131}
132
133static void imx_ldb_encoder_dpms(struct drm_encoder *encoder, int mode)
134{
135}
136
137static bool imx_ldb_encoder_mode_fixup(struct drm_encoder *encoder,
138 const struct drm_display_mode *mode,
139 struct drm_display_mode *adjusted_mode)
140{
141 return true;
142}
143
144static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
145 unsigned long serial_clk, unsigned long di_clk)
146{
147 int ret;
148
149 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
150 clk_get_rate(ldb->clk_pll[chno]), serial_clk);
151 clk_set_rate(ldb->clk_pll[chno], serial_clk);
152
153 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
154 clk_get_rate(ldb->clk_pll[chno]));
155
156 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
157 clk_get_rate(ldb->clk[chno]),
158 (long int)di_clk);
159 clk_set_rate(ldb->clk[chno], di_clk);
160
161 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
162 clk_get_rate(ldb->clk[chno]));
163
164 /* set display clock mux to LDB input clock */
165 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
49f4a9c8 166 if (ret)
e5e1b166
AO		 167 dev_err(ldb->dev,
168 "unable to set di%d parent clock to ldb_di%d\n", mux,
169 chno);
ac4c1a9b
SH		 170}
171
172static void imx_ldb_encoder_prepare(struct drm_encoder *encoder)
173{
174 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
175 struct imx_ldb *ldb = imx_ldb_ch->ldb;
2872c807 176 u32 bus_format;
ac4c1a9b 177
000d73fc
MN		 178 switch (imx_ldb_ch->chno) {
179 case 0:
2872c807 180 bus_format = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH0_24) ?
a7c6e76f 181 MEDIA_BUS_FMT_RGB888_1X24 : MEDIA_BUS_FMT_RGB666_1X18;
000d73fc
MN		 182 break;
183 case 1:
2872c807 184 bus_format = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH1_24) ?
a7c6e76f 185 MEDIA_BUS_FMT_RGB888_1X24 : MEDIA_BUS_FMT_RGB666_1X18;
000d73fc
MN		 186 break;
187 default:
188 dev_err(ldb->dev, "unable to config di%d panel format\n",
189 imx_ldb_ch->chno);
2872c807 190 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
000d73fc
MN		 191 }
192
2872c807 193 imx_drm_set_bus_format(encoder, bus_format);
ac4c1a9b
SH		 194}
195
196static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
197{
198 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
199 struct imx_ldb *ldb = imx_ldb_ch->ldb;
200 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
655b43cc 201 int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
ac4c1a9b 202
751e2676
PZ		 203 drm_panel_prepare(imx_ldb_ch->panel);
204
ac4c1a9b
SH		 205 if (dual) {
206 clk_prepare_enable(ldb->clk[0]);
207 clk_prepare_enable(ldb->clk[1]);
208 }
209
210 if (imx_ldb_ch == &ldb->channel[0] || dual) {
211 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
212 if (mux == 0 || ldb->lvds_mux)
213 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
214 else if (mux == 1)
215 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
216 }
217 if (imx_ldb_ch == &ldb->channel[1] || dual) {
218 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
219 if (mux == 1 || ldb->lvds_mux)
220 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
221 else if (mux == 0)
222 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
223 }
224
225 if (ldb->lvds_mux) {
226 const struct bus_mux *lvds_mux = NULL;
227
228 if (imx_ldb_ch == &ldb->channel[0])
229 lvds_mux = &ldb->lvds_mux[0];
230 else if (imx_ldb_ch == &ldb->channel[1])
231 lvds_mux = &ldb->lvds_mux[1];
232
233 regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
234 mux << lvds_mux->shift);
235 }
236
237 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
751e2676
PZ		 238
239 drm_panel_enable(imx_ldb_ch->panel);
ac4c1a9b
SH		 240}
241
242static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder,
eb10d635
SL		 243 struct drm_display_mode *orig_mode,
244 struct drm_display_mode *mode)
ac4c1a9b
SH		 245{
246 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
247 struct imx_ldb *ldb = imx_ldb_ch->ldb;
248 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
51dac94e
PZ		 249 unsigned long serial_clk;
250 unsigned long di_clk = mode->clock * 1000;
251 int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
ac4c1a9b
SH		 252
253 if (mode->clock > 170000) {
254 dev_warn(ldb->dev,
255 "%s: mode exceeds 170 MHz pixel clock\n", __func__);
256 }
257 if (mode->clock > 85000 && !dual) {
258 dev_warn(ldb->dev,
259 "%s: mode exceeds 85 MHz pixel clock\n", __func__);
260 }
261
51dac94e
PZ		 262 if (dual) {
263 serial_clk = 3500UL * mode->clock;
264 imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
265 imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
266 } else {
267 serial_clk = 7000UL * mode->clock;
268 imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
269 di_clk);
270 }
271
ac4c1a9b
SH		 272 /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
273 if (imx_ldb_ch == &ldb->channel[0]) {
274 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
275 ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
276 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
277 ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
278 }
279 if (imx_ldb_ch == &ldb->channel[1]) {
280 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
281 ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
282 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
283 ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
284 }
285}
286
287static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
288{
289 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
290 struct imx_ldb *ldb = imx_ldb_ch->ldb;
3973aff0 291 int mux, ret;
ac4c1a9b
SH		 292
293 /*
294 * imx_ldb_encoder_disable is called by
295 * drm_helper_disable_unused_functions without
296 * the encoder being enabled before.
297 */
298 if (imx_ldb_ch == &ldb->channel[0] &&
299 (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0)
300 return;
301 else if (imx_ldb_ch == &ldb->channel[1] &&
302 (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0)
303 return;
304
751e2676
PZ		 305 drm_panel_disable(imx_ldb_ch->panel);
306
ac4c1a9b
SH		 307 if (imx_ldb_ch == &ldb->channel[0])
308 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
309 else if (imx_ldb_ch == &ldb->channel[1])
310 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
311
312 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
313
314 if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
315 clk_disable_unprepare(ldb->clk[0]);
316 clk_disable_unprepare(ldb->clk[1]);
317 }
751e2676 318
3973aff0
PZ		 319 if (ldb->lvds_mux) {
320 const struct bus_mux *lvds_mux = NULL;
321
322 if (imx_ldb_ch == &ldb->channel[0])
323 lvds_mux = &ldb->lvds_mux[0];
324 else if (imx_ldb_ch == &ldb->channel[1])
325 lvds_mux = &ldb->lvds_mux[1];
326
327 regmap_read(ldb->regmap, lvds_mux->reg, &mux);
328 mux &= lvds_mux->mask;
329 mux >>= lvds_mux->shift;
330 } else {
331 mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
332 }
333
334 /* set display clock mux back to original input clock */
335 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
336 if (ret)
337 dev_err(ldb->dev,
338 "unable to set di%d parent clock to original parent\n",
339 mux);
340
751e2676 341 drm_panel_unprepare(imx_ldb_ch->panel);
ac4c1a9b
SH		 342}
343
ac4c1a9b
SH		 344static struct drm_connector_funcs imx_ldb_connector_funcs = {
345 .dpms = drm_helper_connector_dpms,
346 .fill_modes = drm_helper_probe_single_connector_modes,
347 .detect = imx_ldb_connector_detect,
1b3f7675 348 .destroy = imx_drm_connector_destroy,
ac4c1a9b
SH		 349};
350
351static struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
352 .get_modes = imx_ldb_connector_get_modes,
353 .best_encoder = imx_ldb_connector_best_encoder,
ac4c1a9b
SH		 354};
355
356static struct drm_encoder_funcs imx_ldb_encoder_funcs = {
1b3f7675 357 .destroy = imx_drm_encoder_destroy,
ac4c1a9b
SH		 358};
359
360static struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
361 .dpms = imx_ldb_encoder_dpms,
362 .mode_fixup = imx_ldb_encoder_mode_fixup,
363 .prepare = imx_ldb_encoder_prepare,
364 .commit = imx_ldb_encoder_commit,
365 .mode_set = imx_ldb_encoder_mode_set,
366 .disable = imx_ldb_encoder_disable,
367};
368
369static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
370{
371 char clkname[16];
372
98dd3b2a 373 snprintf(clkname, sizeof(clkname), "di%d", chno);
ac4c1a9b
SH		 374 ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
375 if (IS_ERR(ldb->clk[chno]))
376 return PTR_ERR(ldb->clk[chno]);
377
98dd3b2a 378 snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
ac4c1a9b 379 ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
ac4c1a9b 380
1f933fa8 381 return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
ac4c1a9b
SH		 382}
383
1b3f7675
RK		 384static int imx_ldb_register(struct drm_device *drm,
385 struct imx_ldb_channel *imx_ldb_ch)
ac4c1a9b 386{
ac4c1a9b 387 struct imx_ldb *ldb = imx_ldb_ch->ldb;
1b3f7675
RK		 388 int ret;
389
390 ret = imx_drm_encoder_parse_of(drm, &imx_ldb_ch->encoder,
391 imx_ldb_ch->child);
392 if (ret)
393 return ret;
ac4c1a9b
SH		 394
395 ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
396 if (ret)
397 return ret;
1b3f7675 398
ac4c1a9b 399 if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
1b3f7675 400 ret = imx_ldb_get_clk(ldb, 1);
ac4c1a9b
SH		 401 if (ret)
402 return ret;
403 }
404
ac4c1a9b
SH		 405 drm_encoder_helper_add(&imx_ldb_ch->encoder,
406 &imx_ldb_encoder_helper_funcs);
1b3f7675
RK		 407 drm_encoder_init(drm, &imx_ldb_ch->encoder, &imx_ldb_encoder_funcs,
408 DRM_MODE_ENCODER_LVDS);
ac4c1a9b
SH		 409
410 drm_connector_helper_add(&imx_ldb_ch->connector,
411 &imx_ldb_connector_helper_funcs);
1b3f7675
RK		 412 drm_connector_init(drm, &imx_ldb_ch->connector,
413 &imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS);
ac4c1a9b 414
751e2676
PZ		 415 if (imx_ldb_ch->panel)
416 drm_panel_attach(imx_ldb_ch->panel, &imx_ldb_ch->connector);
417
ac4c1a9b
SH		 418 drm_mode_connector_attach_encoder(&imx_ldb_ch->connector,
419 &imx_ldb_ch->encoder);
420
421 return 0;
422}
423
424enum {
425 LVDS_BIT_MAP_SPWG,
426 LVDS_BIT_MAP_JEIDA
427};
428
5354cb64 429static const char * const imx_ldb_bit_mappings[] = {
ac4c1a9b
SH		 430 [LVDS_BIT_MAP_SPWG] = "spwg",
431 [LVDS_BIT_MAP_JEIDA] = "jeida",
432};
433
d78b1406 434static const int of_get_data_mapping(struct device_node *np)
ac4c1a9b
SH		 435{
436 const char *bm;
437 int ret, i;
438
439 ret = of_property_read_string(np, "fsl,data-mapping", &bm);
440 if (ret < 0)
441 return ret;
442
443 for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++)
444 if (!strcasecmp(bm, imx_ldb_bit_mappings[i]))
445 return i;
446
447 return -EINVAL;
448}
449
450static struct bus_mux imx6q_lvds_mux[2] = {
451 {
452 .reg = IOMUXC_GPR3,
453 .shift = 6,
454 .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
455 }, {
456 .reg = IOMUXC_GPR3,
457 .shift = 8,
458 .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
459 }
460};
461
462/*
463 * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
464 * of_match_device will walk through this list and take the first entry
465 * matching any of its compatible values. Therefore, the more generic
466 * entries (in this case fsl,imx53-ldb) need to be ordered last.
467 */
468static const struct of_device_id imx_ldb_dt_ids[] = {
469 { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
470 { .compatible = "fsl,imx53-ldb", .data = NULL, },
471 { }
472};
473MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
474
17b5001b 475static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
ac4c1a9b 476{
1b3f7675 477 struct drm_device *drm = data;
17b5001b 478 struct device_node *np = dev->of_node;
ac4c1a9b 479 const struct of_device_id *of_id =
17b5001b 480 of_match_device(imx_ldb_dt_ids, dev);
ac4c1a9b
SH		 481 struct device_node *child;
482 const u8 *edidp;
483 struct imx_ldb *imx_ldb;
484 int datawidth;
485 int mapping;
486 int dual;
487 int ret;
488 int i;
489
17b5001b 490 imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
ac4c1a9b
SH		 491 if (!imx_ldb)
492 return -ENOMEM;
493
494 imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
495 if (IS_ERR(imx_ldb->regmap)) {
17b5001b 496 dev_err(dev, "failed to get parent regmap\n");
ac4c1a9b
SH		 497 return PTR_ERR(imx_ldb->regmap);
498 }
499
17b5001b 500 imx_ldb->dev = dev;
ac4c1a9b
SH		 501
502 if (of_id)
503 imx_ldb->lvds_mux = of_id->data;
504
505 dual = of_property_read_bool(np, "fsl,dual-channel");
506 if (dual)
507 imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
508
509 /*
4599934d 510 * There are three different possible clock mux configurations:
ac4c1a9b
SH		 511 * i.MX53: ipu1_di0_sel, ipu1_di1_sel
512 * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
513 * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
514 * Map them all to di0_sel...di3_sel.
515 */
516 for (i = 0; i < 4; i++) {
517 char clkname[16];
518
519 sprintf(clkname, "di%d_sel", i);
520 imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
521 if (IS_ERR(imx_ldb->clk_sel[i])) {
522 ret = PTR_ERR(imx_ldb->clk_sel[i]);
523 imx_ldb->clk_sel[i] = NULL;
524 break;
525 }
3973aff0
PZ		 526
527 imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
ac4c1a9b
SH		 528 }
529 if (i == 0)
530 return ret;
531
532 for_each_child_of_node(np, child) {
533 struct imx_ldb_channel *channel;
751e2676 534 struct device_node *port;
ac4c1a9b
SH		 535
536 ret = of_property_read_u32(child, "reg", &i);
537 if (ret || i < 0 || i > 1)
538 return -EINVAL;
539
540 if (dual && i > 0) {
17b5001b 541 dev_warn(dev, "dual-channel mode, ignoring second output\n");
ac4c1a9b
SH		 542 continue;
543 }
544
545 if (!of_device_is_available(child))
546 continue;
547
548 channel = &imx_ldb->channel[i];
549 channel->ldb = imx_ldb;
550 channel->chno = i;
1b3f7675 551 channel->child = child;
ac4c1a9b 552
751e2676
PZ		 553 /*
554 * The output port is port@4 with an external 4-port mux or
555 * port@2 with the internal 2-port mux.
556 */
557 port = of_graph_get_port_by_id(child, imx_ldb->lvds_mux ? 4 : 2);
558 if (port) {
559 struct device_node *endpoint, *remote;
560
561 endpoint = of_get_child_by_name(port, "endpoint");
562 if (endpoint) {
563 remote = of_graph_get_remote_port_parent(endpoint);
564 if (remote)
565 channel->panel = of_drm_find_panel(remote);
566 else
567 return -EPROBE_DEFER;
568 if (!channel->panel) {
569 dev_err(dev, "panel not found: %s\n",
570 remote->full_name);
571 return -EPROBE_DEFER;
572 }
573 }
574 }
575
ac4c1a9b
SH		 576 edidp = of_get_property(child, "edid", &channel->edid_len);
577 if (edidp) {
578 channel->edid = kmemdup(edidp, channel->edid_len,
579 GFP_KERNEL);
751e2676 580 } else if (!channel->panel) {
ac4c1a9b
SH		 581 ret = of_get_drm_display_mode(child, &channel->mode, 0);
582 if (!ret)
583 channel->mode_valid = 1;
584 }
585
586 ret = of_property_read_u32(child, "fsl,data-width", &datawidth);
587 if (ret)
588 datawidth = 0;
589 else if (datawidth != 18 && datawidth != 24)
590 return -EINVAL;
591
592 mapping = of_get_data_mapping(child);
593 switch (mapping) {
594 case LVDS_BIT_MAP_SPWG:
595 if (datawidth == 24) {
596 if (i == 0 || dual)
e5e1b166
AO		 597 imx_ldb->ldb_ctrl |=
598 LDB_DATA_WIDTH_CH0_24;
ac4c1a9b 599 if (i == 1 || dual)
e5e1b166
AO		 600 imx_ldb->ldb_ctrl |=
601 LDB_DATA_WIDTH_CH1_24;
ac4c1a9b
SH		 602 }
603 break;
604 case LVDS_BIT_MAP_JEIDA:
605 if (datawidth == 18) {
17b5001b 606 dev_err(dev, "JEIDA standard only supported in 24 bit\n");
ac4c1a9b
SH		 607 return -EINVAL;
608 }
609 if (i == 0 || dual)
e5e1b166
AO		 610 imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
611 LDB_BIT_MAP_CH0_JEIDA;
ac4c1a9b 612 if (i == 1 || dual)
e5e1b166
AO		 613 imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
614 LDB_BIT_MAP_CH1_JEIDA;
ac4c1a9b
SH		 615 break;
616 default:
17b5001b 617 dev_err(dev, "data mapping not specified or invalid\n");
ac4c1a9b
SH		 618 return -EINVAL;
619 }
620
1b3f7675 621 ret = imx_ldb_register(drm, channel);
ac4c1a9b
SH		 622 if (ret)
623 return ret;
ac4c1a9b
SH		 624 }
625
17b5001b 626 dev_set_drvdata(dev, imx_ldb);
ac4c1a9b
SH		 627
628 return 0;
629}
630
17b5001b
RK		 631static void imx_ldb_unbind(struct device *dev, struct device *master,
632 void *data)
ac4c1a9b 633{
17b5001b 634 struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
ac4c1a9b
SH		 635 int i;
636
637 for (i = 0; i < 2; i++) {
638 struct imx_ldb_channel *channel = &imx_ldb->channel[i];
ac4c1a9b 639
d9fdb9fb
RK		 640 if (!channel->connector.funcs)
641 continue;
642
1b3f7675
RK		 643 channel->connector.funcs->destroy(&channel->connector);
644 channel->encoder.funcs->destroy(&channel->encoder);
f4876ffe
PS		 645
646 kfree(channel->edid);
ac4c1a9b 647 }
17b5001b 648}
ac4c1a9b 649
17b5001b
RK		 650static const struct component_ops imx_ldb_ops = {
651 .bind = imx_ldb_bind,
652 .unbind = imx_ldb_unbind,
653};
654
655static int imx_ldb_probe(struct platform_device *pdev)
656{
657 return component_add(&pdev->dev, &imx_ldb_ops);
658}
659
660static int imx_ldb_remove(struct platform_device *pdev)
661{
662 component_del(&pdev->dev, &imx_ldb_ops);
ac4c1a9b
SH		 663 return 0;
664}
665
666static struct platform_driver imx_ldb_driver = {
667 .probe = imx_ldb_probe,
668 .remove = imx_ldb_remove,
669 .driver = {
670 .of_match_table = imx_ldb_dt_ids,
671 .name = DRIVER_NAME,
ac4c1a9b
SH		 672 },
673};
674
675module_platform_driver(imx_ldb_driver);
676
677MODULE_DESCRIPTION("i.MX LVDS driver");
678MODULE_AUTHOR("Sascha Hauer, Pengutronix");
679MODULE_LICENSE("GPL");
bc627387 680MODULE_ALIAS("platform:" DRIVER_NAME);
Linux kernel - Deliverables
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