Commit | Line | Data |
---|---|---|
c8afe684 | 1 | /* |
5eba5d87 | 2 | * Copyright (c) 2014 The Linux Foundation. All rights reserved. |
c8afe684 RC |
3 | * Copyright (C) 2013 Red Hat |
4 | * Author: Rob Clark <robdclark@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published by | |
8 | * the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
f6a8eaca | 19 | #include <linux/of_irq.h> |
1fd6a441 AT |
20 | #include <linux/of_gpio.h> |
21 | ||
c8afe684 RC |
22 | #include "hdmi.h" |
23 | ||
fcda50c8 | 24 | void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on) |
c8afe684 RC |
25 | { |
26 | uint32_t ctrl = 0; | |
c6a57a50 | 27 | unsigned long flags; |
c8afe684 | 28 | |
c6a57a50 | 29 | spin_lock_irqsave(&hdmi->reg_lock, flags); |
c8afe684 RC |
30 | if (power_on) { |
31 | ctrl |= HDMI_CTRL_ENABLE; | |
32 | if (!hdmi->hdmi_mode) { | |
33 | ctrl |= HDMI_CTRL_HDMI; | |
34 | hdmi_write(hdmi, REG_HDMI_CTRL, ctrl); | |
35 | ctrl &= ~HDMI_CTRL_HDMI; | |
36 | } else { | |
37 | ctrl |= HDMI_CTRL_HDMI; | |
38 | } | |
39 | } else { | |
40 | ctrl = HDMI_CTRL_HDMI; | |
41 | } | |
42 | ||
43 | hdmi_write(hdmi, REG_HDMI_CTRL, ctrl); | |
c6a57a50 | 44 | spin_unlock_irqrestore(&hdmi->reg_lock, flags); |
c8afe684 RC |
45 | DBG("HDMI Core: %s, HDMI_CTRL=0x%08x", |
46 | power_on ? "Enable" : "Disable", ctrl); | |
47 | } | |
48 | ||
fcda50c8 | 49 | static irqreturn_t msm_hdmi_irq(int irq, void *dev_id) |
c8afe684 RC |
50 | { |
51 | struct hdmi *hdmi = dev_id; | |
52 | ||
53 | /* Process HPD: */ | |
fcda50c8 | 54 | msm_hdmi_connector_irq(hdmi->connector); |
c8afe684 RC |
55 | |
56 | /* Process DDC: */ | |
fcda50c8 | 57 | msm_hdmi_i2c_irq(hdmi->i2c); |
c8afe684 | 58 | |
c6a57a50 | 59 | /* Process HDCP: */ |
60 | if (hdmi->hdcp_ctrl) | |
fcda50c8 | 61 | msm_hdmi_hdcp_irq(hdmi->hdcp_ctrl); |
c6a57a50 | 62 | |
c8afe684 RC |
63 | /* TODO audio.. */ |
64 | ||
65 | return IRQ_HANDLED; | |
66 | } | |
67 | ||
fcda50c8 | 68 | static void msm_hdmi_destroy(struct hdmi *hdmi) |
c8afe684 | 69 | { |
c6a57a50 | 70 | /* |
71 | * at this point, hpd has been disabled, | |
72 | * after flush workq, it's safe to deinit hdcp | |
73 | */ | |
74 | if (hdmi->workq) { | |
75 | flush_workqueue(hdmi->workq); | |
76 | destroy_workqueue(hdmi->workq); | |
77 | } | |
fcda50c8 | 78 | msm_hdmi_hdcp_destroy(hdmi); |
c8afe684 | 79 | |
e00012b2 AT |
80 | if (hdmi->phy_dev) { |
81 | put_device(hdmi->phy_dev); | |
82 | hdmi->phy = NULL; | |
83 | hdmi->phy_dev = NULL; | |
84 | } | |
85 | ||
c8afe684 | 86 | if (hdmi->i2c) |
fcda50c8 | 87 | msm_hdmi_i2c_destroy(hdmi->i2c); |
c8afe684 | 88 | |
c0c0d9ee | 89 | platform_set_drvdata(hdmi->pdev, NULL); |
c8afe684 RC |
90 | } |
91 | ||
fcda50c8 | 92 | static int msm_hdmi_get_phy(struct hdmi *hdmi) |
e00012b2 AT |
93 | { |
94 | struct platform_device *pdev = hdmi->pdev; | |
95 | struct platform_device *phy_pdev; | |
96 | struct device_node *phy_node; | |
97 | ||
98 | phy_node = of_parse_phandle(pdev->dev.of_node, "phys", 0); | |
99 | if (!phy_node) { | |
100 | dev_err(&pdev->dev, "cannot find phy device\n"); | |
101 | return -ENXIO; | |
102 | } | |
103 | ||
104 | phy_pdev = of_find_device_by_node(phy_node); | |
105 | if (phy_pdev) | |
106 | hdmi->phy = platform_get_drvdata(phy_pdev); | |
107 | ||
108 | of_node_put(phy_node); | |
109 | ||
110 | if (!phy_pdev || !hdmi->phy) { | |
111 | dev_err(&pdev->dev, "phy driver is not ready\n"); | |
112 | return -EPROBE_DEFER; | |
113 | } | |
114 | ||
115 | hdmi->phy_dev = get_device(&phy_pdev->dev); | |
116 | ||
117 | return 0; | |
118 | } | |
119 | ||
067fef37 RC |
120 | /* construct hdmi at bind/probe time, grab all the resources. If |
121 | * we are to EPROBE_DEFER we want to do it here, rather than later | |
122 | * at modeset_init() time | |
123 | */ | |
fcda50c8 | 124 | static struct hdmi *msm_hdmi_init(struct platform_device *pdev) |
c8afe684 | 125 | { |
067fef37 | 126 | struct hdmi_platform_config *config = pdev->dev.platform_data; |
a3376e3e | 127 | struct hdmi *hdmi = NULL; |
c6a57a50 | 128 | struct resource *res; |
dada25bd | 129 | int i, ret; |
c8afe684 | 130 | |
067fef37 | 131 | hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); |
a3376e3e RC |
132 | if (!hdmi) { |
133 | ret = -ENOMEM; | |
134 | goto fail; | |
135 | } | |
136 | ||
c8afe684 | 137 | hdmi->pdev = pdev; |
dada25bd | 138 | hdmi->config = config; |
c6a57a50 | 139 | spin_lock_init(&hdmi->reg_lock); |
c0c0d9ee | 140 | |
dada25bd | 141 | hdmi->mmio = msm_ioremap(pdev, config->mmio_name, "HDMI"); |
c8afe684 RC |
142 | if (IS_ERR(hdmi->mmio)) { |
143 | ret = PTR_ERR(hdmi->mmio); | |
144 | goto fail; | |
145 | } | |
146 | ||
c6a57a50 | 147 | /* HDCP needs physical address of hdmi register */ |
148 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
149 | config->mmio_name); | |
150 | hdmi->mmio_phy_addr = res->start; | |
151 | ||
152 | hdmi->qfprom_mmio = msm_ioremap(pdev, | |
153 | config->qfprom_mmio_name, "HDMI_QFPROM"); | |
154 | if (IS_ERR(hdmi->qfprom_mmio)) { | |
155 | dev_info(&pdev->dev, "can't find qfprom resource\n"); | |
156 | hdmi->qfprom_mmio = NULL; | |
157 | } | |
158 | ||
447fa529 SV |
159 | hdmi->hpd_regs = devm_kzalloc(&pdev->dev, sizeof(hdmi->hpd_regs[0]) * |
160 | config->hpd_reg_cnt, GFP_KERNEL); | |
161 | if (!hdmi->hpd_regs) { | |
162 | ret = -ENOMEM; | |
163 | goto fail; | |
164 | } | |
dada25bd RC |
165 | for (i = 0; i < config->hpd_reg_cnt; i++) { |
166 | struct regulator *reg; | |
167 | ||
3e87599b | 168 | reg = devm_regulator_get(&pdev->dev, |
41e69778 | 169 | config->hpd_reg_names[i]); |
dada25bd RC |
170 | if (IS_ERR(reg)) { |
171 | ret = PTR_ERR(reg); | |
067fef37 | 172 | dev_err(&pdev->dev, "failed to get hpd regulator: %s (%d)\n", |
dada25bd RC |
173 | config->hpd_reg_names[i], ret); |
174 | goto fail; | |
175 | } | |
176 | ||
177 | hdmi->hpd_regs[i] = reg; | |
c8afe684 RC |
178 | } |
179 | ||
447fa529 SV |
180 | hdmi->pwr_regs = devm_kzalloc(&pdev->dev, sizeof(hdmi->pwr_regs[0]) * |
181 | config->pwr_reg_cnt, GFP_KERNEL); | |
182 | if (!hdmi->pwr_regs) { | |
183 | ret = -ENOMEM; | |
184 | goto fail; | |
185 | } | |
dada25bd RC |
186 | for (i = 0; i < config->pwr_reg_cnt; i++) { |
187 | struct regulator *reg; | |
c8afe684 | 188 | |
3e87599b | 189 | reg = devm_regulator_get(&pdev->dev, |
41e69778 | 190 | config->pwr_reg_names[i]); |
dada25bd RC |
191 | if (IS_ERR(reg)) { |
192 | ret = PTR_ERR(reg); | |
067fef37 | 193 | dev_err(&pdev->dev, "failed to get pwr regulator: %s (%d)\n", |
dada25bd RC |
194 | config->pwr_reg_names[i], ret); |
195 | goto fail; | |
196 | } | |
197 | ||
198 | hdmi->pwr_regs[i] = reg; | |
c8afe684 RC |
199 | } |
200 | ||
447fa529 SV |
201 | hdmi->hpd_clks = devm_kzalloc(&pdev->dev, sizeof(hdmi->hpd_clks[0]) * |
202 | config->hpd_clk_cnt, GFP_KERNEL); | |
203 | if (!hdmi->hpd_clks) { | |
204 | ret = -ENOMEM; | |
205 | goto fail; | |
206 | } | |
dada25bd RC |
207 | for (i = 0; i < config->hpd_clk_cnt; i++) { |
208 | struct clk *clk; | |
209 | ||
210 | clk = devm_clk_get(&pdev->dev, config->hpd_clk_names[i]); | |
211 | if (IS_ERR(clk)) { | |
212 | ret = PTR_ERR(clk); | |
067fef37 | 213 | dev_err(&pdev->dev, "failed to get hpd clk: %s (%d)\n", |
dada25bd RC |
214 | config->hpd_clk_names[i], ret); |
215 | goto fail; | |
216 | } | |
217 | ||
218 | hdmi->hpd_clks[i] = clk; | |
c8afe684 RC |
219 | } |
220 | ||
447fa529 SV |
221 | hdmi->pwr_clks = devm_kzalloc(&pdev->dev, sizeof(hdmi->pwr_clks[0]) * |
222 | config->pwr_clk_cnt, GFP_KERNEL); | |
223 | if (!hdmi->pwr_clks) { | |
224 | ret = -ENOMEM; | |
225 | goto fail; | |
226 | } | |
dada25bd RC |
227 | for (i = 0; i < config->pwr_clk_cnt; i++) { |
228 | struct clk *clk; | |
229 | ||
230 | clk = devm_clk_get(&pdev->dev, config->pwr_clk_names[i]); | |
231 | if (IS_ERR(clk)) { | |
232 | ret = PTR_ERR(clk); | |
067fef37 | 233 | dev_err(&pdev->dev, "failed to get pwr clk: %s (%d)\n", |
dada25bd RC |
234 | config->pwr_clk_names[i], ret); |
235 | goto fail; | |
236 | } | |
237 | ||
238 | hdmi->pwr_clks[i] = clk; | |
c8afe684 RC |
239 | } |
240 | ||
c6a57a50 | 241 | hdmi->workq = alloc_ordered_workqueue("msm_hdmi", 0); |
242 | ||
fcda50c8 | 243 | hdmi->i2c = msm_hdmi_i2c_init(hdmi); |
c8afe684 RC |
244 | if (IS_ERR(hdmi->i2c)) { |
245 | ret = PTR_ERR(hdmi->i2c); | |
067fef37 | 246 | dev_err(&pdev->dev, "failed to get i2c: %d\n", ret); |
c8afe684 RC |
247 | hdmi->i2c = NULL; |
248 | goto fail; | |
249 | } | |
250 | ||
fcda50c8 | 251 | ret = msm_hdmi_get_phy(hdmi); |
e00012b2 AT |
252 | if (ret) { |
253 | dev_err(&pdev->dev, "failed to get phy\n"); | |
254 | goto fail; | |
255 | } | |
256 | ||
fcda50c8 | 257 | hdmi->hdcp_ctrl = msm_hdmi_hdcp_init(hdmi); |
c6a57a50 | 258 | if (IS_ERR(hdmi->hdcp_ctrl)) { |
259 | dev_warn(&pdev->dev, "failed to init hdcp: disabled\n"); | |
260 | hdmi->hdcp_ctrl = NULL; | |
261 | } | |
262 | ||
067fef37 RC |
263 | return hdmi; |
264 | ||
265 | fail: | |
266 | if (hdmi) | |
fcda50c8 | 267 | msm_hdmi_destroy(hdmi); |
067fef37 RC |
268 | |
269 | return ERR_PTR(ret); | |
270 | } | |
271 | ||
272 | /* Second part of initialization, the drm/kms level modeset_init, | |
273 | * constructs/initializes mode objects, etc, is called from master | |
274 | * driver (not hdmi sub-device's probe/bind!) | |
275 | * | |
276 | * Any resource (regulator/clk/etc) which could be missing at boot | |
fcda50c8 | 277 | * should be handled in msm_hdmi_init() so that failure happens from |
067fef37 RC |
278 | * hdmi sub-device's probe. |
279 | */ | |
fcda50c8 | 280 | int msm_hdmi_modeset_init(struct hdmi *hdmi, |
067fef37 RC |
281 | struct drm_device *dev, struct drm_encoder *encoder) |
282 | { | |
283 | struct msm_drm_private *priv = dev->dev_private; | |
284 | struct platform_device *pdev = hdmi->pdev; | |
067fef37 RC |
285 | int ret; |
286 | ||
287 | hdmi->dev = dev; | |
288 | hdmi->encoder = encoder; | |
289 | ||
290 | hdmi_audio_infoframe_init(&hdmi->audio.infoframe); | |
291 | ||
fcda50c8 | 292 | hdmi->bridge = msm_hdmi_bridge_init(hdmi); |
a3376e3e RC |
293 | if (IS_ERR(hdmi->bridge)) { |
294 | ret = PTR_ERR(hdmi->bridge); | |
295 | dev_err(dev->dev, "failed to create HDMI bridge: %d\n", ret); | |
296 | hdmi->bridge = NULL; | |
297 | goto fail; | |
298 | } | |
299 | ||
fcda50c8 | 300 | hdmi->connector = msm_hdmi_connector_init(hdmi); |
a3376e3e RC |
301 | if (IS_ERR(hdmi->connector)) { |
302 | ret = PTR_ERR(hdmi->connector); | |
303 | dev_err(dev->dev, "failed to create HDMI connector: %d\n", ret); | |
304 | hdmi->connector = NULL; | |
305 | goto fail; | |
306 | } | |
307 | ||
f6a8eaca RC |
308 | hdmi->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); |
309 | if (hdmi->irq < 0) { | |
310 | ret = hdmi->irq; | |
311 | dev_err(dev->dev, "failed to get irq: %d\n", ret); | |
312 | goto fail; | |
313 | } | |
c8afe684 | 314 | |
f6a8eaca | 315 | ret = devm_request_irq(&pdev->dev, hdmi->irq, |
fcda50c8 | 316 | msm_hdmi_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, |
f6a8eaca RC |
317 | "hdmi_isr", hdmi); |
318 | if (ret < 0) { | |
319 | dev_err(dev->dev, "failed to request IRQ%u: %d\n", | |
320 | hdmi->irq, ret); | |
321 | goto fail; | |
c8afe684 RC |
322 | } |
323 | ||
a3376e3e RC |
324 | encoder->bridge = hdmi->bridge; |
325 | ||
326 | priv->bridges[priv->num_bridges++] = hdmi->bridge; | |
327 | priv->connectors[priv->num_connectors++] = hdmi->connector; | |
328 | ||
c0c0d9ee RC |
329 | platform_set_drvdata(pdev, hdmi); |
330 | ||
067fef37 | 331 | return 0; |
c8afe684 RC |
332 | |
333 | fail: | |
3d3f8b1f | 334 | /* bridge is normally destroyed by drm: */ |
067fef37 | 335 | if (hdmi->bridge) { |
fcda50c8 | 336 | msm_hdmi_bridge_destroy(hdmi->bridge); |
067fef37 RC |
337 | hdmi->bridge = NULL; |
338 | } | |
339 | if (hdmi->connector) { | |
340 | hdmi->connector->funcs->destroy(hdmi->connector); | |
341 | hdmi->connector = NULL; | |
a3376e3e | 342 | } |
c8afe684 | 343 | |
067fef37 | 344 | return ret; |
c8afe684 RC |
345 | } |
346 | ||
347 | /* | |
348 | * The hdmi device: | |
349 | */ | |
350 | ||
5eba5d87 SV |
351 | #define HDMI_CFG(item, entry) \ |
352 | .item ## _names = item ##_names_ ## entry, \ | |
353 | .item ## _cnt = ARRAY_SIZE(item ## _names_ ## entry) | |
354 | ||
0afbe59e SV |
355 | static const char *pwr_reg_names_none[] = {}; |
356 | static const char *hpd_reg_names_none[] = {}; | |
357 | ||
ba3d7bf3 | 358 | static struct hdmi_platform_config hdmi_tx_8660_config; |
5eba5d87 SV |
359 | |
360 | static const char *hpd_reg_names_8960[] = {"core-vdda", "hdmi-mux"}; | |
361 | static const char *hpd_clk_names_8960[] = {"core_clk", "master_iface_clk", "slave_iface_clk"}; | |
362 | ||
363 | static struct hdmi_platform_config hdmi_tx_8960_config = { | |
5eba5d87 SV |
364 | HDMI_CFG(hpd_reg, 8960), |
365 | HDMI_CFG(hpd_clk, 8960), | |
366 | }; | |
367 | ||
368 | static const char *pwr_reg_names_8x74[] = {"core-vdda", "core-vcc"}; | |
369 | static const char *hpd_reg_names_8x74[] = {"hpd-gdsc", "hpd-5v"}; | |
370 | static const char *pwr_clk_names_8x74[] = {"extp_clk", "alt_iface_clk"}; | |
371 | static const char *hpd_clk_names_8x74[] = {"iface_clk", "core_clk", "mdp_core_clk"}; | |
372 | static unsigned long hpd_clk_freq_8x74[] = {0, 19200000, 0}; | |
373 | ||
5cf3a455 | 374 | static struct hdmi_platform_config hdmi_tx_8974_config = { |
5eba5d87 SV |
375 | HDMI_CFG(pwr_reg, 8x74), |
376 | HDMI_CFG(hpd_reg, 8x74), | |
377 | HDMI_CFG(pwr_clk, 8x74), | |
378 | HDMI_CFG(hpd_clk, 8x74), | |
379 | .hpd_freq = hpd_clk_freq_8x74, | |
380 | }; | |
381 | ||
382 | static const char *hpd_reg_names_8084[] = {"hpd-gdsc", "hpd-5v", "hpd-5v-en"}; | |
383 | ||
384 | static struct hdmi_platform_config hdmi_tx_8084_config = { | |
5eba5d87 SV |
385 | HDMI_CFG(pwr_reg, 8x74), |
386 | HDMI_CFG(hpd_reg, 8084), | |
387 | HDMI_CFG(pwr_clk, 8x74), | |
388 | HDMI_CFG(hpd_clk, 8x74), | |
389 | .hpd_freq = hpd_clk_freq_8x74, | |
390 | }; | |
391 | ||
5cf3a455 | 392 | static struct hdmi_platform_config hdmi_tx_8994_config = { |
3a84f846 | 393 | HDMI_CFG(pwr_reg, 8x74), |
0afbe59e SV |
394 | HDMI_CFG(hpd_reg, none), |
395 | HDMI_CFG(pwr_clk, 8x74), | |
396 | HDMI_CFG(hpd_clk, 8x74), | |
397 | .hpd_freq = hpd_clk_freq_8x74, | |
398 | }; | |
399 | ||
400 | static struct hdmi_platform_config hdmi_tx_8996_config = { | |
0afbe59e SV |
401 | HDMI_CFG(pwr_reg, none), |
402 | HDMI_CFG(hpd_reg, none), | |
3a84f846 SV |
403 | HDMI_CFG(pwr_clk, 8x74), |
404 | HDMI_CFG(hpd_clk, 8x74), | |
405 | .hpd_freq = hpd_clk_freq_8x74, | |
406 | }; | |
407 | ||
dc50f782 AT |
408 | static const struct { |
409 | const char *name; | |
410 | const bool output; | |
411 | const int value; | |
412 | const char *label; | |
fcda50c8 | 413 | } msm_hdmi_gpio_pdata[] = { |
dc50f782 AT |
414 | { "qcom,hdmi-tx-ddc-clk", true, 1, "HDMI_DDC_CLK" }, |
415 | { "qcom,hdmi-tx-ddc-data", true, 1, "HDMI_DDC_DATA" }, | |
416 | { "qcom,hdmi-tx-hpd", false, 1, "HDMI_HPD" }, | |
417 | { "qcom,hdmi-tx-mux-en", true, 1, "HDMI_MUX_EN" }, | |
418 | { "qcom,hdmi-tx-mux-sel", true, 0, "HDMI_MUX_SEL" }, | |
419 | { "qcom,hdmi-tx-mux-lpm", true, 1, "HDMI_MUX_LPM" }, | |
420 | }; | |
421 | ||
fcda50c8 | 422 | static int msm_hdmi_get_gpio(struct device_node *of_node, const char *name) |
fc886107 MC |
423 | { |
424 | int gpio = of_get_named_gpio(of_node, name, 0); | |
425 | if (gpio < 0) { | |
426 | char name2[32]; | |
427 | snprintf(name2, sizeof(name2), "%s-gpio", name); | |
428 | gpio = of_get_named_gpio(of_node, name2, 0); | |
429 | if (gpio < 0) { | |
3a84f846 | 430 | DBG("failed to get gpio: %s (%d)", name, gpio); |
fc886107 MC |
431 | gpio = -1; |
432 | } | |
433 | } | |
434 | return gpio; | |
435 | } | |
fc886107 | 436 | |
fcda50c8 | 437 | static int msm_hdmi_bind(struct device *dev, struct device *master, void *data) |
c8afe684 | 438 | { |
d1a717bd RC |
439 | struct drm_device *drm = dev_get_drvdata(master); |
440 | struct msm_drm_private *priv = drm->dev_private; | |
5eba5d87 | 441 | static struct hdmi_platform_config *hdmi_cfg; |
067fef37 | 442 | struct hdmi *hdmi; |
060530f1 | 443 | struct device_node *of_node = dev->of_node; |
dc50f782 | 444 | int i; |
dada25bd | 445 | |
1fd6a441 AT |
446 | hdmi_cfg = (struct hdmi_platform_config *) |
447 | of_device_get_match_data(dev); | |
448 | if (!hdmi_cfg) { | |
449 | dev_err(dev, "unknown hdmi_cfg: %s\n", of_node->name); | |
5eba5d87 | 450 | return -ENXIO; |
41e69778 | 451 | } |
dada25bd | 452 | |
5eba5d87 | 453 | hdmi_cfg->mmio_name = "core_physical"; |
c6a57a50 | 454 | hdmi_cfg->qfprom_mmio_name = "qfprom_physical"; |
dc50f782 AT |
455 | |
456 | for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) { | |
fcda50c8 AB |
457 | hdmi_cfg->gpios[i].num = msm_hdmi_get_gpio(of_node, |
458 | msm_hdmi_gpio_pdata[i].name); | |
459 | hdmi_cfg->gpios[i].output = msm_hdmi_gpio_pdata[i].output; | |
460 | hdmi_cfg->gpios[i].value = msm_hdmi_gpio_pdata[i].value; | |
461 | hdmi_cfg->gpios[i].label = msm_hdmi_gpio_pdata[i].label; | |
dc50f782 | 462 | } |
dada25bd | 463 | |
5eba5d87 SV |
464 | dev->platform_data = hdmi_cfg; |
465 | ||
fcda50c8 | 466 | hdmi = msm_hdmi_init(to_platform_device(dev)); |
067fef37 RC |
467 | if (IS_ERR(hdmi)) |
468 | return PTR_ERR(hdmi); | |
d1a717bd | 469 | priv->hdmi = hdmi; |
5eba5d87 | 470 | |
c8afe684 RC |
471 | return 0; |
472 | } | |
473 | ||
fcda50c8 | 474 | static void msm_hdmi_unbind(struct device *dev, struct device *master, |
060530f1 RC |
475 | void *data) |
476 | { | |
d1a717bd RC |
477 | struct drm_device *drm = dev_get_drvdata(master); |
478 | struct msm_drm_private *priv = drm->dev_private; | |
479 | if (priv->hdmi) { | |
fcda50c8 | 480 | msm_hdmi_destroy(priv->hdmi); |
d1a717bd RC |
481 | priv->hdmi = NULL; |
482 | } | |
060530f1 RC |
483 | } |
484 | ||
fcda50c8 AB |
485 | static const struct component_ops msm_hdmi_ops = { |
486 | .bind = msm_hdmi_bind, | |
487 | .unbind = msm_hdmi_unbind, | |
060530f1 RC |
488 | }; |
489 | ||
fcda50c8 | 490 | static int msm_hdmi_dev_probe(struct platform_device *pdev) |
060530f1 | 491 | { |
fcda50c8 | 492 | return component_add(&pdev->dev, &msm_hdmi_ops); |
060530f1 RC |
493 | } |
494 | ||
fcda50c8 | 495 | static int msm_hdmi_dev_remove(struct platform_device *pdev) |
c8afe684 | 496 | { |
fcda50c8 | 497 | component_del(&pdev->dev, &msm_hdmi_ops); |
c8afe684 RC |
498 | return 0; |
499 | } | |
500 | ||
fcda50c8 | 501 | static const struct of_device_id msm_hdmi_dt_match[] = { |
1fd6a441 AT |
502 | { .compatible = "qcom,hdmi-tx-8996", .data = &hdmi_tx_8996_config }, |
503 | { .compatible = "qcom,hdmi-tx-8994", .data = &hdmi_tx_8994_config }, | |
504 | { .compatible = "qcom,hdmi-tx-8084", .data = &hdmi_tx_8084_config }, | |
505 | { .compatible = "qcom,hdmi-tx-8974", .data = &hdmi_tx_8974_config }, | |
506 | { .compatible = "qcom,hdmi-tx-8960", .data = &hdmi_tx_8960_config }, | |
507 | { .compatible = "qcom,hdmi-tx-8660", .data = &hdmi_tx_8660_config }, | |
508 | {} | |
509 | }; | |
510 | ||
fcda50c8 AB |
511 | static struct platform_driver msm_hdmi_driver = { |
512 | .probe = msm_hdmi_dev_probe, | |
513 | .remove = msm_hdmi_dev_remove, | |
dada25bd RC |
514 | .driver = { |
515 | .name = "hdmi_msm", | |
fcda50c8 | 516 | .of_match_table = msm_hdmi_dt_match, |
dada25bd | 517 | }, |
c8afe684 RC |
518 | }; |
519 | ||
fcda50c8 | 520 | void __init msm_hdmi_register(void) |
c8afe684 | 521 | { |
fcda50c8 AB |
522 | msm_hdmi_phy_driver_register(); |
523 | platform_driver_register(&msm_hdmi_driver); | |
c8afe684 RC |
524 | } |
525 | ||
fcda50c8 | 526 | void __exit msm_hdmi_unregister(void) |
c8afe684 | 527 | { |
fcda50c8 AB |
528 | platform_driver_unregister(&msm_hdmi_driver); |
529 | msm_hdmi_phy_driver_unregister(); | |
c8afe684 | 530 | } |