Commit | Line | Data |
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c8afe684 RC |
1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include <linux/gpio.h> | |
865807d0 | 19 | #include <linux/pinctrl/consumer.h> |
c8afe684 | 20 | |
dd2da6e3 | 21 | #include "msm_kms.h" |
c8afe684 RC |
22 | #include "hdmi.h" |
23 | ||
24 | struct hdmi_connector { | |
a3376e3e RC |
25 | struct drm_connector base; |
26 | struct hdmi *hdmi; | |
dada25bd | 27 | struct work_struct hpd_work; |
c8afe684 RC |
28 | }; |
29 | #define to_hdmi_connector(x) container_of(x, struct hdmi_connector, base) | |
30 | ||
da328552 SV |
31 | static void hdmi_phy_reset(struct hdmi *hdmi) |
32 | { | |
33 | unsigned int val; | |
34 | ||
35 | val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL); | |
36 | ||
37 | if (val & HDMI_PHY_CTRL_SW_RESET_LOW) { | |
38 | /* pull low */ | |
39 | hdmi_write(hdmi, REG_HDMI_PHY_CTRL, | |
40 | val & ~HDMI_PHY_CTRL_SW_RESET); | |
41 | } else { | |
42 | /* pull high */ | |
43 | hdmi_write(hdmi, REG_HDMI_PHY_CTRL, | |
44 | val | HDMI_PHY_CTRL_SW_RESET); | |
45 | } | |
46 | ||
47 | if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) { | |
48 | /* pull low */ | |
49 | hdmi_write(hdmi, REG_HDMI_PHY_CTRL, | |
50 | val & ~HDMI_PHY_CTRL_SW_RESET_PLL); | |
51 | } else { | |
52 | /* pull high */ | |
53 | hdmi_write(hdmi, REG_HDMI_PHY_CTRL, | |
54 | val | HDMI_PHY_CTRL_SW_RESET_PLL); | |
55 | } | |
56 | ||
57 | msleep(100); | |
58 | ||
59 | if (val & HDMI_PHY_CTRL_SW_RESET_LOW) { | |
60 | /* pull high */ | |
61 | hdmi_write(hdmi, REG_HDMI_PHY_CTRL, | |
62 | val | HDMI_PHY_CTRL_SW_RESET); | |
63 | } else { | |
64 | /* pull low */ | |
65 | hdmi_write(hdmi, REG_HDMI_PHY_CTRL, | |
66 | val & ~HDMI_PHY_CTRL_SW_RESET); | |
67 | } | |
68 | ||
69 | if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) { | |
70 | /* pull high */ | |
71 | hdmi_write(hdmi, REG_HDMI_PHY_CTRL, | |
72 | val | HDMI_PHY_CTRL_SW_RESET_PLL); | |
73 | } else { | |
74 | /* pull low */ | |
75 | hdmi_write(hdmi, REG_HDMI_PHY_CTRL, | |
76 | val & ~HDMI_PHY_CTRL_SW_RESET_PLL); | |
77 | } | |
78 | } | |
79 | ||
c8afe684 RC |
80 | static int gpio_config(struct hdmi *hdmi, bool on) |
81 | { | |
5e4eb82f | 82 | struct device *dev = &hdmi->pdev->dev; |
dada25bd | 83 | const struct hdmi_platform_config *config = hdmi->config; |
c8afe684 RC |
84 | int ret; |
85 | ||
86 | if (on) { | |
3a84f846 SV |
87 | if (config->ddc_clk_gpio != -1) { |
88 | ret = gpio_request(config->ddc_clk_gpio, "HDMI_DDC_CLK"); | |
89 | if (ret) { | |
90 | dev_err(dev, "'%s'(%d) gpio_request failed: %d\n", | |
91 | "HDMI_DDC_CLK", config->ddc_clk_gpio, ret); | |
92 | goto error1; | |
93 | } | |
94 | gpio_set_value_cansleep(config->ddc_clk_gpio, 1); | |
c8afe684 | 95 | } |
dada25bd | 96 | |
3a84f846 SV |
97 | if (config->ddc_data_gpio != -1) { |
98 | ret = gpio_request(config->ddc_data_gpio, "HDMI_DDC_DATA"); | |
99 | if (ret) { | |
100 | dev_err(dev, "'%s'(%d) gpio_request failed: %d\n", | |
101 | "HDMI_DDC_DATA", config->ddc_data_gpio, ret); | |
102 | goto error2; | |
103 | } | |
104 | gpio_set_value_cansleep(config->ddc_data_gpio, 1); | |
c8afe684 | 105 | } |
dada25bd | 106 | |
c8afe684 RC |
107 | ret = gpio_request(config->hpd_gpio, "HDMI_HPD"); |
108 | if (ret) { | |
5e4eb82f | 109 | dev_err(dev, "'%s'(%d) gpio_request failed: %d\n", |
c8afe684 RC |
110 | "HDMI_HPD", config->hpd_gpio, ret); |
111 | goto error3; | |
112 | } | |
dada25bd RC |
113 | gpio_direction_input(config->hpd_gpio); |
114 | gpio_set_value_cansleep(config->hpd_gpio, 1); | |
115 | ||
116 | if (config->mux_en_gpio != -1) { | |
117 | ret = gpio_request(config->mux_en_gpio, "HDMI_MUX_EN"); | |
c8afe684 | 118 | if (ret) { |
5e4eb82f | 119 | dev_err(dev, "'%s'(%d) gpio_request failed: %d\n", |
a2fe6cdc | 120 | "HDMI_MUX_EN", config->mux_en_gpio, ret); |
c8afe684 RC |
121 | goto error4; |
122 | } | |
dada25bd RC |
123 | gpio_set_value_cansleep(config->mux_en_gpio, 1); |
124 | } | |
125 | ||
126 | if (config->mux_sel_gpio != -1) { | |
127 | ret = gpio_request(config->mux_sel_gpio, "HDMI_MUX_SEL"); | |
128 | if (ret) { | |
5e4eb82f | 129 | dev_err(dev, "'%s'(%d) gpio_request failed: %d\n", |
dada25bd RC |
130 | "HDMI_MUX_SEL", config->mux_sel_gpio, ret); |
131 | goto error5; | |
132 | } | |
133 | gpio_set_value_cansleep(config->mux_sel_gpio, 0); | |
c8afe684 | 134 | } |
1930f38a BG |
135 | |
136 | if (config->mux_lpm_gpio != -1) { | |
137 | ret = gpio_request(config->mux_lpm_gpio, | |
138 | "HDMI_MUX_LPM"); | |
139 | if (ret) { | |
5e4eb82f | 140 | dev_err(dev, |
1930f38a BG |
141 | "'%s'(%d) gpio_request failed: %d\n", |
142 | "HDMI_MUX_LPM", | |
143 | config->mux_lpm_gpio, ret); | |
144 | goto error6; | |
145 | } | |
146 | gpio_set_value_cansleep(config->mux_lpm_gpio, 1); | |
147 | } | |
c8afe684 RC |
148 | DBG("gpio on"); |
149 | } else { | |
3a84f846 SV |
150 | if (config->ddc_clk_gpio != -1) |
151 | gpio_free(config->ddc_clk_gpio); | |
152 | ||
153 | if (config->ddc_data_gpio != -1) | |
154 | gpio_free(config->ddc_data_gpio); | |
155 | ||
c8afe684 RC |
156 | gpio_free(config->hpd_gpio); |
157 | ||
dada25bd RC |
158 | if (config->mux_en_gpio != -1) { |
159 | gpio_set_value_cansleep(config->mux_en_gpio, 0); | |
160 | gpio_free(config->mux_en_gpio); | |
161 | } | |
162 | ||
163 | if (config->mux_sel_gpio != -1) { | |
164 | gpio_set_value_cansleep(config->mux_sel_gpio, 1); | |
165 | gpio_free(config->mux_sel_gpio); | |
c8afe684 | 166 | } |
1930f38a BG |
167 | |
168 | if (config->mux_lpm_gpio != -1) { | |
169 | gpio_set_value_cansleep(config->mux_lpm_gpio, 0); | |
170 | gpio_free(config->mux_lpm_gpio); | |
171 | } | |
c8afe684 RC |
172 | DBG("gpio off"); |
173 | } | |
174 | ||
175 | return 0; | |
176 | ||
1930f38a BG |
177 | error6: |
178 | if (config->mux_sel_gpio != -1) | |
179 | gpio_free(config->mux_sel_gpio); | |
dada25bd RC |
180 | error5: |
181 | if (config->mux_en_gpio != -1) | |
182 | gpio_free(config->mux_en_gpio); | |
c8afe684 RC |
183 | error4: |
184 | gpio_free(config->hpd_gpio); | |
185 | error3: | |
3a84f846 SV |
186 | if (config->ddc_data_gpio != -1) |
187 | gpio_free(config->ddc_data_gpio); | |
c8afe684 | 188 | error2: |
3a84f846 SV |
189 | if (config->ddc_clk_gpio != -1) |
190 | gpio_free(config->ddc_clk_gpio); | |
c8afe684 RC |
191 | error1: |
192 | return ret; | |
193 | } | |
194 | ||
195 | static int hpd_enable(struct hdmi_connector *hdmi_connector) | |
196 | { | |
a3376e3e | 197 | struct hdmi *hdmi = hdmi_connector->hdmi; |
dada25bd | 198 | const struct hdmi_platform_config *config = hdmi->config; |
5e4eb82f | 199 | struct device *dev = &hdmi->pdev->dev; |
c8afe684 | 200 | uint32_t hpd_ctrl; |
dada25bd | 201 | int i, ret; |
c6a57a50 | 202 | unsigned long flags; |
c8afe684 | 203 | |
e6d7a16f JW |
204 | for (i = 0; i < config->hpd_reg_cnt; i++) { |
205 | ret = regulator_enable(hdmi->hpd_regs[i]); | |
206 | if (ret) { | |
5e4eb82f | 207 | dev_err(dev, "failed to enable hpd regulator: %s (%d)\n", |
e6d7a16f JW |
208 | config->hpd_reg_names[i], ret); |
209 | goto fail; | |
210 | } | |
211 | } | |
212 | ||
865807d0 SV |
213 | ret = pinctrl_pm_select_default_state(dev); |
214 | if (ret) { | |
215 | dev_err(dev, "pinctrl state chg failed: %d\n", ret); | |
216 | goto fail; | |
217 | } | |
218 | ||
c8afe684 RC |
219 | ret = gpio_config(hdmi, true); |
220 | if (ret) { | |
5e4eb82f | 221 | dev_err(dev, "failed to configure GPIOs: %d\n", ret); |
c8afe684 RC |
222 | goto fail; |
223 | } | |
224 | ||
dada25bd | 225 | for (i = 0; i < config->hpd_clk_cnt; i++) { |
b77f47e7 SV |
226 | if (config->hpd_freq && config->hpd_freq[i]) { |
227 | ret = clk_set_rate(hdmi->hpd_clks[i], | |
228 | config->hpd_freq[i]); | |
229 | if (ret) | |
5e4eb82f | 230 | dev_warn(dev, "failed to set clk %s (%d)\n", |
b77f47e7 SV |
231 | config->hpd_clk_names[i], ret); |
232 | } | |
233 | ||
dada25bd RC |
234 | ret = clk_prepare_enable(hdmi->hpd_clks[i]); |
235 | if (ret) { | |
5e4eb82f | 236 | dev_err(dev, "failed to enable hpd clk: %s (%d)\n", |
dada25bd RC |
237 | config->hpd_clk_names[i], ret); |
238 | goto fail; | |
239 | } | |
c8afe684 RC |
240 | } |
241 | ||
c8afe684 | 242 | hdmi_set_mode(hdmi, false); |
da328552 | 243 | hdmi_phy_reset(hdmi); |
c8afe684 RC |
244 | hdmi_set_mode(hdmi, true); |
245 | ||
246 | hdmi_write(hdmi, REG_HDMI_USEC_REFTIMER, 0x0001001b); | |
247 | ||
248 | /* enable HPD events: */ | |
249 | hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, | |
250 | HDMI_HPD_INT_CTRL_INT_CONNECT | | |
251 | HDMI_HPD_INT_CTRL_INT_EN); | |
252 | ||
253 | /* set timeout to 4.1ms (max) for hardware debounce */ | |
c6a57a50 | 254 | spin_lock_irqsave(&hdmi->reg_lock, flags); |
c8afe684 RC |
255 | hpd_ctrl = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); |
256 | hpd_ctrl |= HDMI_HPD_CTRL_TIMEOUT(0x1fff); | |
257 | ||
258 | /* Toggle HPD circuit to trigger HPD sense */ | |
259 | hdmi_write(hdmi, REG_HDMI_HPD_CTRL, | |
260 | ~HDMI_HPD_CTRL_ENABLE & hpd_ctrl); | |
261 | hdmi_write(hdmi, REG_HDMI_HPD_CTRL, | |
262 | HDMI_HPD_CTRL_ENABLE | hpd_ctrl); | |
c6a57a50 | 263 | spin_unlock_irqrestore(&hdmi->reg_lock, flags); |
c8afe684 RC |
264 | |
265 | return 0; | |
266 | ||
267 | fail: | |
268 | return ret; | |
269 | } | |
270 | ||
e6d7a16f | 271 | static void hdp_disable(struct hdmi_connector *hdmi_connector) |
c8afe684 | 272 | { |
a3376e3e | 273 | struct hdmi *hdmi = hdmi_connector->hdmi; |
dada25bd | 274 | const struct hdmi_platform_config *config = hdmi->config; |
5e4eb82f | 275 | struct device *dev = &hdmi->pdev->dev; |
dada25bd | 276 | int i, ret = 0; |
c8afe684 RC |
277 | |
278 | /* Disable HPD interrupt */ | |
279 | hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, 0); | |
280 | ||
281 | hdmi_set_mode(hdmi, false); | |
282 | ||
dada25bd RC |
283 | for (i = 0; i < config->hpd_clk_cnt; i++) |
284 | clk_disable_unprepare(hdmi->hpd_clks[i]); | |
c8afe684 RC |
285 | |
286 | ret = gpio_config(hdmi, false); | |
e6d7a16f | 287 | if (ret) |
5e4eb82f | 288 | dev_warn(dev, "failed to unconfigure GPIOs: %d\n", ret); |
c8afe684 | 289 | |
865807d0 SV |
290 | ret = pinctrl_pm_select_sleep_state(dev); |
291 | if (ret) | |
292 | dev_warn(dev, "pinctrl state chg failed: %d\n", ret); | |
293 | ||
e6d7a16f JW |
294 | for (i = 0; i < config->hpd_reg_cnt; i++) { |
295 | ret = regulator_disable(hdmi->hpd_regs[i]); | |
296 | if (ret) | |
5e4eb82f | 297 | dev_warn(dev, "failed to disable hpd regulator: %s (%d)\n", |
e6d7a16f JW |
298 | config->hpd_reg_names[i], ret); |
299 | } | |
c8afe684 RC |
300 | } |
301 | ||
dada25bd RC |
302 | static void |
303 | hotplug_work(struct work_struct *work) | |
304 | { | |
305 | struct hdmi_connector *hdmi_connector = | |
306 | container_of(work, struct hdmi_connector, hpd_work); | |
307 | struct drm_connector *connector = &hdmi_connector->base; | |
308 | drm_helper_hpd_irq_event(connector->dev); | |
309 | } | |
310 | ||
c8afe684 RC |
311 | void hdmi_connector_irq(struct drm_connector *connector) |
312 | { | |
a3376e3e RC |
313 | struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); |
314 | struct hdmi *hdmi = hdmi_connector->hdmi; | |
c8afe684 RC |
315 | uint32_t hpd_int_status, hpd_int_ctrl; |
316 | ||
317 | /* Process HPD: */ | |
318 | hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS); | |
319 | hpd_int_ctrl = hdmi_read(hdmi, REG_HDMI_HPD_INT_CTRL); | |
320 | ||
321 | if ((hpd_int_ctrl & HDMI_HPD_INT_CTRL_INT_EN) && | |
322 | (hpd_int_status & HDMI_HPD_INT_STATUS_INT)) { | |
323 | bool detected = !!(hpd_int_status & HDMI_HPD_INT_STATUS_CABLE_DETECTED); | |
324 | ||
ff2f974e | 325 | /* ack & disable (temporarily) HPD events: */ |
c8afe684 | 326 | hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, |
ff2f974e JW |
327 | HDMI_HPD_INT_CTRL_INT_ACK); |
328 | ||
329 | DBG("status=%04x, ctrl=%04x", hpd_int_status, hpd_int_ctrl); | |
c8afe684 | 330 | |
c8afe684 RC |
331 | /* detect disconnect if we are connected or visa versa: */ |
332 | hpd_int_ctrl = HDMI_HPD_INT_CTRL_INT_EN; | |
333 | if (!detected) | |
334 | hpd_int_ctrl |= HDMI_HPD_INT_CTRL_INT_CONNECT; | |
335 | hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, hpd_int_ctrl); | |
dada25bd | 336 | |
c6a57a50 | 337 | queue_work(hdmi->workq, &hdmi_connector->hpd_work); |
c8afe684 RC |
338 | } |
339 | } | |
340 | ||
3189650d RC |
341 | static enum drm_connector_status detect_reg(struct hdmi *hdmi) |
342 | { | |
343 | uint32_t hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS); | |
344 | return (hpd_int_status & HDMI_HPD_INT_STATUS_CABLE_DETECTED) ? | |
345 | connector_status_connected : connector_status_disconnected; | |
346 | } | |
347 | ||
348 | static enum drm_connector_status detect_gpio(struct hdmi *hdmi) | |
349 | { | |
350 | const struct hdmi_platform_config *config = hdmi->config; | |
351 | return gpio_get_value(config->hpd_gpio) ? | |
352 | connector_status_connected : | |
353 | connector_status_disconnected; | |
354 | } | |
355 | ||
c8afe684 RC |
356 | static enum drm_connector_status hdmi_connector_detect( |
357 | struct drm_connector *connector, bool force) | |
358 | { | |
a3376e3e RC |
359 | struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); |
360 | struct hdmi *hdmi = hdmi_connector->hdmi; | |
3189650d | 361 | enum drm_connector_status stat_gpio, stat_reg; |
c8afe684 RC |
362 | int retry = 20; |
363 | ||
3189650d RC |
364 | do { |
365 | stat_gpio = detect_gpio(hdmi); | |
366 | stat_reg = detect_reg(hdmi); | |
c8afe684 | 367 | |
3189650d | 368 | if (stat_gpio == stat_reg) |
dada25bd | 369 | break; |
3189650d | 370 | |
c8afe684 | 371 | mdelay(10); |
3189650d RC |
372 | } while (--retry); |
373 | ||
374 | /* the status we get from reading gpio seems to be more reliable, | |
375 | * so trust that one the most if we didn't manage to get hdmi and | |
376 | * gpio status to agree: | |
377 | */ | |
378 | if (stat_gpio != stat_reg) { | |
379 | DBG("HDMI_HPD_INT_STATUS tells us: %d", stat_reg); | |
380 | DBG("hpd gpio tells us: %d", stat_gpio); | |
c8afe684 RC |
381 | } |
382 | ||
3189650d | 383 | return stat_gpio; |
c8afe684 RC |
384 | } |
385 | ||
386 | static void hdmi_connector_destroy(struct drm_connector *connector) | |
387 | { | |
a3376e3e | 388 | struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); |
c8afe684 RC |
389 | |
390 | hdp_disable(hdmi_connector); | |
391 | ||
34ea3d38 | 392 | drm_connector_unregister(connector); |
c8afe684 RC |
393 | drm_connector_cleanup(connector); |
394 | ||
c8afe684 RC |
395 | kfree(hdmi_connector); |
396 | } | |
397 | ||
398 | static int hdmi_connector_get_modes(struct drm_connector *connector) | |
399 | { | |
a3376e3e RC |
400 | struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); |
401 | struct hdmi *hdmi = hdmi_connector->hdmi; | |
c8afe684 RC |
402 | struct edid *edid; |
403 | uint32_t hdmi_ctrl; | |
404 | int ret = 0; | |
405 | ||
406 | hdmi_ctrl = hdmi_read(hdmi, REG_HDMI_CTRL); | |
407 | hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl | HDMI_CTRL_ENABLE); | |
408 | ||
409 | edid = drm_get_edid(connector, hdmi->i2c); | |
410 | ||
411 | hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl); | |
412 | ||
c6a57a50 | 413 | hdmi->hdmi_mode = drm_detect_hdmi_monitor(edid); |
c8afe684 RC |
414 | drm_mode_connector_update_edid_property(connector, edid); |
415 | ||
416 | if (edid) { | |
417 | ret = drm_add_edid_modes(connector, edid); | |
418 | kfree(edid); | |
419 | } | |
420 | ||
421 | return ret; | |
422 | } | |
423 | ||
424 | static int hdmi_connector_mode_valid(struct drm_connector *connector, | |
425 | struct drm_display_mode *mode) | |
426 | { | |
a3376e3e | 427 | struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); |
dada25bd RC |
428 | struct hdmi *hdmi = hdmi_connector->hdmi; |
429 | const struct hdmi_platform_config *config = hdmi->config; | |
c8afe684 RC |
430 | struct msm_drm_private *priv = connector->dev->dev_private; |
431 | struct msm_kms *kms = priv->kms; | |
432 | long actual, requested; | |
433 | ||
434 | requested = 1000 * mode->clock; | |
435 | actual = kms->funcs->round_pixclk(kms, | |
a3376e3e | 436 | requested, hdmi_connector->hdmi->encoder); |
c8afe684 | 437 | |
dada25bd RC |
438 | /* for mdp5/apq8074, we manage our own pixel clk (as opposed to |
439 | * mdp4/dtv stuff where pixel clk is assigned to mdp/encoder | |
440 | * instead): | |
441 | */ | |
442 | if (config->pwr_clk_cnt > 0) | |
443 | actual = clk_round_rate(hdmi->pwr_clks[0], actual); | |
444 | ||
c8afe684 RC |
445 | DBG("requested=%ld, actual=%ld", requested, actual); |
446 | ||
447 | if (actual != requested) | |
448 | return MODE_CLOCK_RANGE; | |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
a3376e3e RC |
453 | static struct drm_encoder * |
454 | hdmi_connector_best_encoder(struct drm_connector *connector) | |
455 | { | |
456 | struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); | |
457 | return hdmi_connector->hdmi->encoder; | |
458 | } | |
459 | ||
c8afe684 | 460 | static const struct drm_connector_funcs hdmi_connector_funcs = { |
0b776d45 | 461 | .dpms = drm_atomic_helper_connector_dpms, |
c8afe684 RC |
462 | .detect = hdmi_connector_detect, |
463 | .fill_modes = drm_helper_probe_single_connector_modes, | |
464 | .destroy = hdmi_connector_destroy, | |
3e7849ef RC |
465 | .reset = drm_atomic_helper_connector_reset, |
466 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, | |
467 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
c8afe684 RC |
468 | }; |
469 | ||
470 | static const struct drm_connector_helper_funcs hdmi_connector_helper_funcs = { | |
471 | .get_modes = hdmi_connector_get_modes, | |
472 | .mode_valid = hdmi_connector_mode_valid, | |
a3376e3e | 473 | .best_encoder = hdmi_connector_best_encoder, |
c8afe684 RC |
474 | }; |
475 | ||
476 | /* initialize connector */ | |
a3376e3e | 477 | struct drm_connector *hdmi_connector_init(struct hdmi *hdmi) |
c8afe684 RC |
478 | { |
479 | struct drm_connector *connector = NULL; | |
480 | struct hdmi_connector *hdmi_connector; | |
481 | int ret; | |
482 | ||
483 | hdmi_connector = kzalloc(sizeof(*hdmi_connector), GFP_KERNEL); | |
484 | if (!hdmi_connector) { | |
485 | ret = -ENOMEM; | |
486 | goto fail; | |
487 | } | |
488 | ||
d1a717bd | 489 | hdmi_connector->hdmi = hdmi; |
dada25bd | 490 | INIT_WORK(&hdmi_connector->hpd_work, hotplug_work); |
a3376e3e RC |
491 | |
492 | connector = &hdmi_connector->base; | |
c8afe684 | 493 | |
a3376e3e | 494 | drm_connector_init(hdmi->dev, connector, &hdmi_connector_funcs, |
c8afe684 RC |
495 | DRM_MODE_CONNECTOR_HDMIA); |
496 | drm_connector_helper_add(connector, &hdmi_connector_helper_funcs); | |
497 | ||
3189650d RC |
498 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
499 | DRM_CONNECTOR_POLL_DISCONNECT; | |
c8afe684 | 500 | |
cddfaebd | 501 | connector->interlace_allowed = 0; |
c8afe684 RC |
502 | connector->doublescan_allowed = 0; |
503 | ||
34ea3d38 | 504 | drm_connector_register(connector); |
c8afe684 | 505 | |
c8afe684 RC |
506 | ret = hpd_enable(hdmi_connector); |
507 | if (ret) { | |
5e4eb82f | 508 | dev_err(&hdmi->pdev->dev, "failed to enable HPD: %d\n", ret); |
c8afe684 RC |
509 | goto fail; |
510 | } | |
511 | ||
a3376e3e | 512 | drm_mode_connector_attach_encoder(connector, hdmi->encoder); |
c8afe684 RC |
513 | |
514 | return connector; | |
515 | ||
516 | fail: | |
517 | if (connector) | |
518 | hdmi_connector_destroy(connector); | |
519 | ||
520 | return ERR_PTR(ret); | |
521 | } |