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c8afe684 RC |
1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include "msm_drv.h" | |
7198e6b0 | 19 | #include "msm_gpu.h" |
dd2da6e3 | 20 | #include "msm_kms.h" |
c8afe684 | 21 | |
c8afe684 RC |
22 | static void msm_fb_output_poll_changed(struct drm_device *dev) |
23 | { | |
24 | struct msm_drm_private *priv = dev->dev_private; | |
25 | if (priv->fbdev) | |
26 | drm_fb_helper_hotplug_event(priv->fbdev); | |
27 | } | |
28 | ||
29 | static const struct drm_mode_config_funcs mode_config_funcs = { | |
30 | .fb_create = msm_framebuffer_create, | |
31 | .output_poll_changed = msm_fb_output_poll_changed, | |
b4274fbe | 32 | .atomic_check = msm_atomic_check, |
cf3a7e4c | 33 | .atomic_commit = msm_atomic_commit, |
c8afe684 RC |
34 | }; |
35 | ||
871d812a | 36 | int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu) |
c8afe684 RC |
37 | { |
38 | struct msm_drm_private *priv = dev->dev_private; | |
871d812a | 39 | int idx = priv->num_mmus++; |
c8afe684 | 40 | |
871d812a | 41 | if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus))) |
c8afe684 RC |
42 | return -EINVAL; |
43 | ||
871d812a | 44 | priv->mmus[idx] = mmu; |
c8afe684 RC |
45 | |
46 | return idx; | |
47 | } | |
48 | ||
c8afe684 RC |
49 | #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING |
50 | static bool reglog = false; | |
51 | MODULE_PARM_DESC(reglog, "Enable register read/write logging"); | |
52 | module_param(reglog, bool, 0600); | |
53 | #else | |
54 | #define reglog 0 | |
55 | #endif | |
56 | ||
a9ee34b7 | 57 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
e90dfec7 RC |
58 | static bool fbdev = true; |
59 | MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); | |
60 | module_param(fbdev, bool, 0600); | |
61 | #endif | |
62 | ||
3a10ba8c | 63 | static char *vram = "16m"; |
871d812a RC |
64 | MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU"); |
65 | module_param(vram, charp, 0); | |
66 | ||
060530f1 RC |
67 | /* |
68 | * Util/helpers: | |
69 | */ | |
70 | ||
c8afe684 RC |
71 | void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, |
72 | const char *dbgname) | |
73 | { | |
74 | struct resource *res; | |
75 | unsigned long size; | |
76 | void __iomem *ptr; | |
77 | ||
78 | if (name) | |
79 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
80 | else | |
81 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
82 | ||
83 | if (!res) { | |
84 | dev_err(&pdev->dev, "failed to get memory resource: %s\n", name); | |
85 | return ERR_PTR(-EINVAL); | |
86 | } | |
87 | ||
88 | size = resource_size(res); | |
89 | ||
90 | ptr = devm_ioremap_nocache(&pdev->dev, res->start, size); | |
91 | if (!ptr) { | |
92 | dev_err(&pdev->dev, "failed to ioremap: %s\n", name); | |
93 | return ERR_PTR(-ENOMEM); | |
94 | } | |
95 | ||
96 | if (reglog) | |
fc99f97a | 97 | printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size); |
c8afe684 RC |
98 | |
99 | return ptr; | |
100 | } | |
101 | ||
102 | void msm_writel(u32 data, void __iomem *addr) | |
103 | { | |
104 | if (reglog) | |
fc99f97a | 105 | printk(KERN_DEBUG "IO:W %p %08x\n", addr, data); |
c8afe684 RC |
106 | writel(data, addr); |
107 | } | |
108 | ||
109 | u32 msm_readl(const void __iomem *addr) | |
110 | { | |
111 | u32 val = readl(addr); | |
112 | if (reglog) | |
fc99f97a | 113 | printk(KERN_ERR "IO:R %p %08x\n", addr, val); |
c8afe684 RC |
114 | return val; |
115 | } | |
116 | ||
78b1d470 HL |
117 | struct vblank_event { |
118 | struct list_head node; | |
119 | int crtc_id; | |
120 | bool enable; | |
121 | }; | |
122 | ||
123 | static void vblank_ctrl_worker(struct work_struct *work) | |
124 | { | |
125 | struct msm_vblank_ctrl *vbl_ctrl = container_of(work, | |
126 | struct msm_vblank_ctrl, work); | |
127 | struct msm_drm_private *priv = container_of(vbl_ctrl, | |
128 | struct msm_drm_private, vblank_ctrl); | |
129 | struct msm_kms *kms = priv->kms; | |
130 | struct vblank_event *vbl_ev, *tmp; | |
131 | unsigned long flags; | |
132 | ||
133 | spin_lock_irqsave(&vbl_ctrl->lock, flags); | |
134 | list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) { | |
135 | list_del(&vbl_ev->node); | |
136 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); | |
137 | ||
138 | if (vbl_ev->enable) | |
139 | kms->funcs->enable_vblank(kms, | |
140 | priv->crtcs[vbl_ev->crtc_id]); | |
141 | else | |
142 | kms->funcs->disable_vblank(kms, | |
143 | priv->crtcs[vbl_ev->crtc_id]); | |
144 | ||
145 | kfree(vbl_ev); | |
146 | ||
147 | spin_lock_irqsave(&vbl_ctrl->lock, flags); | |
148 | } | |
149 | ||
150 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); | |
151 | } | |
152 | ||
153 | static int vblank_ctrl_queue_work(struct msm_drm_private *priv, | |
154 | int crtc_id, bool enable) | |
155 | { | |
156 | struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl; | |
157 | struct vblank_event *vbl_ev; | |
158 | unsigned long flags; | |
159 | ||
160 | vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC); | |
161 | if (!vbl_ev) | |
162 | return -ENOMEM; | |
163 | ||
164 | vbl_ev->crtc_id = crtc_id; | |
165 | vbl_ev->enable = enable; | |
166 | ||
167 | spin_lock_irqsave(&vbl_ctrl->lock, flags); | |
168 | list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list); | |
169 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); | |
170 | ||
171 | queue_work(priv->wq, &vbl_ctrl->work); | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
c8afe684 RC |
176 | /* |
177 | * DRM operations: | |
178 | */ | |
179 | ||
180 | static int msm_unload(struct drm_device *dev) | |
181 | { | |
182 | struct msm_drm_private *priv = dev->dev_private; | |
183 | struct msm_kms *kms = priv->kms; | |
7198e6b0 | 184 | struct msm_gpu *gpu = priv->gpu; |
78b1d470 HL |
185 | struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl; |
186 | struct vblank_event *vbl_ev, *tmp; | |
187 | ||
188 | /* We must cancel and cleanup any pending vblank enable/disable | |
189 | * work before drm_irq_uninstall() to avoid work re-enabling an | |
190 | * irq after uninstall has disabled it. | |
191 | */ | |
192 | cancel_work_sync(&vbl_ctrl->work); | |
193 | list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) { | |
194 | list_del(&vbl_ev->node); | |
195 | kfree(vbl_ev); | |
196 | } | |
c8afe684 RC |
197 | |
198 | drm_kms_helper_poll_fini(dev); | |
199 | drm_mode_config_cleanup(dev); | |
200 | drm_vblank_cleanup(dev); | |
201 | ||
202 | pm_runtime_get_sync(dev->dev); | |
203 | drm_irq_uninstall(dev); | |
204 | pm_runtime_put_sync(dev->dev); | |
205 | ||
206 | flush_workqueue(priv->wq); | |
207 | destroy_workqueue(priv->wq); | |
208 | ||
209 | if (kms) { | |
210 | pm_runtime_disable(dev->dev); | |
211 | kms->funcs->destroy(kms); | |
212 | } | |
213 | ||
7198e6b0 RC |
214 | if (gpu) { |
215 | mutex_lock(&dev->struct_mutex); | |
216 | gpu->funcs->pm_suspend(gpu); | |
7198e6b0 | 217 | mutex_unlock(&dev->struct_mutex); |
774449eb | 218 | gpu->funcs->destroy(gpu); |
7198e6b0 | 219 | } |
c8afe684 | 220 | |
871d812a RC |
221 | if (priv->vram.paddr) { |
222 | DEFINE_DMA_ATTRS(attrs); | |
223 | dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); | |
224 | drm_mm_takedown(&priv->vram.mm); | |
225 | dma_free_attrs(dev->dev, priv->vram.size, NULL, | |
226 | priv->vram.paddr, &attrs); | |
227 | } | |
228 | ||
060530f1 RC |
229 | component_unbind_all(dev->dev, dev); |
230 | ||
c8afe684 RC |
231 | dev->dev_private = NULL; |
232 | ||
233 | kfree(priv); | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
06c0dd96 RC |
238 | static int get_mdp_ver(struct platform_device *pdev) |
239 | { | |
06c0dd96 | 240 | struct device *dev = &pdev->dev; |
e9fbdaf2 AT |
241 | |
242 | return (int) (unsigned long) of_device_get_match_data(dev); | |
06c0dd96 RC |
243 | } |
244 | ||
072f1f91 RC |
245 | #include <linux/of_address.h> |
246 | ||
5bf9c0b6 | 247 | static int msm_init_vram(struct drm_device *dev) |
c8afe684 | 248 | { |
5bf9c0b6 | 249 | struct msm_drm_private *priv = dev->dev_private; |
e9fbdaf2 | 250 | struct device_node *node; |
072f1f91 RC |
251 | unsigned long size = 0; |
252 | int ret = 0; | |
253 | ||
072f1f91 RC |
254 | /* In the device-tree world, we could have a 'memory-region' |
255 | * phandle, which gives us a link to our "vram". Allocating | |
256 | * is all nicely abstracted behind the dma api, but we need | |
257 | * to know the entire size to allocate it all in one go. There | |
258 | * are two cases: | |
259 | * 1) device with no IOMMU, in which case we need exclusive | |
260 | * access to a VRAM carveout big enough for all gpu | |
261 | * buffers | |
262 | * 2) device with IOMMU, but where the bootloader puts up | |
263 | * a splash screen. In this case, the VRAM carveout | |
264 | * need only be large enough for fbdev fb. But we need | |
265 | * exclusive access to the buffer to avoid the kernel | |
266 | * using those pages for other purposes (which appears | |
267 | * as corruption on screen before we have a chance to | |
268 | * load and do initial modeset) | |
269 | */ | |
072f1f91 RC |
270 | |
271 | node = of_parse_phandle(dev->dev->of_node, "memory-region", 0); | |
272 | if (node) { | |
273 | struct resource r; | |
274 | ret = of_address_to_resource(node, 0, &r); | |
275 | if (ret) | |
276 | return ret; | |
277 | size = r.end - r.start; | |
fc99f97a | 278 | DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start); |
c8afe684 | 279 | |
e9fbdaf2 AT |
280 | /* if we have no IOMMU, then we need to use carveout allocator. |
281 | * Grab the entire CMA chunk carved out in early startup in | |
282 | * mach-msm: | |
283 | */ | |
284 | } else if (!iommu_present(&platform_bus_type)) { | |
072f1f91 RC |
285 | DRM_INFO("using %s VRAM carveout\n", vram); |
286 | size = memparse(vram, NULL); | |
287 | } | |
288 | ||
289 | if (size) { | |
871d812a | 290 | DEFINE_DMA_ATTRS(attrs); |
871d812a RC |
291 | void *p; |
292 | ||
871d812a RC |
293 | priv->vram.size = size; |
294 | ||
295 | drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); | |
296 | ||
297 | dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); | |
298 | dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs); | |
299 | ||
300 | /* note that for no-kernel-mapping, the vaddr returned | |
301 | * is bogus, but non-null if allocation succeeded: | |
302 | */ | |
303 | p = dma_alloc_attrs(dev->dev, size, | |
543d3011 | 304 | &priv->vram.paddr, GFP_KERNEL, &attrs); |
871d812a RC |
305 | if (!p) { |
306 | dev_err(dev->dev, "failed to allocate VRAM\n"); | |
307 | priv->vram.paddr = 0; | |
5bf9c0b6 | 308 | return -ENOMEM; |
871d812a RC |
309 | } |
310 | ||
311 | dev_info(dev->dev, "VRAM: %08x->%08x\n", | |
312 | (uint32_t)priv->vram.paddr, | |
313 | (uint32_t)(priv->vram.paddr + size)); | |
314 | } | |
315 | ||
072f1f91 | 316 | return ret; |
5bf9c0b6 RC |
317 | } |
318 | ||
319 | static int msm_load(struct drm_device *dev, unsigned long flags) | |
320 | { | |
321 | struct platform_device *pdev = dev->platformdev; | |
322 | struct msm_drm_private *priv; | |
323 | struct msm_kms *kms; | |
324 | int ret; | |
325 | ||
326 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
327 | if (!priv) { | |
328 | dev_err(dev->dev, "failed to allocate private data\n"); | |
329 | return -ENOMEM; | |
330 | } | |
331 | ||
332 | dev->dev_private = priv; | |
333 | ||
334 | priv->wq = alloc_ordered_workqueue("msm", 0); | |
335 | init_waitqueue_head(&priv->fence_event); | |
336 | init_waitqueue_head(&priv->pending_crtcs_event); | |
337 | ||
338 | INIT_LIST_HEAD(&priv->inactive_list); | |
339 | INIT_LIST_HEAD(&priv->fence_cbs); | |
78b1d470 HL |
340 | INIT_LIST_HEAD(&priv->vblank_ctrl.event_list); |
341 | INIT_WORK(&priv->vblank_ctrl.work, vblank_ctrl_worker); | |
342 | spin_lock_init(&priv->vblank_ctrl.lock); | |
5bf9c0b6 RC |
343 | |
344 | drm_mode_config_init(dev); | |
345 | ||
060530f1 RC |
346 | platform_set_drvdata(pdev, dev); |
347 | ||
348 | /* Bind all our sub-components: */ | |
349 | ret = component_bind_all(dev->dev, dev); | |
350 | if (ret) | |
351 | return ret; | |
352 | ||
13f15565 RC |
353 | ret = msm_init_vram(dev); |
354 | if (ret) | |
355 | goto fail; | |
356 | ||
06c0dd96 RC |
357 | switch (get_mdp_ver(pdev)) { |
358 | case 4: | |
359 | kms = mdp4_kms_init(dev); | |
360 | break; | |
361 | case 5: | |
362 | kms = mdp5_kms_init(dev); | |
363 | break; | |
364 | default: | |
365 | kms = ERR_PTR(-ENODEV); | |
366 | break; | |
367 | } | |
368 | ||
c8afe684 RC |
369 | if (IS_ERR(kms)) { |
370 | /* | |
371 | * NOTE: once we have GPU support, having no kms should not | |
372 | * be considered fatal.. ideally we would still support gpu | |
373 | * and (for example) use dmabuf/prime to share buffers with | |
374 | * imx drm driver on iMX5 | |
375 | */ | |
376 | dev_err(dev->dev, "failed to load kms\n"); | |
e4826a94 | 377 | ret = PTR_ERR(kms); |
c8afe684 RC |
378 | goto fail; |
379 | } | |
380 | ||
381 | priv->kms = kms; | |
382 | ||
383 | if (kms) { | |
384 | pm_runtime_enable(dev->dev); | |
385 | ret = kms->funcs->hw_init(kms); | |
386 | if (ret) { | |
387 | dev_err(dev->dev, "kms hw init failed: %d\n", ret); | |
388 | goto fail; | |
389 | } | |
390 | } | |
391 | ||
c8afe684 RC |
392 | dev->mode_config.funcs = &mode_config_funcs; |
393 | ||
d65bd0e4 | 394 | ret = drm_vblank_init(dev, priv->num_crtcs); |
c8afe684 RC |
395 | if (ret < 0) { |
396 | dev_err(dev->dev, "failed to initialize vblank\n"); | |
397 | goto fail; | |
398 | } | |
399 | ||
400 | pm_runtime_get_sync(dev->dev); | |
bb0f1b5c | 401 | ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0)); |
c8afe684 RC |
402 | pm_runtime_put_sync(dev->dev); |
403 | if (ret < 0) { | |
404 | dev_err(dev->dev, "failed to install IRQ handler\n"); | |
405 | goto fail; | |
406 | } | |
407 | ||
cf3a7e4c RC |
408 | drm_mode_config_reset(dev); |
409 | ||
a9ee34b7 | 410 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
e90dfec7 RC |
411 | if (fbdev) |
412 | priv->fbdev = msm_fbdev_init(dev); | |
c8afe684 RC |
413 | #endif |
414 | ||
a7d3c950 RC |
415 | ret = msm_debugfs_late_init(dev); |
416 | if (ret) | |
417 | goto fail; | |
418 | ||
c8afe684 RC |
419 | drm_kms_helper_poll_init(dev); |
420 | ||
421 | return 0; | |
422 | ||
423 | fail: | |
424 | msm_unload(dev); | |
425 | return ret; | |
426 | } | |
427 | ||
7198e6b0 RC |
428 | static void load_gpu(struct drm_device *dev) |
429 | { | |
a1ad3523 | 430 | static DEFINE_MUTEX(init_lock); |
7198e6b0 | 431 | struct msm_drm_private *priv = dev->dev_private; |
7198e6b0 | 432 | |
a1ad3523 RC |
433 | mutex_lock(&init_lock); |
434 | ||
e2550b7a RC |
435 | if (!priv->gpu) |
436 | priv->gpu = adreno_load_gpu(dev); | |
7198e6b0 | 437 | |
a1ad3523 | 438 | mutex_unlock(&init_lock); |
7198e6b0 RC |
439 | } |
440 | ||
441 | static int msm_open(struct drm_device *dev, struct drm_file *file) | |
442 | { | |
443 | struct msm_file_private *ctx; | |
444 | ||
445 | /* For now, load gpu on open.. to avoid the requirement of having | |
446 | * firmware in the initrd. | |
447 | */ | |
448 | load_gpu(dev); | |
449 | ||
450 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
451 | if (!ctx) | |
452 | return -ENOMEM; | |
453 | ||
454 | file->driver_priv = ctx; | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
c8afe684 RC |
459 | static void msm_preclose(struct drm_device *dev, struct drm_file *file) |
460 | { | |
461 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 | 462 | struct msm_file_private *ctx = file->driver_priv; |
c8afe684 | 463 | struct msm_kms *kms = priv->kms; |
7198e6b0 | 464 | |
c8afe684 RC |
465 | if (kms) |
466 | kms->funcs->preclose(kms, file); | |
7198e6b0 RC |
467 | |
468 | mutex_lock(&dev->struct_mutex); | |
469 | if (ctx == priv->lastctx) | |
470 | priv->lastctx = NULL; | |
471 | mutex_unlock(&dev->struct_mutex); | |
472 | ||
473 | kfree(ctx); | |
c8afe684 RC |
474 | } |
475 | ||
476 | static void msm_lastclose(struct drm_device *dev) | |
477 | { | |
478 | struct msm_drm_private *priv = dev->dev_private; | |
5ea1f752 RC |
479 | if (priv->fbdev) |
480 | drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); | |
c8afe684 RC |
481 | } |
482 | ||
e9f0d76f | 483 | static irqreturn_t msm_irq(int irq, void *arg) |
c8afe684 RC |
484 | { |
485 | struct drm_device *dev = arg; | |
486 | struct msm_drm_private *priv = dev->dev_private; | |
487 | struct msm_kms *kms = priv->kms; | |
488 | BUG_ON(!kms); | |
489 | return kms->funcs->irq(kms); | |
490 | } | |
491 | ||
492 | static void msm_irq_preinstall(struct drm_device *dev) | |
493 | { | |
494 | struct msm_drm_private *priv = dev->dev_private; | |
495 | struct msm_kms *kms = priv->kms; | |
496 | BUG_ON(!kms); | |
497 | kms->funcs->irq_preinstall(kms); | |
498 | } | |
499 | ||
500 | static int msm_irq_postinstall(struct drm_device *dev) | |
501 | { | |
502 | struct msm_drm_private *priv = dev->dev_private; | |
503 | struct msm_kms *kms = priv->kms; | |
504 | BUG_ON(!kms); | |
505 | return kms->funcs->irq_postinstall(kms); | |
506 | } | |
507 | ||
508 | static void msm_irq_uninstall(struct drm_device *dev) | |
509 | { | |
510 | struct msm_drm_private *priv = dev->dev_private; | |
511 | struct msm_kms *kms = priv->kms; | |
512 | BUG_ON(!kms); | |
513 | kms->funcs->irq_uninstall(kms); | |
514 | } | |
515 | ||
88e72717 | 516 | static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe) |
c8afe684 RC |
517 | { |
518 | struct msm_drm_private *priv = dev->dev_private; | |
519 | struct msm_kms *kms = priv->kms; | |
520 | if (!kms) | |
521 | return -ENXIO; | |
88e72717 TR |
522 | DBG("dev=%p, crtc=%u", dev, pipe); |
523 | return vblank_ctrl_queue_work(priv, pipe, true); | |
c8afe684 RC |
524 | } |
525 | ||
88e72717 | 526 | static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe) |
c8afe684 RC |
527 | { |
528 | struct msm_drm_private *priv = dev->dev_private; | |
529 | struct msm_kms *kms = priv->kms; | |
530 | if (!kms) | |
531 | return; | |
88e72717 TR |
532 | DBG("dev=%p, crtc=%u", dev, pipe); |
533 | vblank_ctrl_queue_work(priv, pipe, false); | |
c8afe684 RC |
534 | } |
535 | ||
536 | /* | |
537 | * DRM debugfs: | |
538 | */ | |
539 | ||
540 | #ifdef CONFIG_DEBUG_FS | |
7198e6b0 RC |
541 | static int msm_gpu_show(struct drm_device *dev, struct seq_file *m) |
542 | { | |
543 | struct msm_drm_private *priv = dev->dev_private; | |
544 | struct msm_gpu *gpu = priv->gpu; | |
545 | ||
546 | if (gpu) { | |
547 | seq_printf(m, "%s Status:\n", gpu->name); | |
548 | gpu->funcs->show(gpu, m); | |
549 | } | |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
c8afe684 RC |
554 | static int msm_gem_show(struct drm_device *dev, struct seq_file *m) |
555 | { | |
556 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 RC |
557 | struct msm_gpu *gpu = priv->gpu; |
558 | ||
559 | if (gpu) { | |
560 | seq_printf(m, "Active Objects (%s):\n", gpu->name); | |
561 | msm_gem_describe_objects(&gpu->active_list, m); | |
562 | } | |
c8afe684 | 563 | |
7198e6b0 | 564 | seq_printf(m, "Inactive Objects:\n"); |
c8afe684 RC |
565 | msm_gem_describe_objects(&priv->inactive_list, m); |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | static int msm_mm_show(struct drm_device *dev, struct seq_file *m) | |
571 | { | |
b04a5906 | 572 | return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm); |
c8afe684 RC |
573 | } |
574 | ||
575 | static int msm_fb_show(struct drm_device *dev, struct seq_file *m) | |
576 | { | |
577 | struct msm_drm_private *priv = dev->dev_private; | |
578 | struct drm_framebuffer *fb, *fbdev_fb = NULL; | |
579 | ||
580 | if (priv->fbdev) { | |
581 | seq_printf(m, "fbcon "); | |
582 | fbdev_fb = priv->fbdev->fb; | |
583 | msm_framebuffer_describe(fbdev_fb, m); | |
584 | } | |
585 | ||
586 | mutex_lock(&dev->mode_config.fb_lock); | |
587 | list_for_each_entry(fb, &dev->mode_config.fb_list, head) { | |
588 | if (fb == fbdev_fb) | |
589 | continue; | |
590 | ||
591 | seq_printf(m, "user "); | |
592 | msm_framebuffer_describe(fb, m); | |
593 | } | |
594 | mutex_unlock(&dev->mode_config.fb_lock); | |
595 | ||
596 | return 0; | |
597 | } | |
598 | ||
599 | static int show_locked(struct seq_file *m, void *arg) | |
600 | { | |
601 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
602 | struct drm_device *dev = node->minor->dev; | |
603 | int (*show)(struct drm_device *dev, struct seq_file *m) = | |
604 | node->info_ent->data; | |
605 | int ret; | |
606 | ||
607 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
608 | if (ret) | |
609 | return ret; | |
610 | ||
611 | ret = show(dev, m); | |
612 | ||
613 | mutex_unlock(&dev->struct_mutex); | |
614 | ||
615 | return ret; | |
616 | } | |
617 | ||
618 | static struct drm_info_list msm_debugfs_list[] = { | |
7198e6b0 | 619 | {"gpu", show_locked, 0, msm_gpu_show}, |
c8afe684 RC |
620 | {"gem", show_locked, 0, msm_gem_show}, |
621 | { "mm", show_locked, 0, msm_mm_show }, | |
622 | { "fb", show_locked, 0, msm_fb_show }, | |
623 | }; | |
624 | ||
a7d3c950 RC |
625 | static int late_init_minor(struct drm_minor *minor) |
626 | { | |
627 | int ret; | |
628 | ||
629 | if (!minor) | |
630 | return 0; | |
631 | ||
632 | ret = msm_rd_debugfs_init(minor); | |
633 | if (ret) { | |
634 | dev_err(minor->dev->dev, "could not install rd debugfs\n"); | |
635 | return ret; | |
636 | } | |
637 | ||
70c70f09 RC |
638 | ret = msm_perf_debugfs_init(minor); |
639 | if (ret) { | |
640 | dev_err(minor->dev->dev, "could not install perf debugfs\n"); | |
641 | return ret; | |
642 | } | |
643 | ||
a7d3c950 RC |
644 | return 0; |
645 | } | |
646 | ||
647 | int msm_debugfs_late_init(struct drm_device *dev) | |
648 | { | |
649 | int ret; | |
650 | ret = late_init_minor(dev->primary); | |
651 | if (ret) | |
652 | return ret; | |
653 | ret = late_init_minor(dev->render); | |
654 | if (ret) | |
655 | return ret; | |
656 | ret = late_init_minor(dev->control); | |
657 | return ret; | |
658 | } | |
659 | ||
c8afe684 RC |
660 | static int msm_debugfs_init(struct drm_minor *minor) |
661 | { | |
662 | struct drm_device *dev = minor->dev; | |
663 | int ret; | |
664 | ||
665 | ret = drm_debugfs_create_files(msm_debugfs_list, | |
666 | ARRAY_SIZE(msm_debugfs_list), | |
667 | minor->debugfs_root, minor); | |
668 | ||
669 | if (ret) { | |
670 | dev_err(dev->dev, "could not install msm_debugfs_list\n"); | |
671 | return ret; | |
672 | } | |
673 | ||
a7d3c950 | 674 | return 0; |
c8afe684 RC |
675 | } |
676 | ||
677 | static void msm_debugfs_cleanup(struct drm_minor *minor) | |
678 | { | |
679 | drm_debugfs_remove_files(msm_debugfs_list, | |
680 | ARRAY_SIZE(msm_debugfs_list), minor); | |
a7d3c950 RC |
681 | if (!minor->dev->dev_private) |
682 | return; | |
683 | msm_rd_debugfs_cleanup(minor); | |
70c70f09 | 684 | msm_perf_debugfs_cleanup(minor); |
c8afe684 RC |
685 | } |
686 | #endif | |
687 | ||
7198e6b0 RC |
688 | /* |
689 | * Fences: | |
690 | */ | |
691 | ||
a9702ca2 WX |
692 | int msm_wait_fence(struct drm_device *dev, uint32_t fence, |
693 | ktime_t *timeout , bool interruptible) | |
7198e6b0 RC |
694 | { |
695 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 RC |
696 | int ret; |
697 | ||
f816f272 RC |
698 | if (!priv->gpu) |
699 | return 0; | |
700 | ||
701 | if (fence > priv->gpu->submitted_fence) { | |
702 | DRM_ERROR("waiting on invalid fence: %u (of %u)\n", | |
703 | fence, priv->gpu->submitted_fence); | |
704 | return -EINVAL; | |
705 | } | |
706 | ||
707 | if (!timeout) { | |
708 | /* no-wait: */ | |
709 | ret = fence_completed(dev, fence) ? 0 : -EBUSY; | |
710 | } else { | |
56c2da83 | 711 | ktime_t now = ktime_get(); |
f816f272 RC |
712 | unsigned long remaining_jiffies; |
713 | ||
56c2da83 | 714 | if (ktime_compare(*timeout, now) < 0) { |
f816f272 | 715 | remaining_jiffies = 0; |
56c2da83 RC |
716 | } else { |
717 | ktime_t rem = ktime_sub(*timeout, now); | |
718 | struct timespec ts = ktime_to_timespec(rem); | |
719 | remaining_jiffies = timespec_to_jiffies(&ts); | |
720 | } | |
f816f272 | 721 | |
a9702ca2 WX |
722 | if (interruptible) |
723 | ret = wait_event_interruptible_timeout(priv->fence_event, | |
724 | fence_completed(dev, fence), | |
725 | remaining_jiffies); | |
726 | else | |
727 | ret = wait_event_timeout(priv->fence_event, | |
f816f272 RC |
728 | fence_completed(dev, fence), |
729 | remaining_jiffies); | |
730 | ||
731 | if (ret == 0) { | |
732 | DBG("timeout waiting for fence: %u (completed: %u)", | |
733 | fence, priv->completed_fence); | |
734 | ret = -ETIMEDOUT; | |
735 | } else if (ret != -ERESTARTSYS) { | |
736 | ret = 0; | |
737 | } | |
7198e6b0 RC |
738 | } |
739 | ||
740 | return ret; | |
741 | } | |
742 | ||
69193e50 RC |
743 | int msm_queue_fence_cb(struct drm_device *dev, |
744 | struct msm_fence_cb *cb, uint32_t fence) | |
745 | { | |
746 | struct msm_drm_private *priv = dev->dev_private; | |
747 | int ret = 0; | |
748 | ||
749 | mutex_lock(&dev->struct_mutex); | |
750 | if (!list_empty(&cb->work.entry)) { | |
751 | ret = -EINVAL; | |
752 | } else if (fence > priv->completed_fence) { | |
753 | cb->fence = fence; | |
754 | list_add_tail(&cb->work.entry, &priv->fence_cbs); | |
755 | } else { | |
756 | queue_work(priv->wq, &cb->work); | |
757 | } | |
758 | mutex_unlock(&dev->struct_mutex); | |
759 | ||
760 | return ret; | |
761 | } | |
762 | ||
edd4fc63 | 763 | /* called from workqueue */ |
7198e6b0 RC |
764 | void msm_update_fence(struct drm_device *dev, uint32_t fence) |
765 | { | |
766 | struct msm_drm_private *priv = dev->dev_private; | |
767 | ||
edd4fc63 RC |
768 | mutex_lock(&dev->struct_mutex); |
769 | priv->completed_fence = max(fence, priv->completed_fence); | |
770 | ||
771 | while (!list_empty(&priv->fence_cbs)) { | |
772 | struct msm_fence_cb *cb; | |
773 | ||
774 | cb = list_first_entry(&priv->fence_cbs, | |
775 | struct msm_fence_cb, work.entry); | |
776 | ||
777 | if (cb->fence > priv->completed_fence) | |
778 | break; | |
779 | ||
780 | list_del_init(&cb->work.entry); | |
781 | queue_work(priv->wq, &cb->work); | |
7198e6b0 | 782 | } |
edd4fc63 RC |
783 | |
784 | mutex_unlock(&dev->struct_mutex); | |
785 | ||
786 | wake_up_all(&priv->fence_event); | |
787 | } | |
788 | ||
789 | void __msm_fence_worker(struct work_struct *work) | |
790 | { | |
791 | struct msm_fence_cb *cb = container_of(work, struct msm_fence_cb, work); | |
792 | cb->func(cb); | |
7198e6b0 RC |
793 | } |
794 | ||
795 | /* | |
796 | * DRM ioctls: | |
797 | */ | |
798 | ||
799 | static int msm_ioctl_get_param(struct drm_device *dev, void *data, | |
800 | struct drm_file *file) | |
801 | { | |
802 | struct msm_drm_private *priv = dev->dev_private; | |
803 | struct drm_msm_param *args = data; | |
804 | struct msm_gpu *gpu; | |
805 | ||
806 | /* for now, we just have 3d pipe.. eventually this would need to | |
807 | * be more clever to dispatch to appropriate gpu module: | |
808 | */ | |
809 | if (args->pipe != MSM_PIPE_3D0) | |
810 | return -EINVAL; | |
811 | ||
812 | gpu = priv->gpu; | |
813 | ||
814 | if (!gpu) | |
815 | return -ENXIO; | |
816 | ||
817 | return gpu->funcs->get_param(gpu, args->param, &args->value); | |
818 | } | |
819 | ||
820 | static int msm_ioctl_gem_new(struct drm_device *dev, void *data, | |
821 | struct drm_file *file) | |
822 | { | |
823 | struct drm_msm_gem_new *args = data; | |
93ddb0d3 RC |
824 | |
825 | if (args->flags & ~MSM_BO_FLAGS) { | |
826 | DRM_ERROR("invalid flags: %08x\n", args->flags); | |
827 | return -EINVAL; | |
828 | } | |
829 | ||
7198e6b0 RC |
830 | return msm_gem_new_handle(dev, file, args->size, |
831 | args->flags, &args->handle); | |
832 | } | |
833 | ||
56c2da83 RC |
834 | static inline ktime_t to_ktime(struct drm_msm_timespec timeout) |
835 | { | |
836 | return ktime_set(timeout.tv_sec, timeout.tv_nsec); | |
837 | } | |
7198e6b0 RC |
838 | |
839 | static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, | |
840 | struct drm_file *file) | |
841 | { | |
842 | struct drm_msm_gem_cpu_prep *args = data; | |
843 | struct drm_gem_object *obj; | |
56c2da83 | 844 | ktime_t timeout = to_ktime(args->timeout); |
7198e6b0 RC |
845 | int ret; |
846 | ||
93ddb0d3 RC |
847 | if (args->op & ~MSM_PREP_FLAGS) { |
848 | DRM_ERROR("invalid op: %08x\n", args->op); | |
849 | return -EINVAL; | |
850 | } | |
851 | ||
7198e6b0 RC |
852 | obj = drm_gem_object_lookup(dev, file, args->handle); |
853 | if (!obj) | |
854 | return -ENOENT; | |
855 | ||
56c2da83 | 856 | ret = msm_gem_cpu_prep(obj, args->op, &timeout); |
7198e6b0 RC |
857 | |
858 | drm_gem_object_unreference_unlocked(obj); | |
859 | ||
860 | return ret; | |
861 | } | |
862 | ||
863 | static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, | |
864 | struct drm_file *file) | |
865 | { | |
866 | struct drm_msm_gem_cpu_fini *args = data; | |
867 | struct drm_gem_object *obj; | |
868 | int ret; | |
869 | ||
870 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
871 | if (!obj) | |
872 | return -ENOENT; | |
873 | ||
874 | ret = msm_gem_cpu_fini(obj); | |
875 | ||
876 | drm_gem_object_unreference_unlocked(obj); | |
877 | ||
878 | return ret; | |
879 | } | |
880 | ||
881 | static int msm_ioctl_gem_info(struct drm_device *dev, void *data, | |
882 | struct drm_file *file) | |
883 | { | |
884 | struct drm_msm_gem_info *args = data; | |
885 | struct drm_gem_object *obj; | |
886 | int ret = 0; | |
887 | ||
888 | if (args->pad) | |
889 | return -EINVAL; | |
890 | ||
891 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
892 | if (!obj) | |
893 | return -ENOENT; | |
894 | ||
895 | args->offset = msm_gem_mmap_offset(obj); | |
896 | ||
897 | drm_gem_object_unreference_unlocked(obj); | |
898 | ||
899 | return ret; | |
900 | } | |
901 | ||
902 | static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, | |
903 | struct drm_file *file) | |
904 | { | |
905 | struct drm_msm_wait_fence *args = data; | |
56c2da83 | 906 | ktime_t timeout = to_ktime(args->timeout); |
93ddb0d3 RC |
907 | |
908 | if (args->pad) { | |
909 | DRM_ERROR("invalid pad: %08x\n", args->pad); | |
910 | return -EINVAL; | |
911 | } | |
912 | ||
a9702ca2 | 913 | return msm_wait_fence(dev, args->fence, &timeout, true); |
7198e6b0 RC |
914 | } |
915 | ||
916 | static const struct drm_ioctl_desc msm_ioctls[] = { | |
f8c47144 DV |
917 | DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW), |
918 | DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW), | |
919 | DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW), | |
920 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW), | |
921 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW), | |
922 | DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW), | |
923 | DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW), | |
7198e6b0 RC |
924 | }; |
925 | ||
c8afe684 RC |
926 | static const struct vm_operations_struct vm_ops = { |
927 | .fault = msm_gem_fault, | |
928 | .open = drm_gem_vm_open, | |
929 | .close = drm_gem_vm_close, | |
930 | }; | |
931 | ||
932 | static const struct file_operations fops = { | |
933 | .owner = THIS_MODULE, | |
934 | .open = drm_open, | |
935 | .release = drm_release, | |
936 | .unlocked_ioctl = drm_ioctl, | |
937 | #ifdef CONFIG_COMPAT | |
938 | .compat_ioctl = drm_compat_ioctl, | |
939 | #endif | |
940 | .poll = drm_poll, | |
941 | .read = drm_read, | |
942 | .llseek = no_llseek, | |
943 | .mmap = msm_gem_mmap, | |
944 | }; | |
945 | ||
946 | static struct drm_driver msm_driver = { | |
05b84911 RC |
947 | .driver_features = DRIVER_HAVE_IRQ | |
948 | DRIVER_GEM | | |
949 | DRIVER_PRIME | | |
b4b15c86 | 950 | DRIVER_RENDER | |
a5436e1d | 951 | DRIVER_ATOMIC | |
05b84911 | 952 | DRIVER_MODESET, |
c8afe684 RC |
953 | .load = msm_load, |
954 | .unload = msm_unload, | |
7198e6b0 | 955 | .open = msm_open, |
c8afe684 RC |
956 | .preclose = msm_preclose, |
957 | .lastclose = msm_lastclose, | |
915b4d11 | 958 | .set_busid = drm_platform_set_busid, |
c8afe684 RC |
959 | .irq_handler = msm_irq, |
960 | .irq_preinstall = msm_irq_preinstall, | |
961 | .irq_postinstall = msm_irq_postinstall, | |
962 | .irq_uninstall = msm_irq_uninstall, | |
b44f8408 | 963 | .get_vblank_counter = drm_vblank_no_hw_counter, |
c8afe684 RC |
964 | .enable_vblank = msm_enable_vblank, |
965 | .disable_vblank = msm_disable_vblank, | |
966 | .gem_free_object = msm_gem_free_object, | |
967 | .gem_vm_ops = &vm_ops, | |
968 | .dumb_create = msm_gem_dumb_create, | |
969 | .dumb_map_offset = msm_gem_dumb_map_offset, | |
30600a90 | 970 | .dumb_destroy = drm_gem_dumb_destroy, |
05b84911 RC |
971 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
972 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
973 | .gem_prime_export = drm_gem_prime_export, | |
974 | .gem_prime_import = drm_gem_prime_import, | |
975 | .gem_prime_pin = msm_gem_prime_pin, | |
976 | .gem_prime_unpin = msm_gem_prime_unpin, | |
977 | .gem_prime_get_sg_table = msm_gem_prime_get_sg_table, | |
978 | .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, | |
979 | .gem_prime_vmap = msm_gem_prime_vmap, | |
980 | .gem_prime_vunmap = msm_gem_prime_vunmap, | |
77a147e7 | 981 | .gem_prime_mmap = msm_gem_prime_mmap, |
c8afe684 RC |
982 | #ifdef CONFIG_DEBUG_FS |
983 | .debugfs_init = msm_debugfs_init, | |
984 | .debugfs_cleanup = msm_debugfs_cleanup, | |
985 | #endif | |
7198e6b0 RC |
986 | .ioctls = msm_ioctls, |
987 | .num_ioctls = DRM_MSM_NUM_IOCTLS, | |
c8afe684 RC |
988 | .fops = &fops, |
989 | .name = "msm", | |
990 | .desc = "MSM Snapdragon DRM", | |
991 | .date = "20130625", | |
992 | .major = 1, | |
993 | .minor = 0, | |
994 | }; | |
995 | ||
996 | #ifdef CONFIG_PM_SLEEP | |
997 | static int msm_pm_suspend(struct device *dev) | |
998 | { | |
999 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1000 | ||
1001 | drm_kms_helper_poll_disable(ddev); | |
1002 | ||
1003 | return 0; | |
1004 | } | |
1005 | ||
1006 | static int msm_pm_resume(struct device *dev) | |
1007 | { | |
1008 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1009 | ||
1010 | drm_kms_helper_poll_enable(ddev); | |
1011 | ||
1012 | return 0; | |
1013 | } | |
1014 | #endif | |
1015 | ||
1016 | static const struct dev_pm_ops msm_pm_ops = { | |
1017 | SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) | |
1018 | }; | |
1019 | ||
060530f1 RC |
1020 | /* |
1021 | * Componentized driver support: | |
1022 | */ | |
1023 | ||
e9fbdaf2 AT |
1024 | /* |
1025 | * NOTE: duplication of the same code as exynos or imx (or probably any other). | |
1026 | * so probably some room for some helpers | |
060530f1 RC |
1027 | */ |
1028 | static int compare_of(struct device *dev, void *data) | |
1029 | { | |
1030 | return dev->of_node == data; | |
1031 | } | |
41e69778 RC |
1032 | |
1033 | static int add_components(struct device *dev, struct component_match **matchptr, | |
1034 | const char *name) | |
1035 | { | |
1036 | struct device_node *np = dev->of_node; | |
1037 | unsigned i; | |
1038 | ||
1039 | for (i = 0; ; i++) { | |
1040 | struct device_node *node; | |
1041 | ||
1042 | node = of_parse_phandle(np, name, i); | |
1043 | if (!node) | |
1044 | break; | |
1045 | ||
1046 | component_match_add(dev, matchptr, compare_of, node); | |
1047 | } | |
1048 | ||
1049 | return 0; | |
1050 | } | |
84448288 RK |
1051 | |
1052 | static int msm_drm_bind(struct device *dev) | |
1053 | { | |
1054 | return drm_platform_init(&msm_driver, to_platform_device(dev)); | |
1055 | } | |
1056 | ||
1057 | static void msm_drm_unbind(struct device *dev) | |
1058 | { | |
1059 | drm_put_dev(platform_get_drvdata(to_platform_device(dev))); | |
1060 | } | |
1061 | ||
1062 | static const struct component_master_ops msm_drm_ops = { | |
1063 | .bind = msm_drm_bind, | |
1064 | .unbind = msm_drm_unbind, | |
1065 | }; | |
1066 | ||
1067 | /* | |
1068 | * Platform driver: | |
1069 | */ | |
060530f1 | 1070 | |
84448288 | 1071 | static int msm_pdev_probe(struct platform_device *pdev) |
060530f1 | 1072 | { |
84448288 | 1073 | struct component_match *match = NULL; |
e9fbdaf2 | 1074 | |
41e69778 RC |
1075 | add_components(&pdev->dev, &match, "connectors"); |
1076 | add_components(&pdev->dev, &match, "gpus"); | |
060530f1 | 1077 | |
871d812a | 1078 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); |
84448288 | 1079 | return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); |
c8afe684 RC |
1080 | } |
1081 | ||
1082 | static int msm_pdev_remove(struct platform_device *pdev) | |
1083 | { | |
060530f1 | 1084 | component_master_del(&pdev->dev, &msm_drm_ops); |
c8afe684 RC |
1085 | |
1086 | return 0; | |
1087 | } | |
1088 | ||
1089 | static const struct platform_device_id msm_id[] = { | |
1090 | { "mdp", 0 }, | |
1091 | { } | |
1092 | }; | |
1093 | ||
06c0dd96 | 1094 | static const struct of_device_id dt_match[] = { |
d4fc72ed AT |
1095 | { .compatible = "qcom,mdp4", .data = (void *) 4 }, /* mdp4 */ |
1096 | { .compatible = "qcom,mdp5", .data = (void *) 5 }, /* mdp5 */ | |
1097 | /* to support downstream DT files */ | |
1098 | { .compatible = "qcom,mdss_mdp", .data = (void *) 5 }, /* mdp5 */ | |
06c0dd96 RC |
1099 | {} |
1100 | }; | |
1101 | MODULE_DEVICE_TABLE(of, dt_match); | |
1102 | ||
c8afe684 RC |
1103 | static struct platform_driver msm_platform_driver = { |
1104 | .probe = msm_pdev_probe, | |
1105 | .remove = msm_pdev_remove, | |
1106 | .driver = { | |
c8afe684 | 1107 | .name = "msm", |
06c0dd96 | 1108 | .of_match_table = dt_match, |
c8afe684 RC |
1109 | .pm = &msm_pm_ops, |
1110 | }, | |
1111 | .id_table = msm_id, | |
1112 | }; | |
1113 | ||
1114 | static int __init msm_drm_register(void) | |
1115 | { | |
1116 | DBG("init"); | |
d5af49c9 | 1117 | msm_dsi_register(); |
00453981 | 1118 | msm_edp_register(); |
c8afe684 | 1119 | hdmi_register(); |
bfd28b13 | 1120 | adreno_register(); |
c8afe684 RC |
1121 | return platform_driver_register(&msm_platform_driver); |
1122 | } | |
1123 | ||
1124 | static void __exit msm_drm_unregister(void) | |
1125 | { | |
1126 | DBG("fini"); | |
1127 | platform_driver_unregister(&msm_platform_driver); | |
1128 | hdmi_unregister(); | |
bfd28b13 | 1129 | adreno_unregister(); |
00453981 | 1130 | msm_edp_unregister(); |
d5af49c9 | 1131 | msm_dsi_unregister(); |
c8afe684 RC |
1132 | } |
1133 | ||
1134 | module_init(msm_drm_register); | |
1135 | module_exit(msm_drm_unregister); | |
1136 | ||
1137 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); | |
1138 | MODULE_DESCRIPTION("MSM DRM Driver"); | |
1139 | MODULE_LICENSE("GPL"); |