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1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef __MSM_GPU_H__ | |
19 | #define __MSM_GPU_H__ | |
20 | ||
21 | #include <linux/clk.h> | |
22 | #include <linux/regulator/consumer.h> | |
23 | ||
24 | #include "msm_drv.h" | |
25 | #include "msm_ringbuffer.h" | |
26 | ||
27 | struct msm_gem_submit; | |
70c70f09 | 28 | struct msm_gpu_perfcntr; |
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29 | |
30 | /* So far, with hardware that I've seen to date, we can have: | |
31 | * + zero, one, or two z180 2d cores | |
32 | * + a3xx or a2xx 3d core, which share a common CP (the firmware | |
33 | * for the CP seems to implement some different PM4 packet types | |
34 | * but the basics of cmdstream submission are the same) | |
35 | * | |
36 | * Which means that the eventual complete "class" hierarchy, once | |
37 | * support for all past and present hw is in place, becomes: | |
38 | * + msm_gpu | |
39 | * + adreno_gpu | |
40 | * + a3xx_gpu | |
41 | * + a2xx_gpu | |
42 | * + z180_gpu | |
43 | */ | |
44 | struct msm_gpu_funcs { | |
45 | int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value); | |
46 | int (*hw_init)(struct msm_gpu *gpu); | |
47 | int (*pm_suspend)(struct msm_gpu *gpu); | |
48 | int (*pm_resume)(struct msm_gpu *gpu); | |
49 | int (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit, | |
50 | struct msm_file_private *ctx); | |
51 | void (*flush)(struct msm_gpu *gpu); | |
52 | void (*idle)(struct msm_gpu *gpu); | |
53 | irqreturn_t (*irq)(struct msm_gpu *irq); | |
54 | uint32_t (*last_fence)(struct msm_gpu *gpu); | |
bd6f82d8 | 55 | void (*recover)(struct msm_gpu *gpu); |
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56 | void (*destroy)(struct msm_gpu *gpu); |
57 | #ifdef CONFIG_DEBUG_FS | |
58 | /* show GPU status in debugfs: */ | |
59 | void (*show)(struct msm_gpu *gpu, struct seq_file *m); | |
60 | #endif | |
61 | }; | |
62 | ||
63 | struct msm_gpu { | |
64 | const char *name; | |
65 | struct drm_device *dev; | |
66 | const struct msm_gpu_funcs *funcs; | |
67 | ||
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68 | /* performance counters (hw & sw): */ |
69 | spinlock_t perf_lock; | |
70 | bool perfcntr_active; | |
71 | struct { | |
72 | bool active; | |
73 | ktime_t time; | |
74 | } last_sample; | |
75 | uint32_t totaltime, activetime; /* sw counters */ | |
76 | uint32_t last_cntrs[5]; /* hw counters */ | |
77 | const struct msm_gpu_perfcntr *perfcntrs; | |
78 | uint32_t num_perfcntrs; | |
79 | ||
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80 | struct msm_ringbuffer *rb; |
81 | uint32_t rb_iova; | |
82 | ||
83 | /* list of GEM active objects: */ | |
84 | struct list_head active_list; | |
85 | ||
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86 | uint32_t submitted_fence; |
87 | ||
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88 | /* is gpu powered/active? */ |
89 | int active_cnt; | |
90 | bool inactive; | |
91 | ||
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92 | /* worker for handling active-list retiring: */ |
93 | struct work_struct retire_work; | |
94 | ||
95 | void __iomem *mmio; | |
96 | int irq; | |
97 | ||
871d812a | 98 | struct msm_mmu *mmu; |
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99 | int id; |
100 | ||
101 | /* Power Control: */ | |
102 | struct regulator *gpu_reg, *gpu_cx; | |
de558cd2 | 103 | struct clk *ebi1_clk, *grp_clks[6]; |
7198e6b0 | 104 | uint32_t fast_rate, slow_rate, bus_freq; |
bf2b33af | 105 | |
6490ad47 | 106 | #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING |
bf2b33af | 107 | struct msm_bus_scale_pdata *bus_scale_table; |
7198e6b0 | 108 | uint32_t bsc; |
bf2b33af | 109 | #endif |
bd6f82d8 | 110 | |
37d77c3a RC |
111 | /* Hang and Inactivity Detection: |
112 | */ | |
113 | #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */ | |
114 | #define DRM_MSM_INACTIVE_JIFFIES msecs_to_jiffies(DRM_MSM_INACTIVE_PERIOD) | |
115 | struct timer_list inactive_timer; | |
116 | struct work_struct inactive_work; | |
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117 | #define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */ |
118 | #define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD) | |
119 | struct timer_list hangcheck_timer; | |
120 | uint32_t hangcheck_fence; | |
121 | struct work_struct recover_work; | |
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122 | |
123 | struct list_head submit_list; | |
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124 | }; |
125 | ||
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126 | static inline bool msm_gpu_active(struct msm_gpu *gpu) |
127 | { | |
128 | return gpu->submitted_fence > gpu->funcs->last_fence(gpu); | |
129 | } | |
130 | ||
70c70f09 RC |
131 | /* Perf-Counters: |
132 | * The select_reg and select_val are just there for the benefit of the child | |
133 | * class that actually enables the perf counter.. but msm_gpu base class | |
134 | * will handle sampling/displaying the counters. | |
135 | */ | |
136 | ||
137 | struct msm_gpu_perfcntr { | |
138 | uint32_t select_reg; | |
139 | uint32_t sample_reg; | |
140 | uint32_t select_val; | |
141 | const char *name; | |
142 | }; | |
143 | ||
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144 | static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) |
145 | { | |
146 | msm_writel(data, gpu->mmio + (reg << 2)); | |
147 | } | |
148 | ||
149 | static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) | |
150 | { | |
151 | return msm_readl(gpu->mmio + (reg << 2)); | |
152 | } | |
153 | ||
154 | int msm_gpu_pm_suspend(struct msm_gpu *gpu); | |
155 | int msm_gpu_pm_resume(struct msm_gpu *gpu); | |
156 | ||
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157 | void msm_gpu_perfcntr_start(struct msm_gpu *gpu); |
158 | void msm_gpu_perfcntr_stop(struct msm_gpu *gpu); | |
159 | int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, | |
160 | uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs); | |
161 | ||
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162 | void msm_gpu_retire(struct msm_gpu *gpu); |
163 | int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, | |
164 | struct msm_file_private *ctx); | |
165 | ||
166 | int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, | |
167 | struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, | |
168 | const char *name, const char *ioname, const char *irqname, int ringsz); | |
169 | void msm_gpu_cleanup(struct msm_gpu *gpu); | |
170 | ||
e2550b7a | 171 | struct msm_gpu *adreno_load_gpu(struct drm_device *dev); |
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172 | void __init adreno_register(void); |
173 | void __exit adreno_unregister(void); | |
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174 | |
175 | #endif /* __MSM_GPU_H__ */ |