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drm/nouveau/mc: fetch NV_PMC_INTR again after re-arming MSI
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / device / nv50.c
CommitLineData
9274f4a9
BS		 1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
70c0f263 25#include <subdev/bios.h>
a10220bb 26#include <subdev/bus.h>
e0996aea 27#include <subdev/gpio.h>
4196faa8 28#include <subdev/i2c.h>
8aceb7de 29#include <subdev/clock.h>
aa1b9b48 30#include <subdev/therm.h>
d38ac521 31#include <subdev/mxm.h>
cb75d97e 32#include <subdev/devinit.h>
7d9115de 33#include <subdev/mc.h>
5a5c7432 34#include <subdev/timer.h>
861d2107 35#include <subdev/fb.h>
3863c9bc
BS		 36#include <subdev/instmem.h>
37#include <subdev/vm.h>
38#include <subdev/bar.h>
9274f4a9 39
dded35de 40#include <engine/device.h>
ebb945a9
BS		 41#include <engine/dmaobj.h>
42#include <engine/fifo.h>
43#include <engine/software.h>
44#include <engine/graph.h>
45#include <engine/mpeg.h>
46#include <engine/vp.h>
47#include <engine/crypt.h>
48#include <engine/bsp.h>
49#include <engine/ppp.h>
50#include <engine/copy.h>
51#include <engine/disp.h>
52
9274f4a9
BS		 53int
54nv50_identify(struct nouveau_device *device)
55{
56 switch (device->chipset) {
57 case 0x50:
2094dd82 58 device->cname = "G80";
70c0f263 59 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 60 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c 61 device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
8aceb7de 62 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
aa1b9b48 63 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
d38ac521 64 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e 65 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 66 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
a10220bb 67 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
5a5c7432 68 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 69 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 70 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
71 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
72 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 73 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
74 device->oclass[NVDEV_ENGINE_FIFO ] = &nv50_fifo_oclass;
c46c3ddf 75 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9
BS		 76 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
77 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
78 device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9
BS		 79 break;
80 case 0x84:
2094dd82 81 device->cname = "G84";
70c0f263 82 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 83 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c 84 device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
8aceb7de 85 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
2f457367 86 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 87 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e 88 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 89 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
a10220bb 90 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
5a5c7432 91 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 92 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 93 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
94 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
95 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 96 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
97 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
c46c3ddf 98 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9
BS		 99 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
100 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
101 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
102 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
103 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
70cabe4a 104 device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass;
9274f4a9
BS		 105 break;
106 case 0x86:
2094dd82 107 device->cname = "G86";
70c0f263 108 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 109 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c 110 device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
8aceb7de 111 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
2f457367 112 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 113 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e 114 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 115 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
a10220bb 116 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
5a5c7432 117 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 118 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 119 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
120 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
121 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 122 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
123 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
c46c3ddf 124 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9
BS		 125 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
126 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
127 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
128 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
129 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
70cabe4a 130 device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass;
9274f4a9
BS		 131 break;
132 case 0x92:
2094dd82 133 device->cname = "G92";
70c0f263 134 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 135 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c 136 device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
8aceb7de 137 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
2f457367 138 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 139 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e 140 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 141 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
a10220bb 142 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
5a5c7432 143 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 144 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 145 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
146 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
147 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 148 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
149 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
c46c3ddf 150 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9
BS		 151 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
152 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
153 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
154 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
155 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
70cabe4a 156 device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass;
9274f4a9
BS		 157 break;
158 case 0x94:
2094dd82 159 device->cname = "G94";
70c0f263 160 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 161 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c 162 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
8aceb7de 163 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
2f457367 164 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 165 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e 166 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 167 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
a10220bb 168 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
5a5c7432 169 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 170 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 171 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
172 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
173 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 174 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
175 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
c46c3ddf 176 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9
BS		 177 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
178 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
179 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
180 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
181 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
70cabe4a 182 device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
9274f4a9
BS		 183 break;
184 case 0x96:
2094dd82 185 device->cname = "G96";
70c0f263 186 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 187 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c 188 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
8aceb7de 189 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
2f457367 190 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 191 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e 192 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 193 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
a10220bb 194 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
5a5c7432 195 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 196 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 197 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
198 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
199 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 200 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
201 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
c46c3ddf 202 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9
BS		 203 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
204 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
205 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
206 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
207 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
70cabe4a 208 device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
9274f4a9
BS		 209 break;
210 case 0x98:
2094dd82 211 device->cname = "G98";
70c0f263 212 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 213 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c 214 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
8aceb7de 215 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
2f457367 216 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 217 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e 218 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 219 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
a10220bb 220 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
5a5c7432 221 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 222 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 223 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
224 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
225 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 226 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
227 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
c46c3ddf 228 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9 229 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
0d4a1450 230 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
ebb945a9 231 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
0d4a1450 232 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
ebb945a9 233 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
70cabe4a 234 device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
9274f4a9
BS		 235 break;
236 case 0xa0:
2094dd82 237 device->cname = "G200";
70c0f263 238 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 239 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c 240 device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
8aceb7de 241 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
2f457367 242 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 243 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e 244 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 245 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
a10220bb 246 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
5a5c7432 247 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 248 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 249 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
250 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
251 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 252 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
253 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
c46c3ddf 254 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9
BS		 255 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
256 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
257 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
258 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
259 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
70cabe4a 260 device->oclass[NVDEV_ENGINE_DISP ] = &nva0_disp_oclass;
9274f4a9
BS		 261 break;
262 case 0xaa:
2094dd82 263 device->cname = "MCP77/MCP78";
70c0f263 264 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 265 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c 266 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
8aceb7de 267 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
2f457367 268 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 269 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e 270 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 271 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
a10220bb 272 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
5a5c7432 273 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 274 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 275 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
276 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
277 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 278 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
279 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
c46c3ddf 280 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9 281 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
0d4a1450 282 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
ebb945a9 283 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
0d4a1450 284 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
ebb945a9 285 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
70cabe4a 286 device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
9274f4a9
BS		 287 break;
288 case 0xac:
2094dd82 289 device->cname = "MCP79/MCP7A";
70c0f263 290 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 291 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c 292 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
8aceb7de 293 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
2f457367 294 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 295 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e 296 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 297 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
a10220bb 298 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
5a5c7432 299 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 300 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 301 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
302 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
303 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 304 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
305 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
c46c3ddf 306 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9 307 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
0d4a1450 308 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
ebb945a9 309 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
0d4a1450 310 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
ebb945a9 311 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
70cabe4a 312 device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
9274f4a9
BS		 313 break;
314 case 0xa3:
2094dd82 315 device->cname = "GT215";
70c0f263 316 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 317 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c 318 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
8aceb7de 319 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
7b49bd68 320 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521 321 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
88524bc0 322 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
7d9115de 323 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
a10220bb 324 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
5a5c7432 325 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 326 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 327 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
328 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
329 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 330 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
331 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
c46c3ddf 332 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9
BS		 333 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
334 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
0d4a1450
IM		 335 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
336 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
ebb945a9
BS		 337 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
338 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
70cabe4a 339 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
9274f4a9
BS		 340 break;
341 case 0xa5:
2094dd82 342 device->cname = "GT216";
70c0f263 343 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 344 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c 345 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
8aceb7de 346 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
7b49bd68 347 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521 348 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
88524bc0 349 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
7d9115de 350 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
a10220bb 351 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
5a5c7432 352 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 353 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 354 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
355 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
356 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 357 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
358 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
c46c3ddf 359 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9 360 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
0d4a1450
IM		 361 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
362 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
ebb945a9
BS		 363 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
364 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
70cabe4a 365 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
9274f4a9
BS		 366 break;
367 case 0xa8:
2094dd82 368 device->cname = "GT218";
70c0f263 369 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 370 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c 371 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
8aceb7de 372 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
7b49bd68 373 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521 374 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
88524bc0 375 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
7d9115de 376 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
a10220bb 377 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
5a5c7432 378 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 379 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 380 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
381 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
382 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 383 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
384 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
c46c3ddf 385 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9 386 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
0d4a1450
IM		 387 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
388 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
ebb945a9
BS		 389 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
390 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
70cabe4a 391 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
9274f4a9
BS		 392 break;
393 case 0xaf:
2094dd82 394 device->cname = "MCP89";
70c0f263 395 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 396 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c 397 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
8aceb7de 398 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
7b49bd68 399 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521 400 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
88524bc0 401 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
7d9115de 402 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
a10220bb 403 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
5a5c7432 404 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 405 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 406 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
407 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
408 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 409 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
410 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
c46c3ddf 411 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9 412 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
0d4a1450
IM		 413 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
414 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
ebb945a9
BS		 415 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
416 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
70cabe4a 417 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
9274f4a9
BS		 418 break;
419 default:
420 nv_fatal(device, "unknown Tesla chipset\n");
421 return -EINVAL;
422 }
423
424 return 0;
425}
Linux kernel - Deliverables
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