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drm/nva3/clk: Set intermediate core clock on reclocking
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / device / nv50.c
CommitLineData
9274f4a9
BS		 1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
70c0f263 25#include <subdev/bios.h>
a10220bb 26#include <subdev/bus.h>
e0996aea 27#include <subdev/gpio.h>
4196faa8 28#include <subdev/i2c.h>
8aceb7de 29#include <subdev/clock.h>
aa1b9b48 30#include <subdev/therm.h>
d38ac521 31#include <subdev/mxm.h>
cb75d97e 32#include <subdev/devinit.h>
7d9115de 33#include <subdev/mc.h>
5a5c7432 34#include <subdev/timer.h>
861d2107 35#include <subdev/fb.h>
3863c9bc
BS		 36#include <subdev/instmem.h>
37#include <subdev/vm.h>
38#include <subdev/bar.h>
ff4b42c7 39#include <subdev/pwr.h>
c9c0ccae 40#include <subdev/volt.h>
9274f4a9 41
dded35de 42#include <engine/device.h>
ebb945a9
BS		 43#include <engine/dmaobj.h>
44#include <engine/fifo.h>
45#include <engine/software.h>
46#include <engine/graph.h>
47#include <engine/mpeg.h>
48#include <engine/vp.h>
49#include <engine/crypt.h>
50#include <engine/bsp.h>
51#include <engine/ppp.h>
52#include <engine/copy.h>
53#include <engine/disp.h>
aa4d7a4d 54#include <engine/perfmon.h>
ebb945a9 55
9274f4a9
BS		 56int
57nv50_identify(struct nouveau_device *device)
58{
59 switch (device->chipset) {
60 case 0x50:
2094dd82 61 device->cname = "G80";
70c0f263 62 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
d93174ec 63 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
c26fe843 64 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
7c856522 65 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass;
aa1b9b48 66 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
d38ac521 67 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cf336014 68 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
08f6fbdb 69 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
48ae0b35 70 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
5a5c7432 71 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 72 device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass;
24a4ae86 73 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
3863c9bc
BS		 74 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
75 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 76 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 77 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 78 device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
c46c3ddf 79 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9
BS		 80 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
81 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
a8f8b489 82 device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass;
aa4d7a4d 83 device->oclass[NVDEV_ENGINE_PERFMON] = nv50_perfmon_oclass;
9274f4a9
BS		 84 break;
85 case 0x84:
2094dd82 86 device->cname = "G84";
70c0f263 87 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
d93174ec 88 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
c26fe843 89 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
7c856522 90 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
2f457367 91 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 92 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
4019aaa2 93 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
08f6fbdb 94 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
48ae0b35 95 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
5a5c7432 96 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
9ca3037e 97 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
24a4ae86 98 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
3863c9bc
BS		 99 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
100 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 101 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 102 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 103 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
c46c3ddf 104 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9
BS		 105 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
106 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
107 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
108 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
109 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
a8f8b489 110 device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
aa4d7a4d 111 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
9274f4a9
BS		 112 break;
113 case 0x86:
2094dd82 114 device->cname = "G86";
70c0f263 115 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
d93174ec 116 device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
c26fe843 117 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
7c856522 118 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
2f457367 119 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 120 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
4019aaa2 121 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
08f6fbdb 122 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
48ae0b35 123 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
5a5c7432 124 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
9ca3037e 125 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
24a4ae86 126 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
3863c9bc
BS		 127 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
128 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 129 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 130 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 131 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
c46c3ddf 132 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9
BS		 133 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
134 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
135 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
136 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
137 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
a8f8b489 138 device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
aa4d7a4d 139 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
9274f4a9
BS		 140 break;
141 case 0x92:
2094dd82 142 device->cname = "G92";
70c0f263 143 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
7356859a 144 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
c26fe843 145 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
7c856522 146 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
2f457367 147 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 148 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
4019aaa2 149 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
08f6fbdb 150 device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
48ae0b35 151 device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
5a5c7432 152 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
9ca3037e 153 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
24a4ae86 154 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
3863c9bc
BS		 155 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
156 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 157 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 158 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 159 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
c46c3ddf 160 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9
BS		 161 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
162 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
163 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
164 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
165 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
a8f8b489 166 device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
aa4d7a4d 167 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
9274f4a9
BS		 168 break;
169 case 0x94:
2094dd82 170 device->cname = "G94";
70c0f263 171 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
7356859a 172 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
c26fe843 173 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
7c856522 174 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
2f457367 175 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 176 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
4019aaa2 177 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
9a9d5c64 178 device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
2984506f 179 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
5a5c7432 180 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
9ca3037e 181 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
24a4ae86 182 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
3863c9bc
BS		 183 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
184 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 185 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 186 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 187 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
c46c3ddf 188 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9
BS		 189 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
190 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
191 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
192 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
193 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
a8f8b489 194 device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
aa4d7a4d 195 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
9274f4a9
BS		 196 break;
197 case 0x96:
2094dd82 198 device->cname = "G96";
70c0f263 199 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
7356859a 200 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
c26fe843 201 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
7c856522 202 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
2f457367 203 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 204 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
4019aaa2 205 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
9a9d5c64 206 device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
2984506f 207 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
5a5c7432 208 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
9ca3037e 209 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
24a4ae86 210 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
3863c9bc
BS		 211 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
212 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 213 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 214 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 215 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
c46c3ddf 216 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9
BS		 217 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
218 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
219 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
220 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
221 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
a8f8b489 222 device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
aa4d7a4d 223 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
9274f4a9
BS		 224 break;
225 case 0x98:
2094dd82 226 device->cname = "G98";
70c0f263 227 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
7356859a 228 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
c26fe843 229 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
7c856522 230 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
2f457367 231 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 232 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
4019aaa2 233 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
08f6fbdb 234 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
2984506f 235 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
5a5c7432 236 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
9ca3037e 237 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
24a4ae86 238 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
3863c9bc
BS		 239 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
240 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 241 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 242 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 243 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
c46c3ddf 244 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9 245 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
0d4a1450 246 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
ebb945a9 247 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
0d4a1450 248 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
ebb945a9 249 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
a8f8b489 250 device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
aa4d7a4d 251 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
9274f4a9
BS		 252 break;
253 case 0xa0:
2094dd82 254 device->cname = "G200";
70c0f263 255 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
7356859a 256 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
c26fe843 257 device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
7c856522 258 device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
2f457367 259 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 260 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
4019aaa2 261 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
08f6fbdb 262 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
2984506f 263 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
5a5c7432 264 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
9ca3037e 265 device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
24a4ae86 266 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
3863c9bc
BS		 267 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
268 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 269 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 270 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 271 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
c46c3ddf 272 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9
BS		 273 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
274 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
275 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
276 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
277 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
a8f8b489 278 device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass;
aa4d7a4d 279 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
9274f4a9
BS		 280 break;
281 case 0xaa:
2094dd82 282 device->cname = "MCP77/MCP78";
70c0f263 283 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
7356859a 284 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
c26fe843 285 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
a7e4201f 286 device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass;
2f457367 287 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 288 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
4019aaa2 289 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
08f6fbdb 290 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
2984506f 291 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
5a5c7432 292 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
9ca3037e 293 device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
24a4ae86 294 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
3863c9bc
BS		 295 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
296 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 297 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 298 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 299 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
c46c3ddf 300 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9 301 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
0d4a1450 302 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
ebb945a9 303 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
0d4a1450 304 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
ebb945a9 305 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
a8f8b489 306 device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
aa4d7a4d 307 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
9274f4a9
BS		 308 break;
309 case 0xac:
2094dd82 310 device->cname = "MCP79/MCP7A";
70c0f263 311 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
7356859a 312 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
c26fe843 313 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
a7e4201f 314 device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass;
2f457367 315 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
d38ac521 316 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
4019aaa2 317 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
08f6fbdb 318 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
2984506f 319 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
5a5c7432 320 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
9ca3037e 321 device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
24a4ae86 322 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
3863c9bc
BS		 323 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
324 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
c9c0ccae 325 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 326 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 327 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
c46c3ddf 328 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9 329 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
0d4a1450 330 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
ebb945a9 331 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
0d4a1450 332 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
ebb945a9 333 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
a8f8b489 334 device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
aa4d7a4d 335 device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
9274f4a9
BS		 336 break;
337 case 0xa3:
2094dd82 338 device->cname = "GT215";
70c0f263 339 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
7356859a 340 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
c26fe843 341 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
8aceb7de 342 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
7b49bd68 343 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521 344 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cf336014 345 device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
08f6fbdb 346 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
2984506f 347 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
5a5c7432 348 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
9ca3037e 349 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
24a4ae86 350 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
3863c9bc
BS		 351 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
352 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
adec9bc3 353 device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass;
c9c0ccae 354 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 355 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 356 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
c46c3ddf 357 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9
BS		 358 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
359 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
0d4a1450
IM		 360 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
361 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
ebb945a9
BS		 362 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
363 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
a8f8b489 364 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
aa4d7a4d 365 device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
9274f4a9
BS		 366 break;
367 case 0xa5:
2094dd82 368 device->cname = "GT216";
70c0f263 369 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
7356859a 370 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
c26fe843 371 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
8aceb7de 372 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
7b49bd68 373 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521 374 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cf336014 375 device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
08f6fbdb 376 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
2984506f 377 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
5a5c7432 378 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
9ca3037e 379 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
24a4ae86 380 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
3863c9bc
BS		 381 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
382 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
adec9bc3 383 device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass;
c9c0ccae 384 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 385 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 386 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
c46c3ddf 387 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9 388 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
0d4a1450
IM		 389 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
390 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
ebb945a9
BS		 391 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
392 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
a8f8b489 393 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
aa4d7a4d 394 device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
9274f4a9
BS		 395 break;
396 case 0xa8:
2094dd82 397 device->cname = "GT218";
70c0f263 398 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
7356859a 399 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
c26fe843 400 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
8aceb7de 401 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
7b49bd68 402 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521 403 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cf336014 404 device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
08f6fbdb 405 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
2984506f 406 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
5a5c7432 407 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
9ca3037e 408 device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
24a4ae86 409 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
3863c9bc
BS		 410 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
411 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
adec9bc3 412 device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass;
c9c0ccae 413 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 414 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 415 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
c46c3ddf 416 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9 417 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
0d4a1450
IM		 418 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
419 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
ebb945a9
BS		 420 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
421 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
a8f8b489 422 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
aa4d7a4d 423 device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
9274f4a9
BS		 424 break;
425 case 0xaf:
2094dd82 426 device->cname = "MCP89";
70c0f263 427 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
7356859a 428 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
c26fe843 429 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
8aceb7de 430 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
7b49bd68 431 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521 432 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
4019aaa2 433 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass;
08f6fbdb 434 device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
2984506f 435 device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
5a5c7432 436 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
9ca3037e 437 device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass;
24a4ae86 438 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
3863c9bc
BS		 439 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
440 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
adec9bc3 441 device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass;
c9c0ccae 442 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 443 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
16c4f227 444 device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
c46c3ddf 445 device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
ebb945a9 446 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
0d4a1450
IM		 447 device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
448 device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
ebb945a9
BS		 449 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
450 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
a8f8b489 451 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
aa4d7a4d 452 device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
9274f4a9
BS		 453 break;
454 default:
455 nv_fatal(device, "unknown Tesla chipset\n");
456 return -EINVAL;
457 }
458
459 return 0;
460}
Linux kernel - Deliverables
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