Commit | Line | Data |
---|---|---|
9274f4a9 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
70c0f263 | 25 | #include <subdev/bios.h> |
a10220bb | 26 | #include <subdev/bus.h> |
e0996aea | 27 | #include <subdev/gpio.h> |
4196faa8 | 28 | #include <subdev/i2c.h> |
8aceb7de | 29 | #include <subdev/clock.h> |
aa1b9b48 | 30 | #include <subdev/therm.h> |
d38ac521 | 31 | #include <subdev/mxm.h> |
cb75d97e | 32 | #include <subdev/devinit.h> |
7d9115de | 33 | #include <subdev/mc.h> |
5a5c7432 | 34 | #include <subdev/timer.h> |
861d2107 BS |
35 | #include <subdev/fb.h> |
36 | #include <subdev/ltcg.h> | |
2c1a425e | 37 | #include <subdev/ibus.h> |
3863c9bc BS |
38 | #include <subdev/instmem.h> |
39 | #include <subdev/vm.h> | |
40 | #include <subdev/bar.h> | |
9274f4a9 | 41 | |
dded35de | 42 | #include <engine/device.h> |
ebb945a9 BS |
43 | #include <engine/dmaobj.h> |
44 | #include <engine/fifo.h> | |
45 | #include <engine/software.h> | |
46 | #include <engine/graph.h> | |
47 | #include <engine/disp.h> | |
4f32656d | 48 | #include <engine/copy.h> |
b2f04fc6 | 49 | #include <engine/bsp.h> |
a7416d0d | 50 | #include <engine/vp.h> |
fb9bff26 | 51 | #include <engine/ppp.h> |
ebb945a9 | 52 | |
9274f4a9 BS |
53 | int |
54 | nve0_identify(struct nouveau_device *device) | |
55 | { | |
56 | switch (device->chipset) { | |
57 | case 0xe4: | |
2094dd82 | 58 | device->cname = "GK104"; |
70c0f263 | 59 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
fa531bc8 | 60 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass; |
7dcd060c | 61 | device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass; |
8aceb7de | 62 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
bc79202f | 63 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
d38ac521 | 64 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
88524bc0 | 65 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; |
1b4fea0f | 66 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
a10220bb | 67 | device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; |
5a5c7432 | 68 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 69 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
861d2107 | 70 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
2c1a425e | 71 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
3863c9bc BS |
72 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; |
73 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | |
74 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | |
344e107d | 75 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; |
16c4f227 | 76 | device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; |
c46c3ddf | 77 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
30f4e087 | 78 | device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; |
46654061 | 79 | device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; |
4f32656d BS |
80 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; |
81 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; | |
b0bc5304 | 82 | device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; |
b2f04fc6 | 83 | device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; |
a7416d0d | 84 | device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; |
fb9bff26 | 85 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
9274f4a9 BS |
86 | break; |
87 | case 0xe7: | |
2094dd82 | 88 | device->cname = "GK107"; |
70c0f263 | 89 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
fa531bc8 | 90 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass; |
7dcd060c | 91 | device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass; |
8aceb7de | 92 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
bc79202f | 93 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
d38ac521 | 94 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
88524bc0 | 95 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; |
1b4fea0f | 96 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
a10220bb | 97 | device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; |
5a5c7432 | 98 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 99 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
caba5570 BS |
100 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
101 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; | |
102 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | |
103 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | |
104 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | |
105 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; | |
16c4f227 | 106 | device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; |
c46c3ddf | 107 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
30f4e087 | 108 | device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; |
caba5570 BS |
109 | device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; |
110 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; | |
111 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; | |
b0bc5304 | 112 | device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; |
caba5570 BS |
113 | device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; |
114 | device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; | |
115 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; | |
116 | break; | |
117 | case 0xe6: | |
118 | device->cname = "GK106"; | |
119 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | |
fa531bc8 | 120 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass; |
7dcd060c | 121 | device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass; |
caba5570 | 122 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
bc79202f | 123 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
caba5570 | 124 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
88524bc0 | 125 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; |
1b4fea0f | 126 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
a10220bb | 127 | device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; |
caba5570 | 128 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
1e9fc30e | 129 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
861d2107 | 130 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
2c1a425e | 131 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
3863c9bc BS |
132 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; |
133 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | |
134 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | |
344e107d | 135 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; |
16c4f227 | 136 | device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; |
c46c3ddf | 137 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
30f4e087 | 138 | device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; |
46654061 | 139 | device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; |
4f32656d BS |
140 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; |
141 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; | |
b0bc5304 | 142 | device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; |
b2f04fc6 | 143 | device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; |
a7416d0d | 144 | device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; |
fb9bff26 | 145 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
9274f4a9 | 146 | break; |
7b4f638b BS |
147 | case 0xf0: |
148 | device->cname = "GK110"; | |
149 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | |
150 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass; | |
151 | device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass; | |
152 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | |
153 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | |
154 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | |
88524bc0 | 155 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; |
1b4fea0f | 156 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
7b4f638b BS |
157 | device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; |
158 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | |
1e9fc30e | 159 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
7b4f638b BS |
160 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
161 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; | |
162 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | |
163 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | |
164 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | |
165 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; | |
16c4f227 | 166 | device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; |
c46c3ddf | 167 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
30f4e087 | 168 | device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; |
7b4f638b | 169 | device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass; |
7b4f638b BS |
170 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; |
171 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; | |
172 | device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; | |
9ec2dbba | 173 | #if 0 |
7b4f638b BS |
174 | device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; |
175 | device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; | |
176 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; | |
aabf19c2 BS |
177 | #endif |
178 | break; | |
179 | case 0x108: | |
180 | device->cname = "GK208"; | |
181 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | |
182 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass; | |
183 | device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass; | |
184 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | |
185 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | |
186 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | |
187 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; | |
188 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | |
189 | device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass; | |
190 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | |
191 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | |
192 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | |
193 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; | |
194 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | |
195 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | |
196 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | |
197 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; | |
198 | #if 0 | |
16c4f227 | 199 | device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; |
aabf19c2 BS |
200 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
201 | device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; | |
202 | #endif | |
203 | device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass; | |
204 | #if 0 | |
205 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; | |
206 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; | |
207 | device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; | |
208 | device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; | |
209 | device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; | |
210 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; | |
7b4f638b BS |
211 | #endif |
212 | break; | |
9274f4a9 BS |
213 | default: |
214 | nv_fatal(device, "unknown Kepler chipset\n"); | |
215 | return -EINVAL; | |
216 | } | |
217 | ||
218 | return 0; | |
219 | } |