[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / device / nve0.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <subdev/bios.h>
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/clock.h>
#include <subdev/therm.h>
#include <subdev/mxm.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/ltcg.h>
#include <subdev/ibus.h>
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/bar.h>
#include <subdev/pwr.h>
#include <subdev/volt.h>

#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/software.h>
#include <engine/graph.h>
#include <engine/disp.h>
#include <engine/copy.h>
#include <engine/bsp.h>
#include <engine/vp.h>
#include <engine/ppp.h>
#include <engine/perfmon.h>

int
nve0_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
	case 0xe4:
		device->cname = "GK104";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nve0_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvd0_pwr_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
		break;
	case 0xe7:
		device->cname = "GK107";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nve0_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvd0_pwr_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
		break;
	case 0xe6:
		device->cname = "GK106";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nve0_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvd0_pwr_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
		break;
	case 0xf0:
		device->cname = "GK110";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nve0_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PWR    ] = &nvd0_pwr_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  nvf0_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nvf0_disp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
#if 0
		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
#endif
		device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass;
		break;
	case 0x108:
		device->cname = "GK208";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nve0_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nve0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nvc0_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] =  nve0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nve0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_SUBDEV_PWR    ] = &nv108_pwr_oclass;
		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] =  nv108_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nvf0_disp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
#if 0
		device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
#endif
		break;
	default:
		nv_fatal(device, "unknown Kepler chipset\n");
		return -EINVAL;
	}

	return 0;
}
Commit	Line	Data
9274f4a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
70c0f263	25	#include <subdev/bios.h>
a10220bb	26	#include <subdev/bus.h>
e0996aea	27	#include <subdev/gpio.h>
4196faa8	28	#include <subdev/i2c.h>
8aceb7de	29	#include <subdev/clock.h>
aa1b9b48	30	#include <subdev/therm.h>
d38ac521	31	#include <subdev/mxm.h>
cb75d97e	32	#include <subdev/devinit.h>
7d9115de	33	#include <subdev/mc.h>
5a5c7432	34	#include <subdev/timer.h>
861d2107 BS	35	#include <subdev/fb.h>
861d2107 BS	36	#include <subdev/ltcg.h>
2c1a425e	37	#include <subdev/ibus.h>
3863c9bc BS	38	#include <subdev/instmem.h>
	39	#include <subdev/vm.h>
	40	#include <subdev/bar.h>
ff4b42c7	41	#include <subdev/pwr.h>
c9c0ccae	42	#include <subdev/volt.h>
9274f4a9	43
dded35de	44	#include <engine/device.h>
ebb945a9 BS	45	#include <engine/dmaobj.h>
	46	#include <engine/fifo.h>
	47	#include <engine/software.h>
	48	#include <engine/graph.h>
	49	#include <engine/disp.h>
4f32656d	50	#include <engine/copy.h>
b2f04fc6	51	#include <engine/bsp.h>
a7416d0d	52	#include <engine/vp.h>
fb9bff26	53	#include <engine/ppp.h>
aa4d7a4d	54	#include <engine/perfmon.h>
ebb945a9	55
9274f4a9 BS	56	int
	57	nve0_identify(struct nouveau_device *device)
	58	{
	59	switch (device->chipset) {
	60	case 0xe4:
2094dd82	61	device->cname = "GK104";
70c0f263	62	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
fa531bc8	63	device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
7dcd060c	64	device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
7c856522	65	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
bc79202f	66	device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
d38ac521	67	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cf336014	68	device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
1b4fea0f	69	device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
48ae0b35	70	device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
5a5c7432	71	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
aae95ca7	72	device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
861d2107	73	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
2c1a425e	74	device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
24a4ae86	75	device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
3863c9bc BS	76	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
3863c9bc BS	77	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ff4b42c7	78	device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
c9c0ccae	79	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
344e107d	80	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
16c4f227	81	device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
c46c3ddf	82	device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
30f4e087	83	device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
46654061	84	device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass;
4f32656d BS	85	device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
4f32656d BS	86	device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
b0bc5304	87	device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
b2f04fc6	88	device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
a7416d0d	89	device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
fb9bff26	90	device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
aa4d7a4d	91	device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
9274f4a9 BS	92	break;
9274f4a9 BS	93	case 0xe7:
2094dd82	94	device->cname = "GK107";
70c0f263	95	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
fa531bc8	96	device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
7dcd060c	97	device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
7c856522	98	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
bc79202f	99	device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
d38ac521	100	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cf336014	101	device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
1b4fea0f	102	device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
48ae0b35	103	device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
5a5c7432	104	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
aae95ca7	105	device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
caba5570 BS	106	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
caba5570 BS	107	device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
24a4ae86	108	device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
caba5570 BS	109	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
caba5570 BS	110	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ff4b42c7	111	device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
c9c0ccae	112	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
caba5570	113	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
16c4f227	114	device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
c46c3ddf	115	device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
30f4e087	116	device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
caba5570 BS	117	device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass;
	118	device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
	119	device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
b0bc5304	120	device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
caba5570 BS	121	device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
	122	device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
	123	device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
aa4d7a4d	124	device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
caba5570 BS	125	break;
	126	case 0xe6:
	127	device->cname = "GK106";
	128	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
fa531bc8	129	device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
7dcd060c	130	device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
7c856522	131	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
bc79202f	132	device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
caba5570	133	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cf336014	134	device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
1b4fea0f	135	device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
48ae0b35	136	device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
caba5570	137	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
aae95ca7	138	device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
861d2107	139	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
2c1a425e	140	device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
24a4ae86	141	device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
3863c9bc BS	142	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
3863c9bc BS	143	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ff4b42c7	144	device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
c9c0ccae	145	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
344e107d	146	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
16c4f227	147	device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
c46c3ddf	148	device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
30f4e087	149	device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
46654061	150	device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass;
4f32656d BS	151	device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
4f32656d BS	152	device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
b0bc5304	153	device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
b2f04fc6	154	device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
a7416d0d	155	device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
fb9bff26	156	device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
aa4d7a4d	157	device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
9274f4a9	158	break;
7b4f638b BS	159	case 0xf0:
	160	device->cname = "GK110";
	161	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
	162	device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
	163	device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
7c856522	164	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
7b4f638b BS	165	device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
7b4f638b BS	166	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cf336014	167	device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
1b4fea0f	168	device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
48ae0b35	169	device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
7b4f638b	170	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
aae95ca7	171	device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
7b4f638b BS	172	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
7b4f638b BS	173	device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
24a4ae86	174	device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
7b4f638b BS	175	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
7b4f638b BS	176	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ff4b42c7	177	device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
c9c0ccae	178	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
7b4f638b	179	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
16c4f227	180	device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
c46c3ddf	181	device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
30f4e087	182	device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass;
7b4f638b	183	device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass;
7b4f638b BS	184	device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
	185	device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
	186	device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
9ec2dbba	187	#if 0
7b4f638b BS	188	device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
	189	device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
	190	device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
aabf19c2	191	#endif
aa4d7a4d	192	device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass;
aabf19c2 BS	193	break;
	194	case 0x108:
	195	device->cname = "GK208";
	196	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
	197	device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
	198	device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
7c856522	199	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
aabf19c2 BS	200	device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
aabf19c2 BS	201	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cf336014	202	device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
aabf19c2	203	device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
48ae0b35	204	device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
aabf19c2	205	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
aae95ca7	206	device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
aabf19c2 BS	207	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
aabf19c2 BS	208	device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
24a4ae86	209	device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
aabf19c2 BS	210	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
aabf19c2 BS	211	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ff4b42c7	212	device->oclass[NVDEV_SUBDEV_PWR ] = &nv108_pwr_oclass;
c9c0ccae	213	device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
aabf19c2	214	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
a763951a	215	device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
aabf19c2	216	device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
96616b4c	217	device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass;
aabf19c2	218	device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass;
aabf19c2 BS	219	device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
	220	device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
	221	device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
daa9ab58	222	#if 0
aabf19c2 BS	223	device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
	224	device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
	225	device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
7b4f638b BS	226	#endif
7b4f638b BS	227	break;
9274f4a9 BS	228	default:
	229	nv_fatal(device, "unknown Kepler chipset\n");
	230	return -EINVAL;
	231	}
	232
	233	return 0;
	234	}