[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / dmaobj / nvd0.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <core/client.h>
#include <core/device.h>
#include <core/gpuobj.h>
#include <nvif/unpack.h>
#include <nvif/class.h>

#include <subdev/fb.h>

#include "priv.h"

struct nvd0_dmaobj_priv {
	struct nouveau_dmaobj base;
	u32 flags0;
};

static int
nvd0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
		 struct nouveau_object *parent,
		 struct nouveau_gpuobj **pgpuobj)
{
	struct nvd0_dmaobj_priv *priv = (void *)dmaobj;
	int ret;

	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
		switch (nv_mclass(parent->parent)) {
		case GF110_DISP_CORE_CHANNEL_DMA:
		case GK104_DISP_CORE_CHANNEL_DMA:
		case GK110_DISP_CORE_CHANNEL_DMA:
		case GM107_DISP_CORE_CHANNEL_DMA:
		case GM204_DISP_CORE_CHANNEL_DMA:
		case GF110_DISP_BASE_CHANNEL_DMA:
		case GK104_DISP_BASE_CHANNEL_DMA:
		case GK110_DISP_BASE_CHANNEL_DMA:
		case GF110_DISP_OVERLAY_CONTROL_DMA:
		case GK104_DISP_OVERLAY_CONTROL_DMA:
			break;
		default:
			return -EINVAL;
		}
	} else
		return 0;

	ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
	if (ret == 0) {
		nv_wo32(*pgpuobj, 0x00, priv->flags0);
		nv_wo32(*pgpuobj, 0x04, priv->base.start >> 8);
		nv_wo32(*pgpuobj, 0x08, priv->base.limit >> 8);
		nv_wo32(*pgpuobj, 0x0c, 0x00000000);
		nv_wo32(*pgpuobj, 0x10, 0x00000000);
		nv_wo32(*pgpuobj, 0x14, 0x00000000);
	}

	return ret;
}

static int
nvd0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
		 struct nouveau_oclass *oclass, void *data, u32 size,
		 struct nouveau_object **pobject)
{
	struct nouveau_dmaeng *dmaeng = (void *)engine;
	union {
		struct gf110_dma_v0 v0;
	} *args;
	struct nvd0_dmaobj_priv *priv;
	u32 kind, page;
	int ret;

	ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;
	args = data;

	nv_ioctl(parent, "create gf110 dma size %d\n", size);
	if (nvif_unpack(args->v0, 0, 0, false)) {
		nv_ioctl(parent, "create gf100 dma vers %d page %d kind %02x\n",
			 args->v0.version, args->v0.page, args->v0.kind);
		kind = args->v0.kind;
		page = args->v0.page;
	} else
	if (size == 0) {
		if (priv->base.target != NV_MEM_TARGET_VM) {
			kind = GF110_DMA_V0_KIND_PITCH;
			page = GF110_DMA_V0_PAGE_SP;
		} else {
			kind = GF110_DMA_V0_KIND_VM;
			page = GF110_DMA_V0_PAGE_LP;
		}
	} else
		return ret;

	if (page > 1)
		return -EINVAL;
	priv->flags0 = (kind << 20) | (page << 6);

	switch (priv->base.target) {
	case NV_MEM_TARGET_VRAM:
		priv->flags0 |= 0x00000009;
		break;
	case NV_MEM_TARGET_VM:
	case NV_MEM_TARGET_PCI:
	case NV_MEM_TARGET_PCI_NOSNOOP:
		/* XXX: don't currently know how to construct a real one
		 *      of these.  we only use them to represent pushbufs
		 *      on these chipsets, and the classes that use them
		 *      deal with the target themselves.
		 */
		break;
	default:
		return -EINVAL;
	}

	return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
}

static struct nouveau_ofuncs
nvd0_dmaobj_ofuncs = {
	.ctor =  nvd0_dmaobj_ctor,
	.dtor = _nvkm_dmaobj_dtor,
	.init = _nvkm_dmaobj_init,
	.fini = _nvkm_dmaobj_fini,
};

static struct nouveau_oclass
nvd0_dmaeng_sclass[] = {
	{ NV_DMA_FROM_MEMORY, &nvd0_dmaobj_ofuncs },
	{ NV_DMA_TO_MEMORY, &nvd0_dmaobj_ofuncs },
	{ NV_DMA_IN_MEMORY, &nvd0_dmaobj_ofuncs },
	{}
};

struct nouveau_oclass *
nvd0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
	.base.handle = NV_ENGINE(DMAOBJ, 0xd0),
	.base.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = _nvkm_dmaeng_ctor,
		.dtor = _nvkm_dmaeng_dtor,
		.init = _nvkm_dmaeng_init,
		.fini = _nvkm_dmaeng_fini,
	},
	.sclass = nvd0_dmaeng_sclass,
	.bind = nvd0_dmaobj_bind,
}.base;
Commit	Line	Data
344e107d BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
4acfd707	25	#include <core/client.h>
344e107d BS	26	#include <core/device.h>
344e107d BS	27	#include <core/gpuobj.h>
4acfd707 BS	28	#include <nvif/unpack.h>
4acfd707 BS	29	#include <nvif/class.h>
344e107d BS	30
344e107d BS	31	#include <subdev/fb.h>
bc98540b BS	32
bc98540b BS	33	#include "priv.h"
344e107d	34
b2c81703 BS	35	struct nvd0_dmaobj_priv {
	36	struct nouveau_dmaobj base;
	37	u32 flags0;
344e107d BS	38	};
	39
	40	static int
b2c81703	41	nvd0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
344e107d	42	struct nouveau_object *parent,
344e107d BS	43	struct nouveau_gpuobj **pgpuobj)
344e107d BS	44	{
b2c81703	45	struct nvd0_dmaobj_priv priv = (void )dmaobj;
47a1e0fe	46	int ret;
344e107d BS	47
	48	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
	49	switch (nv_mclass(parent->parent)) {
648d4dfd BS	50	case GF110_DISP_CORE_CHANNEL_DMA:
	51	case GK104_DISP_CORE_CHANNEL_DMA:
	52	case GK110_DISP_CORE_CHANNEL_DMA:
	53	case GM107_DISP_CORE_CHANNEL_DMA:
1f89b475	54	case GM204_DISP_CORE_CHANNEL_DMA:
648d4dfd BS	55	case GF110_DISP_BASE_CHANNEL_DMA:
	56	case GK104_DISP_BASE_CHANNEL_DMA:
	57	case GK110_DISP_BASE_CHANNEL_DMA:
	58	case GF110_DISP_OVERLAY_CONTROL_DMA:
	59	case GK104_DISP_OVERLAY_CONTROL_DMA:
344e107d BS	60	break;
	61	default:
	62	return -EINVAL;
	63	}
	64	} else
	65	return 0;
	66
b2c81703 BS	67	ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
	68	if (ret == 0) {
	69	nv_wo32(*pgpuobj, 0x00, priv->flags0);
	70	nv_wo32(*pgpuobj, 0x04, priv->base.start >> 8);
	71	nv_wo32(*pgpuobj, 0x08, priv->base.limit >> 8);
	72	nv_wo32(*pgpuobj, 0x0c, 0x00000000);
	73	nv_wo32(*pgpuobj, 0x10, 0x00000000);
	74	nv_wo32(*pgpuobj, 0x14, 0x00000000);
	75	}
	76
	77	return ret;
	78	}
	79
	80	static int
	81	nvd0_dmaobj_ctor(struct nouveau_object parent, struct nouveau_object engine,
	82	struct nouveau_oclass oclass, void data, u32 size,
	83	struct nouveau_object **pobject)
	84	{
	85	struct nouveau_dmaeng dmaeng = (void )engine;
b2c81703	86	union {
4acfd707	87	struct gf110_dma_v0 v0;
b2c81703	88	} *args;
4acfd707 BS	89	struct nvd0_dmaobj_priv *priv;
4acfd707 BS	90	u32 kind, page;
b2c81703 BS	91	int ret;
	92
	93	ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
	94	*pobject = nv_object(priv);
	95	if (ret)
	96	return ret;
	97	args = data;
	98
4acfd707 BS	99	nv_ioctl(parent, "create gf110 dma size %d\n", size);
	100	if (nvif_unpack(args->v0, 0, 0, false)) {
	101	nv_ioctl(parent, "create gf100 dma vers %d page %d kind %02x\n",
	102	args->v0.version, args->v0.page, args->v0.kind);
	103	kind = args->v0.kind;
	104	page = args->v0.page;
	105	} else
	106	if (size == 0) {
	107	if (priv->base.target != NV_MEM_TARGET_VM) {
	108	kind = GF110_DMA_V0_KIND_PITCH;
	109	page = GF110_DMA_V0_PAGE_SP;
47a1e0fe	110	} else {
4acfd707 BS	111	kind = GF110_DMA_V0_KIND_VM;
4acfd707 BS	112	page = GF110_DMA_V0_PAGE_LP;
47a1e0fe	113	}
4acfd707 BS	114	} else
4acfd707 BS	115	return ret;
47a1e0fe	116
4acfd707 BS	117	if (page > 1)
	118	return -EINVAL;
	119	priv->flags0 = (kind << 20) \| (page << 6);
47a1e0fe	120
b2c81703	121	switch (priv->base.target) {
47a1e0fe	122	case NV_MEM_TARGET_VRAM:
b2c81703 BS	123	priv->flags0 \|= 0x00000009;
	124	break;
	125	case NV_MEM_TARGET_VM:
	126	case NV_MEM_TARGET_PCI:
	127	case NV_MEM_TARGET_PCI_NOSNOOP:
	128	/* XXX: don't currently know how to construct a real one
	129	* of these. we only use them to represent pushbufs
	130	* on these chipsets, and the classes that use them
	131	* deal with the target themselves.
	132	*/
47a1e0fe BS	133	break;
	134	default:
	135	return -EINVAL;
47a1e0fe BS	136	}
47a1e0fe BS	137
b2c81703	138	return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
344e107d BS	139	}
344e107d BS	140
b2c81703 BS	141	static struct nouveau_ofuncs
	142	nvd0_dmaobj_ofuncs = {
	143	.ctor = nvd0_dmaobj_ctor,
	144	.dtor = _nvkm_dmaobj_dtor,
	145	.init = _nvkm_dmaobj_init,
	146	.fini = _nvkm_dmaobj_fini,
	147	};
	148
	149	static struct nouveau_oclass
	150	nvd0_dmaeng_sclass[] = {
4acfd707 BS	151	{ NV_DMA_FROM_MEMORY, &nvd0_dmaobj_ofuncs },
	152	{ NV_DMA_TO_MEMORY, &nvd0_dmaobj_ofuncs },
	153	{ NV_DMA_IN_MEMORY, &nvd0_dmaobj_ofuncs },
b2c81703 BS	154	{}
	155	};
	156
bc98540b BS	157	struct nouveau_oclass *
	158	nvd0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
	159	.base.handle = NV_ENGINE(DMAOBJ, 0xd0),
	160	.base.ofuncs = &(struct nouveau_ofuncs) {
	161	.ctor = _nvkm_dmaeng_ctor,
	162	.dtor = _nvkm_dmaeng_dtor,
	163	.init = _nvkm_dmaeng_init,
	164	.fini = _nvkm_dmaeng_fini,
344e107d	165	},
b2c81703	166	.sclass = nvd0_dmaeng_sclass,
bc98540b BS	167	.bind = nvd0_dmaobj_bind,
bc98540b BS	168	}.base;