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1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | */ | |
22 | ||
a0fd4ec8 | 23 | #include <engine/falcon.h> |
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24 | #include <subdev/timer.h> |
25 | ||
9b234db3 ML |
26 | void |
27 | nouveau_falcon_intr(struct nouveau_subdev *subdev) | |
28 | { | |
29 | struct nouveau_falcon *falcon = (void *)subdev; | |
30 | u32 dispatch = nv_ro32(falcon, 0x01c); | |
31 | u32 intr = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16); | |
32 | ||
33 | if (intr & 0x00000010) { | |
34 | nv_debug(falcon, "ucode halted\n"); | |
35 | nv_wo32(falcon, 0x004, 0x00000010); | |
36 | intr &= ~0x00000010; | |
37 | } | |
38 | ||
39 | if (intr) { | |
40 | nv_error(falcon, "unhandled intr 0x%08x\n", intr); | |
41 | nv_wo32(falcon, 0x004, intr); | |
42 | } | |
43 | } | |
44 | ||
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45 | u32 |
46 | _nouveau_falcon_rd32(struct nouveau_object *object, u64 addr) | |
47 | { | |
48 | struct nouveau_falcon *falcon = (void *)object; | |
49 | return nv_rd32(falcon, falcon->addr + addr); | |
50 | } | |
51 | ||
52 | void | |
53 | _nouveau_falcon_wr32(struct nouveau_object *object, u64 addr, u32 data) | |
54 | { | |
55 | struct nouveau_falcon *falcon = (void *)object; | |
56 | nv_wr32(falcon, falcon->addr + addr, data); | |
57 | } | |
58 | ||
59 | int | |
60 | _nouveau_falcon_init(struct nouveau_object *object) | |
61 | { | |
62 | struct nouveau_device *device = nv_device(object); | |
63 | struct nouveau_falcon *falcon = (void *)object; | |
64 | const struct firmware *fw; | |
65 | char name[32] = "internal"; | |
66 | int ret, i; | |
67 | u32 caps; | |
68 | ||
69 | /* enable engine, and determine its capabilities */ | |
70 | ret = nouveau_engine_init(&falcon->base); | |
71 | if (ret) | |
72 | return ret; | |
73 | ||
74 | if (device->chipset < 0xa3 || | |
75 | device->chipset == 0xaa || device->chipset == 0xac) { | |
76 | falcon->version = 0; | |
77 | falcon->secret = (falcon->addr == 0x087000) ? 1 : 0; | |
78 | } else { | |
79 | caps = nv_ro32(falcon, 0x12c); | |
80 | falcon->version = (caps & 0x0000000f); | |
81 | falcon->secret = (caps & 0x00000030) >> 4; | |
82 | } | |
83 | ||
84 | caps = nv_ro32(falcon, 0x108); | |
85 | falcon->code.limit = (caps & 0x000001ff) << 8; | |
86 | falcon->data.limit = (caps & 0x0003fe00) >> 1; | |
87 | ||
88 | nv_debug(falcon, "falcon version: %d\n", falcon->version); | |
89 | nv_debug(falcon, "secret level: %d\n", falcon->secret); | |
90 | nv_debug(falcon, "code limit: %d\n", falcon->code.limit); | |
91 | nv_debug(falcon, "data limit: %d\n", falcon->data.limit); | |
92 | ||
93 | /* wait for 'uc halted' to be signalled before continuing */ | |
1e98380c ML |
94 | if (falcon->secret && falcon->version < 4) { |
95 | if (!falcon->version) | |
96 | nv_wait(falcon, 0x008, 0x00000010, 0x00000010); | |
97 | else | |
98 | nv_wait(falcon, 0x180, 0x80000000, 0); | |
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99 | nv_wo32(falcon, 0x004, 0x00000010); |
100 | } | |
101 | ||
102 | /* disable all interrupts */ | |
103 | nv_wo32(falcon, 0x014, 0xffffffff); | |
104 | ||
105 | /* no default ucode provided by the engine implementation, try and | |
106 | * locate a "self-bootstrapping" firmware image for the engine | |
107 | */ | |
108 | if (!falcon->code.data) { | |
109 | snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03x", | |
110 | device->chipset, falcon->addr >> 12); | |
111 | ||
112 | ret = request_firmware(&fw, name, &device->pdev->dev); | |
113 | if (ret == 0) { | |
114 | falcon->code.data = kmemdup(fw->data, fw->size, GFP_KERNEL); | |
115 | falcon->code.size = fw->size; | |
116 | falcon->data.data = NULL; | |
117 | falcon->data.size = 0; | |
118 | release_firmware(fw); | |
119 | } | |
120 | ||
121 | falcon->external = true; | |
122 | } | |
123 | ||
124 | /* next step is to try and load "static code/data segment" firmware | |
125 | * images for the engine | |
126 | */ | |
127 | if (!falcon->code.data) { | |
128 | snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xd", | |
129 | device->chipset, falcon->addr >> 12); | |
130 | ||
131 | ret = request_firmware(&fw, name, &device->pdev->dev); | |
132 | if (ret) { | |
133 | nv_error(falcon, "unable to load firmware data\n"); | |
134 | return ret; | |
135 | } | |
136 | ||
137 | falcon->data.data = kmemdup(fw->data, fw->size, GFP_KERNEL); | |
138 | falcon->data.size = fw->size; | |
139 | release_firmware(fw); | |
140 | if (!falcon->data.data) | |
141 | return -ENOMEM; | |
142 | ||
143 | snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xc", | |
144 | device->chipset, falcon->addr >> 12); | |
145 | ||
146 | ret = request_firmware(&fw, name, &device->pdev->dev); | |
147 | if (ret) { | |
148 | nv_error(falcon, "unable to load firmware code\n"); | |
149 | return ret; | |
150 | } | |
151 | ||
152 | falcon->code.data = kmemdup(fw->data, fw->size, GFP_KERNEL); | |
153 | falcon->code.size = fw->size; | |
154 | release_firmware(fw); | |
155 | if (!falcon->code.data) | |
156 | return -ENOMEM; | |
157 | } | |
158 | ||
159 | nv_debug(falcon, "firmware: %s (%s)\n", name, falcon->data.data ? | |
160 | "static code/data segments" : "self-bootstrapping"); | |
161 | ||
162 | /* ensure any "self-bootstrapping" firmware image is in vram */ | |
163 | if (!falcon->data.data && !falcon->core) { | |
164 | ret = nouveau_gpuobj_new(object->parent, NULL, | |
165 | falcon->code.size, 256, 0, | |
166 | &falcon->core); | |
167 | if (ret) { | |
168 | nv_error(falcon, "core allocation failed, %d\n", ret); | |
169 | return ret; | |
170 | } | |
171 | ||
172 | for (i = 0; i < falcon->code.size; i += 4) | |
173 | nv_wo32(falcon->core, i, falcon->code.data[i / 4]); | |
174 | } | |
175 | ||
176 | /* upload firmware bootloader (or the full code segments) */ | |
177 | if (falcon->core) { | |
178 | if (device->card_type < NV_C0) | |
179 | nv_wo32(falcon, 0x618, 0x04000000); | |
180 | else | |
181 | nv_wo32(falcon, 0x618, 0x00000114); | |
182 | nv_wo32(falcon, 0x11c, 0); | |
183 | nv_wo32(falcon, 0x110, falcon->core->addr >> 8); | |
184 | nv_wo32(falcon, 0x114, 0); | |
185 | nv_wo32(falcon, 0x118, 0x00006610); | |
186 | } else { | |
187 | if (falcon->code.size > falcon->code.limit || | |
188 | falcon->data.size > falcon->data.limit) { | |
189 | nv_error(falcon, "ucode exceeds falcon limit(s)\n"); | |
190 | return -EINVAL; | |
191 | } | |
192 | ||
193 | if (falcon->version < 3) { | |
194 | nv_wo32(falcon, 0xff8, 0x00100000); | |
195 | for (i = 0; i < falcon->code.size / 4; i++) | |
196 | nv_wo32(falcon, 0xff4, falcon->code.data[i]); | |
197 | } else { | |
198 | nv_wo32(falcon, 0x180, 0x01000000); | |
199 | for (i = 0; i < falcon->code.size / 4; i++) { | |
200 | if ((i & 0x3f) == 0) | |
201 | nv_wo32(falcon, 0x188, i >> 6); | |
202 | nv_wo32(falcon, 0x184, falcon->code.data[i]); | |
203 | } | |
204 | } | |
205 | } | |
206 | ||
207 | /* upload data segment (if necessary), zeroing the remainder */ | |
208 | if (falcon->version < 3) { | |
209 | nv_wo32(falcon, 0xff8, 0x00000000); | |
210 | for (i = 0; !falcon->core && i < falcon->data.size / 4; i++) | |
211 | nv_wo32(falcon, 0xff4, falcon->data.data[i]); | |
212 | for (; i < falcon->data.limit; i += 4) | |
213 | nv_wo32(falcon, 0xff4, 0x00000000); | |
214 | } else { | |
215 | nv_wo32(falcon, 0x1c0, 0x01000000); | |
216 | for (i = 0; !falcon->core && i < falcon->data.size / 4; i++) | |
217 | nv_wo32(falcon, 0x1c4, falcon->data.data[i]); | |
218 | for (; i < falcon->data.limit / 4; i++) | |
219 | nv_wo32(falcon, 0x1c4, 0x00000000); | |
220 | } | |
221 | ||
222 | /* start it running */ | |
223 | nv_wo32(falcon, 0x10c, 0x00000001); /* BLOCK_ON_FIFO */ | |
224 | nv_wo32(falcon, 0x104, 0x00000000); /* ENTRY */ | |
225 | nv_wo32(falcon, 0x100, 0x00000002); /* TRIGGER */ | |
226 | nv_wo32(falcon, 0x048, 0x00000003); /* FIFO | CHSW */ | |
227 | return 0; | |
228 | } | |
229 | ||
230 | int | |
231 | _nouveau_falcon_fini(struct nouveau_object *object, bool suspend) | |
232 | { | |
233 | struct nouveau_falcon *falcon = (void *)object; | |
234 | ||
235 | if (!suspend) { | |
236 | nouveau_gpuobj_ref(NULL, &falcon->core); | |
237 | if (falcon->external) { | |
238 | kfree(falcon->data.data); | |
239 | kfree(falcon->code.data); | |
240 | falcon->code.data = NULL; | |
241 | } | |
242 | } | |
243 | ||
244 | nv_mo32(falcon, 0x048, 0x00000003, 0x00000000); | |
245 | nv_wo32(falcon, 0x014, 0xffffffff); | |
246 | ||
247 | return nouveau_engine_fini(&falcon->base, suspend); | |
248 | } | |
249 | ||
250 | int | |
251 | nouveau_falcon_create_(struct nouveau_object *parent, | |
252 | struct nouveau_object *engine, | |
253 | struct nouveau_oclass *oclass, u32 addr, bool enable, | |
254 | const char *iname, const char *fname, | |
255 | int length, void **pobject) | |
256 | { | |
257 | struct nouveau_falcon *falcon; | |
258 | int ret; | |
259 | ||
260 | ret = nouveau_engine_create_(parent, engine, oclass, enable, iname, | |
261 | fname, length, pobject); | |
262 | falcon = *pobject; | |
263 | if (ret) | |
264 | return ret; | |
265 | ||
266 | falcon->addr = addr; | |
267 | return 0; | |
268 | } |