drm/gf100-/gr: split gpc state into its subunits
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / graph / ctxnvd7.c
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1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24
c33b1e8c 25#include "ctxnvc0.h"
26410c67 26
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27/*******************************************************************************
28 * PGRAPH context register lists
29 ******************************************************************************/
26410c67 30
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31static const struct nvc0_graph_init
32nvd7_grctx_init_ds_0[] = {
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33 { 0x405800, 1, 0x04, 0x0f8000bf },
34 { 0x405830, 1, 0x04, 0x02180324 },
35 { 0x405834, 1, 0x04, 0x08000000 },
36 { 0x405838, 1, 0x04, 0x00000000 },
37 { 0x405854, 1, 0x04, 0x00000000 },
38 { 0x405870, 4, 0x04, 0x00000001 },
39 { 0x405a00, 2, 0x04, 0x00000000 },
40 { 0x405a18, 1, 0x04, 0x00000000 },
41 {}
42};
43
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44static const struct nvc0_graph_init
45nvd7_grctx_init_pd_0[] = {
46 { 0x406020, 1, 0x04, 0x000103c1 },
47 { 0x406028, 4, 0x04, 0x00000001 },
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48 { 0x4064a8, 1, 0x04, 0x00000000 },
49 { 0x4064ac, 1, 0x04, 0x00003fff },
50 { 0x4064b4, 3, 0x04, 0x00000000 },
51 { 0x4064c0, 1, 0x04, 0x801a0078 },
52 { 0x4064c4, 1, 0x04, 0x00c9ffff },
53 { 0x4064d0, 8, 0x04, 0x00000000 },
54 {}
55};
56
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57static const struct nvc0_graph_pack
58nvd7_grctx_pack_hub[] = {
59 { nvc0_grctx_init_main_0 },
60 { nvd9_grctx_init_fe_0 },
61 { nvc0_grctx_init_pri_0 },
62 { nvc0_grctx_init_memfmt_0 },
63 { nvd7_grctx_init_ds_0 },
64 { nvd7_grctx_init_pd_0 },
65 { nvc0_grctx_init_rstr2d_0 },
66 { nvc0_grctx_init_scc_0 },
67 { nvd9_grctx_init_be_0 },
68 {}
69};
70
71static const struct nvc0_graph_init
97af71fa 72nvd7_grctx_init_setup_0[] = {
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73 { 0x418800, 1, 0x04, 0x7006860a },
74 { 0x418808, 3, 0x04, 0x00000000 },
75 { 0x418828, 1, 0x04, 0x00008442 },
76 { 0x418830, 1, 0x04, 0x10000001 },
77 { 0x4188d8, 1, 0x04, 0x00000008 },
78 { 0x4188e0, 1, 0x04, 0x01000000 },
79 { 0x4188e8, 5, 0x04, 0x00000000 },
80 { 0x4188fc, 1, 0x04, 0x20100018 },
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81 {}
82};
83
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84static const struct nvc0_graph_pack
85nvd7_grctx_pack_gpc[] = {
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86 { nvc0_grctx_init_gpc_unk_0 },
87 { nvd9_grctx_init_prop_0 },
88 { nvd9_grctx_init_gpc_unk_1 },
89 { nvd7_grctx_init_setup_0 },
90 { nvc0_grctx_init_zcull_0 },
91 { nvd9_grctx_init_crstr_0 },
92 { nvc1_grctx_init_gpm_0 },
93 { nvc0_grctx_init_gcc_0 },
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94 {}
95};
96
97static const struct nvc0_graph_init
98nvd7_grctx_init_tpc_0[] = {
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99 { 0x419848, 1, 0x04, 0x00000000 },
100 { 0x419864, 1, 0x04, 0x00000129 },
101 { 0x419888, 1, 0x04, 0x00000000 },
102 { 0x419a00, 1, 0x04, 0x000001f0 },
103 { 0x419a04, 1, 0x04, 0x00000001 },
104 { 0x419a08, 1, 0x04, 0x00000023 },
105 { 0x419a0c, 1, 0x04, 0x00020000 },
106 { 0x419a10, 1, 0x04, 0x00000000 },
107 { 0x419a14, 1, 0x04, 0x00000200 },
108 { 0x419a1c, 1, 0x04, 0x00008000 },
109 { 0x419a20, 1, 0x04, 0x00000800 },
110 { 0x419ac4, 1, 0x04, 0x0017f440 },
111 { 0x419c00, 1, 0x04, 0x0000000a },
112 { 0x419c04, 1, 0x04, 0x00000006 },
113 { 0x419c08, 1, 0x04, 0x00000002 },
114 { 0x419c20, 1, 0x04, 0x00000000 },
115 { 0x419c24, 1, 0x04, 0x00084210 },
116 { 0x419c28, 1, 0x04, 0x3efbefbe },
117 { 0x419cb0, 1, 0x04, 0x00020048 },
118 { 0x419ce8, 1, 0x04, 0x00000000 },
119 { 0x419cf4, 1, 0x04, 0x00000183 },
120 { 0x419e04, 3, 0x04, 0x00000000 },
121 { 0x419e10, 1, 0x04, 0x00000002 },
122 { 0x419e44, 1, 0x04, 0x001beff2 },
123 { 0x419e48, 1, 0x04, 0x00000000 },
124 { 0x419e4c, 1, 0x04, 0x0000000f },
125 { 0x419e50, 17, 0x04, 0x00000000 },
126 { 0x419e98, 1, 0x04, 0x00000000 },
127 { 0x419ee0, 1, 0x04, 0x00010110 },
128 { 0x419f30, 11, 0x04, 0x00000000 },
129 {}
130};
131
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132static const struct nvc0_graph_pack
133nvd7_grctx_pack_tpc[] = {
134 { nvd7_grctx_init_tpc_0 },
135 {}
136};
137
138static const struct nvc0_graph_init
139nvd7_grctx_init_ppc_0[] = {
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140 { 0x41be24, 1, 0x04, 0x00000002 },
141 { 0x41bec0, 1, 0x04, 0x12180000 },
142 { 0x41bec4, 1, 0x04, 0x00003fff },
143 { 0x41bee4, 1, 0x04, 0x03240218 },
144 { 0x41bf00, 1, 0x04, 0x0a418820 },
145 { 0x41bf04, 1, 0x04, 0x062080e6 },
146 { 0x41bf08, 1, 0x04, 0x020398a4 },
147 { 0x41bf0c, 1, 0x04, 0x0e629062 },
148 { 0x41bf10, 1, 0x04, 0x0a418820 },
149 { 0x41bf14, 1, 0x04, 0x000000e6 },
150 { 0x41bfd0, 1, 0x04, 0x00900103 },
151 { 0x41bfe0, 1, 0x04, 0x00400001 },
152 { 0x41bfe4, 1, 0x04, 0x00000000 },
153 {}
154};
155
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156static const struct nvc0_graph_pack
157nvd7_grctx_pack_ppc[] = {
158 { nvd7_grctx_init_ppc_0 },
159 {}
160};
161
162/*******************************************************************************
163 * PGRAPH context implementation
164 ******************************************************************************/
165
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166static void
167nvd7_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
168{
169 u32 magic[GPC_MAX][2];
170 u32 offset;
171 int gpc;
172
173 mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
174 mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
175 mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
176 mmio_list(0x40800c, 0x00000000, 8, 1);
177 mmio_list(0x408010, 0x80000000, 0, 0);
178 mmio_list(0x419004, 0x00000000, 8, 1);
179 mmio_list(0x419008, 0x00000000, 0, 0);
180 mmio_list(0x408004, 0x00000000, 8, 0);
181 mmio_list(0x408008, 0x80000018, 0, 0);
182 mmio_list(0x418808, 0x00000000, 8, 0);
183 mmio_list(0x41880c, 0x80000018, 0, 0);
184 mmio_list(0x418810, 0x80000000, 12, 2);
185 mmio_list(0x419848, 0x10000000, 12, 2);
186
187 mmio_list(0x405830, 0x02180324, 0, 0);
188 mmio_list(0x4064c4, 0x00c9ffff, 0, 0);
189
190 for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
191 u16 magic0 = 0x0218 * priv->tpc_nr[gpc];
192 u16 magic1 = 0x0324 * priv->tpc_nr[gpc];
193 magic[gpc][0] = 0x10000000 | (magic0 << 16) | offset;
194 magic[gpc][1] = 0x00000000 | (magic1 << 16);
195 offset += 0x0324 * priv->tpc_nr[gpc];
196 }
197
198 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
199 mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0);
200 mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0);
201 offset += 0x07ff * priv->tpc_nr[gpc];
202 }
203 mmio_list(0x17e91c, 0x03060609, 0, 0); /* different from kepler */
204}
205
206void
207nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
208{
209 struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
210 int i;
211
212 nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
213
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214 nvc0_graph_mmio(priv, oclass->hub);
215 nvc0_graph_mmio(priv, oclass->gpc);
216 nvc0_graph_mmio(priv, oclass->zcull);
217 nvc0_graph_mmio(priv, oclass->tpc);
218 nvc0_graph_mmio(priv, oclass->ppc);
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219
220 nv_wr32(priv, 0x404154, 0x00000000);
221
222 oclass->mods(priv, info);
d196e16e 223 oclass->unkn(priv);
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224
225 nvc0_grctx_generate_tpcid(priv);
226 nvc0_grctx_generate_r406028(priv);
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227 nvc0_grctx_generate_r4060a8(priv);
228 nve4_grctx_generate_r418bb8(priv);
229 nvc0_grctx_generate_r406800(priv);
230
231 for (i = 0; i < 8; i++)
232 nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
233
234 nvc0_graph_icmd(priv, oclass->icmd);
235 nv_wr32(priv, 0x404154, 0x00000400);
236 nvc0_graph_mthd(priv, oclass->mthd);
237 nv_mask(priv, 0x000260, 0x00000001, 0x00000001);
238}
239
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240struct nouveau_oclass *
241nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
242 .base.handle = NV_ENGCTX(GR, 0xd7),
243 .base.ofuncs = &(struct nouveau_ofuncs) {
244 .ctor = nvc0_graph_context_ctor,
245 .dtor = nvc0_graph_context_dtor,
246 .init = _nouveau_graph_context_init,
247 .fini = _nouveau_graph_context_fini,
248 .rd32 = _nouveau_graph_context_rd32,
249 .wr32 = _nouveau_graph_context_wr32,
250 },
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251 .main = nvd7_grctx_generate_main,
252 .mods = nvd7_grctx_generate_mods,
253 .unkn = nve4_grctx_generate_unkn,
254 .hub = nvd7_grctx_pack_hub,
255 .gpc = nvd7_grctx_pack_gpc,
256 .zcull = nvc0_grctx_pack_zcull,
257 .tpc = nvd7_grctx_pack_tpc,
258 .ppc = nvd7_grctx_pack_ppc,
259 .icmd = nvd9_grctx_pack_icmd,
260 .mthd = nvd9_grctx_pack_mthd,
26410c67 261}.base;
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