[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / software / nv50.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <core/os.h>
#include <core/class.h>
#include <core/engctx.h>
#include <core/namedb.h>
#include <core/handle.h>
#include <core/gpuobj.h>
#include <core/event.h>

#include <subdev/bar.h>

#include <engine/disp.h>

#include "nv50.h"

/*******************************************************************************
 * software object classes
 ******************************************************************************/

static int
nv50_software_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd,
			      void *args, u32 size)
{
	struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
	struct nouveau_fifo_chan *fifo = (void *)nv_object(chan)->parent;
	struct nouveau_handle *handle;
	int ret = -EINVAL;

	handle = nouveau_namedb_get(nv_namedb(fifo), *(u32 *)args);
	if (!handle)
		return -ENOENT;

	if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) {
		struct nouveau_gpuobj *gpuobj = nv_gpuobj(handle->object);
		chan->vblank.ctxdma = gpuobj->node->offset >> 4;
		ret = 0;
	}
	nouveau_namedb_put(handle);
	return ret;
}

static int
nv50_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
				 void *args, u32 size)
{
	struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
	chan->vblank.offset = *(u32 *)args;
	return 0;
}

static int
nv50_software_mthd_vblsem_value(struct nouveau_object *object, u32 mthd,
				void *args, u32 size)
{
	struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
	chan->vblank.value = *(u32 *)args;
	return 0;
}

static int
nv50_software_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
				  void *args, u32 size)
{
	struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
	struct nouveau_disp *disp = nouveau_disp(object);
	u32 crtc = *(u32 *)args;
	if (crtc > 1)
		return -EINVAL;

	nouveau_event_get(disp->vblank, crtc, &chan->vblank.event);
	return 0;
}

static int
nv50_software_mthd_flip(struct nouveau_object *object, u32 mthd,
			void *args, u32 size)
{
	struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
	if (chan->base.flip)
		return chan->base.flip(chan->base.flip_data);
	return -EINVAL;
}

static struct nouveau_omthds
nv50_software_omthds[] = {
	{ 0x018c, 0x018c, nv50_software_mthd_dma_vblsem },
	{ 0x0400, 0x0400, nv50_software_mthd_vblsem_offset },
	{ 0x0404, 0x0404, nv50_software_mthd_vblsem_value },
	{ 0x0408, 0x0408, nv50_software_mthd_vblsem_release },
	{ 0x0500, 0x0500, nv50_software_mthd_flip },
	{}
};

static struct nouveau_oclass
nv50_software_sclass[] = {
	{ 0x506e, &nouveau_object_ofuncs, nv50_software_omthds },
	{}
};

/*******************************************************************************
 * software context
 ******************************************************************************/

static int
nv50_software_vblsem_release(struct nouveau_eventh *event, int head)
{
	struct nv50_software_chan *chan =
		container_of(event, typeof(*chan), vblank.event);
	struct nv50_software_priv *priv = (void *)nv_object(chan)->engine;
	struct nouveau_bar *bar = nouveau_bar(priv);

	nv_wr32(priv, 0x001704, chan->vblank.channel);
	nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
	bar->flush(bar);

	if (nv_device(priv)->chipset == 0x50) {
		nv_wr32(priv, 0x001570, chan->vblank.offset);
		nv_wr32(priv, 0x001574, chan->vblank.value);
	} else {
		nv_wr32(priv, 0x060010, chan->vblank.offset);
		nv_wr32(priv, 0x060014, chan->vblank.value);
	}

	return NVKM_EVENT_DROP;
}

int
nv50_software_context_ctor(struct nouveau_object *parent,
			   struct nouveau_object *engine,
			   struct nouveau_oclass *oclass, void *data, u32 size,
			   struct nouveau_object **pobject)
{
	struct nv50_software_cclass *pclass = (void *)oclass;
	struct nv50_software_chan *chan;
	int ret;

	ret = nouveau_software_context_create(parent, engine, oclass, &chan);
	*pobject = nv_object(chan);
	if (ret)
		return ret;

	chan->vblank.channel = nv_gpuobj(parent->parent)->addr >> 12;
	chan->vblank.event.func = pclass->vblank;
	return 0;
}

static struct nv50_software_cclass
nv50_software_cclass = {
	.base.handle = NV_ENGCTX(SW, 0x50),
	.base.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv50_software_context_ctor,
		.dtor = _nouveau_software_context_dtor,
		.init = _nouveau_software_context_init,
		.fini = _nouveau_software_context_fini,
	},
	.vblank = nv50_software_vblsem_release,
};

/*******************************************************************************
 * software engine/subdev functions
 ******************************************************************************/

int
nv50_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
		   struct nouveau_oclass *oclass, void *data, u32 size,
		   struct nouveau_object **pobject)
{
	struct nv50_software_oclass *pclass = (void *)oclass;
	struct nv50_software_priv *priv;
	int ret;

	ret = nouveau_software_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_engine(priv)->cclass = pclass->cclass;
	nv_engine(priv)->sclass = pclass->sclass;
	nv_subdev(priv)->intr = nv04_software_intr;
	return 0;
}

struct nouveau_oclass *
nv50_software_oclass = &(struct nv50_software_oclass) {
	.base.handle = NV_ENGINE(SW, 0x50),
	.base.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv50_software_ctor,
		.dtor = _nouveau_software_dtor,
		.init = _nouveau_software_init,
		.fini = _nouveau_software_fini,
	},
	.cclass = &nv50_software_cclass.base,
	.sclass =  nv50_software_sclass,
}.base;
Commit	Line	Data
ebb945a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include <core/os.h>
	26	#include <core/class.h>
	27	#include <core/engctx.h>
	28	#include <core/namedb.h>
	29	#include <core/handle.h>
	30	#include <core/gpuobj.h>
1d7c71a3 BS	31	#include <core/event.h>
	32
	33	#include <subdev/bar.h>
ebb945a9	34
ebb945a9 BS	35	#include <engine/disp.h>
ebb945a9 BS	36
3bfcec35	37	#include "nv50.h"
ebb945a9 BS	38
	39	/*******************************************************************************
	40	* software object classes
	41	******************************************************************************/
	42
	43	static int
	44	nv50_software_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd,
	45	void *args, u32 size)
	46	{
	47	struct nv50_software_chan chan = (void )nv_engctx(object->parent);
	48	struct nouveau_fifo_chan fifo = (void )nv_object(chan)->parent;
	49	struct nouveau_handle *handle;
	50	int ret = -EINVAL;
	51
	52	handle = nouveau_namedb_get(nv_namedb(fifo), (u32 )args);
	53	if (!handle)
	54	return -ENOENT;
	55
	56	if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) {
	57	struct nouveau_gpuobj *gpuobj = nv_gpuobj(handle->object);
ef8d4781	58	chan->vblank.ctxdma = gpuobj->node->offset >> 4;
ebb945a9 BS	59	ret = 0;
	60	}
	61	nouveau_namedb_put(handle);
	62	return ret;
	63	}
	64
	65	static int
	66	nv50_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
	67	void *args, u32 size)
	68	{
	69	struct nv50_software_chan chan = (void )nv_engctx(object->parent);
ef8d4781	70	chan->vblank.offset = (u32 )args;
ebb945a9 BS	71	return 0;
	72	}
	73
	74	static int
	75	nv50_software_mthd_vblsem_value(struct nouveau_object *object, u32 mthd,
	76	void *args, u32 size)
	77	{
	78	struct nv50_software_chan chan = (void )nv_engctx(object->parent);
ef8d4781	79	chan->vblank.value = (u32 )args;
ebb945a9 BS	80	return 0;
	81	}
	82
	83	static int
	84	nv50_software_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
	85	void *args, u32 size)
	86	{
	87	struct nv50_software_chan chan = (void )nv_engctx(object->parent);
	88	struct nouveau_disp *disp = nouveau_disp(object);
ebb945a9	89	u32 crtc = (u32 )args;
ebb945a9 BS	90	if (crtc > 1)
	91	return -EINVAL;
	92
ef8d4781	93	nouveau_event_get(disp->vblank, crtc, &chan->vblank.event);
ebb945a9 BS	94	return 0;
	95	}
	96
	97	static int
	98	nv50_software_mthd_flip(struct nouveau_object *object, u32 mthd,
	99	void *args, u32 size)
	100	{
	101	struct nv50_software_chan chan = (void )nv_engctx(object->parent);
	102	if (chan->base.flip)
	103	return chan->base.flip(chan->base.flip_data);
	104	return -EINVAL;
	105	}
	106
	107	static struct nouveau_omthds
	108	nv50_software_omthds[] = {
fb445b3c BS	109	{ 0x018c, 0x018c, nv50_software_mthd_dma_vblsem },
	110	{ 0x0400, 0x0400, nv50_software_mthd_vblsem_offset },
	111	{ 0x0404, 0x0404, nv50_software_mthd_vblsem_value },
	112	{ 0x0408, 0x0408, nv50_software_mthd_vblsem_release },
	113	{ 0x0500, 0x0500, nv50_software_mthd_flip },
ebb945a9 BS	114	{}
	115	};
	116
	117	static struct nouveau_oclass
	118	nv50_software_sclass[] = {
	119	{ 0x506e, &nouveau_object_ofuncs, nv50_software_omthds },
	120	{}
	121	};
	122
	123	/*******************************************************************************
	124	* software context
	125	******************************************************************************/
	126
1d7c71a3 BS	127	static int
	128	nv50_software_vblsem_release(struct nouveau_eventh *event, int head)
	129	{
ef8d4781 BS	130	struct nv50_software_chan *chan =
ef8d4781 BS	131	container_of(event, typeof(*chan), vblank.event);
1d7c71a3 BS	132	struct nv50_software_priv priv = (void )nv_object(chan)->engine;
	133	struct nouveau_bar *bar = nouveau_bar(priv);
	134
	135	nv_wr32(priv, 0x001704, chan->vblank.channel);
	136	nv_wr32(priv, 0x001710, 0x80000000 \| chan->vblank.ctxdma);
	137	bar->flush(bar);
	138
	139	if (nv_device(priv)->chipset == 0x50) {
	140	nv_wr32(priv, 0x001570, chan->vblank.offset);
	141	nv_wr32(priv, 0x001574, chan->vblank.value);
	142	} else {
	143	nv_wr32(priv, 0x060010, chan->vblank.offset);
	144	nv_wr32(priv, 0x060014, chan->vblank.value);
	145	}
	146
	147	return NVKM_EVENT_DROP;
	148	}
	149
7589563e	150	int
ebb945a9 BS	151	nv50_software_context_ctor(struct nouveau_object *parent,
	152	struct nouveau_object *engine,
	153	struct nouveau_oclass oclass, void data, u32 size,
	154	struct nouveau_object **pobject)
	155	{
7589563e	156	struct nv50_software_cclass pclass = (void )oclass;
ebb945a9 BS	157	struct nv50_software_chan *chan;
	158	int ret;
	159
	160	ret = nouveau_software_context_create(parent, engine, oclass, &chan);
	161	*pobject = nv_object(chan);
	162	if (ret)
	163	return ret;
	164
ef8d4781	165	chan->vblank.channel = nv_gpuobj(parent->parent)->addr >> 12;
7589563e	166	chan->vblank.event.func = pclass->vblank;
ebb945a9 BS	167	return 0;
	168	}
	169
7589563e	170	static struct nv50_software_cclass
ebb945a9	171	nv50_software_cclass = {
7589563e BS	172	.base.handle = NV_ENGCTX(SW, 0x50),
7589563e BS	173	.base.ofuncs = &(struct nouveau_ofuncs) {
ebb945a9 BS	174	.ctor = nv50_software_context_ctor,
	175	.dtor = _nouveau_software_context_dtor,
	176	.init = _nouveau_software_context_init,
	177	.fini = _nouveau_software_context_fini,
	178	},
7589563e	179	.vblank = nv50_software_vblsem_release,
ebb945a9 BS	180	};
	181
	182	/*******************************************************************************
	183	* software engine/subdev functions
	184	******************************************************************************/
	185
7589563e	186	int
ebb945a9	187	nv50_software_ctor(struct nouveau_object parent, struct nouveau_object engine,
1d7c71a3 BS	188	struct nouveau_oclass oclass, void data, u32 size,
1d7c71a3 BS	189	struct nouveau_object **pobject)
ebb945a9	190	{
7589563e	191	struct nv50_software_oclass pclass = (void )oclass;
ebb945a9 BS	192	struct nv50_software_priv *priv;
	193	int ret;
	194
	195	ret = nouveau_software_create(parent, engine, oclass, &priv);
	196	*pobject = nv_object(priv);
	197	if (ret)
	198	return ret;
	199
7589563e BS	200	nv_engine(priv)->cclass = pclass->cclass;
7589563e BS	201	nv_engine(priv)->sclass = pclass->sclass;
757833cc	202	nv_subdev(priv)->intr = nv04_software_intr;
ebb945a9 BS	203	return 0;
	204	}
	205
c46c3ddf BS	206	struct nouveau_oclass *
	207	nv50_software_oclass = &(struct nv50_software_oclass) {
	208	.base.handle = NV_ENGINE(SW, 0x50),
	209	.base.ofuncs = &(struct nouveau_ofuncs) {
ebb945a9 BS	210	.ctor = nv50_software_ctor,
	211	.dtor = _nouveau_software_dtor,
	212	.init = _nouveau_software_init,
	213	.fini = _nouveau_software_fini,
	214	},
7589563e BS	215	.cclass = &nv50_software_cclass.base,
7589563e BS	216	.sclass = nv50_software_sclass,
c46c3ddf	217	}.base;