projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 9274f4a9 BS |
1 | #ifndef __NOUVEAU_CLASS_H__ |
| 2 | #define __NOUVEAU_CLASS_H__ | |
| 3 | ||
| 9456f7d1 BS |
4 | /* Device class |
| 5 | * | |
| 6 | * 0080: NV_DEVICE | |
| 9274f4a9 | 7 | */ |
| 9456f7d1 | 8 | #define NV_DEVICE_CLASS 0x00000080 |
| 9274f4a9 BS |
9 | |
| 10 | #define NV_DEVICE_DISABLE_IDENTIFY 0x0000000000000001ULL | |
| 11 | #define NV_DEVICE_DISABLE_MMIO 0x0000000000000002ULL | |
| 12 | #define NV_DEVICE_DISABLE_VBIOS 0x0000000000000004ULL | |
| 13 | #define NV_DEVICE_DISABLE_CORE 0x0000000000000008ULL | |
| 14 | #define NV_DEVICE_DISABLE_DISP 0x0000000000010000ULL | |
| 15 | #define NV_DEVICE_DISABLE_FIFO 0x0000000000020000ULL | |
| 16 | #define NV_DEVICE_DISABLE_GRAPH 0x0000000100000000ULL | |
| 17 | #define NV_DEVICE_DISABLE_MPEG 0x0000000200000000ULL | |
| 18 | #define NV_DEVICE_DISABLE_ME 0x0000000400000000ULL | |
| 19 | #define NV_DEVICE_DISABLE_VP 0x0000000800000000ULL | |
| 20 | #define NV_DEVICE_DISABLE_CRYPT 0x0000001000000000ULL | |
| 21 | #define NV_DEVICE_DISABLE_BSP 0x0000002000000000ULL | |
| 22 | #define NV_DEVICE_DISABLE_PPP 0x0000004000000000ULL | |
| 23 | #define NV_DEVICE_DISABLE_COPY0 0x0000008000000000ULL | |
| 24 | #define NV_DEVICE_DISABLE_COPY1 0x0000010000000000ULL | |
| 25 | #define NV_DEVICE_DISABLE_UNK1C1 0x0000020000000000ULL | |
| 26 | ||
| 27 | struct nv_device_class { | |
| 28 | u64 device; /* device identifier, ~0 for client default */ | |
| 29 | u64 disable; /* disable particular subsystems */ | |
| 30 | u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */ | |
| 31 | }; | |
| 32 | ||
| 9456f7d1 BS |
33 | /* DMA object classes |
| 34 | * | |
| 35 | * 0002: NV_DMA_FROM_MEMORY | |
| 9274f4a9 BS |
36 | * 0003: NV_DMA_TO_MEMORY |
| 37 | * 003d: NV_DMA_IN_MEMORY | |
| 38 | */ | |
| 9456f7d1 BS |
39 | #define NV_DMA_FROM_MEMORY_CLASS 0x00000002 |
| 40 | #define NV_DMA_TO_MEMORY_CLASS 0x00000003 | |
| 41 | #define NV_DMA_IN_MEMORY_CLASS 0x0000003d | |
| 9274f4a9 BS |
42 | |
| 43 | #define NV_DMA_TARGET_MASK 0x000000ff | |
| 44 | #define NV_DMA_TARGET_VM 0x00000000 | |
| 45 | #define NV_DMA_TARGET_VRAM 0x00000001 | |
| 46 | #define NV_DMA_TARGET_PCI 0x00000002 | |
| 47 | #define NV_DMA_TARGET_PCI_US 0x00000003 | |
| 48 | #define NV_DMA_TARGET_AGP 0x00000004 | |
| 49 | #define NV_DMA_ACCESS_MASK 0x00000f00 | |
| 50 | #define NV_DMA_ACCESS_VM 0x00000000 | |
| 51 | #define NV_DMA_ACCESS_RD 0x00000100 | |
| 52 | #define NV_DMA_ACCESS_WR 0x00000200 | |
| 53 | #define NV_DMA_ACCESS_RDWR 0x00000300 | |
| 54 | ||
| f756944a BS |
55 | /* NV50:NVC0 */ |
| 56 | #define NV50_DMA_CONF0_ENABLE 0x80000000 | |
| 57 | #define NV50_DMA_CONF0_PRIV 0x00300000 | |
| 58 | #define NV50_DMA_CONF0_PRIV_VM 0x00000000 | |
| 59 | #define NV50_DMA_CONF0_PRIV_US 0x00100000 | |
| 60 | #define NV50_DMA_CONF0_PRIV__S 0x00200000 | |
| 61 | #define NV50_DMA_CONF0_PART 0x00030000 | |
| 62 | #define NV50_DMA_CONF0_PART_VM 0x00000000 | |
| 63 | #define NV50_DMA_CONF0_PART_256 0x00010000 | |
| 64 | #define NV50_DMA_CONF0_PART_1KB 0x00020000 | |
| 65 | #define NV50_DMA_CONF0_COMP 0x00000180 | |
| 66 | #define NV50_DMA_CONF0_COMP_NONE 0x00000000 | |
| 67 | #define NV50_DMA_CONF0_COMP_VM 0x00000180 | |
| 68 | #define NV50_DMA_CONF0_TYPE 0x0000007f | |
| 69 | #define NV50_DMA_CONF0_TYPE_LINEAR 0x00000000 | |
| 70 | #define NV50_DMA_CONF0_TYPE_VM 0x0000007f | |
| 71 | ||
| 80fe155b BS |
72 | /* NVC0:NVD9 */ |
| 73 | #define NVC0_DMA_CONF0_ENABLE 0x80000000 | |
| 74 | #define NVC0_DMA_CONF0_PRIV 0x00300000 | |
| 75 | #define NVC0_DMA_CONF0_PRIV_VM 0x00000000 | |
| 76 | #define NVC0_DMA_CONF0_PRIV_US 0x00100000 | |
| 77 | #define NVC0_DMA_CONF0_PRIV__S 0x00200000 | |
| 78 | #define NVC0_DMA_CONF0_UNKN /* PART? */ 0x00030000 | |
| 79 | #define NVC0_DMA_CONF0_TYPE 0x000000ff | |
| 80 | #define NVC0_DMA_CONF0_TYPE_LINEAR 0x00000000 | |
| 81 | #define NVC0_DMA_CONF0_TYPE_VM 0x000000ff | |
| 47a1e0fe BS |
82 | |
| 83 | /* NVD9- */ | |
| 84 | #define NVD0_DMA_CONF0_ENABLE 0x80000000 | |
| 85 | #define NVD0_DMA_CONF0_PAGE 0x00000400 | |
| 86 | #define NVD0_DMA_CONF0_PAGE_LP 0x00000000 | |
| 87 | #define NVD0_DMA_CONF0_PAGE_SP 0x00000400 | |
| 88 | #define NVD0_DMA_CONF0_TYPE 0x000000ff | |
| 89 | #define NVD0_DMA_CONF0_TYPE_LINEAR 0x00000000 | |
| 90 | #define NVD0_DMA_CONF0_TYPE_VM 0x000000ff | |
| 80fe155b | 91 | |
| 9274f4a9 BS |
92 | struct nv_dma_class { |
| 93 | u32 flags; | |
| 94 | u32 pad0; | |
| 95 | u64 start; | |
| 96 | u64 limit; | |
| f756944a | 97 | u32 conf0; |
| 9274f4a9 BS |
98 | }; |
| 99 | ||
| 9456f7d1 BS |
100 | /* DMA FIFO channel classes |
| 101 | * | |
| 102 | * 006b: NV03_CHANNEL_DMA | |
| 9274f4a9 | 103 | * 006e: NV10_CHANNEL_DMA |
| 503b0f1c | 104 | * 176e: NV17_CHANNEL_DMA |
| 9274f4a9 | 105 | * 406e: NV40_CHANNEL_DMA |
| 368be5f1 | 106 | * 506e: NV50_CHANNEL_DMA |
| ab285892 | 107 | * 826e: NV84_CHANNEL_DMA |
| 9274f4a9 | 108 | */ |
| 9456f7d1 BS |
109 | #define NV03_CHANNEL_DMA_CLASS 0x0000006b |
| 110 | #define NV10_CHANNEL_DMA_CLASS 0x0000006e | |
| 111 | #define NV17_CHANNEL_DMA_CLASS 0x0000176e | |
| 112 | #define NV40_CHANNEL_DMA_CLASS 0x0000406e | |
| 113 | #define NV50_CHANNEL_DMA_CLASS 0x0000506e | |
| 114 | #define NV84_CHANNEL_DMA_CLASS 0x0000826e | |
| 9274f4a9 | 115 | |
| a7c6e75e | 116 | struct nv03_channel_dma_class { |
| 9274f4a9 BS |
117 | u32 pushbuf; |
| 118 | u32 pad0; | |
| 119 | u64 offset; | |
| 120 | }; | |
| 121 | ||
| 9456f7d1 BS |
122 | /* Indirect FIFO channel classes |
| 123 | * | |
| 124 | * 506f: NV50_CHANNEL_IND | |
| 9274f4a9 BS |
125 | * 826f: NV84_CHANNEL_IND |
| 126 | * 906f: NVC0_CHANNEL_IND | |
| 9456f7d1 | 127 | * a06f: NVE0_CHANNEL_IND |
| 9274f4a9 BS |
128 | */ |
| 129 | ||
| 9456f7d1 BS |
130 | #define NV50_CHANNEL_IND_CLASS 0x0000506f |
| 131 | #define NV84_CHANNEL_IND_CLASS 0x0000826f | |
| 132 | #define NVC0_CHANNEL_IND_CLASS 0x0000906f | |
| 133 | #define NVE0_CHANNEL_IND_CLASS 0x0000a06f | |
| 134 | ||
| dbff2dee | 135 | struct nv50_channel_ind_class { |
| 9274f4a9 BS |
136 | u32 pushbuf; |
| 137 | u32 ilength; | |
| 138 | u64 ioffset; | |
| 139 | }; | |
| 140 | ||
| 9456f7d1 BS |
141 | #define NVE0_CHANNEL_IND_ENGINE_GR 0x00000001 |
| 142 | #define NVE0_CHANNEL_IND_ENGINE_VP 0x00000002 | |
| 143 | #define NVE0_CHANNEL_IND_ENGINE_PPP 0x00000004 | |
| 144 | #define NVE0_CHANNEL_IND_ENGINE_BSP 0x00000008 | |
| 145 | #define NVE0_CHANNEL_IND_ENGINE_CE0 0x00000010 | |
| 146 | #define NVE0_CHANNEL_IND_ENGINE_CE1 0x00000020 | |
| 147 | #define NVE0_CHANNEL_IND_ENGINE_ENC 0x00000040 | |
| dbff2dee BS |
148 | |
| 149 | struct nve0_channel_ind_class { | |
| 150 | u32 pushbuf; | |
| 151 | u32 ilength; | |
| 152 | u64 ioffset; | |
| 153 | u32 engine; | |
| 154 | }; | |
| 155 | ||
| 370c00f9 BS |
156 | /* 5070: NV50_DISP |
| 157 | * 8270: NV84_DISP | |
| 158 | * 8370: NVA0_DISP | |
| 159 | * 8870: NV94_DISP | |
| 160 | * 8570: NVA3_DISP | |
| 46654061 BS |
161 | * 9070: NVD0_DISP |
| 162 | * 9170: NVE0_DISP | |
| 370c00f9 BS |
163 | */ |
| 164 | ||
| 165 | #define NV50_DISP_CLASS 0x00005070 | |
| 166 | #define NV84_DISP_CLASS 0x00008270 | |
| 167 | #define NVA0_DISP_CLASS 0x00008370 | |
| 168 | #define NV94_DISP_CLASS 0x00008870 | |
| 169 | #define NVA3_DISP_CLASS 0x00008570 | |
| 46654061 BS |
170 | #define NVD0_DISP_CLASS 0x00009070 |
| 171 | #define NVE0_DISP_CLASS 0x00009170 | |
| 370c00f9 BS |
172 | |
| 173 | struct nv50_display_class { | |
| 174 | }; | |
| 175 | ||
| 176 | /* 507a: NV50_DISP_CURS | |
| 177 | * 827a: NV84_DISP_CURS | |
| 178 | * 837a: NVA0_DISP_CURS | |
| 179 | * 887a: NV94_DISP_CURS | |
| 180 | * 857a: NVA3_DISP_CURS | |
| 46654061 BS |
181 | * 907a: NVD0_DISP_CURS |
| 182 | * 917a: NVE0_DISP_CURS | |
| 370c00f9 BS |
183 | */ |
| 184 | ||
| 185 | #define NV50_DISP_CURS_CLASS 0x0000507a | |
| 186 | #define NV84_DISP_CURS_CLASS 0x0000827a | |
| 187 | #define NVA0_DISP_CURS_CLASS 0x0000837a | |
| 188 | #define NV94_DISP_CURS_CLASS 0x0000887a | |
| 189 | #define NVA3_DISP_CURS_CLASS 0x0000857a | |
| 46654061 BS |
190 | #define NVD0_DISP_CURS_CLASS 0x0000907a |
| 191 | #define NVE0_DISP_CURS_CLASS 0x0000917a | |
| 370c00f9 BS |
192 | |
| 193 | struct nv50_display_curs_class { | |
| 194 | u32 head; | |
| 195 | }; | |
| 196 | ||
| 197 | /* 507b: NV50_DISP_OIMM | |
| 198 | * 827b: NV84_DISP_OIMM | |
| 199 | * 837b: NVA0_DISP_OIMM | |
| 200 | * 887b: NV94_DISP_OIMM | |
| 201 | * 857b: NVA3_DISP_OIMM | |
| 46654061 BS |
202 | * 907b: NVD0_DISP_OIMM |
| 203 | * 917b: NVE0_DISP_OIMM | |
| 370c00f9 BS |
204 | */ |
| 205 | ||
| 206 | #define NV50_DISP_OIMM_CLASS 0x0000507b | |
| 207 | #define NV84_DISP_OIMM_CLASS 0x0000827b | |
| 208 | #define NVA0_DISP_OIMM_CLASS 0x0000837b | |
| 209 | #define NV94_DISP_OIMM_CLASS 0x0000887b | |
| 210 | #define NVA3_DISP_OIMM_CLASS 0x0000857b | |
| 46654061 BS |
211 | #define NVD0_DISP_OIMM_CLASS 0x0000907b |
| 212 | #define NVE0_DISP_OIMM_CLASS 0x0000917b | |
| 370c00f9 BS |
213 | |
| 214 | struct nv50_display_oimm_class { | |
| 215 | u32 head; | |
| 216 | }; | |
| 217 | ||
| 218 | /* 507c: NV50_DISP_SYNC | |
| 219 | * 827c: NV84_DISP_SYNC | |
| 220 | * 837c: NVA0_DISP_SYNC | |
| 221 | * 887c: NV94_DISP_SYNC | |
| 222 | * 857c: NVA3_DISP_SYNC | |
| 46654061 BS |
223 | * 907c: NVD0_DISP_SYNC |
| 224 | * 917c: NVE0_DISP_SYNC | |
| 370c00f9 BS |
225 | */ |
| 226 | ||
| 227 | #define NV50_DISP_SYNC_CLASS 0x0000507c | |
| 228 | #define NV84_DISP_SYNC_CLASS 0x0000827c | |
| 229 | #define NVA0_DISP_SYNC_CLASS 0x0000837c | |
| 230 | #define NV94_DISP_SYNC_CLASS 0x0000887c | |
| 231 | #define NVA3_DISP_SYNC_CLASS 0x0000857c | |
| 46654061 BS |
232 | #define NVD0_DISP_SYNC_CLASS 0x0000907c |
| 233 | #define NVE0_DISP_SYNC_CLASS 0x0000917c | |
| 370c00f9 BS |
234 | |
| 235 | struct nv50_display_sync_class { | |
| 236 | u32 pushbuf; | |
| 237 | u32 head; | |
| 238 | }; | |
| 239 | ||
| 240 | /* 507d: NV50_DISP_MAST | |
| 241 | * 827d: NV84_DISP_MAST | |
| 242 | * 837d: NVA0_DISP_MAST | |
| 243 | * 887d: NV94_DISP_MAST | |
| 244 | * 857d: NVA3_DISP_MAST | |
| 46654061 BS |
245 | * 907d: NVD0_DISP_MAST |
| 246 | * 917d: NVE0_DISP_MAST | |
| 370c00f9 BS |
247 | */ |
| 248 | ||
| 249 | #define NV50_DISP_MAST_CLASS 0x0000507d | |
| 250 | #define NV84_DISP_MAST_CLASS 0x0000827d | |
| 251 | #define NVA0_DISP_MAST_CLASS 0x0000837d | |
| 252 | #define NV94_DISP_MAST_CLASS 0x0000887d | |
| 253 | #define NVA3_DISP_MAST_CLASS 0x0000857d | |
| 46654061 BS |
254 | #define NVD0_DISP_MAST_CLASS 0x0000907d |
| 255 | #define NVE0_DISP_MAST_CLASS 0x0000917d | |
| 370c00f9 BS |
256 | |
| 257 | struct nv50_display_mast_class { | |
| 258 | u32 pushbuf; | |
| 259 | }; | |
| 260 | ||
| 261 | /* 507e: NV50_DISP_OVLY | |
| 262 | * 827e: NV84_DISP_OVLY | |
| 263 | * 837e: NVA0_DISP_OVLY | |
| 264 | * 887e: NV94_DISP_OVLY | |
| 265 | * 857e: NVA3_DISP_OVLY | |
| 46654061 BS |
266 | * 907e: NVD0_DISP_OVLY |
| 267 | * 917e: NVE0_DISP_OVLY | |
| 370c00f9 BS |
268 | */ |
| 269 | ||
| 270 | #define NV50_DISP_OVLY_CLASS 0x0000507e | |
| 271 | #define NV84_DISP_OVLY_CLASS 0x0000827e | |
| 272 | #define NVA0_DISP_OVLY_CLASS 0x0000837e | |
| 273 | #define NV94_DISP_OVLY_CLASS 0x0000887e | |
| 274 | #define NVA3_DISP_OVLY_CLASS 0x0000857e | |
| 46654061 BS |
275 | #define NVD0_DISP_OVLY_CLASS 0x0000907e |
| 276 | #define NVE0_DISP_OVLY_CLASS 0x0000917e | |
| 370c00f9 BS |
277 | |
| 278 | struct nv50_display_ovly_class { | |
| 279 | u32 pushbuf; | |
| 280 | u32 head; | |
| 281 | }; | |
| 282 | ||
| 9274f4a9 | 283 | #endif |