Commit | Line | Data |
---|---|---|
9274f4a9 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
25 | #include <subdev/device.h> | |
70c0f263 | 26 | #include <subdev/bios.h> |
e0996aea | 27 | #include <subdev/gpio.h> |
4196faa8 | 28 | #include <subdev/i2c.h> |
8aceb7de | 29 | #include <subdev/clock.h> |
cb75d97e | 30 | #include <subdev/devinit.h> |
7d9115de | 31 | #include <subdev/mc.h> |
5a5c7432 | 32 | #include <subdev/timer.h> |
861d2107 | 33 | #include <subdev/fb.h> |
3863c9bc BS |
34 | #include <subdev/instmem.h> |
35 | #include <subdev/vm.h> | |
9274f4a9 | 36 | |
ebb945a9 BS |
37 | #include <engine/dmaobj.h> |
38 | #include <engine/fifo.h> | |
39 | #include <engine/software.h> | |
40 | #include <engine/graph.h> | |
41 | #include <engine/disp.h> | |
42 | ||
9274f4a9 BS |
43 | int |
44 | nv10_identify(struct nouveau_device *device) | |
45 | { | |
46 | switch (device->chipset) { | |
47 | case 0x10: | |
70c0f263 | 48 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 49 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 50 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 51 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
cb75d97e | 52 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; |
7d9115de | 53 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
5a5c7432 | 54 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
861d2107 | 55 | device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass; |
3863c9bc BS |
56 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; |
57 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | |
ebb945a9 BS |
58 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
59 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; | |
60 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
61 | break; |
62 | case 0x15: | |
70c0f263 | 63 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 64 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 65 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 66 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
cb75d97e | 67 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; |
7d9115de | 68 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
5a5c7432 | 69 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
861d2107 | 70 | device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass; |
3863c9bc BS |
71 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; |
72 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | |
ebb945a9 BS |
73 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
74 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass; | |
75 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
76 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; | |
77 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
78 | break; |
79 | case 0x16: | |
70c0f263 | 80 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 81 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 82 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 83 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
cb75d97e | 84 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; |
7d9115de | 85 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
5a5c7432 | 86 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
861d2107 | 87 | device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass; |
3863c9bc BS |
88 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; |
89 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | |
ebb945a9 BS |
90 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
91 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass; | |
92 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
93 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; | |
94 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
95 | break; |
96 | case 0x1a: | |
70c0f263 | 97 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 98 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 99 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 100 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
cb75d97e | 101 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 102 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
5a5c7432 | 103 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
861d2107 | 104 | device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass; |
3863c9bc BS |
105 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; |
106 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | |
ebb945a9 BS |
107 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
108 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass; | |
109 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
110 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; | |
111 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
112 | break; |
113 | case 0x11: | |
70c0f263 | 114 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 115 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 116 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 117 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
cb75d97e | 118 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; |
7d9115de | 119 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
5a5c7432 | 120 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
861d2107 | 121 | device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass; |
3863c9bc BS |
122 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; |
123 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | |
ebb945a9 BS |
124 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
125 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass; | |
126 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
127 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; | |
128 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
129 | break; |
130 | case 0x17: | |
70c0f263 | 131 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 132 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 133 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 134 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
cb75d97e | 135 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; |
7d9115de | 136 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
5a5c7432 | 137 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
861d2107 | 138 | device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass; |
3863c9bc BS |
139 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; |
140 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | |
ebb945a9 BS |
141 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
142 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; | |
143 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
144 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; | |
145 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
146 | break; |
147 | case 0x1f: | |
70c0f263 | 148 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 149 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 150 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 151 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
cb75d97e | 152 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 153 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
5a5c7432 | 154 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
861d2107 | 155 | device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass; |
3863c9bc BS |
156 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; |
157 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | |
ebb945a9 BS |
158 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
159 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; | |
160 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
161 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; | |
162 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
163 | break; |
164 | case 0x18: | |
70c0f263 | 165 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 166 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 167 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 168 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
cb75d97e | 169 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; |
7d9115de | 170 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
5a5c7432 | 171 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
861d2107 | 172 | device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass; |
3863c9bc BS |
173 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; |
174 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | |
ebb945a9 BS |
175 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
176 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; | |
177 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
178 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; | |
179 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
180 | break; |
181 | default: | |
182 | nv_fatal(device, "unknown Celsius chipset\n"); | |
183 | return -EINVAL; | |
184 | } | |
185 | ||
186 | return 0; | |
187 | } |