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1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
25 | #include <subdev/device.h> | |
70c0f263 | 26 | #include <subdev/bios.h> |
e0996aea | 27 | #include <subdev/gpio.h> |
4196faa8 | 28 | #include <subdev/i2c.h> |
8aceb7de | 29 | #include <subdev/clock.h> |
cb75d97e | 30 | #include <subdev/devinit.h> |
7d9115de | 31 | #include <subdev/mc.h> |
5a5c7432 | 32 | #include <subdev/timer.h> |
861d2107 | 33 | #include <subdev/fb.h> |
3863c9bc BS |
34 | #include <subdev/instmem.h> |
35 | #include <subdev/vm.h> | |
9274f4a9 | 36 | |
ebb945a9 BS |
37 | #include <engine/dmaobj.h> |
38 | #include <engine/fifo.h> | |
39 | #include <engine/software.h> | |
40 | #include <engine/graph.h> | |
41 | #include <engine/disp.h> | |
42 | ||
9274f4a9 BS |
43 | int |
44 | nv20_identify(struct nouveau_device *device) | |
45 | { | |
46 | switch (device->chipset) { | |
47 | case 0x20: | |
2094dd82 | 48 | device->cname = "NV20"; |
70c0f263 | 49 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 50 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 51 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 52 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
cb75d97e | 53 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; |
7d9115de | 54 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
5a5c7432 | 55 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
861d2107 | 56 | device->oclass[NVDEV_SUBDEV_FB ] = &nv20_fb_oclass; |
3863c9bc BS |
57 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; |
58 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | |
ebb945a9 BS |
59 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
60 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; | |
61 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
62 | device->oclass[NVDEV_ENGINE_GR ] = &nv20_graph_oclass; | |
63 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
64 | break; |
65 | case 0x25: | |
2094dd82 | 66 | device->cname = "NV25"; |
70c0f263 | 67 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 68 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 69 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 70 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
cb75d97e | 71 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; |
7d9115de | 72 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
5a5c7432 | 73 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
861d2107 | 74 | device->oclass[NVDEV_SUBDEV_FB ] = &nv20_fb_oclass; |
3863c9bc BS |
75 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; |
76 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | |
ebb945a9 BS |
77 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
78 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; | |
79 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
80 | device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass; | |
81 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
82 | break; |
83 | case 0x28: | |
2094dd82 | 84 | device->cname = "NV28"; |
70c0f263 | 85 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 86 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 87 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 88 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
cb75d97e | 89 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; |
7d9115de | 90 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
5a5c7432 | 91 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
861d2107 | 92 | device->oclass[NVDEV_SUBDEV_FB ] = &nv20_fb_oclass; |
3863c9bc BS |
93 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; |
94 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | |
ebb945a9 BS |
95 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
96 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; | |
97 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
98 | device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass; | |
99 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
100 | break; |
101 | case 0x2a: | |
2094dd82 | 102 | device->cname = "NV2A"; |
70c0f263 | 103 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 104 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 105 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 106 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
cb75d97e | 107 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; |
7d9115de | 108 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
5a5c7432 | 109 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
861d2107 | 110 | device->oclass[NVDEV_SUBDEV_FB ] = &nv20_fb_oclass; |
3863c9bc BS |
111 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; |
112 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | |
ebb945a9 BS |
113 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
114 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass; | |
115 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
116 | device->oclass[NVDEV_ENGINE_GR ] = &nv2a_graph_oclass; | |
117 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
118 | break; |
119 | default: | |
120 | nv_fatal(device, "unknown Kelvin chipset\n"); | |
121 | return -EINVAL; | |
122 | } | |
123 | ||
124 | return 0; | |
125 | } |