[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / subdev / device / nv30.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <subdev/device.h>
#include <subdev/bios.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/clock.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
#include <subdev/vm.h>

#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/software.h>
#include <engine/graph.h>
#include <engine/mpeg.h>
#include <engine/disp.h>

int
nv30_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
	case 0x30:
		device->cname = "NV30";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv30_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv30_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x35:
		device->cname = "NV35";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv30_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv35_graph_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x31:
		device->cname = "NV31";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv30_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv30_graph_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x36:
		device->cname = "NV36";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv30_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv35_graph_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	case 0x34:
		device->cname = "NV34";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv04_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nv30_fb_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nv04_vmmgr_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nv17_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nv10_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nv34_graph_oclass;
		device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv04_disp_oclass;
		break;
	default:
		nv_fatal(device, "unknown Rankine chipset\n");
		return -EINVAL;
	}

	return 0;
}
Commit	Line	Data
9274f4a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include <subdev/device.h>
70c0f263	26	#include <subdev/bios.h>
e0996aea	27	#include <subdev/gpio.h>
4196faa8	28	#include <subdev/i2c.h>
8aceb7de	29	#include <subdev/clock.h>
cb75d97e	30	#include <subdev/devinit.h>
7d9115de	31	#include <subdev/mc.h>
5a5c7432	32	#include <subdev/timer.h>
861d2107	33	#include <subdev/fb.h>
3863c9bc BS	34	#include <subdev/instmem.h>
3863c9bc BS	35	#include <subdev/vm.h>
9274f4a9	36
ebb945a9 BS	37	#include <engine/dmaobj.h>
	38	#include <engine/fifo.h>
	39	#include <engine/software.h>
	40	#include <engine/graph.h>
	41	#include <engine/mpeg.h>
	42	#include <engine/disp.h>
	43
9274f4a9 BS	44	int
	45	nv30_identify(struct nouveau_device *device)
	46	{
	47	switch (device->chipset) {
	48	case 0x30:
2094dd82	49	device->cname = "NV30";
70c0f263	50	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	51	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	52	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	53	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
cb75d97e	54	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
7d9115de	55	device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
5a5c7432	56	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107	57	device->oclass[NVDEV_SUBDEV_FB ] = &nv30_fb_oclass;
3863c9bc BS	58	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
3863c9bc BS	59	device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
ebb945a9 BS	60	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
	61	device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
	62	device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
	63	device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass;
	64	device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
9274f4a9 BS	65	break;
9274f4a9 BS	66	case 0x35:
2094dd82	67	device->cname = "NV35";
70c0f263	68	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	69	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	70	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	71	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
cb75d97e	72	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
7d9115de	73	device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
5a5c7432	74	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107	75	device->oclass[NVDEV_SUBDEV_FB ] = &nv30_fb_oclass;
3863c9bc BS	76	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
3863c9bc BS	77	device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
ebb945a9 BS	78	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
	79	device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
	80	device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
	81	device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass;
	82	device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
9274f4a9 BS	83	break;
9274f4a9 BS	84	case 0x31:
2094dd82	85	device->cname = "NV31";
70c0f263	86	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	87	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	88	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	89	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
cb75d97e	90	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
7d9115de	91	device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
5a5c7432	92	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107	93	device->oclass[NVDEV_SUBDEV_FB ] = &nv30_fb_oclass;
3863c9bc BS	94	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
3863c9bc BS	95	device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
ebb945a9 BS	96	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
	97	device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
	98	device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
	99	device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass;
	100	device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
	101	device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
9274f4a9 BS	102	break;
9274f4a9 BS	103	case 0x36:
2094dd82	104	device->cname = "NV36";
70c0f263	105	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	106	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	107	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	108	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
cb75d97e	109	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
7d9115de	110	device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
5a5c7432	111	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107	112	device->oclass[NVDEV_SUBDEV_FB ] = &nv30_fb_oclass;
3863c9bc BS	113	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
3863c9bc BS	114	device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
ebb945a9 BS	115	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
	116	device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
	117	device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
	118	device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass;
	119	device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
	120	device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
9274f4a9 BS	121	break;
9274f4a9 BS	122	case 0x34:
2094dd82	123	device->cname = "NV34";
70c0f263	124	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	125	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	126	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	127	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
cb75d97e	128	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
7d9115de	129	device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
5a5c7432	130	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107	131	device->oclass[NVDEV_SUBDEV_FB ] = &nv30_fb_oclass;
3863c9bc BS	132	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
3863c9bc BS	133	device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
ebb945a9 BS	134	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
	135	device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
	136	device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
	137	device->oclass[NVDEV_ENGINE_GR ] = &nv34_graph_oclass;
	138	device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
	139	device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
9274f4a9 BS	140	break;
	141	default:
	142	nv_fatal(device, "unknown Rankine chipset\n");
	143	return -EINVAL;
	144	}
	145
	146	return 0;
	147	}