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9274f4a9 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
25 | #include <subdev/device.h> | |
70c0f263 | 26 | #include <subdev/bios.h> |
a10220bb MP |
27 | #include <subdev/bus.h> |
28 | #include <subdev/vm.h> | |
e0996aea | 29 | #include <subdev/gpio.h> |
4196faa8 | 30 | #include <subdev/i2c.h> |
8aceb7de | 31 | #include <subdev/clock.h> |
aa1b9b48 | 32 | #include <subdev/therm.h> |
cb75d97e | 33 | #include <subdev/devinit.h> |
7d9115de | 34 | #include <subdev/mc.h> |
5a5c7432 | 35 | #include <subdev/timer.h> |
861d2107 | 36 | #include <subdev/fb.h> |
3863c9bc BS |
37 | #include <subdev/instmem.h> |
38 | #include <subdev/vm.h> | |
9274f4a9 | 39 | |
ebb945a9 BS |
40 | #include <engine/dmaobj.h> |
41 | #include <engine/fifo.h> | |
42 | #include <engine/software.h> | |
43 | #include <engine/graph.h> | |
44 | #include <engine/mpeg.h> | |
45 | #include <engine/disp.h> | |
46 | ||
9274f4a9 BS |
47 | int |
48 | nv40_identify(struct nouveau_device *device) | |
49 | { | |
50 | switch (device->chipset) { | |
51 | case 0x40: | |
2094dd82 | 52 | device->cname = "NV40"; |
70c0f263 | 53 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 54 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 55 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 56 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
aa1b9b48 | 57 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
cb75d97e | 58 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 59 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
a10220bb | 60 | device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; |
5a5c7432 | 61 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
861d2107 | 62 | device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass; |
3863c9bc BS |
63 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; |
64 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | |
ebb945a9 BS |
65 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
66 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; | |
67 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
68 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; | |
69 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; | |
70 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
71 | break; |
72 | case 0x41: | |
2094dd82 | 73 | device->cname = "NV41"; |
70c0f263 | 74 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 75 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 76 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 77 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
aa1b9b48 | 78 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
cb75d97e | 79 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 80 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
a10220bb | 81 | device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; |
5a5c7432 | 82 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
4ae20745 | 83 | device->oclass[NVDEV_SUBDEV_FB ] = &nv41_fb_oclass; |
3863c9bc | 84 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; |
002d0c73 | 85 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
ebb945a9 BS |
86 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
87 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; | |
88 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
89 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; | |
90 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; | |
91 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
92 | break; |
93 | case 0x42: | |
2094dd82 | 94 | device->cname = "NV42"; |
70c0f263 | 95 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 96 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 97 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 98 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
aa1b9b48 | 99 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
cb75d97e | 100 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 101 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
a10220bb | 102 | device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; |
5a5c7432 | 103 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
4ae20745 | 104 | device->oclass[NVDEV_SUBDEV_FB ] = &nv41_fb_oclass; |
3863c9bc | 105 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; |
002d0c73 | 106 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
ebb945a9 BS |
107 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
108 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; | |
109 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
110 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; | |
111 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; | |
112 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
113 | break; |
114 | case 0x43: | |
2094dd82 | 115 | device->cname = "NV43"; |
70c0f263 | 116 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 117 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 118 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 119 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
aa1b9b48 | 120 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
cb75d97e | 121 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 122 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
a10220bb | 123 | device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; |
5a5c7432 | 124 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
4ae20745 | 125 | device->oclass[NVDEV_SUBDEV_FB ] = &nv41_fb_oclass; |
3863c9bc | 126 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; |
002d0c73 | 127 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
ebb945a9 BS |
128 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
129 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; | |
130 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
131 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; | |
132 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; | |
133 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
134 | break; |
135 | case 0x45: | |
2094dd82 | 136 | device->cname = "NV45"; |
70c0f263 | 137 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 138 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 139 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 140 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
aa1b9b48 | 141 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
cb75d97e | 142 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 143 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
a10220bb | 144 | device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; |
5a5c7432 | 145 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
861d2107 | 146 | device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass; |
3863c9bc BS |
147 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; |
148 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | |
ebb945a9 BS |
149 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
150 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; | |
151 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
152 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; | |
153 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; | |
154 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
155 | break; |
156 | case 0x47: | |
2094dd82 | 157 | device->cname = "G70"; |
70c0f263 | 158 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 159 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 160 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 161 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
aa1b9b48 | 162 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
cb75d97e | 163 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 164 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
a10220bb | 165 | device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; |
5a5c7432 | 166 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
4ae20745 | 167 | device->oclass[NVDEV_SUBDEV_FB ] = &nv47_fb_oclass; |
3863c9bc | 168 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; |
002d0c73 | 169 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
ebb945a9 BS |
170 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
171 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; | |
172 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
173 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; | |
174 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; | |
175 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
176 | break; |
177 | case 0x49: | |
2094dd82 | 178 | device->cname = "G71"; |
70c0f263 | 179 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 180 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 181 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 182 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
aa1b9b48 | 183 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
cb75d97e | 184 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 185 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
a10220bb | 186 | device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; |
5a5c7432 | 187 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
4ae20745 | 188 | device->oclass[NVDEV_SUBDEV_FB ] = &nv49_fb_oclass; |
3863c9bc | 189 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; |
002d0c73 | 190 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
ebb945a9 BS |
191 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
192 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; | |
193 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
194 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; | |
195 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; | |
196 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
197 | break; |
198 | case 0x4b: | |
2094dd82 | 199 | device->cname = "G73"; |
70c0f263 | 200 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 201 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 202 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 203 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
aa1b9b48 | 204 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
cb75d97e | 205 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 206 | device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass; |
a10220bb | 207 | device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; |
5a5c7432 | 208 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
4ae20745 | 209 | device->oclass[NVDEV_SUBDEV_FB ] = &nv49_fb_oclass; |
3863c9bc | 210 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; |
002d0c73 | 211 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
ebb945a9 BS |
212 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
213 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; | |
214 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
215 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; | |
216 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; | |
217 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
218 | break; |
219 | case 0x44: | |
2094dd82 | 220 | device->cname = "NV44"; |
70c0f263 | 221 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 222 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 223 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 224 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
aa1b9b48 | 225 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
cb75d97e | 226 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 227 | device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass; |
a10220bb | 228 | device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; |
5a5c7432 | 229 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
4ae20745 | 230 | device->oclass[NVDEV_SUBDEV_FB ] = &nv44_fb_oclass; |
3863c9bc | 231 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; |
e5f186c4 | 232 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
ebb945a9 BS |
233 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
234 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; | |
235 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
236 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; | |
237 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; | |
238 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
239 | break; |
240 | case 0x46: | |
2094dd82 | 241 | device->cname = "G72"; |
70c0f263 | 242 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 243 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 244 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 245 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
aa1b9b48 | 246 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
cb75d97e | 247 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 248 | device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass; |
a10220bb | 249 | device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; |
5a5c7432 | 250 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
4ae20745 | 251 | device->oclass[NVDEV_SUBDEV_FB ] = &nv46_fb_oclass; |
3863c9bc | 252 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; |
e5f186c4 | 253 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
ebb945a9 BS |
254 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
255 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; | |
256 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
257 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; | |
258 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; | |
259 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
260 | break; |
261 | case 0x4a: | |
2094dd82 | 262 | device->cname = "NV44A"; |
70c0f263 | 263 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 264 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 265 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 266 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
aa1b9b48 | 267 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
cb75d97e | 268 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 269 | device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass; |
a10220bb | 270 | device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; |
5a5c7432 | 271 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
4ae20745 | 272 | device->oclass[NVDEV_SUBDEV_FB ] = &nv44_fb_oclass; |
3863c9bc | 273 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; |
e5f186c4 | 274 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
ebb945a9 BS |
275 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
276 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; | |
277 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
278 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; | |
279 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; | |
280 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
281 | break; |
282 | case 0x4c: | |
2094dd82 | 283 | device->cname = "C61"; |
70c0f263 | 284 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 285 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 286 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 287 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
aa1b9b48 | 288 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
cb75d97e | 289 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 290 | device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass; |
a10220bb | 291 | device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; |
5a5c7432 | 292 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
4ae20745 | 293 | device->oclass[NVDEV_SUBDEV_FB ] = &nv46_fb_oclass; |
3863c9bc | 294 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; |
e5f186c4 | 295 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
ebb945a9 BS |
296 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
297 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; | |
298 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
299 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; | |
300 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; | |
301 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
302 | break; |
303 | case 0x4e: | |
2094dd82 | 304 | device->cname = "C51"; |
70c0f263 | 305 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 306 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 307 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 308 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
aa1b9b48 | 309 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
cb75d97e | 310 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 311 | device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass; |
a10220bb | 312 | device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; |
5a5c7432 | 313 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
4ae20745 | 314 | device->oclass[NVDEV_SUBDEV_FB ] = &nv4e_fb_oclass; |
3863c9bc | 315 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; |
e5f186c4 | 316 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
ebb945a9 BS |
317 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
318 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; | |
319 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
320 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; | |
321 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; | |
322 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
323 | break; |
324 | case 0x63: | |
2094dd82 | 325 | device->cname = "C73"; |
70c0f263 | 326 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 327 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 328 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 329 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
aa1b9b48 | 330 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
cb75d97e | 331 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 332 | device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass; |
a10220bb | 333 | device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; |
5a5c7432 | 334 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
4ae20745 | 335 | device->oclass[NVDEV_SUBDEV_FB ] = &nv46_fb_oclass; |
3863c9bc | 336 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; |
e5f186c4 | 337 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
ebb945a9 BS |
338 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
339 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; | |
340 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
341 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; | |
342 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; | |
343 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
344 | break; |
345 | case 0x67: | |
2094dd82 | 346 | device->cname = "C67"; |
70c0f263 | 347 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 348 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 349 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 350 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
aa1b9b48 | 351 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
cb75d97e | 352 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 353 | device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass; |
a10220bb | 354 | device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; |
5a5c7432 | 355 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
4ae20745 | 356 | device->oclass[NVDEV_SUBDEV_FB ] = &nv46_fb_oclass; |
3863c9bc | 357 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; |
e5f186c4 | 358 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
ebb945a9 BS |
359 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
360 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; | |
361 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
362 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; | |
363 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; | |
364 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
365 | break; |
366 | case 0x68: | |
2094dd82 | 367 | device->cname = "C68"; |
70c0f263 | 368 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 369 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
4196faa8 | 370 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 371 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
aa1b9b48 | 372 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
cb75d97e | 373 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; |
7d9115de | 374 | device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass; |
a10220bb | 375 | device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass; |
5a5c7432 | 376 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
4ae20745 | 377 | device->oclass[NVDEV_SUBDEV_FB ] = &nv46_fb_oclass; |
3863c9bc | 378 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; |
e5f186c4 | 379 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
ebb945a9 BS |
380 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
381 | device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass; | |
382 | device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass; | |
383 | device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; | |
384 | device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; | |
385 | device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; | |
9274f4a9 BS |
386 | break; |
387 | default: | |
388 | nv_fatal(device, "unknown Curie chipset\n"); | |
389 | return -EINVAL; | |
390 | } | |
391 | ||
392 | return 0; | |
393 | } |