[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / subdev / device / nv50.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <subdev/device.h>
#include <subdev/bios.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>

int
nv50_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
	case 0x50:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		break;
	case 0x84:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		break;
	case 0x86:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		break;
	case 0x92:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		break;
	case 0x94:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		break;
	case 0x96:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		break;
	case 0x98:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		break;
	case 0xa0:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		break;
	case 0xaa:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		break;
	case 0xac:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		break;
	case 0xa3:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		break;
	case 0xa5:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		break;
	case 0xa8:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		break;
	case 0xaf:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		break;
	default:
		nv_fatal(device, "unknown Tesla chipset\n");
		return -EINVAL;
	}

	return 0;
}
Commit	Line	Data
9274f4a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include <subdev/device.h>
70c0f263	26	#include <subdev/bios.h>
e0996aea	27	#include <subdev/gpio.h>
4196faa8	28	#include <subdev/i2c.h>
9274f4a9 BS	29
	30	int
	31	nv50_identify(struct nouveau_device *device)
	32	{
	33	switch (device->chipset) {
	34	case 0x50:
70c0f263	35	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	36	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	37	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
9274f4a9 BS	38	break;
9274f4a9 BS	39	case 0x84:
70c0f263	40	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	41	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	42	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
9274f4a9 BS	43	break;
9274f4a9 BS	44	case 0x86:
70c0f263	45	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	46	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	47	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
9274f4a9 BS	48	break;
9274f4a9 BS	49	case 0x92:
70c0f263	50	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	51	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	52	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
9274f4a9 BS	53	break;
9274f4a9 BS	54	case 0x94:
70c0f263	55	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	56	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	57	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
9274f4a9 BS	58	break;
9274f4a9 BS	59	case 0x96:
70c0f263	60	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	61	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	62	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
9274f4a9 BS	63	break;
9274f4a9 BS	64	case 0x98:
70c0f263	65	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	66	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	67	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
9274f4a9 BS	68	break;
9274f4a9 BS	69	case 0xa0:
70c0f263	70	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	71	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	72	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
9274f4a9 BS	73	break;
9274f4a9 BS	74	case 0xaa:
70c0f263	75	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	76	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	77	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
9274f4a9 BS	78	break;
9274f4a9 BS	79	case 0xac:
70c0f263	80	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	81	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	82	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
9274f4a9 BS	83	break;
9274f4a9 BS	84	case 0xa3:
70c0f263	85	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	86	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	87	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
9274f4a9 BS	88	break;
9274f4a9 BS	89	case 0xa5:
70c0f263	90	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	91	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	92	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
9274f4a9 BS	93	break;
9274f4a9 BS	94	case 0xa8:
70c0f263	95	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	96	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	97	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
9274f4a9 BS	98	break;
9274f4a9 BS	99	case 0xaf:
70c0f263	100	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	101	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	102	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
9274f4a9 BS	103	break;
	104	default:
	105	nv_fatal(device, "unknown Tesla chipset\n");
	106	return -EINVAL;
	107	}
	108
	109	return 0;
	110	}