[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / subdev / device / nvc0.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <subdev/device.h>
#include <subdev/bios.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/clock.h>
#include <subdev/mxm.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/ltcg.h>
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/bar.h>

#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/software.h>
#include <engine/graph.h>
#include <engine/vp.h>
#include <engine/bsp.h>
#include <engine/ppp.h>
#include <engine/copy.h>
#include <engine/disp.h>

int
nvc0_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
	case 0xc0:
		device->cname = "GF100";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv50_disp_oclass;
		break;
	case 0xc4:
		device->cname = "GF104";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv50_disp_oclass;
		break;
	case 0xc3:
		device->cname = "GF106";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv50_disp_oclass;
		break;
	case 0xce:
		device->cname = "GF114";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv50_disp_oclass;
		break;
	case 0xcf:
		device->cname = "GF116";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv50_disp_oclass;
		break;
	case 0xc1:
		device->cname = "GF108";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv50_disp_oclass;
		break;
	case 0xc8:
		device->cname = "GF110";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv50_disp_oclass;
		break;
	case 0xd9:
		device->cname = "GF119";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nvd0_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nvd0_disp_oclass;
		break;
	default:
		nv_fatal(device, "unknown Fermi chipset\n");
		return -EINVAL;
	}

	return 0;
}
Commit	Line	Data
9274f4a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include <subdev/device.h>
70c0f263	26	#include <subdev/bios.h>
e0996aea	27	#include <subdev/gpio.h>
4196faa8	28	#include <subdev/i2c.h>
8aceb7de	29	#include <subdev/clock.h>
d38ac521	30	#include <subdev/mxm.h>
cb75d97e	31	#include <subdev/devinit.h>
7d9115de	32	#include <subdev/mc.h>
5a5c7432	33	#include <subdev/timer.h>
861d2107 BS	34	#include <subdev/fb.h>
861d2107 BS	35	#include <subdev/ltcg.h>
3863c9bc BS	36	#include <subdev/instmem.h>
	37	#include <subdev/vm.h>
	38	#include <subdev/bar.h>
9274f4a9	39
ebb945a9 BS	40	#include <engine/dmaobj.h>
	41	#include <engine/fifo.h>
	42	#include <engine/software.h>
	43	#include <engine/graph.h>
	44	#include <engine/vp.h>
	45	#include <engine/bsp.h>
	46	#include <engine/ppp.h>
	47	#include <engine/copy.h>
	48	#include <engine/disp.h>
	49
9274f4a9 BS	50	int
	51	nvc0_identify(struct nouveau_device *device)
	52	{
	53	switch (device->chipset) {
	54	case 0xc0:
2094dd82	55	device->cname = "GF100";
70c0f263	56	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	57	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	58	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	59	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
d38ac521	60	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e	61	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	62	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
5a5c7432	63	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	64	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	65	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
3863c9bc BS	66	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	67	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	68	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	69	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	70	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	71	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	72	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	73	device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
	74	device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
	75	device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
	76	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	77	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
	78	device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9 BS	79	break;
9274f4a9 BS	80	case 0xc4:
2094dd82	81	device->cname = "GF104";
70c0f263	82	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	83	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	84	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	85	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
d38ac521	86	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e	87	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	88	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
5a5c7432	89	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	90	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	91	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
3863c9bc BS	92	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	93	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	94	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	95	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	96	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	97	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	98	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	99	device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
	100	device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
	101	device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
	102	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	103	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
	104	device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9 BS	105	break;
9274f4a9 BS	106	case 0xc3:
2094dd82	107	device->cname = "GF106";
70c0f263	108	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	109	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	110	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	111	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
d38ac521	112	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e	113	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	114	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
5a5c7432	115	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	116	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	117	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
3863c9bc BS	118	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	119	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	120	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	121	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	122	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	123	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	124	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	125	device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
	126	device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
	127	device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
	128	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	129	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
	130	device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9 BS	131	break;
9274f4a9 BS	132	case 0xce:
2094dd82	133	device->cname = "GF114";
70c0f263	134	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	135	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	136	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	137	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
d38ac521	138	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e	139	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	140	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
5a5c7432	141	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	142	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	143	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
3863c9bc BS	144	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	145	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	146	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	147	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	148	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	149	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	150	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	151	device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
	152	device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
	153	device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
	154	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	155	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
	156	device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9 BS	157	break;
9274f4a9 BS	158	case 0xcf:
2094dd82	159	device->cname = "GF116";
70c0f263	160	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	161	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	162	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	163	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
d38ac521	164	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e	165	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	166	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
5a5c7432	167	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	168	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	169	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
3863c9bc BS	170	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	171	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	172	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	173	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	174	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	175	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	176	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	177	device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
	178	device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
	179	device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
	180	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	181	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
	182	device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9 BS	183	break;
9274f4a9 BS	184	case 0xc1:
2094dd82	185	device->cname = "GF108";
70c0f263	186	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	187	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	188	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	189	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
d38ac521	190	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e	191	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	192	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
5a5c7432	193	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	194	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	195	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
3863c9bc BS	196	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	197	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	198	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	199	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	200	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	201	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	202	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	203	device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
	204	device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
	205	device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
	206	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	207	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
	208	device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9 BS	209	break;
9274f4a9 BS	210	case 0xc8:
2094dd82	211	device->cname = "GF110";
70c0f263	212	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	213	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	214	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	215	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
d38ac521	216	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e	217	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	218	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
5a5c7432	219	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	220	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	221	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
3863c9bc BS	222	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	223	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	224	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	225	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	226	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	227	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	228	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	229	device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
	230	device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
	231	device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
	232	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	233	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
	234	device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9 BS	235	break;
9274f4a9 BS	236	case 0xd9:
2094dd82	237	device->cname = "GF119";
70c0f263	238	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	239	device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass;
4196faa8	240	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	241	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
d38ac521	242	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e	243	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	244	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
5a5c7432	245	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	246	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	247	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
3863c9bc BS	248	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	249	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	250	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	251	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	252	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	253	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	254	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	255	device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
	256	device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
	257	device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
	258	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	259	device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass;
9274f4a9 BS	260	break;
	261	default:
	262	nv_fatal(device, "unknown Fermi chipset\n");
	263	return -EINVAL;
	264	}
	265
	266	return 0;
	267	}