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9274f4a9 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
25 | #include <subdev/device.h> | |
70c0f263 | 26 | #include <subdev/bios.h> |
e0996aea | 27 | #include <subdev/gpio.h> |
4196faa8 | 28 | #include <subdev/i2c.h> |
8aceb7de | 29 | #include <subdev/clock.h> |
aa1b9b48 | 30 | #include <subdev/therm.h> |
d38ac521 | 31 | #include <subdev/mxm.h> |
cb75d97e | 32 | #include <subdev/devinit.h> |
7d9115de | 33 | #include <subdev/mc.h> |
5a5c7432 | 34 | #include <subdev/timer.h> |
861d2107 BS |
35 | #include <subdev/fb.h> |
36 | #include <subdev/ltcg.h> | |
2c1a425e | 37 | #include <subdev/ibus.h> |
3863c9bc BS |
38 | #include <subdev/instmem.h> |
39 | #include <subdev/vm.h> | |
40 | #include <subdev/bar.h> | |
9274f4a9 | 41 | |
ebb945a9 BS |
42 | #include <engine/dmaobj.h> |
43 | #include <engine/fifo.h> | |
44 | #include <engine/software.h> | |
45 | #include <engine/graph.h> | |
46 | #include <engine/disp.h> | |
4f32656d | 47 | #include <engine/copy.h> |
b2f04fc6 | 48 | #include <engine/bsp.h> |
a7416d0d | 49 | #include <engine/vp.h> |
fb9bff26 | 50 | #include <engine/ppp.h> |
ebb945a9 | 51 | |
9274f4a9 BS |
52 | int |
53 | nve0_identify(struct nouveau_device *device) | |
54 | { | |
55 | switch (device->chipset) { | |
56 | case 0xe4: | |
2094dd82 | 57 | device->cname = "GK104"; |
70c0f263 | 58 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 59 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass; |
4196faa8 | 60 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 61 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
aa1b9b48 | 62 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; |
d38ac521 | 63 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
cb75d97e | 64 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; |
7d9115de | 65 | device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass; |
5a5c7432 | 66 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
861d2107 BS |
67 | device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass; |
68 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | |
2c1a425e | 69 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
3863c9bc BS |
70 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; |
71 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | |
72 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | |
344e107d | 73 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; |
ebb945a9 BS |
74 | device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; |
75 | device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; | |
76 | device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass; | |
46654061 | 77 | device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; |
4f32656d BS |
78 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; |
79 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; | |
b2f04fc6 | 80 | device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; |
a7416d0d | 81 | device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; |
fb9bff26 | 82 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
9274f4a9 BS |
83 | break; |
84 | case 0xe7: | |
2094dd82 | 85 | device->cname = "GK107"; |
70c0f263 | 86 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
e0996aea | 87 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass; |
4196faa8 | 88 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
8aceb7de | 89 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
aa1b9b48 | 90 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; |
d38ac521 | 91 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
cb75d97e | 92 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; |
7d9115de | 93 | device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass; |
5a5c7432 | 94 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
861d2107 BS |
95 | device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass; |
96 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | |
2c1a425e | 97 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
3863c9bc BS |
98 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; |
99 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | |
100 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | |
344e107d | 101 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; |
ebb945a9 BS |
102 | device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass; |
103 | device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass; | |
104 | device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass; | |
46654061 | 105 | device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; |
4f32656d BS |
106 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; |
107 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; | |
b2f04fc6 | 108 | device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; |
a7416d0d | 109 | device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; |
fb9bff26 | 110 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
9274f4a9 BS |
111 | break; |
112 | default: | |
113 | nv_fatal(device, "unknown Kepler chipset\n"); | |
114 | return -EINVAL; | |
115 | } | |
116 | ||
117 | return 0; | |
118 | } |