Commit | Line | Data |
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45284162 | 1 | /* |
e0996aea | 2 | * Copyright 2012 Red Hat Inc. |
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3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
02a841d4 | 25 | #include <subdev/gpio.h> |
45284162 | 26 | |
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27 | struct nv50_gpio_priv { |
28 | struct nouveau_gpio base; | |
29 | }; | |
30 | ||
31 | static void | |
32 | nv50_gpio_reset(struct nouveau_gpio *gpio) | |
33 | { | |
34 | struct nouveau_bios *bios = nouveau_bios(gpio); | |
35 | struct nv50_gpio_priv *priv = (void *)gpio; | |
d2bcea68 | 36 | u8 ver, len; |
e0996aea | 37 | u16 entry; |
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38 | int ent = -1; |
39 | ||
d2bcea68 | 40 | while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) { |
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41 | static const u32 regs[] = { 0xe100, 0xe28c }; |
42 | u32 data = nv_ro32(bios, entry); | |
43 | u8 line = (data & 0x0000001f); | |
44 | u8 func = (data & 0x0000ff00) >> 8; | |
45 | u8 defs = !!(data & 0x01000000); | |
46 | u8 unk0 = !!(data & 0x02000000); | |
47 | u8 unk1 = !!(data & 0x04000000); | |
48 | u32 val = (unk1 << 16) | unk0; | |
49 | u32 reg = regs[line >> 4]; line &= 0x0f; | |
50 | ||
51 | if (func == 0xff) | |
52 | continue; | |
53 | ||
54 | gpio->set(gpio, 0, func, line, defs); | |
55 | ||
56 | nv_mask(priv, reg, 0x00010001 << line, val << line); | |
57 | } | |
58 | } | |
19b7fc7b | 59 | |
45284162 | 60 | static int |
a0b25635 | 61 | nv50_gpio_location(int line, u32 *reg, u32 *shift) |
45284162 | 62 | { |
e0996aea | 63 | const u32 nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; |
45284162 | 64 | |
a0b25635 | 65 | if (line >= 32) |
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66 | return -EINVAL; |
67 | ||
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68 | *reg = nv50_gpio_reg[line >> 3]; |
69 | *shift = (line & 7) << 2; | |
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70 | return 0; |
71 | } | |
72 | ||
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73 | static int |
74 | nv50_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out) | |
45284162 | 75 | { |
a0b25635 | 76 | u32 reg, shift; |
45284162 | 77 | |
a0b25635 | 78 | if (nv50_gpio_location(line, ®, &shift)) |
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79 | return -EINVAL; |
80 | ||
e0996aea | 81 | nv_mask(gpio, reg, 7 << shift, (((dir ^ 1) << 1) | out) << shift); |
a0b25635 | 82 | return 0; |
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83 | } |
84 | ||
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85 | static int |
86 | nv50_gpio_sense(struct nouveau_gpio *gpio, int line) | |
45284162 | 87 | { |
a0b25635 | 88 | u32 reg, shift; |
45284162 | 89 | |
a0b25635 | 90 | if (nv50_gpio_location(line, ®, &shift)) |
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91 | return -EINVAL; |
92 | ||
e0996aea | 93 | return !!(nv_rd32(gpio, reg) & (4 << shift)); |
45284162 | 94 | } |
d0875edd | 95 | |
a0b25635 | 96 | void |
e0996aea | 97 | nv50_gpio_irq_enable(struct nouveau_gpio *gpio, int line, bool on) |
d7f8172c | 98 | { |
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99 | u32 reg = line < 16 ? 0xe050 : 0xe070; |
100 | u32 mask = 0x00010001 << (line & 0xf); | |
d7f8172c | 101 | |
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102 | nv_wr32(gpio, reg + 4, mask); |
103 | nv_mask(gpio, reg + 0, mask, on ? mask : 0); | |
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104 | } |
105 | ||
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106 | void |
107 | nv50_gpio_intr(struct nouveau_subdev *subdev) | |
fce2bad0 | 108 | { |
e0996aea | 109 | struct nv50_gpio_priv *priv = (void *)subdev; |
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110 | u32 intr0, intr1 = 0; |
111 | u32 hi, lo; | |
fce2bad0 | 112 | |
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113 | intr0 = nv_rd32(priv, 0xe054) & nv_rd32(priv, 0xe050); |
114 | if (nv_device(priv)->chipset >= 0x90) | |
115 | intr1 = nv_rd32(priv, 0xe074) & nv_rd32(priv, 0xe070); | |
fce2bad0 | 116 | |
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117 | hi = (intr0 & 0x0000ffff) | (intr1 << 16); |
118 | lo = (intr0 >> 16) | (intr1 & 0xffff0000); | |
e0996aea | 119 | priv->base.isr_run(&priv->base, 0, hi | lo); |
fce2bad0 | 120 | |
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121 | nv_wr32(priv, 0xe054, intr0); |
122 | if (nv_device(priv)->chipset >= 0x90) | |
123 | nv_wr32(priv, 0xe074, intr1); | |
d0875edd | 124 | } |
ee2e0131 | 125 | |
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126 | static int |
127 | nv50_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |
128 | struct nouveau_oclass *oclass, void *data, u32 size, | |
129 | struct nouveau_object **pobject) | |
130 | { | |
131 | struct nv50_gpio_priv *priv; | |
132 | int ret; | |
133 | ||
134 | ret = nouveau_gpio_create(parent, engine, oclass, &priv); | |
135 | *pobject = nv_object(priv); | |
136 | if (ret) | |
137 | return ret; | |
138 | ||
139 | priv->base.reset = nv50_gpio_reset; | |
140 | priv->base.drive = nv50_gpio_drive; | |
141 | priv->base.sense = nv50_gpio_sense; | |
142 | priv->base.irq_enable = nv50_gpio_irq_enable; | |
143 | nv_subdev(priv)->intr = nv50_gpio_intr; | |
144 | return 0; | |
145 | } | |
146 | ||
147 | void | |
148 | nv50_gpio_dtor(struct nouveau_object *object) | |
149 | { | |
150 | struct nv50_gpio_priv *priv = (void *)object; | |
151 | nouveau_gpio_destroy(&priv->base); | |
152 | } | |
6c06d608 | 153 | |
ee2e0131 | 154 | int |
e0996aea | 155 | nv50_gpio_init(struct nouveau_object *object) |
ee2e0131 | 156 | { |
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157 | struct nv50_gpio_priv *priv = (void *)object; |
158 | int ret; | |
ee2e0131 | 159 | |
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160 | ret = nouveau_gpio_init(&priv->base); |
161 | if (ret) | |
162 | return ret; | |
6c06d608 | 163 | |
ee2e0131 | 164 | /* disable, and ack any pending gpio interrupts */ |
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165 | nv_wr32(priv, 0xe050, 0x00000000); |
166 | nv_wr32(priv, 0xe054, 0xffffffff); | |
167 | if (nv_device(priv)->chipset >= 0x90) { | |
168 | nv_wr32(priv, 0xe070, 0x00000000); | |
169 | nv_wr32(priv, 0xe074, 0xffffffff); | |
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170 | } |
171 | ||
172 | return 0; | |
173 | } | |
2cbd4c81 | 174 | |
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175 | int |
176 | nv50_gpio_fini(struct nouveau_object *object, bool suspend) | |
2cbd4c81 | 177 | { |
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178 | struct nv50_gpio_priv *priv = (void *)object; |
179 | nv_wr32(priv, 0xe050, 0x00000000); | |
180 | if (nv_device(priv)->chipset >= 0x90) | |
181 | nv_wr32(priv, 0xe070, 0x00000000); | |
182 | return nouveau_gpio_fini(&priv->base, suspend); | |
2cbd4c81 | 183 | } |
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184 | |
185 | struct nouveau_oclass | |
186 | nv50_gpio_oclass = { | |
187 | .handle = NV_SUBDEV(GPIO, 0x50), | |
188 | .ofuncs = &(struct nouveau_ofuncs) { | |
189 | .ctor = nv50_gpio_ctor, | |
190 | .dtor = nv50_gpio_dtor, | |
191 | .init = nv50_gpio_init, | |
192 | .fini = nv50_gpio_fini, | |
193 | }, | |
194 | }; |