[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_chan.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <nvif/os.h>
#include <nvif/class.h>
#include <nvif/cl0002.h>
#include <nvif/cl006b.h>
#include <nvif/cl506f.h>
#include <nvif/cl906f.h>
#include <nvif/cla06f.h>
#include <nvif/ioctl.h>

/*XXX*/
#include <core/client.h>

#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nouveau_bo.h"
#include "nouveau_chan.h"
#include "nouveau_fence.h"
#include "nouveau_abi16.h"

MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
int nouveau_vram_pushbuf;
module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);

int
nouveau_channel_idle(struct nouveau_channel *chan)
{
	if (likely(chan && chan->fence)) {
		struct nouveau_cli *cli = (void *)chan->user.client;
		struct nouveau_fence *fence = NULL;
		int ret;

		ret = nouveau_fence_new(chan, false, &fence);
		if (!ret) {
			ret = nouveau_fence_wait(fence, false, false);
			nouveau_fence_unref(&fence);
		}

		if (ret) {
			NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n",
				  chan->chid, nvxx_client(&cli->base)->name);
			return ret;
		}
	}
	return 0;
}

void
nouveau_channel_del(struct nouveau_channel **pchan)
{
	struct nouveau_channel *chan = *pchan;
	if (chan) {
		if (chan->fence)
			nouveau_fence(chan->drm)->context_del(chan);
		nvif_object_fini(&chan->nvsw);
		nvif_object_fini(&chan->gart);
		nvif_object_fini(&chan->vram);
		nvif_object_fini(&chan->user);
		nvif_object_fini(&chan->push.ctxdma);
		nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma);
		nouveau_bo_unmap(chan->push.buffer);
		if (chan->push.buffer && chan->push.buffer->pin_refcnt)
			nouveau_bo_unpin(chan->push.buffer);
		nouveau_bo_ref(NULL, &chan->push.buffer);
		kfree(chan);
	}
	*pchan = NULL;
}

static int
nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
		     u32 size, struct nouveau_channel **pchan)
{
	struct nouveau_cli *cli = (void *)device->object.client;
	struct nvkm_mmu *mmu = nvxx_mmu(device);
	struct nv_dma_v0 args = {};
	struct nouveau_channel *chan;
	u32 target;
	int ret;

	chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL);
	if (!chan)
		return -ENOMEM;

	chan->device = device;
	chan->drm = drm;

	/* allocate memory for dma push buffer */
	target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
	if (nouveau_vram_pushbuf)
		target = TTM_PL_FLAG_VRAM;

	ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, NULL,
			    &chan->push.buffer);
	if (ret == 0) {
		ret = nouveau_bo_pin(chan->push.buffer, target, false);
		if (ret == 0)
			ret = nouveau_bo_map(chan->push.buffer);
	}

	if (ret) {
		nouveau_channel_del(pchan);
		return ret;
	}

	/* create dma object covering the *entire* memory space that the
	 * pushbuf lives in, this is because the GEM code requires that
	 * we be able to call out to other (indirect) push buffers
	 */
	chan->push.vma.offset = chan->push.buffer->bo.offset;

	if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
		ret = nouveau_bo_vma_add(chan->push.buffer, cli->vm,
					&chan->push.vma);
		if (ret) {
			nouveau_channel_del(pchan);
			return ret;
		}

		args.target = NV_DMA_V0_TARGET_VM;
		args.access = NV_DMA_V0_ACCESS_VM;
		args.start = 0;
		args.limit = cli->vm->mmu->limit - 1;
	} else
	if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
		if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
			/* nv04 vram pushbuf hack, retarget to its location in
			 * the framebuffer bar rather than direct vram access..
			 * nfi why this exists, it came from the -nv ddx.
			 */
			args.target = NV_DMA_V0_TARGET_PCI;
			args.access = NV_DMA_V0_ACCESS_RDWR;
			args.start = nvxx_device(device)->func->
				resource_addr(nvxx_device(device), 1);
			args.limit = args.start + device->info.ram_user - 1;
		} else {
			args.target = NV_DMA_V0_TARGET_VRAM;
			args.access = NV_DMA_V0_ACCESS_RDWR;
			args.start = 0;
			args.limit = device->info.ram_user - 1;
		}
	} else {
		if (chan->drm->agp.bridge) {
			args.target = NV_DMA_V0_TARGET_AGP;
			args.access = NV_DMA_V0_ACCESS_RDWR;
			args.start = chan->drm->agp.base;
			args.limit = chan->drm->agp.base +
				     chan->drm->agp.size - 1;
		} else {
			args.target = NV_DMA_V0_TARGET_VM;
			args.access = NV_DMA_V0_ACCESS_RDWR;
			args.start = 0;
			args.limit = mmu->limit - 1;
		}
	}

	ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
			       &args, sizeof(args), &chan->push.ctxdma);
	if (ret) {
		nouveau_channel_del(pchan);
		return ret;
	}

	return 0;
}

static int
nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
		    u32 engine, struct nouveau_channel **pchan)
{
	static const u16 oclasses[] = { MAXWELL_CHANNEL_GPFIFO_A,
					KEPLER_CHANNEL_GPFIFO_B,
					KEPLER_CHANNEL_GPFIFO_A,
					FERMI_CHANNEL_GPFIFO,
					G82_CHANNEL_GPFIFO,
					NV50_CHANNEL_GPFIFO,
					0 };
	const u16 *oclass = oclasses;
	union {
		struct nv50_channel_gpfifo_v0 nv50;
		struct fermi_channel_gpfifo_v0 fermi;
		struct kepler_channel_gpfifo_a_v0 kepler;
	} args;
	struct nouveau_channel *chan;
	u32 size;
	int ret;

	/* allocate dma push buffer */
	ret = nouveau_channel_prep(drm, device, 0x12000, &chan);
	*pchan = chan;
	if (ret)
		return ret;

	/* create channel object */
	do {
		if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) {
			args.kepler.version = 0;
			args.kepler.engines = engine;
			args.kepler.ilength = 0x02000;
			args.kepler.ioffset = 0x10000 + chan->push.vma.offset;
			args.kepler.vm = 0;
			size = sizeof(args.kepler);
		} else
		if (oclass[0] >= FERMI_CHANNEL_GPFIFO) {
			args.fermi.version = 0;
			args.fermi.ilength = 0x02000;
			args.fermi.ioffset = 0x10000 + chan->push.vma.offset;
			args.fermi.vm = 0;
			size = sizeof(args.fermi);
		} else {
			args.nv50.version = 0;
			args.nv50.ilength = 0x02000;
			args.nv50.ioffset = 0x10000 + chan->push.vma.offset;
			args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma);
			args.nv50.vm = 0;
			size = sizeof(args.nv50);
		}

		ret = nvif_object_init(&device->object, 0, *oclass++,
				       &args, size, &chan->user);
		if (ret == 0) {
			if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A)
				chan->chid = args.kepler.chid;
			else
			if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO)
				chan->chid = args.fermi.chid;
			else
				chan->chid = args.nv50.chid;
			return ret;
		}
	} while (*oclass);

	nouveau_channel_del(pchan);
	return ret;
}

static int
nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device,
		    struct nouveau_channel **pchan)
{
	static const u16 oclasses[] = { NV40_CHANNEL_DMA,
					NV17_CHANNEL_DMA,
					NV10_CHANNEL_DMA,
					NV03_CHANNEL_DMA,
					0 };
	const u16 *oclass = oclasses;
	struct nv03_channel_dma_v0 args;
	struct nouveau_channel *chan;
	int ret;

	/* allocate dma push buffer */
	ret = nouveau_channel_prep(drm, device, 0x10000, &chan);
	*pchan = chan;
	if (ret)
		return ret;

	/* create channel object */
	args.version = 0;
	args.pushbuf = nvif_handle(&chan->push.ctxdma);
	args.offset = chan->push.vma.offset;

	do {
		ret = nvif_object_init(&device->object, 0, *oclass++,
				       &args, sizeof(args), &chan->user);
		if (ret == 0) {
			chan->chid = args.chid;
			return ret;
		}
	} while (ret && *oclass);

	nouveau_channel_del(pchan);
	return ret;
}

static int
nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
{
	struct nvif_device *device = chan->device;
	struct nouveau_cli *cli = (void *)chan->user.client;
	struct nvkm_mmu *mmu = nvxx_mmu(device);
	struct nv_dma_v0 args = {};
	int ret, i;

	nvif_object_map(&chan->user);

	/* allocate dma objects to cover all allowed vram, and gart */
	if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
		if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
			args.target = NV_DMA_V0_TARGET_VM;
			args.access = NV_DMA_V0_ACCESS_VM;
			args.start = 0;
			args.limit = cli->vm->mmu->limit - 1;
		} else {
			args.target = NV_DMA_V0_TARGET_VRAM;
			args.access = NV_DMA_V0_ACCESS_RDWR;
			args.start = 0;
			args.limit = device->info.ram_user - 1;
		}

		ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY,
				       &args, sizeof(args), &chan->vram);
		if (ret)
			return ret;

		if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
			args.target = NV_DMA_V0_TARGET_VM;
			args.access = NV_DMA_V0_ACCESS_VM;
			args.start = 0;
			args.limit = cli->vm->mmu->limit - 1;
		} else
		if (chan->drm->agp.bridge) {
			args.target = NV_DMA_V0_TARGET_AGP;
			args.access = NV_DMA_V0_ACCESS_RDWR;
			args.start = chan->drm->agp.base;
			args.limit = chan->drm->agp.base +
				     chan->drm->agp.size - 1;
		} else {
			args.target = NV_DMA_V0_TARGET_VM;
			args.access = NV_DMA_V0_ACCESS_RDWR;
			args.start = 0;
			args.limit = mmu->limit - 1;
		}

		ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY,
				       &args, sizeof(args), &chan->gart);
		if (ret)
			return ret;
	}

	/* initialise dma tracking parameters */
	switch (chan->user.oclass & 0x00ff) {
	case 0x006b:
	case 0x006e:
		chan->user_put = 0x40;
		chan->user_get = 0x44;
		chan->dma.max = (0x10000 / 4) - 2;
		break;
	default:
		chan->user_put = 0x40;
		chan->user_get = 0x44;
		chan->user_get_hi = 0x60;
		chan->dma.ib_base =  0x10000 / 4;
		chan->dma.ib_max  = (0x02000 / 8) - 1;
		chan->dma.ib_put  = 0;
		chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
		chan->dma.max = chan->dma.ib_base;
		break;
	}

	chan->dma.put = 0;
	chan->dma.cur = chan->dma.put;
	chan->dma.free = chan->dma.max - chan->dma.cur;

	ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
	if (ret)
		return ret;

	for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
		OUT_RING(chan, 0x00000000);

	/* allocate software object class (used for fences on <= nv05) */
	if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
		ret = nvif_object_init(&chan->user, 0x006e,
				       NVIF_CLASS_SW_NV04,
				       NULL, 0, &chan->nvsw);
		if (ret)
			return ret;

		ret = RING_SPACE(chan, 2);
		if (ret)
			return ret;

		BEGIN_NV04(chan, NvSubSw, 0x0000, 1);
		OUT_RING  (chan, chan->nvsw.handle);
		FIRE_RING (chan);
	}

	/* initialise synchronisation */
	return nouveau_fence(chan->drm)->context_new(chan);
}

int
nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device,
		    u32 arg0, u32 arg1, struct nouveau_channel **pchan)
{
	struct nouveau_cli *cli = (void *)device->object.client;
	bool super;
	int ret;

	/* hack until fencenv50 is fixed, and agp access relaxed */
	super = cli->base.super;
	cli->base.super = true;

	ret = nouveau_channel_ind(drm, device, arg0, pchan);
	if (ret) {
		NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret);
		ret = nouveau_channel_dma(drm, device, pchan);
		if (ret) {
			NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret);
			goto done;
		}
	}

	ret = nouveau_channel_init(*pchan, arg0, arg1);
	if (ret) {
		NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret);
		nouveau_channel_del(pchan);
	}

done:
	cli->base.super = super;
	return ret;
}
Commit	Line	Data
ebb945a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
fdb751ef BS	25	#include <nvif/os.h>
fdb751ef BS	26	#include <nvif/class.h>
845f2725	27	#include <nvif/cl0002.h>
8ed1730c BS	28	#include <nvif/cl006b.h>
	29	#include <nvif/cl506f.h>
	30	#include <nvif/cl906f.h>
	31	#include <nvif/cla06f.h>
f58ddf95	32	#include <nvif/ioctl.h>
fdb751ef BS	33
fdb751ef BS	34	/XXX/
ebb945a9	35	#include <core/client.h>
ebb945a9	36
ebb945a9 BS	37	#include "nouveau_drm.h"
	38	#include "nouveau_dma.h"
	39	#include "nouveau_bo.h"
	40	#include "nouveau_chan.h"
	41	#include "nouveau_fence.h"
	42	#include "nouveau_abi16.h"
	43
	44	MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
703fa264	45	int nouveau_vram_pushbuf;
ebb945a9 BS	46	module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
	47
	48	int
	49	nouveau_channel_idle(struct nouveau_channel *chan)
	50	{
fbd58ebd BS	51	if (likely(chan && chan->fence)) {
	52	struct nouveau_cli cli = (void )chan->user.client;
	53	struct nouveau_fence *fence = NULL;
	54	int ret;
ebb945a9	55
fbd58ebd BS	56	ret = nouveau_fence_new(chan, false, &fence);
	57	if (!ret) {
	58	ret = nouveau_fence_wait(fence, false, false);
	59	nouveau_fence_unref(&fence);
	60	}
ebb945a9	61
fbd58ebd	62	if (ret) {
fcf3f91c BS	63	NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n",
fcf3f91c BS	64	chan->chid, nvxx_client(&cli->base)->name);
fbd58ebd BS	65	return ret;
	66	}
	67	}
	68	return 0;
ebb945a9 BS	69	}
	70
	71	void
	72	nouveau_channel_del(struct nouveau_channel **pchan)
	73	{
	74	struct nouveau_channel chan = pchan;
	75	if (chan) {
fbd58ebd	76	if (chan->fence)
ebb945a9	77	nouveau_fence(chan->drm)->context_del(chan);
0ad72863 BS	78	nvif_object_fini(&chan->nvsw);
	79	nvif_object_fini(&chan->gart);
	80	nvif_object_fini(&chan->vram);
a01ca78c	81	nvif_object_fini(&chan->user);
0ad72863	82	nvif_object_fini(&chan->push.ctxdma);
ebb945a9 BS	83	nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma);
ebb945a9 BS	84	nouveau_bo_unmap(chan->push.buffer);
124ea297 MS	85	if (chan->push.buffer && chan->push.buffer->pin_refcnt)
124ea297 MS	86	nouveau_bo_unpin(chan->push.buffer);
ebb945a9 BS	87	nouveau_bo_ref(NULL, &chan->push.buffer);
	88	kfree(chan);
	89	}
	90	*pchan = NULL;
	91	}
	92
	93	static int
0ad72863	94	nouveau_channel_prep(struct nouveau_drm drm, struct nvif_device device,
fcf3f91c	95	u32 size, struct nouveau_channel **pchan)
ebb945a9	96	{
a01ca78c	97	struct nouveau_cli cli = (void )device->object.client;
be83cd4e	98	struct nvkm_mmu *mmu = nvxx_mmu(device);
4acfd707	99	struct nv_dma_v0 args = {};
ebb945a9	100	struct nouveau_channel *chan;
ebb945a9 BS	101	u32 target;
	102	int ret;
	103
	104	chan = pchan = kzalloc(sizeof(chan), GFP_KERNEL);
	105	if (!chan)
	106	return -ENOMEM;
	107
a01ca78c	108	chan->device = device;
ebb945a9	109	chan->drm = drm;
ebb945a9 BS	110
ebb945a9 BS	111	/* allocate memory for dma push buffer */
a81349a7	112	target = TTM_PL_FLAG_TT \| TTM_PL_FLAG_UNCACHED;
ebb945a9 BS	113	if (nouveau_vram_pushbuf)
	114	target = TTM_PL_FLAG_VRAM;
	115
bb6178b0	116	ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, NULL,
ebb945a9 BS	117	&chan->push.buffer);
ebb945a9 BS	118	if (ret == 0) {
ad76b3f7	119	ret = nouveau_bo_pin(chan->push.buffer, target, false);
ebb945a9 BS	120	if (ret == 0)
	121	ret = nouveau_bo_map(chan->push.buffer);
	122	}
	123
	124	if (ret) {
	125	nouveau_channel_del(pchan);
	126	return ret;
	127	}
	128
	129	/* create dma object covering the entire memory space that the
	130	* pushbuf lives in, this is because the GEM code requires that
	131	* we be able to call out to other (indirect) push buffers
	132	*/
	133	chan->push.vma.offset = chan->push.buffer->bo.offset;
ebb945a9	134
967e7bde	135	if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
0ad72863	136	ret = nouveau_bo_vma_add(chan->push.buffer, cli->vm,
ebb945a9 BS	137	&chan->push.vma);
	138	if (ret) {
	139	nouveau_channel_del(pchan);
	140	return ret;
	141	}
	142
4acfd707 BS	143	args.target = NV_DMA_V0_TARGET_VM;
4acfd707 BS	144	args.access = NV_DMA_V0_ACCESS_VM;
ebb945a9	145	args.start = 0;
5ce3bf3c	146	args.limit = cli->vm->mmu->limit - 1;
ebb945a9 BS	147	} else
ebb945a9 BS	148	if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
967e7bde	149	if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
ebb945a9 BS	150	/* nv04 vram pushbuf hack, retarget to its location in
	151	* the framebuffer bar rather than direct vram access..
	152	* nfi why this exists, it came from the -nv ddx.
	153	*/
4acfd707 BS	154	args.target = NV_DMA_V0_TARGET_PCI;
4acfd707 BS	155	args.access = NV_DMA_V0_ACCESS_RDWR;
7e8820fe BS	156	args.start = nvxx_device(device)->func->
7e8820fe BS	157	resource_addr(nvxx_device(device), 1);
f392ec4b	158	args.limit = args.start + device->info.ram_user - 1;
ebb945a9	159	} else {
4acfd707 BS	160	args.target = NV_DMA_V0_TARGET_VRAM;
4acfd707 BS	161	args.access = NV_DMA_V0_ACCESS_RDWR;
ebb945a9	162	args.start = 0;
f392ec4b	163	args.limit = device->info.ram_user - 1;
ebb945a9 BS	164	}
ebb945a9 BS	165	} else {
340b0e7c	166	if (chan->drm->agp.bridge) {
4acfd707 BS	167	args.target = NV_DMA_V0_TARGET_AGP;
4acfd707 BS	168	args.access = NV_DMA_V0_ACCESS_RDWR;
ebb945a9 BS	169	args.start = chan->drm->agp.base;
	170	args.limit = chan->drm->agp.base +
	171	chan->drm->agp.size - 1;
	172	} else {
4acfd707 BS	173	args.target = NV_DMA_V0_TARGET_VM;
4acfd707 BS	174	args.access = NV_DMA_V0_ACCESS_RDWR;
ebb945a9	175	args.start = 0;
5ce3bf3c	176	args.limit = mmu->limit - 1;
ebb945a9 BS	177	}
	178	}
	179
fcf3f91c	180	ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
0ad72863	181	&args, sizeof(args), &chan->push.ctxdma);
ebb945a9 BS	182	if (ret) {
	183	nouveau_channel_del(pchan);
	184	return ret;
	185	}
	186
	187	return 0;
	188	}
	189
5b8a43ae	190	static int
0ad72863	191	nouveau_channel_ind(struct nouveau_drm drm, struct nvif_device device,
fcf3f91c	192	u32 engine, struct nouveau_channel **pchan)
ebb945a9	193	{
a1020afe	194	static const u16 oclasses[] = { MAXWELL_CHANNEL_GPFIFO_A,
63f8c9b7	195	KEPLER_CHANNEL_GPFIFO_B,
a1020afe	196	KEPLER_CHANNEL_GPFIFO_A,
bbf8906b BS	197	FERMI_CHANNEL_GPFIFO,
	198	G82_CHANNEL_GPFIFO,
	199	NV50_CHANNEL_GPFIFO,
c97f8c92	200	0 };
ebb945a9	201	const u16 *oclass = oclasses;
bbf8906b BS	202	union {
bbf8906b BS	203	struct nv50_channel_gpfifo_v0 nv50;
159045cd	204	struct fermi_channel_gpfifo_v0 fermi;
bbf8906b	205	struct kepler_channel_gpfifo_a_v0 kepler;
a01ca78c	206	} args;
ebb945a9	207	struct nouveau_channel *chan;
bbf8906b	208	u32 size;
ebb945a9 BS	209	int ret;
	210
	211	/* allocate dma push buffer */
fcf3f91c	212	ret = nouveau_channel_prep(drm, device, 0x12000, &chan);
ebb945a9 BS	213	*pchan = chan;
	214	if (ret)
	215	return ret;
	216
	217	/* create channel object */
ebb945a9	218	do {
bbf8906b BS	219	if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) {
bbf8906b BS	220	args.kepler.version = 0;
1f5ff7f5	221	args.kepler.engines = engine;
bbf8906b BS	222	args.kepler.ilength = 0x02000;
bbf8906b BS	223	args.kepler.ioffset = 0x10000 + chan->push.vma.offset;
159045cd	224	args.kepler.vm = 0;
bbf8906b	225	size = sizeof(args.kepler);
159045cd BS	226	} else
	227	if (oclass[0] >= FERMI_CHANNEL_GPFIFO) {
	228	args.fermi.version = 0;
	229	args.fermi.ilength = 0x02000;
	230	args.fermi.ioffset = 0x10000 + chan->push.vma.offset;
	231	args.fermi.vm = 0;
	232	size = sizeof(args.fermi);
bbf8906b BS	233	} else {
bbf8906b BS	234	args.nv50.version = 0;
bbf8906b BS	235	args.nv50.ilength = 0x02000;
bbf8906b BS	236	args.nv50.ioffset = 0x10000 + chan->push.vma.offset;
159045cd BS	237	args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma);
159045cd BS	238	args.nv50.vm = 0;
bbf8906b BS	239	size = sizeof(args.nv50);
	240	}
	241
fcf3f91c	242	ret = nvif_object_init(&device->object, 0, *oclass++,
a01ca78c	243	&args, size, &chan->user);
bbf8906b	244	if (ret == 0) {
a01ca78c BS	245	if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A)
a01ca78c BS	246	chan->chid = args.kepler.chid;
159045cd BS	247	else
	248	if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO)
	249	chan->chid = args.fermi.chid;
bbf8906b	250	else
a01ca78c	251	chan->chid = args.nv50.chid;
ebb945a9	252	return ret;
bbf8906b	253	}
ebb945a9 BS	254	} while (*oclass);
	255
	256	nouveau_channel_del(pchan);
	257	return ret;
	258	}
	259
	260	static int
0ad72863	261	nouveau_channel_dma(struct nouveau_drm drm, struct nvif_device device,
fcf3f91c	262	struct nouveau_channel **pchan)
ebb945a9	263	{
bbf8906b BS	264	static const u16 oclasses[] = { NV40_CHANNEL_DMA,
	265	NV17_CHANNEL_DMA,
	266	NV10_CHANNEL_DMA,
	267	NV03_CHANNEL_DMA,
c97f8c92	268	0 };
ebb945a9	269	const u16 *oclass = oclasses;
a01ca78c	270	struct nv03_channel_dma_v0 args;
ebb945a9 BS	271	struct nouveau_channel *chan;
	272	int ret;
	273
	274	/* allocate dma push buffer */
fcf3f91c	275	ret = nouveau_channel_prep(drm, device, 0x10000, &chan);
ebb945a9 BS	276	*pchan = chan;
	277	if (ret)
	278	return ret;
	279
	280	/* create channel object */
bbf8906b	281	args.version = 0;
bf81df9b	282	args.pushbuf = nvif_handle(&chan->push.ctxdma);
ebb945a9 BS	283	args.offset = chan->push.vma.offset;
	284
	285	do {
fcf3f91c	286	ret = nvif_object_init(&device->object, 0, *oclass++,
a01ca78c	287	&args, sizeof(args), &chan->user);
bbf8906b	288	if (ret == 0) {
a01ca78c	289	chan->chid = args.chid;
ebb945a9	290	return ret;
bbf8906b	291	}
ebb945a9 BS	292	} while (ret && *oclass);
	293
	294	nouveau_channel_del(pchan);
	295	return ret;
	296	}
	297
	298	static int
	299	nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
	300	{
0ad72863	301	struct nvif_device *device = chan->device;
a01ca78c	302	struct nouveau_cli cli = (void )chan->user.client;
be83cd4e	303	struct nvkm_mmu *mmu = nvxx_mmu(device);
4acfd707	304	struct nv_dma_v0 args = {};
ebb945a9 BS	305	int ret, i;
ebb945a9 BS	306
a01ca78c	307	nvif_object_map(&chan->user);
6c6ae061	308
ebb945a9	309	/* allocate dma objects to cover all allowed vram, and gart */
967e7bde BS	310	if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
967e7bde BS	311	if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
4acfd707 BS	312	args.target = NV_DMA_V0_TARGET_VM;
4acfd707 BS	313	args.access = NV_DMA_V0_ACCESS_VM;
ebb945a9	314	args.start = 0;
5ce3bf3c	315	args.limit = cli->vm->mmu->limit - 1;
ebb945a9	316	} else {
4acfd707 BS	317	args.target = NV_DMA_V0_TARGET_VRAM;
4acfd707 BS	318	args.access = NV_DMA_V0_ACCESS_RDWR;
ebb945a9	319	args.start = 0;
f392ec4b	320	args.limit = device->info.ram_user - 1;
ebb945a9 BS	321	}
ebb945a9 BS	322
a01ca78c BS	323	ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY,
a01ca78c BS	324	&args, sizeof(args), &chan->vram);
ebb945a9 BS	325	if (ret)
	326	return ret;
	327
967e7bde	328	if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
4acfd707 BS	329	args.target = NV_DMA_V0_TARGET_VM;
4acfd707 BS	330	args.access = NV_DMA_V0_ACCESS_VM;
ebb945a9	331	args.start = 0;
5ce3bf3c	332	args.limit = cli->vm->mmu->limit - 1;
ebb945a9	333	} else
340b0e7c	334	if (chan->drm->agp.bridge) {
4acfd707 BS	335	args.target = NV_DMA_V0_TARGET_AGP;
4acfd707 BS	336	args.access = NV_DMA_V0_ACCESS_RDWR;
ebb945a9 BS	337	args.start = chan->drm->agp.base;
	338	args.limit = chan->drm->agp.base +
	339	chan->drm->agp.size - 1;
	340	} else {
4acfd707 BS	341	args.target = NV_DMA_V0_TARGET_VM;
4acfd707 BS	342	args.access = NV_DMA_V0_ACCESS_RDWR;
ebb945a9	343	args.start = 0;
5ce3bf3c	344	args.limit = mmu->limit - 1;
ebb945a9 BS	345	}
ebb945a9 BS	346
a01ca78c BS	347	ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY,
a01ca78c BS	348	&args, sizeof(args), &chan->gart);
ebb945a9 BS	349	if (ret)
	350	return ret;
	351	}
	352
	353	/* initialise dma tracking parameters */
a01ca78c	354	switch (chan->user.oclass & 0x00ff) {
503b0f1c	355	case 0x006b:
ebb945a9 BS	356	case 0x006e:
	357	chan->user_put = 0x40;
	358	chan->user_get = 0x44;
	359	chan->dma.max = (0x10000 / 4) - 2;
	360	break;
	361	default:
	362	chan->user_put = 0x40;
	363	chan->user_get = 0x44;
	364	chan->user_get_hi = 0x60;
	365	chan->dma.ib_base = 0x10000 / 4;
	366	chan->dma.ib_max = (0x02000 / 8) - 1;
	367	chan->dma.ib_put = 0;
	368	chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
	369	chan->dma.max = chan->dma.ib_base;
	370	break;
	371	}
	372
	373	chan->dma.put = 0;
	374	chan->dma.cur = chan->dma.put;
	375	chan->dma.free = chan->dma.max - chan->dma.cur;
	376
	377	ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
	378	if (ret)
	379	return ret;
	380
	381	for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
	382	OUT_RING(chan, 0x00000000);
	383
69a6146d	384	/* allocate software object class (used for fences on <= nv05) */
967e7bde	385	if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
f58ddf95	386	ret = nvif_object_init(&chan->user, 0x006e,
08f7633c	387	NVIF_CLASS_SW_NV04,
0ad72863	388	NULL, 0, &chan->nvsw);
49981046 BS	389	if (ret)
49981046 BS	390	return ret;
ebb945a9	391
ebb945a9 BS	392	ret = RING_SPACE(chan, 2);
	393	if (ret)
	394	return ret;
	395
	396	BEGIN_NV04(chan, NvSubSw, 0x0000, 1);
f45f55c4	397	OUT_RING (chan, chan->nvsw.handle);
ebb945a9 BS	398	FIRE_RING (chan);
	399	}
	400
	401	/* initialise synchronisation */
4894f662	402	return nouveau_fence(chan->drm)->context_new(chan);
ebb945a9 BS	403	}
	404
	405	int
0ad72863	406	nouveau_channel_new(struct nouveau_drm drm, struct nvif_device device,
fcf3f91c	407	u32 arg0, u32 arg1, struct nouveau_channel **pchan)
ebb945a9	408	{
a01ca78c	409	struct nouveau_cli cli = (void )device->object.client;
67e26e41	410	bool super;
ebb945a9 BS	411	int ret;
ebb945a9 BS	412
67e26e41 BS	413	/* hack until fencenv50 is fixed, and agp access relaxed */
	414	super = cli->base.super;
	415	cli->base.super = true;
	416
fcf3f91c	417	ret = nouveau_channel_ind(drm, device, arg0, pchan);
ebb945a9	418	if (ret) {
9ad97ede	419	NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret);
fcf3f91c	420	ret = nouveau_channel_dma(drm, device, pchan);
ebb945a9	421	if (ret) {
9ad97ede	422	NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret);
67e26e41	423	goto done;
ebb945a9 BS	424	}
	425	}
	426
49981046	427	ret = nouveau_channel_init(*pchan, arg0, arg1);
ebb945a9	428	if (ret) {
9ad97ede	429	NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret);
ebb945a9	430	nouveau_channel_del(pchan);
ebb945a9 BS	431	}
ebb945a9 BS	432
67e26e41 BS	433	done:
	434	cli->base.super = super;
	435	return ret;
ebb945a9	436	}