Commit | Line | Data |
---|---|---|
94580299 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
77145f1c | 25 | #include <linux/console.h> |
94580299 BS |
26 | #include <linux/module.h> |
27 | #include <linux/pci.h> | |
28 | ||
29 | #include <core/device.h> | |
30 | #include <core/client.h> | |
ebb945a9 | 31 | #include <core/gpuobj.h> |
94580299 BS |
32 | #include <core/class.h> |
33 | ||
34 | #include <subdev/device.h> | |
ebb945a9 | 35 | #include <subdev/vm.h> |
94580299 | 36 | |
1d7c71a3 BS |
37 | #include <engine/disp.h> |
38 | ||
94580299 | 39 | #include "nouveau_drm.h" |
77145f1c | 40 | #include "nouveau_irq.h" |
ebb945a9 | 41 | #include "nouveau_dma.h" |
77145f1c BS |
42 | #include "nouveau_ttm.h" |
43 | #include "nouveau_gem.h" | |
cb75d97e | 44 | #include "nouveau_agp.h" |
77145f1c BS |
45 | #include "nouveau_vga.h" |
46 | #include "nouveau_pm.h" | |
47 | #include "nouveau_acpi.h" | |
48 | #include "nouveau_bios.h" | |
49 | #include "nouveau_ioctl.h" | |
ebb945a9 BS |
50 | #include "nouveau_abi16.h" |
51 | #include "nouveau_fbcon.h" | |
52 | #include "nouveau_fence.h" | |
33b903e8 | 53 | #include "nouveau_debugfs.h" |
ebb945a9 | 54 | |
94580299 BS |
55 | MODULE_PARM_DESC(config, "option string to pass to driver core"); |
56 | static char *nouveau_config; | |
57 | module_param_named(config, nouveau_config, charp, 0400); | |
58 | ||
59 | MODULE_PARM_DESC(debug, "debug string to pass to driver core"); | |
60 | static char *nouveau_debug; | |
61 | module_param_named(debug, nouveau_debug, charp, 0400); | |
62 | ||
ebb945a9 BS |
63 | MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration"); |
64 | static int nouveau_noaccel = 0; | |
65 | module_param_named(noaccel, nouveau_noaccel, int, 0400); | |
66 | ||
9430738d BS |
67 | MODULE_PARM_DESC(modeset, "enable driver (default: auto, " |
68 | "0 = disabled, 1 = enabled, 2 = headless)"); | |
69 | int nouveau_modeset = -1; | |
77145f1c BS |
70 | module_param_named(modeset, nouveau_modeset, int, 0400); |
71 | ||
72 | static struct drm_driver driver; | |
73 | ||
1d7c71a3 BS |
74 | static int |
75 | nouveau_drm_vblank_enable(struct drm_device *dev, int head) | |
76 | { | |
77 | struct nouveau_drm *drm = nouveau_drm(dev); | |
78 | struct nouveau_disp *pdisp = nouveau_disp(drm->device); | |
79 | nouveau_event_get(pdisp->vblank, head, &drm->vblank); | |
80 | return 0; | |
81 | } | |
82 | ||
83 | static void | |
84 | nouveau_drm_vblank_disable(struct drm_device *dev, int head) | |
85 | { | |
86 | struct nouveau_drm *drm = nouveau_drm(dev); | |
87 | struct nouveau_disp *pdisp = nouveau_disp(drm->device); | |
88 | nouveau_event_put(pdisp->vblank, head, &drm->vblank); | |
89 | } | |
90 | ||
91 | static int | |
92 | nouveau_drm_vblank_handler(struct nouveau_eventh *event, int head) | |
93 | { | |
94 | struct nouveau_drm *drm = | |
95 | container_of(event, struct nouveau_drm, vblank); | |
96 | drm_handle_vblank(drm->dev, head); | |
97 | return NVKM_EVENT_KEEP; | |
98 | } | |
99 | ||
94580299 BS |
100 | static u64 |
101 | nouveau_name(struct pci_dev *pdev) | |
102 | { | |
103 | u64 name = (u64)pci_domain_nr(pdev->bus) << 32; | |
104 | name |= pdev->bus->number << 16; | |
105 | name |= PCI_SLOT(pdev->devfn) << 8; | |
106 | return name | PCI_FUNC(pdev->devfn); | |
107 | } | |
108 | ||
109 | static int | |
fa6df8c1 BS |
110 | nouveau_cli_create(struct pci_dev *pdev, const char *name, |
111 | int size, void **pcli) | |
94580299 BS |
112 | { |
113 | struct nouveau_cli *cli; | |
114 | int ret; | |
115 | ||
dd5700ea | 116 | *pcli = NULL; |
94580299 BS |
117 | ret = nouveau_client_create_(name, nouveau_name(pdev), nouveau_config, |
118 | nouveau_debug, size, pcli); | |
119 | cli = *pcli; | |
dd5700ea MS |
120 | if (ret) { |
121 | if (cli) | |
122 | nouveau_client_destroy(&cli->base); | |
123 | *pcli = NULL; | |
94580299 | 124 | return ret; |
dd5700ea | 125 | } |
94580299 BS |
126 | |
127 | mutex_init(&cli->mutex); | |
128 | return 0; | |
129 | } | |
130 | ||
131 | static void | |
132 | nouveau_cli_destroy(struct nouveau_cli *cli) | |
133 | { | |
134 | struct nouveau_object *client = nv_object(cli); | |
ebb945a9 | 135 | nouveau_vm_ref(NULL, &cli->base.vm, NULL); |
94580299 BS |
136 | nouveau_client_fini(&cli->base, false); |
137 | atomic_set(&client->refcount, 1); | |
138 | nouveau_object_ref(NULL, &client); | |
139 | } | |
140 | ||
ebb945a9 BS |
141 | static void |
142 | nouveau_accel_fini(struct nouveau_drm *drm) | |
143 | { | |
144 | nouveau_gpuobj_ref(NULL, &drm->notify); | |
145 | nouveau_channel_del(&drm->channel); | |
49981046 | 146 | nouveau_channel_del(&drm->cechan); |
ebb945a9 BS |
147 | if (drm->fence) |
148 | nouveau_fence(drm)->dtor(drm); | |
149 | } | |
150 | ||
151 | static void | |
152 | nouveau_accel_init(struct nouveau_drm *drm) | |
153 | { | |
154 | struct nouveau_device *device = nv_device(drm->device); | |
155 | struct nouveau_object *object; | |
49981046 | 156 | u32 arg0, arg1; |
ebb945a9 BS |
157 | int ret; |
158 | ||
159 | if (nouveau_noaccel) | |
160 | return; | |
161 | ||
162 | /* initialise synchronisation routines */ | |
163 | if (device->card_type < NV_10) ret = nv04_fence_create(drm); | |
60e5cb79 BS |
164 | else if (device->chipset < 0x17) ret = nv10_fence_create(drm); |
165 | else if (device->card_type < NV_50) ret = nv17_fence_create(drm); | |
ace5a9b8 | 166 | else if (device->chipset < 0x84) ret = nv50_fence_create(drm); |
ebb945a9 BS |
167 | else if (device->card_type < NV_C0) ret = nv84_fence_create(drm); |
168 | else ret = nvc0_fence_create(drm); | |
169 | if (ret) { | |
170 | NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret); | |
171 | nouveau_accel_fini(drm); | |
172 | return; | |
173 | } | |
174 | ||
49981046 BS |
175 | if (device->card_type >= NV_E0) { |
176 | ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE, | |
177 | NVDRM_CHAN + 1, | |
178 | NVE0_CHANNEL_IND_ENGINE_CE0 | | |
179 | NVE0_CHANNEL_IND_ENGINE_CE1, 0, | |
180 | &drm->cechan); | |
181 | if (ret) | |
182 | NV_ERROR(drm, "failed to create ce channel, %d\n", ret); | |
183 | ||
184 | arg0 = NVE0_CHANNEL_IND_ENGINE_GR; | |
49469800 | 185 | arg1 = 1; |
49981046 BS |
186 | } else { |
187 | arg0 = NvDmaFB; | |
188 | arg1 = NvDmaTT; | |
189 | } | |
190 | ||
ebb945a9 | 191 | ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE, NVDRM_CHAN, |
49981046 | 192 | arg0, arg1, &drm->channel); |
ebb945a9 BS |
193 | if (ret) { |
194 | NV_ERROR(drm, "failed to create kernel channel, %d\n", ret); | |
195 | nouveau_accel_fini(drm); | |
196 | return; | |
197 | } | |
198 | ||
199 | if (device->card_type < NV_C0) { | |
200 | ret = nouveau_gpuobj_new(drm->device, NULL, 32, 0, 0, | |
201 | &drm->notify); | |
202 | if (ret) { | |
203 | NV_ERROR(drm, "failed to allocate notifier, %d\n", ret); | |
204 | nouveau_accel_fini(drm); | |
205 | return; | |
206 | } | |
207 | ||
208 | ret = nouveau_object_new(nv_object(drm), | |
209 | drm->channel->handle, NvNotify0, | |
210 | 0x003d, &(struct nv_dma_class) { | |
211 | .flags = NV_DMA_TARGET_VRAM | | |
212 | NV_DMA_ACCESS_RDWR, | |
213 | .start = drm->notify->addr, | |
214 | .limit = drm->notify->addr + 31 | |
215 | }, sizeof(struct nv_dma_class), | |
216 | &object); | |
217 | if (ret) { | |
218 | nouveau_accel_fini(drm); | |
219 | return; | |
220 | } | |
221 | } | |
222 | ||
223 | ||
49981046 | 224 | nouveau_bo_move_init(drm); |
ebb945a9 BS |
225 | } |
226 | ||
56550d94 GKH |
227 | static int nouveau_drm_probe(struct pci_dev *pdev, |
228 | const struct pci_device_id *pent) | |
94580299 BS |
229 | { |
230 | struct nouveau_device *device; | |
ebb945a9 BS |
231 | struct apertures_struct *aper; |
232 | bool boot = false; | |
94580299 BS |
233 | int ret; |
234 | ||
ebb945a9 BS |
235 | /* remove conflicting drivers (vesafb, efifb etc) */ |
236 | aper = alloc_apertures(3); | |
237 | if (!aper) | |
238 | return -ENOMEM; | |
239 | ||
240 | aper->ranges[0].base = pci_resource_start(pdev, 1); | |
241 | aper->ranges[0].size = pci_resource_len(pdev, 1); | |
242 | aper->count = 1; | |
243 | ||
244 | if (pci_resource_len(pdev, 2)) { | |
245 | aper->ranges[aper->count].base = pci_resource_start(pdev, 2); | |
246 | aper->ranges[aper->count].size = pci_resource_len(pdev, 2); | |
247 | aper->count++; | |
248 | } | |
249 | ||
250 | if (pci_resource_len(pdev, 3)) { | |
251 | aper->ranges[aper->count].base = pci_resource_start(pdev, 3); | |
252 | aper->ranges[aper->count].size = pci_resource_len(pdev, 3); | |
253 | aper->count++; | |
254 | } | |
255 | ||
256 | #ifdef CONFIG_X86 | |
257 | boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
258 | #endif | |
259 | remove_conflicting_framebuffers(aper, "nouveaufb", boot); | |
83ef7777 | 260 | kfree(aper); |
ebb945a9 | 261 | |
94580299 BS |
262 | ret = nouveau_device_create(pdev, nouveau_name(pdev), pci_name(pdev), |
263 | nouveau_config, nouveau_debug, &device); | |
264 | if (ret) | |
265 | return ret; | |
266 | ||
267 | pci_set_master(pdev); | |
268 | ||
77145f1c | 269 | ret = drm_get_pci_dev(pdev, pent, &driver); |
94580299 | 270 | if (ret) { |
ebb945a9 | 271 | nouveau_object_ref(NULL, (struct nouveau_object **)&device); |
94580299 BS |
272 | return ret; |
273 | } | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
5b8a43ae | 278 | static int |
94580299 BS |
279 | nouveau_drm_load(struct drm_device *dev, unsigned long flags) |
280 | { | |
281 | struct pci_dev *pdev = dev->pdev; | |
ebb945a9 | 282 | struct nouveau_device *device; |
94580299 BS |
283 | struct nouveau_drm *drm; |
284 | int ret; | |
285 | ||
fa6df8c1 | 286 | ret = nouveau_cli_create(pdev, "DRM", sizeof(*drm), (void**)&drm); |
94580299 BS |
287 | if (ret) |
288 | return ret; | |
289 | ||
77145f1c BS |
290 | dev->dev_private = drm; |
291 | drm->dev = dev; | |
1d7c71a3 | 292 | drm->vblank.func = nouveau_drm_vblank_handler; |
77145f1c | 293 | |
94580299 | 294 | INIT_LIST_HEAD(&drm->clients); |
ebb945a9 | 295 | spin_lock_init(&drm->tile.lock); |
94580299 | 296 | |
cb75d97e BS |
297 | /* make sure AGP controller is in a consistent state before we |
298 | * (possibly) execute vbios init tables (see nouveau_agp.h) | |
299 | */ | |
300 | if (drm_pci_device_is_agp(dev) && dev->agp) { | |
301 | /* dummy device object, doesn't init anything, but allows | |
302 | * agp code access to registers | |
303 | */ | |
304 | ret = nouveau_object_new(nv_object(drm), NVDRM_CLIENT, | |
305 | NVDRM_DEVICE, 0x0080, | |
306 | &(struct nv_device_class) { | |
307 | .device = ~0, | |
308 | .disable = | |
309 | ~(NV_DEVICE_DISABLE_MMIO | | |
310 | NV_DEVICE_DISABLE_IDENTIFY), | |
311 | .debug0 = ~0, | |
312 | }, sizeof(struct nv_device_class), | |
313 | &drm->device); | |
314 | if (ret) | |
ebb945a9 | 315 | goto fail_device; |
cb75d97e BS |
316 | |
317 | nouveau_agp_reset(drm); | |
318 | nouveau_object_del(nv_object(drm), NVDRM_CLIENT, NVDRM_DEVICE); | |
319 | } | |
320 | ||
94580299 BS |
321 | ret = nouveau_object_new(nv_object(drm), NVDRM_CLIENT, NVDRM_DEVICE, |
322 | 0x0080, &(struct nv_device_class) { | |
323 | .device = ~0, | |
324 | .disable = 0, | |
325 | .debug0 = 0, | |
326 | }, sizeof(struct nv_device_class), | |
327 | &drm->device); | |
328 | if (ret) | |
329 | goto fail_device; | |
330 | ||
77145f1c BS |
331 | /* workaround an odd issue on nvc1 by disabling the device's |
332 | * nosnoop capability. hopefully won't cause issues until a | |
333 | * better fix is found - assuming there is one... | |
334 | */ | |
ebb945a9 | 335 | device = nv_device(drm->device); |
77145f1c BS |
336 | if (nv_device(drm->device)->chipset == 0xc1) |
337 | nv_mask(device, 0x00088080, 0x00000800, 0x00000000); | |
ebb945a9 | 338 | |
77145f1c | 339 | nouveau_vga_init(drm); |
cb75d97e BS |
340 | nouveau_agp_init(drm); |
341 | ||
ebb945a9 BS |
342 | if (device->card_type >= NV_50) { |
343 | ret = nouveau_vm_new(nv_device(drm->device), 0, (1ULL << 40), | |
344 | 0x1000, &drm->client.base.vm); | |
345 | if (ret) | |
346 | goto fail_device; | |
347 | } | |
348 | ||
349 | ret = nouveau_ttm_init(drm); | |
94580299 | 350 | if (ret) |
77145f1c BS |
351 | goto fail_ttm; |
352 | ||
353 | ret = nouveau_bios_init(dev); | |
354 | if (ret) | |
355 | goto fail_bios; | |
356 | ||
357 | ret = nouveau_irq_init(dev); | |
358 | if (ret) | |
359 | goto fail_irq; | |
94580299 | 360 | |
77145f1c | 361 | ret = nouveau_display_create(dev); |
ebb945a9 | 362 | if (ret) |
77145f1c BS |
363 | goto fail_dispctor; |
364 | ||
365 | if (dev->mode_config.num_crtc) { | |
366 | ret = nouveau_display_init(dev); | |
367 | if (ret) | |
368 | goto fail_dispinit; | |
369 | } | |
370 | ||
371 | nouveau_pm_init(dev); | |
ebb945a9 BS |
372 | |
373 | nouveau_accel_init(drm); | |
374 | nouveau_fbcon_init(dev); | |
94580299 BS |
375 | return 0; |
376 | ||
77145f1c BS |
377 | fail_dispinit: |
378 | nouveau_display_destroy(dev); | |
379 | fail_dispctor: | |
380 | nouveau_irq_fini(dev); | |
381 | fail_irq: | |
382 | nouveau_bios_takedown(dev); | |
383 | fail_bios: | |
ebb945a9 | 384 | nouveau_ttm_fini(drm); |
77145f1c BS |
385 | fail_ttm: |
386 | nouveau_agp_fini(drm); | |
387 | nouveau_vga_fini(drm); | |
94580299 BS |
388 | fail_device: |
389 | nouveau_cli_destroy(&drm->client); | |
390 | return ret; | |
391 | } | |
392 | ||
5b8a43ae | 393 | static int |
94580299 BS |
394 | nouveau_drm_unload(struct drm_device *dev) |
395 | { | |
77145f1c | 396 | struct nouveau_drm *drm = nouveau_drm(dev); |
94580299 | 397 | |
ebb945a9 BS |
398 | nouveau_fbcon_fini(dev); |
399 | nouveau_accel_fini(drm); | |
400 | ||
77145f1c BS |
401 | nouveau_pm_fini(dev); |
402 | ||
9430738d BS |
403 | if (dev->mode_config.num_crtc) |
404 | nouveau_display_fini(dev); | |
77145f1c BS |
405 | nouveau_display_destroy(dev); |
406 | ||
407 | nouveau_irq_fini(dev); | |
408 | nouveau_bios_takedown(dev); | |
94580299 | 409 | |
ebb945a9 | 410 | nouveau_ttm_fini(drm); |
cb75d97e | 411 | nouveau_agp_fini(drm); |
77145f1c | 412 | nouveau_vga_fini(drm); |
cb75d97e | 413 | |
94580299 BS |
414 | nouveau_cli_destroy(&drm->client); |
415 | return 0; | |
416 | } | |
417 | ||
418 | static void | |
419 | nouveau_drm_remove(struct pci_dev *pdev) | |
420 | { | |
77145f1c BS |
421 | struct drm_device *dev = pci_get_drvdata(pdev); |
422 | struct nouveau_drm *drm = nouveau_drm(dev); | |
ebb945a9 | 423 | struct nouveau_object *device; |
77145f1c BS |
424 | |
425 | device = drm->client.base.device; | |
426 | drm_put_dev(dev); | |
427 | ||
ebb945a9 BS |
428 | nouveau_object_ref(NULL, &device); |
429 | nouveau_object_debug(); | |
94580299 BS |
430 | } |
431 | ||
cd897837 | 432 | static int |
2d8b9ccb | 433 | nouveau_do_suspend(struct drm_device *dev) |
94580299 | 434 | { |
77145f1c | 435 | struct nouveau_drm *drm = nouveau_drm(dev); |
94580299 BS |
436 | struct nouveau_cli *cli; |
437 | int ret; | |
438 | ||
9430738d BS |
439 | if (dev->mode_config.num_crtc) { |
440 | NV_INFO(drm, "suspending fbcon...\n"); | |
441 | nouveau_fbcon_set_suspend(dev, 1); | |
ebb945a9 | 442 | |
9430738d BS |
443 | NV_INFO(drm, "suspending display...\n"); |
444 | ret = nouveau_display_suspend(dev); | |
445 | if (ret) | |
446 | return ret; | |
447 | } | |
94580299 | 448 | |
ebb945a9 BS |
449 | NV_INFO(drm, "evicting buffers...\n"); |
450 | ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM); | |
451 | ||
452 | if (drm->fence && nouveau_fence(drm)->suspend) { | |
453 | if (!nouveau_fence(drm)->suspend(drm)) | |
454 | return -ENOMEM; | |
455 | } | |
456 | ||
457 | NV_INFO(drm, "suspending client object trees...\n"); | |
94580299 BS |
458 | list_for_each_entry(cli, &drm->clients, head) { |
459 | ret = nouveau_client_fini(&cli->base, true); | |
460 | if (ret) | |
461 | goto fail_client; | |
462 | } | |
463 | ||
464 | ret = nouveau_client_fini(&drm->client.base, true); | |
465 | if (ret) | |
466 | goto fail_client; | |
467 | ||
cb75d97e | 468 | nouveau_agp_fini(drm); |
94580299 BS |
469 | return 0; |
470 | ||
471 | fail_client: | |
472 | list_for_each_entry_continue_reverse(cli, &drm->clients, head) { | |
473 | nouveau_client_init(&cli->base); | |
474 | } | |
475 | ||
9430738d BS |
476 | if (dev->mode_config.num_crtc) { |
477 | NV_INFO(drm, "resuming display...\n"); | |
478 | nouveau_display_resume(dev); | |
479 | } | |
94580299 BS |
480 | return ret; |
481 | } | |
482 | ||
2d8b9ccb | 483 | int nouveau_pmops_suspend(struct device *dev) |
94580299 | 484 | { |
2d8b9ccb DA |
485 | struct pci_dev *pdev = to_pci_dev(dev); |
486 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
94580299 BS |
487 | int ret; |
488 | ||
2d8b9ccb | 489 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
94580299 BS |
490 | return 0; |
491 | ||
2d8b9ccb | 492 | ret = nouveau_do_suspend(drm_dev); |
94580299 BS |
493 | if (ret) |
494 | return ret; | |
2d8b9ccb DA |
495 | |
496 | pci_save_state(pdev); | |
497 | pci_disable_device(pdev); | |
498 | pci_set_power_state(pdev, PCI_D3hot); | |
499 | ||
500 | return 0; | |
501 | } | |
502 | ||
cd897837 | 503 | static int |
2d8b9ccb DA |
504 | nouveau_do_resume(struct drm_device *dev) |
505 | { | |
506 | struct nouveau_drm *drm = nouveau_drm(dev); | |
507 | struct nouveau_cli *cli; | |
508 | ||
509 | NV_INFO(drm, "re-enabling device...\n"); | |
94580299 | 510 | |
cb75d97e BS |
511 | nouveau_agp_reset(drm); |
512 | ||
ebb945a9 | 513 | NV_INFO(drm, "resuming client object trees...\n"); |
94580299 | 514 | nouveau_client_init(&drm->client.base); |
ebb945a9 | 515 | nouveau_agp_init(drm); |
94580299 BS |
516 | |
517 | list_for_each_entry(cli, &drm->clients, head) { | |
518 | nouveau_client_init(&cli->base); | |
519 | } | |
cb75d97e | 520 | |
ebb945a9 BS |
521 | if (drm->fence && nouveau_fence(drm)->resume) |
522 | nouveau_fence(drm)->resume(drm); | |
94580299 | 523 | |
77145f1c BS |
524 | nouveau_run_vbios_init(dev); |
525 | nouveau_irq_postinstall(dev); | |
526 | nouveau_pm_resume(dev); | |
527 | ||
9430738d BS |
528 | if (dev->mode_config.num_crtc) { |
529 | NV_INFO(drm, "resuming display...\n"); | |
530 | nouveau_display_resume(dev); | |
531 | } | |
77145f1c | 532 | return 0; |
94580299 BS |
533 | } |
534 | ||
2d8b9ccb DA |
535 | int nouveau_pmops_resume(struct device *dev) |
536 | { | |
537 | struct pci_dev *pdev = to_pci_dev(dev); | |
538 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
539 | int ret; | |
540 | ||
541 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
542 | return 0; | |
543 | ||
544 | pci_set_power_state(pdev, PCI_D0); | |
545 | pci_restore_state(pdev); | |
546 | ret = pci_enable_device(pdev); | |
547 | if (ret) | |
548 | return ret; | |
549 | pci_set_master(pdev); | |
550 | ||
551 | return nouveau_do_resume(drm_dev); | |
552 | } | |
553 | ||
554 | static int nouveau_pmops_freeze(struct device *dev) | |
555 | { | |
556 | struct pci_dev *pdev = to_pci_dev(dev); | |
557 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
558 | ||
559 | return nouveau_do_suspend(drm_dev); | |
560 | } | |
561 | ||
562 | static int nouveau_pmops_thaw(struct device *dev) | |
563 | { | |
564 | struct pci_dev *pdev = to_pci_dev(dev); | |
565 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
566 | ||
567 | return nouveau_do_resume(drm_dev); | |
568 | } | |
569 | ||
570 | ||
5b8a43ae | 571 | static int |
ebb945a9 BS |
572 | nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) |
573 | { | |
574 | struct pci_dev *pdev = dev->pdev; | |
575 | struct nouveau_drm *drm = nouveau_drm(dev); | |
576 | struct nouveau_cli *cli; | |
a2896ced | 577 | char name[32], tmpname[TASK_COMM_LEN]; |
ebb945a9 BS |
578 | int ret; |
579 | ||
a2896ced MS |
580 | get_task_comm(tmpname, current); |
581 | snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid)); | |
fa6df8c1 BS |
582 | |
583 | ret = nouveau_cli_create(pdev, name, sizeof(*cli), (void **)&cli); | |
ebb945a9 BS |
584 | if (ret) |
585 | return ret; | |
586 | ||
587 | if (nv_device(drm->device)->card_type >= NV_50) { | |
588 | ret = nouveau_vm_new(nv_device(drm->device), 0, (1ULL << 40), | |
589 | 0x1000, &cli->base.vm); | |
590 | if (ret) { | |
591 | nouveau_cli_destroy(cli); | |
592 | return ret; | |
593 | } | |
594 | } | |
595 | ||
596 | fpriv->driver_priv = cli; | |
597 | ||
598 | mutex_lock(&drm->client.mutex); | |
599 | list_add(&cli->head, &drm->clients); | |
600 | mutex_unlock(&drm->client.mutex); | |
601 | return 0; | |
602 | } | |
603 | ||
5b8a43ae | 604 | static void |
ebb945a9 BS |
605 | nouveau_drm_preclose(struct drm_device *dev, struct drm_file *fpriv) |
606 | { | |
607 | struct nouveau_cli *cli = nouveau_cli(fpriv); | |
608 | struct nouveau_drm *drm = nouveau_drm(dev); | |
609 | ||
610 | if (cli->abi16) | |
611 | nouveau_abi16_fini(cli->abi16); | |
612 | ||
613 | mutex_lock(&drm->client.mutex); | |
614 | list_del(&cli->head); | |
615 | mutex_unlock(&drm->client.mutex); | |
616 | } | |
617 | ||
5b8a43ae | 618 | static void |
ebb945a9 BS |
619 | nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv) |
620 | { | |
621 | struct nouveau_cli *cli = nouveau_cli(fpriv); | |
622 | nouveau_cli_destroy(cli); | |
623 | } | |
624 | ||
77145f1c BS |
625 | static struct drm_ioctl_desc |
626 | nouveau_ioctls[] = { | |
627 | DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH), | |
628 | DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
629 | DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH), | |
630 | DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH), | |
631 | DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH), | |
632 | DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH), | |
633 | DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH), | |
634 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH), | |
635 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH), | |
636 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH), | |
637 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH), | |
638 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH), | |
639 | }; | |
640 | ||
641 | static const struct file_operations | |
642 | nouveau_driver_fops = { | |
643 | .owner = THIS_MODULE, | |
644 | .open = drm_open, | |
645 | .release = drm_release, | |
646 | .unlocked_ioctl = drm_ioctl, | |
647 | .mmap = nouveau_ttm_mmap, | |
648 | .poll = drm_poll, | |
649 | .fasync = drm_fasync, | |
650 | .read = drm_read, | |
651 | #if defined(CONFIG_COMPAT) | |
652 | .compat_ioctl = nouveau_compat_ioctl, | |
653 | #endif | |
654 | .llseek = noop_llseek, | |
655 | }; | |
656 | ||
657 | static struct drm_driver | |
658 | driver = { | |
659 | .driver_features = | |
660 | DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG | | |
661 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | | |
662 | DRIVER_MODESET | DRIVER_PRIME, | |
663 | ||
664 | .load = nouveau_drm_load, | |
665 | .unload = nouveau_drm_unload, | |
666 | .open = nouveau_drm_open, | |
667 | .preclose = nouveau_drm_preclose, | |
668 | .postclose = nouveau_drm_postclose, | |
669 | .lastclose = nouveau_vga_lastclose, | |
670 | ||
33b903e8 MS |
671 | #if defined(CONFIG_DEBUG_FS) |
672 | .debugfs_init = nouveau_debugfs_init, | |
673 | .debugfs_cleanup = nouveau_debugfs_takedown, | |
674 | #endif | |
675 | ||
77145f1c BS |
676 | .irq_preinstall = nouveau_irq_preinstall, |
677 | .irq_postinstall = nouveau_irq_postinstall, | |
678 | .irq_uninstall = nouveau_irq_uninstall, | |
679 | .irq_handler = nouveau_irq_handler, | |
680 | ||
681 | .get_vblank_counter = drm_vblank_count, | |
1d7c71a3 BS |
682 | .enable_vblank = nouveau_drm_vblank_enable, |
683 | .disable_vblank = nouveau_drm_vblank_disable, | |
77145f1c BS |
684 | |
685 | .ioctls = nouveau_ioctls, | |
686 | .fops = &nouveau_driver_fops, | |
687 | ||
688 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
689 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
690 | .gem_prime_export = nouveau_gem_prime_export, | |
691 | .gem_prime_import = nouveau_gem_prime_import, | |
692 | ||
693 | .gem_init_object = nouveau_gem_object_new, | |
694 | .gem_free_object = nouveau_gem_object_del, | |
695 | .gem_open_object = nouveau_gem_object_open, | |
696 | .gem_close_object = nouveau_gem_object_close, | |
697 | ||
698 | .dumb_create = nouveau_display_dumb_create, | |
699 | .dumb_map_offset = nouveau_display_dumb_map_offset, | |
700 | .dumb_destroy = nouveau_display_dumb_destroy, | |
701 | ||
702 | .name = DRIVER_NAME, | |
703 | .desc = DRIVER_DESC, | |
704 | #ifdef GIT_REVISION | |
705 | .date = GIT_REVISION, | |
706 | #else | |
707 | .date = DRIVER_DATE, | |
708 | #endif | |
709 | .major = DRIVER_MAJOR, | |
710 | .minor = DRIVER_MINOR, | |
711 | .patchlevel = DRIVER_PATCHLEVEL, | |
712 | }; | |
713 | ||
94580299 BS |
714 | static struct pci_device_id |
715 | nouveau_drm_pci_table[] = { | |
716 | { | |
717 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), | |
718 | .class = PCI_BASE_CLASS_DISPLAY << 16, | |
719 | .class_mask = 0xff << 16, | |
720 | }, | |
721 | { | |
722 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID), | |
723 | .class = PCI_BASE_CLASS_DISPLAY << 16, | |
724 | .class_mask = 0xff << 16, | |
725 | }, | |
726 | {} | |
727 | }; | |
728 | ||
2d8b9ccb DA |
729 | static const struct dev_pm_ops nouveau_pm_ops = { |
730 | .suspend = nouveau_pmops_suspend, | |
731 | .resume = nouveau_pmops_resume, | |
732 | .freeze = nouveau_pmops_freeze, | |
733 | .thaw = nouveau_pmops_thaw, | |
734 | .poweroff = nouveau_pmops_freeze, | |
735 | .restore = nouveau_pmops_resume, | |
736 | }; | |
737 | ||
94580299 BS |
738 | static struct pci_driver |
739 | nouveau_drm_pci_driver = { | |
740 | .name = "nouveau", | |
741 | .id_table = nouveau_drm_pci_table, | |
742 | .probe = nouveau_drm_probe, | |
743 | .remove = nouveau_drm_remove, | |
2d8b9ccb | 744 | .driver.pm = &nouveau_pm_ops, |
94580299 BS |
745 | }; |
746 | ||
747 | static int __init | |
748 | nouveau_drm_init(void) | |
749 | { | |
77145f1c BS |
750 | driver.num_ioctls = ARRAY_SIZE(nouveau_ioctls); |
751 | ||
752 | if (nouveau_modeset == -1) { | |
753 | #ifdef CONFIG_VGA_CONSOLE | |
754 | if (vgacon_text_force()) | |
755 | nouveau_modeset = 0; | |
77145f1c | 756 | #endif |
77145f1c BS |
757 | } |
758 | ||
759 | if (!nouveau_modeset) | |
760 | return 0; | |
761 | ||
762 | nouveau_register_dsm_handler(); | |
763 | return drm_pci_init(&driver, &nouveau_drm_pci_driver); | |
94580299 BS |
764 | } |
765 | ||
766 | static void __exit | |
767 | nouveau_drm_exit(void) | |
768 | { | |
77145f1c BS |
769 | if (!nouveau_modeset) |
770 | return; | |
771 | ||
772 | drm_pci_exit(&driver, &nouveau_drm_pci_driver); | |
773 | nouveau_unregister_dsm_handler(); | |
94580299 BS |
774 | } |
775 | ||
776 | module_init(nouveau_drm_init); | |
777 | module_exit(nouveau_drm_exit); | |
778 | ||
779 | MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table); | |
77145f1c BS |
780 | MODULE_AUTHOR(DRIVER_AUTHOR); |
781 | MODULE_DESCRIPTION(DRIVER_DESC); | |
94580299 | 782 | MODULE_LICENSE("GPL and additional rights"); |