Commit | Line | Data |
---|---|---|
94580299 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
77145f1c | 25 | #include <linux/console.h> |
94580299 BS |
26 | #include <linux/module.h> |
27 | #include <linux/pci.h> | |
5addcf0a DA |
28 | #include <linux/pm_runtime.h> |
29 | #include <linux/vga_switcheroo.h> | |
fdb751ef | 30 | |
5addcf0a DA |
31 | #include "drmP.h" |
32 | #include "drm_crtc_helper.h" | |
fdb751ef | 33 | |
94580299 | 34 | #include <core/device.h> |
ebb945a9 | 35 | #include <core/gpuobj.h> |
c33e05a1 | 36 | #include <core/option.h> |
94580299 | 37 | |
94580299 | 38 | #include "nouveau_drm.h" |
ebb945a9 | 39 | #include "nouveau_dma.h" |
77145f1c BS |
40 | #include "nouveau_ttm.h" |
41 | #include "nouveau_gem.h" | |
cb75d97e | 42 | #include "nouveau_agp.h" |
77145f1c | 43 | #include "nouveau_vga.h" |
26fdd78c | 44 | #include "nouveau_sysfs.h" |
b9ed919f | 45 | #include "nouveau_hwmon.h" |
77145f1c BS |
46 | #include "nouveau_acpi.h" |
47 | #include "nouveau_bios.h" | |
48 | #include "nouveau_ioctl.h" | |
ebb945a9 BS |
49 | #include "nouveau_abi16.h" |
50 | #include "nouveau_fbcon.h" | |
51 | #include "nouveau_fence.h" | |
33b903e8 | 52 | #include "nouveau_debugfs.h" |
27111a23 | 53 | #include "nouveau_usif.h" |
703fa264 | 54 | #include "nouveau_connector.h" |
055a65d5 | 55 | #include "nouveau_platform.h" |
ebb945a9 | 56 | |
94580299 BS |
57 | MODULE_PARM_DESC(config, "option string to pass to driver core"); |
58 | static char *nouveau_config; | |
59 | module_param_named(config, nouveau_config, charp, 0400); | |
60 | ||
61 | MODULE_PARM_DESC(debug, "debug string to pass to driver core"); | |
62 | static char *nouveau_debug; | |
63 | module_param_named(debug, nouveau_debug, charp, 0400); | |
64 | ||
ebb945a9 BS |
65 | MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration"); |
66 | static int nouveau_noaccel = 0; | |
67 | module_param_named(noaccel, nouveau_noaccel, int, 0400); | |
68 | ||
9430738d BS |
69 | MODULE_PARM_DESC(modeset, "enable driver (default: auto, " |
70 | "0 = disabled, 1 = enabled, 2 = headless)"); | |
71 | int nouveau_modeset = -1; | |
77145f1c BS |
72 | module_param_named(modeset, nouveau_modeset, int, 0400); |
73 | ||
5addcf0a DA |
74 | MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)"); |
75 | int nouveau_runtime_pm = -1; | |
76 | module_param_named(runpm, nouveau_runtime_pm, int, 0400); | |
77 | ||
915b4d11 DH |
78 | static struct drm_driver driver_stub; |
79 | static struct drm_driver driver_pci; | |
80 | static struct drm_driver driver_platform; | |
77145f1c | 81 | |
94580299 | 82 | static u64 |
420b9469 | 83 | nouveau_pci_name(struct pci_dev *pdev) |
94580299 BS |
84 | { |
85 | u64 name = (u64)pci_domain_nr(pdev->bus) << 32; | |
86 | name |= pdev->bus->number << 16; | |
87 | name |= PCI_SLOT(pdev->devfn) << 8; | |
88 | return name | PCI_FUNC(pdev->devfn); | |
89 | } | |
90 | ||
420b9469 AC |
91 | static u64 |
92 | nouveau_platform_name(struct platform_device *platformdev) | |
93 | { | |
94 | return platformdev->id; | |
95 | } | |
96 | ||
97 | static u64 | |
98 | nouveau_name(struct drm_device *dev) | |
99 | { | |
100 | if (dev->pdev) | |
101 | return nouveau_pci_name(dev->pdev); | |
102 | else | |
103 | return nouveau_platform_name(dev->platformdev); | |
104 | } | |
105 | ||
94580299 | 106 | static int |
420b9469 | 107 | nouveau_cli_create(u64 name, const char *sname, |
fa6df8c1 | 108 | int size, void **pcli) |
94580299 | 109 | { |
0ad72863 BS |
110 | struct nouveau_cli *cli = *pcli = kzalloc(size, GFP_KERNEL); |
111 | if (cli) { | |
112 | int ret = nvif_client_init(NULL, NULL, sname, name, | |
113 | nouveau_config, nouveau_debug, | |
114 | &cli->base); | |
27111a23 | 115 | if (ret == 0) { |
0ad72863 | 116 | mutex_init(&cli->mutex); |
27111a23 BS |
117 | usif_client_init(cli); |
118 | } | |
94580299 | 119 | return ret; |
dd5700ea | 120 | } |
0ad72863 | 121 | return -ENOMEM; |
94580299 BS |
122 | } |
123 | ||
124 | static void | |
125 | nouveau_cli_destroy(struct nouveau_cli *cli) | |
126 | { | |
be83cd4e | 127 | nvkm_vm_ref(NULL, &nvxx_client(&cli->base)->vm, NULL); |
0ad72863 | 128 | nvif_client_fini(&cli->base); |
27111a23 | 129 | usif_client_fini(cli); |
94580299 BS |
130 | } |
131 | ||
ebb945a9 BS |
132 | static void |
133 | nouveau_accel_fini(struct nouveau_drm *drm) | |
134 | { | |
ebb945a9 | 135 | nouveau_channel_del(&drm->channel); |
0ad72863 | 136 | nvif_object_fini(&drm->ntfy); |
be83cd4e | 137 | nvkm_gpuobj_ref(NULL, &drm->notify); |
0ad72863 | 138 | nvif_object_fini(&drm->nvsw); |
49981046 | 139 | nouveau_channel_del(&drm->cechan); |
0ad72863 | 140 | nvif_object_fini(&drm->ttm.copy); |
ebb945a9 BS |
141 | if (drm->fence) |
142 | nouveau_fence(drm)->dtor(drm); | |
143 | } | |
144 | ||
145 | static void | |
146 | nouveau_accel_init(struct nouveau_drm *drm) | |
147 | { | |
967e7bde | 148 | struct nvif_device *device = &drm->device; |
49981046 | 149 | u32 arg0, arg1; |
967e7bde BS |
150 | u32 sclass[16]; |
151 | int ret, i; | |
ebb945a9 | 152 | |
967e7bde | 153 | if (nouveau_noaccel) |
ebb945a9 BS |
154 | return; |
155 | ||
156 | /* initialise synchronisation routines */ | |
967e7bde BS |
157 | /*XXX: this is crap, but the fence/channel stuff is a little |
158 | * backwards in some places. this will be fixed. | |
159 | */ | |
0ad72863 | 160 | ret = nvif_object_sclass(&device->base, sclass, ARRAY_SIZE(sclass)); |
967e7bde BS |
161 | if (ret < 0) |
162 | return; | |
163 | ||
164 | for (ret = -ENOSYS, i = 0; ret && i < ARRAY_SIZE(sclass); i++) { | |
165 | switch (sclass[i]) { | |
bbf8906b | 166 | case NV03_CHANNEL_DMA: |
967e7bde BS |
167 | ret = nv04_fence_create(drm); |
168 | break; | |
bbf8906b | 169 | case NV10_CHANNEL_DMA: |
967e7bde BS |
170 | ret = nv10_fence_create(drm); |
171 | break; | |
bbf8906b BS |
172 | case NV17_CHANNEL_DMA: |
173 | case NV40_CHANNEL_DMA: | |
967e7bde BS |
174 | ret = nv17_fence_create(drm); |
175 | break; | |
bbf8906b | 176 | case NV50_CHANNEL_GPFIFO: |
967e7bde BS |
177 | ret = nv50_fence_create(drm); |
178 | break; | |
bbf8906b | 179 | case G82_CHANNEL_GPFIFO: |
967e7bde BS |
180 | ret = nv84_fence_create(drm); |
181 | break; | |
bbf8906b BS |
182 | case FERMI_CHANNEL_GPFIFO: |
183 | case KEPLER_CHANNEL_GPFIFO_A: | |
a1020afe | 184 | case MAXWELL_CHANNEL_GPFIFO_A: |
967e7bde BS |
185 | ret = nvc0_fence_create(drm); |
186 | break; | |
187 | default: | |
188 | break; | |
189 | } | |
190 | } | |
191 | ||
ebb945a9 BS |
192 | if (ret) { |
193 | NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret); | |
194 | nouveau_accel_fini(drm); | |
195 | return; | |
196 | } | |
197 | ||
967e7bde | 198 | if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { |
0ad72863 | 199 | ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1, |
bbf8906b BS |
200 | KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0| |
201 | KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1, | |
202 | 0, &drm->cechan); | |
49981046 BS |
203 | if (ret) |
204 | NV_ERROR(drm, "failed to create ce channel, %d\n", ret); | |
205 | ||
bbf8906b | 206 | arg0 = KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR; |
49469800 | 207 | arg1 = 1; |
00fc6f6f | 208 | } else |
967e7bde BS |
209 | if (device->info.chipset >= 0xa3 && |
210 | device->info.chipset != 0xaa && | |
211 | device->info.chipset != 0xac) { | |
0ad72863 BS |
212 | ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1, |
213 | NvDmaFB, NvDmaTT, &drm->cechan); | |
00fc6f6f BS |
214 | if (ret) |
215 | NV_ERROR(drm, "failed to create ce channel, %d\n", ret); | |
216 | ||
217 | arg0 = NvDmaFB; | |
218 | arg1 = NvDmaTT; | |
49981046 BS |
219 | } else { |
220 | arg0 = NvDmaFB; | |
221 | arg1 = NvDmaTT; | |
222 | } | |
223 | ||
0ad72863 BS |
224 | ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN, arg0, arg1, |
225 | &drm->channel); | |
ebb945a9 BS |
226 | if (ret) { |
227 | NV_ERROR(drm, "failed to create kernel channel, %d\n", ret); | |
228 | nouveau_accel_fini(drm); | |
229 | return; | |
230 | } | |
231 | ||
0ad72863 BS |
232 | ret = nvif_object_init(drm->channel->object, NULL, NVDRM_NVSW, |
233 | nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw); | |
69a6146d | 234 | if (ret == 0) { |
be83cd4e | 235 | struct nvkm_sw_chan *swch; |
69a6146d BS |
236 | ret = RING_SPACE(drm->channel, 2); |
237 | if (ret == 0) { | |
967e7bde | 238 | if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { |
69a6146d BS |
239 | BEGIN_NV04(drm->channel, NvSubSw, 0, 1); |
240 | OUT_RING (drm->channel, NVDRM_NVSW); | |
241 | } else | |
967e7bde | 242 | if (device->info.family < NV_DEVICE_INFO_V0_KEPLER) { |
69a6146d BS |
243 | BEGIN_NVC0(drm->channel, FermiSw, 0, 1); |
244 | OUT_RING (drm->channel, 0x001f0000); | |
245 | } | |
246 | } | |
989aa5b7 | 247 | swch = (void *)nvxx_object(&drm->nvsw)->parent; |
69a6146d BS |
248 | swch->flip = nouveau_flip_complete; |
249 | swch->flip_data = drm->channel; | |
250 | } | |
251 | ||
252 | if (ret) { | |
253 | NV_ERROR(drm, "failed to allocate software object, %d\n", ret); | |
254 | nouveau_accel_fini(drm); | |
255 | return; | |
256 | } | |
257 | ||
967e7bde | 258 | if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { |
be83cd4e BS |
259 | ret = nvkm_gpuobj_new(nvxx_object(&drm->device), NULL, 32, |
260 | 0, 0, &drm->notify); | |
ebb945a9 BS |
261 | if (ret) { |
262 | NV_ERROR(drm, "failed to allocate notifier, %d\n", ret); | |
263 | nouveau_accel_fini(drm); | |
264 | return; | |
265 | } | |
266 | ||
0ad72863 | 267 | ret = nvif_object_init(drm->channel->object, NULL, NvNotify0, |
4acfd707 BS |
268 | NV_DMA_IN_MEMORY, |
269 | &(struct nv_dma_v0) { | |
270 | .target = NV_DMA_V0_TARGET_VRAM, | |
271 | .access = NV_DMA_V0_ACCESS_RDWR, | |
ebb945a9 BS |
272 | .start = drm->notify->addr, |
273 | .limit = drm->notify->addr + 31 | |
4acfd707 | 274 | }, sizeof(struct nv_dma_v0), |
0ad72863 | 275 | &drm->ntfy); |
ebb945a9 BS |
276 | if (ret) { |
277 | nouveau_accel_fini(drm); | |
278 | return; | |
279 | } | |
280 | } | |
281 | ||
282 | ||
49981046 | 283 | nouveau_bo_move_init(drm); |
ebb945a9 BS |
284 | } |
285 | ||
56550d94 GKH |
286 | static int nouveau_drm_probe(struct pci_dev *pdev, |
287 | const struct pci_device_id *pent) | |
94580299 | 288 | { |
be83cd4e | 289 | struct nvkm_device *device; |
ebb945a9 BS |
290 | struct apertures_struct *aper; |
291 | bool boot = false; | |
94580299 BS |
292 | int ret; |
293 | ||
ebb945a9 BS |
294 | /* remove conflicting drivers (vesafb, efifb etc) */ |
295 | aper = alloc_apertures(3); | |
296 | if (!aper) | |
297 | return -ENOMEM; | |
298 | ||
299 | aper->ranges[0].base = pci_resource_start(pdev, 1); | |
300 | aper->ranges[0].size = pci_resource_len(pdev, 1); | |
301 | aper->count = 1; | |
302 | ||
303 | if (pci_resource_len(pdev, 2)) { | |
304 | aper->ranges[aper->count].base = pci_resource_start(pdev, 2); | |
305 | aper->ranges[aper->count].size = pci_resource_len(pdev, 2); | |
306 | aper->count++; | |
307 | } | |
308 | ||
309 | if (pci_resource_len(pdev, 3)) { | |
310 | aper->ranges[aper->count].base = pci_resource_start(pdev, 3); | |
311 | aper->ranges[aper->count].size = pci_resource_len(pdev, 3); | |
312 | aper->count++; | |
313 | } | |
314 | ||
315 | #ifdef CONFIG_X86 | |
316 | boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
317 | #endif | |
771fa0e4 BS |
318 | if (nouveau_modeset != 2) |
319 | remove_conflicting_framebuffers(aper, "nouveaufb", boot); | |
83ef7777 | 320 | kfree(aper); |
ebb945a9 | 321 | |
be83cd4e BS |
322 | ret = nvkm_device_create(pdev, NVKM_BUS_PCI, |
323 | nouveau_pci_name(pdev), pci_name(pdev), | |
324 | nouveau_config, nouveau_debug, &device); | |
94580299 BS |
325 | if (ret) |
326 | return ret; | |
327 | ||
328 | pci_set_master(pdev); | |
329 | ||
915b4d11 | 330 | ret = drm_get_pci_dev(pdev, pent, &driver_pci); |
94580299 | 331 | if (ret) { |
be83cd4e | 332 | nvkm_object_ref(NULL, (struct nvkm_object **)&device); |
94580299 BS |
333 | return ret; |
334 | } | |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
5addcf0a DA |
339 | #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 |
340 | ||
341 | static void | |
46941b0f | 342 | nouveau_get_hdmi_dev(struct nouveau_drm *drm) |
5addcf0a | 343 | { |
46941b0f | 344 | struct pci_dev *pdev = drm->dev->pdev; |
5addcf0a | 345 | |
420b9469 | 346 | if (!pdev) { |
40189b0c | 347 | DRM_INFO("not a PCI device; no HDMI\n"); |
420b9469 AC |
348 | drm->hdmi_device = NULL; |
349 | return; | |
350 | } | |
351 | ||
5addcf0a DA |
352 | /* subfunction one is a hdmi audio device? */ |
353 | drm->hdmi_device = pci_get_bus_and_slot((unsigned int)pdev->bus->number, | |
354 | PCI_DEVFN(PCI_SLOT(pdev->devfn), 1)); | |
355 | ||
356 | if (!drm->hdmi_device) { | |
46941b0f | 357 | NV_DEBUG(drm, "hdmi device not found %d %d %d\n", pdev->bus->number, PCI_SLOT(pdev->devfn), 1); |
5addcf0a DA |
358 | return; |
359 | } | |
360 | ||
361 | if ((drm->hdmi_device->class >> 8) != PCI_CLASS_MULTIMEDIA_HD_AUDIO) { | |
46941b0f | 362 | NV_DEBUG(drm, "possible hdmi device not audio %d\n", drm->hdmi_device->class); |
5addcf0a DA |
363 | pci_dev_put(drm->hdmi_device); |
364 | drm->hdmi_device = NULL; | |
365 | return; | |
366 | } | |
367 | } | |
368 | ||
5b8a43ae | 369 | static int |
94580299 BS |
370 | nouveau_drm_load(struct drm_device *dev, unsigned long flags) |
371 | { | |
372 | struct pci_dev *pdev = dev->pdev; | |
373 | struct nouveau_drm *drm; | |
374 | int ret; | |
375 | ||
420b9469 AC |
376 | ret = nouveau_cli_create(nouveau_name(dev), "DRM", sizeof(*drm), |
377 | (void **)&drm); | |
94580299 BS |
378 | if (ret) |
379 | return ret; | |
380 | ||
77145f1c BS |
381 | dev->dev_private = drm; |
382 | drm->dev = dev; | |
989aa5b7 | 383 | nvxx_client(&drm->client.base)->debug = |
be83cd4e | 384 | nvkm_dbgopt(nouveau_debug, "DRM"); |
77145f1c | 385 | |
94580299 | 386 | INIT_LIST_HEAD(&drm->clients); |
ebb945a9 | 387 | spin_lock_init(&drm->tile.lock); |
94580299 | 388 | |
46941b0f | 389 | nouveau_get_hdmi_dev(drm); |
5addcf0a | 390 | |
cb75d97e BS |
391 | /* make sure AGP controller is in a consistent state before we |
392 | * (possibly) execute vbios init tables (see nouveau_agp.h) | |
393 | */ | |
420b9469 | 394 | if (pdev && drm_pci_device_is_agp(dev) && dev->agp) { |
586491e6 BS |
395 | const u64 enables = NV_DEVICE_V0_DISABLE_IDENTIFY | |
396 | NV_DEVICE_V0_DISABLE_MMIO; | |
cb75d97e BS |
397 | /* dummy device object, doesn't init anything, but allows |
398 | * agp code access to registers | |
399 | */ | |
0ad72863 | 400 | ret = nvif_device_init(&drm->client.base.base, NULL, |
586491e6 BS |
401 | NVDRM_DEVICE, NV_DEVICE, |
402 | &(struct nv_device_v0) { | |
cb75d97e | 403 | .device = ~0, |
586491e6 | 404 | .disable = ~enables, |
cb75d97e | 405 | .debug0 = ~0, |
586491e6 | 406 | }, sizeof(struct nv_device_v0), |
0ad72863 | 407 | &drm->device); |
cb75d97e | 408 | if (ret) |
ebb945a9 | 409 | goto fail_device; |
cb75d97e BS |
410 | |
411 | nouveau_agp_reset(drm); | |
0ad72863 | 412 | nvif_device_fini(&drm->device); |
cb75d97e BS |
413 | } |
414 | ||
0ad72863 | 415 | ret = nvif_device_init(&drm->client.base.base, NULL, NVDRM_DEVICE, |
586491e6 BS |
416 | NV_DEVICE, |
417 | &(struct nv_device_v0) { | |
94580299 BS |
418 | .device = ~0, |
419 | .disable = 0, | |
420 | .debug0 = 0, | |
586491e6 | 421 | }, sizeof(struct nv_device_v0), |
0ad72863 | 422 | &drm->device); |
94580299 BS |
423 | if (ret) |
424 | goto fail_device; | |
425 | ||
7d3428cd IM |
426 | dev->irq_enabled = true; |
427 | ||
77145f1c BS |
428 | /* workaround an odd issue on nvc1 by disabling the device's |
429 | * nosnoop capability. hopefully won't cause issues until a | |
430 | * better fix is found - assuming there is one... | |
431 | */ | |
967e7bde BS |
432 | if (drm->device.info.chipset == 0xc1) |
433 | nvif_mask(&drm->device, 0x00088080, 0x00000800, 0x00000000); | |
ebb945a9 | 434 | |
77145f1c | 435 | nouveau_vga_init(drm); |
cb75d97e BS |
436 | nouveau_agp_init(drm); |
437 | ||
967e7bde | 438 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { |
be83cd4e BS |
439 | ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40), |
440 | 0x1000, &drm->client.vm); | |
ebb945a9 BS |
441 | if (ret) |
442 | goto fail_device; | |
3ee6f5b5 | 443 | |
989aa5b7 | 444 | nvxx_client(&drm->client.base)->vm = drm->client.vm; |
ebb945a9 BS |
445 | } |
446 | ||
447 | ret = nouveau_ttm_init(drm); | |
94580299 | 448 | if (ret) |
77145f1c BS |
449 | goto fail_ttm; |
450 | ||
451 | ret = nouveau_bios_init(dev); | |
452 | if (ret) | |
453 | goto fail_bios; | |
454 | ||
77145f1c | 455 | ret = nouveau_display_create(dev); |
ebb945a9 | 456 | if (ret) |
77145f1c BS |
457 | goto fail_dispctor; |
458 | ||
459 | if (dev->mode_config.num_crtc) { | |
460 | ret = nouveau_display_init(dev); | |
461 | if (ret) | |
462 | goto fail_dispinit; | |
463 | } | |
464 | ||
26fdd78c | 465 | nouveau_sysfs_init(dev); |
b9ed919f | 466 | nouveau_hwmon_init(dev); |
ebb945a9 BS |
467 | nouveau_accel_init(drm); |
468 | nouveau_fbcon_init(dev); | |
5addcf0a DA |
469 | |
470 | if (nouveau_runtime_pm != 0) { | |
471 | pm_runtime_use_autosuspend(dev->dev); | |
472 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); | |
473 | pm_runtime_set_active(dev->dev); | |
474 | pm_runtime_allow(dev->dev); | |
475 | pm_runtime_mark_last_busy(dev->dev); | |
476 | pm_runtime_put(dev->dev); | |
477 | } | |
94580299 BS |
478 | return 0; |
479 | ||
77145f1c BS |
480 | fail_dispinit: |
481 | nouveau_display_destroy(dev); | |
482 | fail_dispctor: | |
77145f1c BS |
483 | nouveau_bios_takedown(dev); |
484 | fail_bios: | |
ebb945a9 | 485 | nouveau_ttm_fini(drm); |
77145f1c BS |
486 | fail_ttm: |
487 | nouveau_agp_fini(drm); | |
488 | nouveau_vga_fini(drm); | |
94580299 | 489 | fail_device: |
0ad72863 | 490 | nvif_device_fini(&drm->device); |
94580299 BS |
491 | nouveau_cli_destroy(&drm->client); |
492 | return ret; | |
493 | } | |
494 | ||
5b8a43ae | 495 | static int |
94580299 BS |
496 | nouveau_drm_unload(struct drm_device *dev) |
497 | { | |
77145f1c | 498 | struct nouveau_drm *drm = nouveau_drm(dev); |
94580299 | 499 | |
5addcf0a | 500 | pm_runtime_get_sync(dev->dev); |
ebb945a9 BS |
501 | nouveau_fbcon_fini(dev); |
502 | nouveau_accel_fini(drm); | |
b9ed919f | 503 | nouveau_hwmon_fini(dev); |
26fdd78c | 504 | nouveau_sysfs_fini(dev); |
77145f1c | 505 | |
9430738d BS |
506 | if (dev->mode_config.num_crtc) |
507 | nouveau_display_fini(dev); | |
77145f1c BS |
508 | nouveau_display_destroy(dev); |
509 | ||
77145f1c | 510 | nouveau_bios_takedown(dev); |
94580299 | 511 | |
ebb945a9 | 512 | nouveau_ttm_fini(drm); |
cb75d97e | 513 | nouveau_agp_fini(drm); |
77145f1c | 514 | nouveau_vga_fini(drm); |
cb75d97e | 515 | |
0ad72863 | 516 | nvif_device_fini(&drm->device); |
5addcf0a DA |
517 | if (drm->hdmi_device) |
518 | pci_dev_put(drm->hdmi_device); | |
94580299 BS |
519 | nouveau_cli_destroy(&drm->client); |
520 | return 0; | |
521 | } | |
522 | ||
8ba9ff11 AC |
523 | void |
524 | nouveau_drm_device_remove(struct drm_device *dev) | |
94580299 | 525 | { |
77145f1c | 526 | struct nouveau_drm *drm = nouveau_drm(dev); |
be83cd4e BS |
527 | struct nvkm_client *client; |
528 | struct nvkm_object *device; | |
77145f1c | 529 | |
7d3428cd | 530 | dev->irq_enabled = false; |
989aa5b7 | 531 | client = nvxx_client(&drm->client.base); |
0ad72863 | 532 | device = client->device; |
77145f1c BS |
533 | drm_put_dev(dev); |
534 | ||
be83cd4e BS |
535 | nvkm_object_ref(NULL, &device); |
536 | nvkm_object_debug(); | |
94580299 | 537 | } |
8ba9ff11 AC |
538 | |
539 | static void | |
540 | nouveau_drm_remove(struct pci_dev *pdev) | |
541 | { | |
542 | struct drm_device *dev = pci_get_drvdata(pdev); | |
543 | ||
544 | nouveau_drm_device_remove(dev); | |
545 | } | |
94580299 | 546 | |
cd897837 | 547 | static int |
05c63c2f | 548 | nouveau_do_suspend(struct drm_device *dev, bool runtime) |
94580299 | 549 | { |
77145f1c | 550 | struct nouveau_drm *drm = nouveau_drm(dev); |
94580299 BS |
551 | struct nouveau_cli *cli; |
552 | int ret; | |
553 | ||
6fbb702e BS |
554 | if (dev->mode_config.num_crtc) { |
555 | NV_INFO(drm, "suspending console...\n"); | |
556 | nouveau_fbcon_set_suspend(dev, 1); | |
c52f4fa6 | 557 | NV_INFO(drm, "suspending display...\n"); |
6fbb702e | 558 | ret = nouveau_display_suspend(dev, runtime); |
9430738d BS |
559 | if (ret) |
560 | return ret; | |
561 | } | |
94580299 | 562 | |
c52f4fa6 | 563 | NV_INFO(drm, "evicting buffers...\n"); |
ebb945a9 BS |
564 | ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM); |
565 | ||
c52f4fa6 | 566 | NV_INFO(drm, "waiting for kernel channels to go idle...\n"); |
81dff21b BS |
567 | if (drm->cechan) { |
568 | ret = nouveau_channel_idle(drm->cechan); | |
569 | if (ret) | |
f3980dc5 | 570 | goto fail_display; |
81dff21b BS |
571 | } |
572 | ||
573 | if (drm->channel) { | |
574 | ret = nouveau_channel_idle(drm->channel); | |
575 | if (ret) | |
f3980dc5 | 576 | goto fail_display; |
81dff21b BS |
577 | } |
578 | ||
c52f4fa6 | 579 | NV_INFO(drm, "suspending client object trees...\n"); |
ebb945a9 | 580 | if (drm->fence && nouveau_fence(drm)->suspend) { |
f3980dc5 IM |
581 | if (!nouveau_fence(drm)->suspend(drm)) { |
582 | ret = -ENOMEM; | |
583 | goto fail_display; | |
584 | } | |
ebb945a9 BS |
585 | } |
586 | ||
94580299 | 587 | list_for_each_entry(cli, &drm->clients, head) { |
0ad72863 | 588 | ret = nvif_client_suspend(&cli->base); |
94580299 BS |
589 | if (ret) |
590 | goto fail_client; | |
591 | } | |
592 | ||
c52f4fa6 | 593 | NV_INFO(drm, "suspending kernel object tree...\n"); |
0ad72863 | 594 | ret = nvif_client_suspend(&drm->client.base); |
94580299 BS |
595 | if (ret) |
596 | goto fail_client; | |
597 | ||
cb75d97e | 598 | nouveau_agp_fini(drm); |
94580299 BS |
599 | return 0; |
600 | ||
601 | fail_client: | |
602 | list_for_each_entry_continue_reverse(cli, &drm->clients, head) { | |
0ad72863 | 603 | nvif_client_resume(&cli->base); |
94580299 BS |
604 | } |
605 | ||
f3980dc5 IM |
606 | if (drm->fence && nouveau_fence(drm)->resume) |
607 | nouveau_fence(drm)->resume(drm); | |
608 | ||
609 | fail_display: | |
9430738d | 610 | if (dev->mode_config.num_crtc) { |
c52f4fa6 | 611 | NV_INFO(drm, "resuming display...\n"); |
6fbb702e | 612 | nouveau_display_resume(dev, runtime); |
9430738d | 613 | } |
94580299 BS |
614 | return ret; |
615 | } | |
616 | ||
cd897837 | 617 | static int |
6fbb702e | 618 | nouveau_do_resume(struct drm_device *dev, bool runtime) |
2d8b9ccb DA |
619 | { |
620 | struct nouveau_drm *drm = nouveau_drm(dev); | |
621 | struct nouveau_cli *cli; | |
622 | ||
c52f4fa6 | 623 | NV_INFO(drm, "re-enabling device...\n"); |
94580299 | 624 | |
cb75d97e BS |
625 | nouveau_agp_reset(drm); |
626 | ||
c52f4fa6 | 627 | NV_INFO(drm, "resuming kernel object tree...\n"); |
0ad72863 | 628 | nvif_client_resume(&drm->client.base); |
ebb945a9 | 629 | nouveau_agp_init(drm); |
94580299 | 630 | |
c52f4fa6 | 631 | NV_INFO(drm, "resuming client object trees...\n"); |
81dff21b BS |
632 | if (drm->fence && nouveau_fence(drm)->resume) |
633 | nouveau_fence(drm)->resume(drm); | |
634 | ||
94580299 | 635 | list_for_each_entry(cli, &drm->clients, head) { |
0ad72863 | 636 | nvif_client_resume(&cli->base); |
94580299 | 637 | } |
cb75d97e | 638 | |
77145f1c | 639 | nouveau_run_vbios_init(dev); |
77145f1c | 640 | |
9430738d | 641 | if (dev->mode_config.num_crtc) { |
c52f4fa6 | 642 | NV_INFO(drm, "resuming display...\n"); |
6fbb702e BS |
643 | nouveau_display_resume(dev, runtime); |
644 | NV_INFO(drm, "resuming console...\n"); | |
645 | nouveau_fbcon_set_suspend(dev, 0); | |
9430738d | 646 | } |
5addcf0a | 647 | |
77145f1c | 648 | return 0; |
94580299 BS |
649 | } |
650 | ||
7bb6d442 BS |
651 | int |
652 | nouveau_pmops_suspend(struct device *dev) | |
653 | { | |
654 | struct pci_dev *pdev = to_pci_dev(dev); | |
655 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
656 | int ret; | |
657 | ||
658 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || | |
659 | drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) | |
660 | return 0; | |
661 | ||
662 | ret = nouveau_do_suspend(drm_dev, false); | |
663 | if (ret) | |
664 | return ret; | |
665 | ||
666 | pci_save_state(pdev); | |
667 | pci_disable_device(pdev); | |
7bb6d442 BS |
668 | pci_set_power_state(pdev, PCI_D3hot); |
669 | return 0; | |
670 | } | |
671 | ||
672 | int | |
673 | nouveau_pmops_resume(struct device *dev) | |
2d8b9ccb DA |
674 | { |
675 | struct pci_dev *pdev = to_pci_dev(dev); | |
676 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
677 | int ret; | |
678 | ||
5addcf0a DA |
679 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || |
680 | drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) | |
2d8b9ccb DA |
681 | return 0; |
682 | ||
683 | pci_set_power_state(pdev, PCI_D0); | |
684 | pci_restore_state(pdev); | |
685 | ret = pci_enable_device(pdev); | |
686 | if (ret) | |
687 | return ret; | |
688 | pci_set_master(pdev); | |
689 | ||
6fbb702e | 690 | return nouveau_do_resume(drm_dev, false); |
2d8b9ccb DA |
691 | } |
692 | ||
7bb6d442 BS |
693 | static int |
694 | nouveau_pmops_freeze(struct device *dev) | |
2d8b9ccb DA |
695 | { |
696 | struct pci_dev *pdev = to_pci_dev(dev); | |
697 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
6fbb702e | 698 | return nouveau_do_suspend(drm_dev, false); |
2d8b9ccb DA |
699 | } |
700 | ||
7bb6d442 BS |
701 | static int |
702 | nouveau_pmops_thaw(struct device *dev) | |
2d8b9ccb DA |
703 | { |
704 | struct pci_dev *pdev = to_pci_dev(dev); | |
705 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
6fbb702e | 706 | return nouveau_do_resume(drm_dev, false); |
2d8b9ccb DA |
707 | } |
708 | ||
7bb6d442 BS |
709 | static int |
710 | nouveau_pmops_runtime_suspend(struct device *dev) | |
711 | { | |
712 | struct pci_dev *pdev = to_pci_dev(dev); | |
713 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
714 | int ret; | |
715 | ||
716 | if (nouveau_runtime_pm == 0) { | |
717 | pm_runtime_forbid(dev); | |
718 | return -EBUSY; | |
719 | } | |
720 | ||
721 | /* are we optimus enabled? */ | |
722 | if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) { | |
723 | DRM_DEBUG_DRIVER("failing to power off - not optimus\n"); | |
724 | pm_runtime_forbid(dev); | |
725 | return -EBUSY; | |
726 | } | |
727 | ||
728 | nv_debug_level(SILENT); | |
729 | drm_kms_helper_poll_disable(drm_dev); | |
730 | vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); | |
731 | nouveau_switcheroo_optimus_dsm(); | |
732 | ret = nouveau_do_suspend(drm_dev, true); | |
733 | pci_save_state(pdev); | |
734 | pci_disable_device(pdev); | |
8c863944 | 735 | pci_ignore_hotplug(pdev); |
7bb6d442 BS |
736 | pci_set_power_state(pdev, PCI_D3cold); |
737 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; | |
738 | return ret; | |
739 | } | |
740 | ||
741 | static int | |
742 | nouveau_pmops_runtime_resume(struct device *dev) | |
743 | { | |
744 | struct pci_dev *pdev = to_pci_dev(dev); | |
745 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
746 | struct nvif_device *device = &nouveau_drm(drm_dev)->device; | |
747 | int ret; | |
748 | ||
749 | if (nouveau_runtime_pm == 0) | |
750 | return -EINVAL; | |
751 | ||
752 | pci_set_power_state(pdev, PCI_D0); | |
753 | pci_restore_state(pdev); | |
754 | ret = pci_enable_device(pdev); | |
755 | if (ret) | |
756 | return ret; | |
757 | pci_set_master(pdev); | |
758 | ||
759 | ret = nouveau_do_resume(drm_dev, true); | |
760 | drm_kms_helper_poll_enable(drm_dev); | |
761 | /* do magic */ | |
762 | nvif_mask(device, 0x88488, (1 << 25), (1 << 25)); | |
763 | vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); | |
764 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
765 | nv_debug_level(NORMAL); | |
766 | return ret; | |
767 | } | |
768 | ||
769 | static int | |
770 | nouveau_pmops_runtime_idle(struct device *dev) | |
771 | { | |
772 | struct pci_dev *pdev = to_pci_dev(dev); | |
773 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
774 | struct nouveau_drm *drm = nouveau_drm(drm_dev); | |
775 | struct drm_crtc *crtc; | |
776 | ||
777 | if (nouveau_runtime_pm == 0) { | |
778 | pm_runtime_forbid(dev); | |
779 | return -EBUSY; | |
780 | } | |
781 | ||
782 | /* are we optimus enabled? */ | |
783 | if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) { | |
784 | DRM_DEBUG_DRIVER("failing to power off - not optimus\n"); | |
785 | pm_runtime_forbid(dev); | |
786 | return -EBUSY; | |
787 | } | |
788 | ||
789 | /* if we have a hdmi audio device - make sure it has a driver loaded */ | |
790 | if (drm->hdmi_device) { | |
791 | if (!drm->hdmi_device->driver) { | |
792 | DRM_DEBUG_DRIVER("failing to power off - no HDMI audio driver loaded\n"); | |
793 | pm_runtime_mark_last_busy(dev); | |
794 | return -EBUSY; | |
795 | } | |
796 | } | |
797 | ||
798 | list_for_each_entry(crtc, &drm->dev->mode_config.crtc_list, head) { | |
799 | if (crtc->enabled) { | |
800 | DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); | |
801 | return -EBUSY; | |
802 | } | |
803 | } | |
804 | pm_runtime_mark_last_busy(dev); | |
805 | pm_runtime_autosuspend(dev); | |
806 | /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ | |
807 | return 1; | |
808 | } | |
2d8b9ccb | 809 | |
5b8a43ae | 810 | static int |
ebb945a9 BS |
811 | nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) |
812 | { | |
ebb945a9 BS |
813 | struct nouveau_drm *drm = nouveau_drm(dev); |
814 | struct nouveau_cli *cli; | |
a2896ced | 815 | char name[32], tmpname[TASK_COMM_LEN]; |
ebb945a9 BS |
816 | int ret; |
817 | ||
5addcf0a DA |
818 | /* need to bring up power immediately if opening device */ |
819 | ret = pm_runtime_get_sync(dev->dev); | |
b6c4285a | 820 | if (ret < 0 && ret != -EACCES) |
5addcf0a DA |
821 | return ret; |
822 | ||
a2896ced MS |
823 | get_task_comm(tmpname, current); |
824 | snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid)); | |
fa6df8c1 | 825 | |
420b9469 AC |
826 | ret = nouveau_cli_create(nouveau_name(dev), name, sizeof(*cli), |
827 | (void **)&cli); | |
828 | ||
ebb945a9 | 829 | if (ret) |
5addcf0a | 830 | goto out_suspend; |
ebb945a9 | 831 | |
0ad72863 BS |
832 | cli->base.super = false; |
833 | ||
967e7bde | 834 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { |
be83cd4e BS |
835 | ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40), |
836 | 0x1000, &cli->vm); | |
ebb945a9 BS |
837 | if (ret) { |
838 | nouveau_cli_destroy(cli); | |
5addcf0a | 839 | goto out_suspend; |
ebb945a9 | 840 | } |
3ee6f5b5 | 841 | |
989aa5b7 | 842 | nvxx_client(&cli->base)->vm = cli->vm; |
ebb945a9 BS |
843 | } |
844 | ||
845 | fpriv->driver_priv = cli; | |
846 | ||
847 | mutex_lock(&drm->client.mutex); | |
848 | list_add(&cli->head, &drm->clients); | |
849 | mutex_unlock(&drm->client.mutex); | |
5addcf0a DA |
850 | |
851 | out_suspend: | |
852 | pm_runtime_mark_last_busy(dev->dev); | |
853 | pm_runtime_put_autosuspend(dev->dev); | |
854 | ||
855 | return ret; | |
ebb945a9 BS |
856 | } |
857 | ||
5b8a43ae | 858 | static void |
ebb945a9 BS |
859 | nouveau_drm_preclose(struct drm_device *dev, struct drm_file *fpriv) |
860 | { | |
861 | struct nouveau_cli *cli = nouveau_cli(fpriv); | |
862 | struct nouveau_drm *drm = nouveau_drm(dev); | |
863 | ||
5addcf0a DA |
864 | pm_runtime_get_sync(dev->dev); |
865 | ||
ebb945a9 BS |
866 | if (cli->abi16) |
867 | nouveau_abi16_fini(cli->abi16); | |
868 | ||
869 | mutex_lock(&drm->client.mutex); | |
870 | list_del(&cli->head); | |
871 | mutex_unlock(&drm->client.mutex); | |
5addcf0a | 872 | |
ebb945a9 BS |
873 | } |
874 | ||
5b8a43ae | 875 | static void |
ebb945a9 BS |
876 | nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv) |
877 | { | |
878 | struct nouveau_cli *cli = nouveau_cli(fpriv); | |
879 | nouveau_cli_destroy(cli); | |
5addcf0a DA |
880 | pm_runtime_mark_last_busy(dev->dev); |
881 | pm_runtime_put_autosuspend(dev->dev); | |
ebb945a9 BS |
882 | } |
883 | ||
baa70943 | 884 | static const struct drm_ioctl_desc |
77145f1c | 885 | nouveau_ioctls[] = { |
7d761258 | 886 | DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), |
77145f1c | 887 | DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
7d761258 MP |
888 | DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), |
889 | DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
890 | DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
891 | DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
892 | DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
893 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
894 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
895 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
896 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
897 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
77145f1c BS |
898 | }; |
899 | ||
27111a23 BS |
900 | long |
901 | nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |
5addcf0a | 902 | { |
27111a23 BS |
903 | struct drm_file *filp = file->private_data; |
904 | struct drm_device *dev = filp->minor->dev; | |
5addcf0a | 905 | long ret; |
5addcf0a DA |
906 | |
907 | ret = pm_runtime_get_sync(dev->dev); | |
b6c4285a | 908 | if (ret < 0 && ret != -EACCES) |
5addcf0a DA |
909 | return ret; |
910 | ||
27111a23 BS |
911 | switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) { |
912 | case DRM_NOUVEAU_NVIF: | |
913 | ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd)); | |
914 | break; | |
915 | default: | |
916 | ret = drm_ioctl(file, cmd, arg); | |
917 | break; | |
918 | } | |
5addcf0a DA |
919 | |
920 | pm_runtime_mark_last_busy(dev->dev); | |
921 | pm_runtime_put_autosuspend(dev->dev); | |
922 | return ret; | |
923 | } | |
27111a23 | 924 | |
77145f1c BS |
925 | static const struct file_operations |
926 | nouveau_driver_fops = { | |
927 | .owner = THIS_MODULE, | |
928 | .open = drm_open, | |
929 | .release = drm_release, | |
5addcf0a | 930 | .unlocked_ioctl = nouveau_drm_ioctl, |
77145f1c BS |
931 | .mmap = nouveau_ttm_mmap, |
932 | .poll = drm_poll, | |
77145f1c BS |
933 | .read = drm_read, |
934 | #if defined(CONFIG_COMPAT) | |
935 | .compat_ioctl = nouveau_compat_ioctl, | |
936 | #endif | |
937 | .llseek = noop_llseek, | |
938 | }; | |
939 | ||
940 | static struct drm_driver | |
915b4d11 | 941 | driver_stub = { |
77145f1c | 942 | .driver_features = |
4cb4ea39 | 943 | DRIVER_USE_AGP | |
7d761258 | 944 | DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER, |
77145f1c BS |
945 | |
946 | .load = nouveau_drm_load, | |
947 | .unload = nouveau_drm_unload, | |
948 | .open = nouveau_drm_open, | |
949 | .preclose = nouveau_drm_preclose, | |
950 | .postclose = nouveau_drm_postclose, | |
951 | .lastclose = nouveau_vga_lastclose, | |
952 | ||
33b903e8 MS |
953 | #if defined(CONFIG_DEBUG_FS) |
954 | .debugfs_init = nouveau_debugfs_init, | |
955 | .debugfs_cleanup = nouveau_debugfs_takedown, | |
956 | #endif | |
957 | ||
77145f1c | 958 | .get_vblank_counter = drm_vblank_count, |
51cb4b39 BS |
959 | .enable_vblank = nouveau_display_vblank_enable, |
960 | .disable_vblank = nouveau_display_vblank_disable, | |
d83ef853 BS |
961 | .get_scanout_position = nouveau_display_scanoutpos, |
962 | .get_vblank_timestamp = nouveau_display_vblstamp, | |
77145f1c BS |
963 | |
964 | .ioctls = nouveau_ioctls, | |
baa70943 | 965 | .num_ioctls = ARRAY_SIZE(nouveau_ioctls), |
77145f1c BS |
966 | .fops = &nouveau_driver_fops, |
967 | ||
968 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
969 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
ab9ccb96 AP |
970 | .gem_prime_export = drm_gem_prime_export, |
971 | .gem_prime_import = drm_gem_prime_import, | |
972 | .gem_prime_pin = nouveau_gem_prime_pin, | |
3aac4502 | 973 | .gem_prime_res_obj = nouveau_gem_prime_res_obj, |
1af7c7dd | 974 | .gem_prime_unpin = nouveau_gem_prime_unpin, |
ab9ccb96 AP |
975 | .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table, |
976 | .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table, | |
977 | .gem_prime_vmap = nouveau_gem_prime_vmap, | |
978 | .gem_prime_vunmap = nouveau_gem_prime_vunmap, | |
77145f1c | 979 | |
77145f1c BS |
980 | .gem_free_object = nouveau_gem_object_del, |
981 | .gem_open_object = nouveau_gem_object_open, | |
982 | .gem_close_object = nouveau_gem_object_close, | |
983 | ||
984 | .dumb_create = nouveau_display_dumb_create, | |
985 | .dumb_map_offset = nouveau_display_dumb_map_offset, | |
43387b37 | 986 | .dumb_destroy = drm_gem_dumb_destroy, |
77145f1c BS |
987 | |
988 | .name = DRIVER_NAME, | |
989 | .desc = DRIVER_DESC, | |
990 | #ifdef GIT_REVISION | |
991 | .date = GIT_REVISION, | |
992 | #else | |
993 | .date = DRIVER_DATE, | |
994 | #endif | |
995 | .major = DRIVER_MAJOR, | |
996 | .minor = DRIVER_MINOR, | |
997 | .patchlevel = DRIVER_PATCHLEVEL, | |
998 | }; | |
999 | ||
94580299 BS |
1000 | static struct pci_device_id |
1001 | nouveau_drm_pci_table[] = { | |
1002 | { | |
1003 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), | |
1004 | .class = PCI_BASE_CLASS_DISPLAY << 16, | |
1005 | .class_mask = 0xff << 16, | |
1006 | }, | |
1007 | { | |
1008 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID), | |
1009 | .class = PCI_BASE_CLASS_DISPLAY << 16, | |
1010 | .class_mask = 0xff << 16, | |
1011 | }, | |
1012 | {} | |
1013 | }; | |
1014 | ||
703fa264 PM |
1015 | static void nouveau_display_options(void) |
1016 | { | |
1017 | DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n"); | |
1018 | ||
1019 | DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable); | |
1020 | DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid); | |
1021 | DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink); | |
1022 | DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel); | |
1023 | DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config); | |
1024 | DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug); | |
1025 | DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel); | |
1026 | DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset); | |
1027 | DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm); | |
1028 | DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf); | |
1029 | DRM_DEBUG_DRIVER("... pstate : %d\n", nouveau_pstate); | |
1030 | } | |
1031 | ||
2d8b9ccb DA |
1032 | static const struct dev_pm_ops nouveau_pm_ops = { |
1033 | .suspend = nouveau_pmops_suspend, | |
1034 | .resume = nouveau_pmops_resume, | |
1035 | .freeze = nouveau_pmops_freeze, | |
1036 | .thaw = nouveau_pmops_thaw, | |
1037 | .poweroff = nouveau_pmops_freeze, | |
1038 | .restore = nouveau_pmops_resume, | |
5addcf0a DA |
1039 | .runtime_suspend = nouveau_pmops_runtime_suspend, |
1040 | .runtime_resume = nouveau_pmops_runtime_resume, | |
1041 | .runtime_idle = nouveau_pmops_runtime_idle, | |
2d8b9ccb DA |
1042 | }; |
1043 | ||
94580299 BS |
1044 | static struct pci_driver |
1045 | nouveau_drm_pci_driver = { | |
1046 | .name = "nouveau", | |
1047 | .id_table = nouveau_drm_pci_table, | |
1048 | .probe = nouveau_drm_probe, | |
1049 | .remove = nouveau_drm_remove, | |
2d8b9ccb | 1050 | .driver.pm = &nouveau_pm_ops, |
94580299 BS |
1051 | }; |
1052 | ||
8ba9ff11 AC |
1053 | struct drm_device * |
1054 | nouveau_platform_device_create_(struct platform_device *pdev, int size, | |
1055 | void **pobject) | |
420b9469 | 1056 | { |
8ba9ff11 AC |
1057 | struct drm_device *drm; |
1058 | int err; | |
420b9469 | 1059 | |
be83cd4e BS |
1060 | err = nvkm_device_create_(pdev, NVKM_BUS_PLATFORM, |
1061 | nouveau_platform_name(pdev), | |
1062 | dev_name(&pdev->dev), nouveau_config, | |
1063 | nouveau_debug, size, pobject); | |
8ba9ff11 AC |
1064 | if (err) |
1065 | return ERR_PTR(err); | |
1066 | ||
915b4d11 | 1067 | drm = drm_dev_alloc(&driver_platform, &pdev->dev); |
8ba9ff11 AC |
1068 | if (!drm) { |
1069 | err = -ENOMEM; | |
1070 | goto err_free; | |
420b9469 AC |
1071 | } |
1072 | ||
8ba9ff11 AC |
1073 | err = drm_dev_set_unique(drm, "%s", dev_name(&pdev->dev)); |
1074 | if (err < 0) | |
1075 | goto err_free; | |
1076 | ||
1077 | drm->platformdev = pdev; | |
1078 | platform_set_drvdata(pdev, drm); | |
1079 | ||
1080 | return drm; | |
1081 | ||
1082 | err_free: | |
be83cd4e | 1083 | nvkm_object_ref(NULL, (struct nvkm_object **)pobject); |
8ba9ff11 AC |
1084 | |
1085 | return ERR_PTR(err); | |
420b9469 AC |
1086 | } |
1087 | ||
94580299 BS |
1088 | static int __init |
1089 | nouveau_drm_init(void) | |
1090 | { | |
915b4d11 DH |
1091 | driver_pci = driver_stub; |
1092 | driver_pci.set_busid = drm_pci_set_busid; | |
1093 | driver_platform = driver_stub; | |
1094 | driver_platform.set_busid = drm_platform_set_busid; | |
1095 | ||
703fa264 PM |
1096 | nouveau_display_options(); |
1097 | ||
77145f1c BS |
1098 | if (nouveau_modeset == -1) { |
1099 | #ifdef CONFIG_VGA_CONSOLE | |
1100 | if (vgacon_text_force()) | |
1101 | nouveau_modeset = 0; | |
77145f1c | 1102 | #endif |
77145f1c BS |
1103 | } |
1104 | ||
1105 | if (!nouveau_modeset) | |
1106 | return 0; | |
1107 | ||
055a65d5 AC |
1108 | #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER |
1109 | platform_driver_register(&nouveau_platform_driver); | |
1110 | #endif | |
1111 | ||
77145f1c | 1112 | nouveau_register_dsm_handler(); |
915b4d11 | 1113 | return drm_pci_init(&driver_pci, &nouveau_drm_pci_driver); |
94580299 BS |
1114 | } |
1115 | ||
1116 | static void __exit | |
1117 | nouveau_drm_exit(void) | |
1118 | { | |
77145f1c BS |
1119 | if (!nouveau_modeset) |
1120 | return; | |
1121 | ||
915b4d11 | 1122 | drm_pci_exit(&driver_pci, &nouveau_drm_pci_driver); |
77145f1c | 1123 | nouveau_unregister_dsm_handler(); |
055a65d5 AC |
1124 | |
1125 | #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER | |
1126 | platform_driver_unregister(&nouveau_platform_driver); | |
1127 | #endif | |
94580299 BS |
1128 | } |
1129 | ||
1130 | module_init(nouveau_drm_init); | |
1131 | module_exit(nouveau_drm_exit); | |
1132 | ||
1133 | MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table); | |
77145f1c BS |
1134 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1135 | MODULE_DESCRIPTION(DRIVER_DESC); | |
94580299 | 1136 | MODULE_LICENSE("GPL and additional rights"); |