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drm/nouveau: Add cache_flush/pull fifo engine functions.
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
37#define DRIVER_PATCHLEVEL 15
38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
054b93e4 57struct nouveau_grctx;
6ee73861
BS		 58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
62
63#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
64#define NV50_VM_BLOCK (512*1024*1024ULL)
65#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
66
67struct nouveau_bo {
68 struct ttm_buffer_object bo;
69 struct ttm_placement placement;
70 u32 placements[3];
71 struct ttm_bo_kmap_obj kmap;
72 struct list_head head;
73
74 /* protected by ttm_bo_reserve() */
75 struct drm_file *reserved_by;
76 struct list_head entry;
77 int pbbo_index;
78
79 struct nouveau_channel *channel;
80
81 bool mappable;
82 bool no_vm;
83
84 uint32_t tile_mode;
85 uint32_t tile_flags;
86
87 struct drm_gem_object *gem;
88 struct drm_file *cpu_filp;
89 int pin_refcnt;
90};
91
92static inline struct nouveau_bo *
93nouveau_bo(struct ttm_buffer_object *bo)
94{
95 return container_of(bo, struct nouveau_bo, bo);
96}
97
98static inline struct nouveau_bo *
99nouveau_gem_object(struct drm_gem_object *gem)
100{
101 return gem ? gem->driver_private : NULL;
102}
103
104/* TODO: submit equivalent to TTM generic API upstream? */
105static inline void __iomem *
106nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
107{
108 bool is_iomem;
109 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
110 &nvbo->kmap, &is_iomem);
111 WARN_ON_ONCE(ioptr && !is_iomem);
112 return ioptr;
113}
114
115struct mem_block {
116 struct mem_block *next;
117 struct mem_block *prev;
118 uint64_t start;
119 uint64_t size;
120 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
121};
122
123enum nouveau_flags {
124 NV_NFORCE = 0x10000000,
125 NV_NFORCE2 = 0x20000000
126};
127
128#define NVOBJ_ENGINE_SW 0
129#define NVOBJ_ENGINE_GR 1
130#define NVOBJ_ENGINE_DISPLAY 2
131#define NVOBJ_ENGINE_INT 0xdeadbeef
132
133#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
134#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
135#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
136#define NVOBJ_FLAG_FAKE (1 << 3)
137struct nouveau_gpuobj {
138 struct list_head list;
139
140 struct nouveau_channel *im_channel;
141 struct mem_block *im_pramin;
142 struct nouveau_bo *im_backing;
143 uint32_t im_backing_start;
144 uint32_t *im_backing_suspend;
145 int im_bound;
146
147 uint32_t flags;
148 int refcount;
149
150 uint32_t engine;
151 uint32_t class;
152
153 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
154 void *priv;
155};
156
157struct nouveau_gpuobj_ref {
158 struct list_head list;
159
160 struct nouveau_gpuobj *gpuobj;
161 uint32_t instance;
162
163 struct nouveau_channel *channel;
164 int handle;
165};
166
167struct nouveau_channel {
168 struct drm_device *dev;
169 int id;
170
171 /* owner of this fifo */
172 struct drm_file *file_priv;
173 /* mapping of the fifo itself */
174 struct drm_local_map *map;
175
176 /* mapping of the regs controling the fifo */
177 void __iomem *user;
178 uint32_t user_get;
179 uint32_t user_put;
180
181 /* Fencing */
182 struct {
183 /* lock protects the pending list only */
184 spinlock_t lock;
185 struct list_head pending;
186 uint32_t sequence;
187 uint32_t sequence_ack;
188 uint32_t last_sequence_irq;
189 } fence;
190
191 /* DMA push buffer */
192 struct nouveau_gpuobj_ref *pushbuf;
193 struct nouveau_bo *pushbuf_bo;
194 uint32_t pushbuf_base;
195
196 /* Notifier memory */
197 struct nouveau_bo *notifier_bo;
198 struct mem_block *notifier_heap;
199
200 /* PFIFO context */
201 struct nouveau_gpuobj_ref *ramfc;
202 struct nouveau_gpuobj_ref *cache;
203
204 /* PGRAPH context */
205 /* XXX may be merge 2 pointers as private data ??? */
206 struct nouveau_gpuobj_ref *ramin_grctx;
207 void *pgraph_ctx;
208
209 /* NV50 VM */
210 struct nouveau_gpuobj *vm_pd;
211 struct nouveau_gpuobj_ref *vm_gart_pt;
212 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
213
214 /* Objects */
215 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
216 struct mem_block *ramin_heap; /* Private PRAMIN heap */
217 struct nouveau_gpuobj_ref *ramht; /* Hash table */
218 struct list_head ramht_refs; /* Objects referenced by RAMHT */
219
220 /* GPU object info for stuff used in-kernel (mm_enabled) */
221 uint32_t m2mf_ntfy;
222 uint32_t vram_handle;
223 uint32_t gart_handle;
224 bool accel_done;
225
226 /* Push buffer state (only for drm's channel on !mm_enabled) */
227 struct {
228 int max;
229 int free;
230 int cur;
231 int put;
232 /* access via pushbuf_bo */
233 } dma;
234
235 uint32_t sw_subchannel[8];
236
237 struct {
238 struct nouveau_gpuobj *vblsem;
239 uint32_t vblsem_offset;
240 uint32_t vblsem_rval;
241 struct list_head vbl_wait;
242 } nvsw;
243
244 struct {
245 bool active;
246 char name[32];
247 struct drm_info_list info;
248 } debugfs;
249};
250
251struct nouveau_instmem_engine {
252 void *priv;
253
254 int (*init)(struct drm_device *dev);
255 void (*takedown)(struct drm_device *dev);
256 int (*suspend)(struct drm_device *dev);
257 void (*resume)(struct drm_device *dev);
258
259 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
260 uint32_t *size);
261 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
262 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
263 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
264 void (*prepare_access)(struct drm_device *, bool write);
265 void (*finish_access)(struct drm_device *);
266};
267
268struct nouveau_mc_engine {
269 int (*init)(struct drm_device *dev);
270 void (*takedown)(struct drm_device *dev);
271};
272
273struct nouveau_timer_engine {
274 int (*init)(struct drm_device *dev);
275 void (*takedown)(struct drm_device *dev);
276 uint64_t (*read)(struct drm_device *dev);
277};
278
279struct nouveau_fb_engine {
280 int (*init)(struct drm_device *dev);
281 void (*takedown)(struct drm_device *dev);
282};
283
284struct nouveau_fifo_engine {
285 void *priv;
286
287 int channels;
288
289 int (*init)(struct drm_device *);
290 void (*takedown)(struct drm_device *);
291
292 void (*disable)(struct drm_device *);
293 void (*enable)(struct drm_device *);
294 bool (*reassign)(struct drm_device *, bool enable);
588d7d12
FJ		 295 bool (*cache_flush)(struct drm_device *dev);
296 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 297
298 int (*channel_id)(struct drm_device *);
299
300 int (*create_context)(struct nouveau_channel *);
301 void (*destroy_context)(struct nouveau_channel *);
302 int (*load_context)(struct nouveau_channel *);
303 int (*unload_context)(struct drm_device *);
304};
305
306struct nouveau_pgraph_object_method {
307 int id;
308 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
309 uint32_t data);
310};
311
312struct nouveau_pgraph_object_class {
313 int id;
314 bool software;
315 struct nouveau_pgraph_object_method *methods;
316};
317
318struct nouveau_pgraph_engine {
319 struct nouveau_pgraph_object_class *grclass;
320 bool accel_blocked;
321 void *ctxprog;
322 void *ctxvals;
054b93e4 323 int grctx_size;
6ee73861
BS		 324
325 int (*init)(struct drm_device *);
326 void (*takedown)(struct drm_device *);
327
328 void (*fifo_access)(struct drm_device *, bool);
329
330 struct nouveau_channel *(*channel)(struct drm_device *);
331 int (*create_context)(struct nouveau_channel *);
332 void (*destroy_context)(struct nouveau_channel *);
333 int (*load_context)(struct nouveau_channel *);
334 int (*unload_context)(struct drm_device *);
335};
336
337struct nouveau_engine {
338 struct nouveau_instmem_engine instmem;
339 struct nouveau_mc_engine mc;
340 struct nouveau_timer_engine timer;
341 struct nouveau_fb_engine fb;
342 struct nouveau_pgraph_engine graph;
343 struct nouveau_fifo_engine fifo;
344};
345
346struct nouveau_pll_vals {
347 union {
348 struct {
349#ifdef __BIG_ENDIAN
350 uint8_t N1, M1, N2, M2;
351#else
352 uint8_t M1, N1, M2, N2;
353#endif
354 };
355 struct {
356 uint16_t NM1, NM2;
357 } __attribute__((packed));
358 };
359 int log2P;
360
361 int refclk;
362};
363
364enum nv04_fp_display_regs {
365 FP_DISPLAY_END,
366 FP_TOTAL,
367 FP_CRTC,
368 FP_SYNC_START,
369 FP_SYNC_END,
370 FP_VALID_START,
371 FP_VALID_END
372};
373
374struct nv04_crtc_reg {
375 unsigned char MiscOutReg; /* */
376 uint8_t CRTC[0x9f];
377 uint8_t CR58[0x10];
378 uint8_t Sequencer[5];
379 uint8_t Graphics[9];
380 uint8_t Attribute[21];
381 unsigned char DAC[768]; /* Internal Colorlookuptable */
382
383 /* PCRTC regs */
384 uint32_t fb_start;
385 uint32_t crtc_cfg;
386 uint32_t cursor_cfg;
387 uint32_t gpio_ext;
388 uint32_t crtc_830;
389 uint32_t crtc_834;
390 uint32_t crtc_850;
391 uint32_t crtc_eng_ctrl;
392
393 /* PRAMDAC regs */
394 uint32_t nv10_cursync;
395 struct nouveau_pll_vals pllvals;
396 uint32_t ramdac_gen_ctrl;
397 uint32_t ramdac_630;
398 uint32_t ramdac_634;
399 uint32_t tv_setup;
400 uint32_t tv_vtotal;
401 uint32_t tv_vskew;
402 uint32_t tv_vsync_delay;
403 uint32_t tv_htotal;
404 uint32_t tv_hskew;
405 uint32_t tv_hsync_delay;
406 uint32_t tv_hsync_delay2;
407 uint32_t fp_horiz_regs[7];
408 uint32_t fp_vert_regs[7];
409 uint32_t dither;
410 uint32_t fp_control;
411 uint32_t dither_regs[6];
412 uint32_t fp_debug_0;
413 uint32_t fp_debug_1;
414 uint32_t fp_debug_2;
415 uint32_t fp_margin_color;
416 uint32_t ramdac_8c0;
417 uint32_t ramdac_a20;
418 uint32_t ramdac_a24;
419 uint32_t ramdac_a34;
420 uint32_t ctv_regs[38];
421};
422
423struct nv04_output_reg {
424 uint32_t output;
425 int head;
426};
427
428struct nv04_mode_state {
429 uint32_t bpp;
430 uint32_t width;
431 uint32_t height;
432 uint32_t interlace;
433 uint32_t repaint0;
434 uint32_t repaint1;
435 uint32_t screen;
436 uint32_t scale;
437 uint32_t dither;
438 uint32_t extra;
439 uint32_t fifo;
440 uint32_t pixel;
441 uint32_t horiz;
442 int arbitration0;
443 int arbitration1;
444 uint32_t pll;
445 uint32_t pllB;
446 uint32_t vpll;
447 uint32_t vpll2;
448 uint32_t vpllB;
449 uint32_t vpll2B;
450 uint32_t pllsel;
451 uint32_t sel_clk;
452 uint32_t general;
453 uint32_t crtcOwner;
454 uint32_t head;
455 uint32_t head2;
456 uint32_t cursorConfig;
457 uint32_t cursor0;
458 uint32_t cursor1;
459 uint32_t cursor2;
460 uint32_t timingH;
461 uint32_t timingV;
462 uint32_t displayV;
463 uint32_t crtcSync;
464
465 struct nv04_crtc_reg crtc_reg[2];
466};
467
468enum nouveau_card_type {
469 NV_04 = 0x00,
470 NV_10 = 0x10,
471 NV_20 = 0x20,
472 NV_30 = 0x30,
473 NV_40 = 0x40,
474 NV_50 = 0x50,
475};
476
477struct drm_nouveau_private {
478 struct drm_device *dev;
479 enum {
480 NOUVEAU_CARD_INIT_DOWN,
481 NOUVEAU_CARD_INIT_DONE,
482 NOUVEAU_CARD_INIT_FAILED
483 } init_state;
484
485 /* the card type, takes NV_* as values */
486 enum nouveau_card_type card_type;
487 /* exact chipset, derived from NV_PMC_BOOT_0 */
488 int chipset;
489 int flags;
490
491 void __iomem *mmio;
492 void __iomem *ramin;
493 uint32_t ramin_size;
494
495 struct workqueue_struct *wq;
496 struct work_struct irq_work;
497
498 struct list_head vbl_waiting;
499
500 struct {
501 struct ttm_global_reference mem_global_ref;
502 struct ttm_bo_global_ref bo_global_ref;
503 struct ttm_bo_device bdev;
504 spinlock_t bo_list_lock;
505 struct list_head bo_list;
506 atomic_t validate_sequence;
507 } ttm;
508
509 struct fb_info *fbdev_info;
510
511 int fifo_alloc_count;
512 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
513
514 struct nouveau_engine engine;
515 struct nouveau_channel *channel;
516
517 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
518 struct nouveau_gpuobj *ramht;
519 uint32_t ramin_rsvd_vram;
520 uint32_t ramht_offset;
521 uint32_t ramht_size;
522 uint32_t ramht_bits;
523 uint32_t ramfc_offset;
524 uint32_t ramfc_size;
525 uint32_t ramro_offset;
526 uint32_t ramro_size;
527
528 /* base physical adresses */
529 uint64_t fb_phys;
530 uint64_t fb_available_size;
531 uint64_t fb_mappable_pages;
532 uint64_t fb_aper_free;
533
534 struct {
535 enum {
536 NOUVEAU_GART_NONE = 0,
537 NOUVEAU_GART_AGP,
538 NOUVEAU_GART_SGDMA
539 } type;
540 uint64_t aper_base;
541 uint64_t aper_size;
542 uint64_t aper_free;
543
544 struct nouveau_gpuobj *sg_ctxdma;
545 struct page *sg_dummy_page;
546 dma_addr_t sg_dummy_bus;
547
548 /* nottm hack */
549 struct drm_ttm_backend *sg_be;
550 unsigned long sg_handle;
551 } gart_info;
552
553 /* G8x/G9x virtual address space */
554 uint64_t vm_gart_base;
555 uint64_t vm_gart_size;
556 uint64_t vm_vram_base;
557 uint64_t vm_vram_size;
558 uint64_t vm_end;
559 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
560 int vm_vram_pt_nr;
561
562 /* the mtrr covering the FB */
563 int fb_mtrr;
564
565 struct mem_block *ramin_heap;
566
567 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
568 uint32_t ctx_table_size;
569 struct nouveau_gpuobj_ref *ctx_table;
570
571 struct list_head gpuobj_list;
572
573 struct nvbios VBIOS;
574 struct nouveau_bios_info *vbios;
575
576 struct nv04_mode_state mode_reg;
577 struct nv04_mode_state saved_reg;
578 uint32_t saved_vga_font[4][16384];
579 uint32_t crtc_owner;
580 uint32_t dac_users[4];
581
582 struct nouveau_suspend_resume {
583 uint32_t fifo_mode;
584 uint32_t graph_ctx_control;
585 uint32_t graph_state;
586 uint32_t *ramin_copy;
587 uint64_t ramin_size;
588 } susres;
589
590 struct backlight_device *backlight;
591 bool acpi_dsm;
592
593 struct nouveau_channel *evo;
594
595 struct {
596 struct dentry *channel_root;
597 } debugfs;
598};
599
600static inline struct drm_nouveau_private *
601nouveau_bdev(struct ttm_bo_device *bd)
602{
603 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
604}
605
606static inline int
607nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
608{
609 struct nouveau_bo *prev;
610
611 if (!pnvbo)
612 return -EINVAL;
613 prev = *pnvbo;
614
615 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
616 if (prev) {
617 struct ttm_buffer_object *bo = &prev->bo;
618
619 ttm_bo_unref(&bo);
620 }
621
622 return 0;
623}
624
625#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
626 struct drm_nouveau_private *nv = dev->dev_private; \
627 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
628 NV_ERROR(dev, "called without init\n"); \
629 return -EINVAL; \
630 } \
631} while (0)
632
633#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
634 struct drm_nouveau_private *nv = dev->dev_private; \
635 if (!nouveau_channel_owner(dev, (cl), (id))) { \
636 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
637 DRM_CURRENTPID, (id)); \
638 return -EPERM; \
639 } \
640 (ch) = nv->fifos[(id)]; \
641} while (0)
642
643/* nouveau_drv.c */
644extern int nouveau_noagp;
645extern int nouveau_duallink;
646extern int nouveau_uscript_lvds;
647extern int nouveau_uscript_tmds;
648extern int nouveau_vram_pushbuf;
649extern int nouveau_vram_notify;
650extern int nouveau_fbpercrtc;
651extern char *nouveau_tv_norm;
652extern int nouveau_reg_debug;
653extern char *nouveau_vbios;
054b93e4 654extern int nouveau_ctxfw;
6ee73861
BS		 655
656/* nouveau_state.c */
657extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
658extern int nouveau_load(struct drm_device *, unsigned long flags);
659extern int nouveau_firstopen(struct drm_device *);
660extern void nouveau_lastclose(struct drm_device *);
661extern int nouveau_unload(struct drm_device *);
662extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
663 struct drm_file *);
664extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
665 struct drm_file *);
666extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
667 uint32_t reg, uint32_t mask, uint32_t val);
668extern bool nouveau_wait_for_idle(struct drm_device *);
669extern int nouveau_card_init(struct drm_device *);
670extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
671 struct drm_file *);
672extern int nouveau_ioctl_suspend(struct drm_device *, void *data,
673 struct drm_file *);
674extern int nouveau_ioctl_resume(struct drm_device *, void *data,
675 struct drm_file *);
676
677/* nouveau_mem.c */
678extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
679 uint64_t size);
680extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
681 uint64_t size, int align2,
682 struct drm_file *, int tail);
683extern void nouveau_mem_takedown(struct mem_block **heap);
684extern void nouveau_mem_free_block(struct mem_block *);
685extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
686extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
687extern int nouveau_mem_init(struct drm_device *);
688extern int nouveau_mem_init_agp(struct drm_device *);
689extern void nouveau_mem_close(struct drm_device *);
690extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
691 uint32_t size, uint32_t flags,
692 uint64_t phys);
693extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
694 uint32_t size);
695
696/* nouveau_notifier.c */
697extern int nouveau_notifier_init_channel(struct nouveau_channel *);
698extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
699extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
700 int cout, uint32_t *offset);
701extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
702extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
703 struct drm_file *);
704extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
705 struct drm_file *);
706
707/* nouveau_channel.c */
708extern struct drm_ioctl_desc nouveau_ioctls[];
709extern int nouveau_max_ioctl;
710extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
711extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
712 int channel);
713extern int nouveau_channel_alloc(struct drm_device *dev,
714 struct nouveau_channel **chan,
715 struct drm_file *file_priv,
716 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
717extern void nouveau_channel_free(struct nouveau_channel *);
718extern int nouveau_channel_idle(struct nouveau_channel *chan);
719
720/* nouveau_object.c */
721extern int nouveau_gpuobj_early_init(struct drm_device *);
722extern int nouveau_gpuobj_init(struct drm_device *);
723extern void nouveau_gpuobj_takedown(struct drm_device *);
724extern void nouveau_gpuobj_late_takedown(struct drm_device *);
725extern int nouveau_gpuobj_suspend(struct drm_device *dev);
726extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
727extern void nouveau_gpuobj_resume(struct drm_device *dev);
728extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
729 uint32_t vram_h, uint32_t tt_h);
730extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
731extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
732 uint32_t size, int align, uint32_t flags,
733 struct nouveau_gpuobj **);
734extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
735extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
736 uint32_t handle, struct nouveau_gpuobj *,
737 struct nouveau_gpuobj_ref **);
738extern int nouveau_gpuobj_ref_del(struct drm_device *,
739 struct nouveau_gpuobj_ref **);
740extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
741 struct nouveau_gpuobj_ref **ref_ret);
742extern int nouveau_gpuobj_new_ref(struct drm_device *,
743 struct nouveau_channel *alloc_chan,
744 struct nouveau_channel *ref_chan,
745 uint32_t handle, uint32_t size, int align,
746 uint32_t flags, struct nouveau_gpuobj_ref **);
747extern int nouveau_gpuobj_new_fake(struct drm_device *,
748 uint32_t p_offset, uint32_t b_offset,
749 uint32_t size, uint32_t flags,
750 struct nouveau_gpuobj **,
751 struct nouveau_gpuobj_ref**);
752extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
753 uint64_t offset, uint64_t size, int access,
754 int target, struct nouveau_gpuobj **);
755extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
756 uint64_t offset, uint64_t size,
757 int access, struct nouveau_gpuobj **,
758 uint32_t *o_ret);
759extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
760 struct nouveau_gpuobj **);
761extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
762 struct drm_file *);
763extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
764 struct drm_file *);
765
766/* nouveau_irq.c */
767extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
768extern void nouveau_irq_preinstall(struct drm_device *);
769extern int nouveau_irq_postinstall(struct drm_device *);
770extern void nouveau_irq_uninstall(struct drm_device *);
771
772/* nouveau_sgdma.c */
773extern int nouveau_sgdma_init(struct drm_device *);
774extern void nouveau_sgdma_takedown(struct drm_device *);
775extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
776 uint32_t *page);
777extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
778
779/* nouveau_debugfs.c */
780#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
781extern int nouveau_debugfs_init(struct drm_minor *);
782extern void nouveau_debugfs_takedown(struct drm_minor *);
783extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
784extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
785#else
786static inline int
787nouveau_debugfs_init(struct drm_minor *minor)
788{
789 return 0;
790}
791
792static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
793{
794}
795
796static inline int
797nouveau_debugfs_channel_init(struct nouveau_channel *chan)
798{
799 return 0;
800}
801
802static inline void
803nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
804{
805}
806#endif
807
808/* nouveau_dma.c */
809extern int nouveau_dma_init(struct nouveau_channel *);
810extern int nouveau_dma_wait(struct nouveau_channel *, int size);
811
812/* nouveau_acpi.c */
813#ifdef CONFIG_ACPI
814extern int nouveau_hybrid_setup(struct drm_device *dev);
815extern bool nouveau_dsm_probe(struct drm_device *dev);
816#else
817static inline int nouveau_hybrid_setup(struct drm_device *dev)
818{
819 return 0;
820}
821static inline bool nouveau_dsm_probe(struct drm_device *dev)
822{
823 return false;
824}
825#endif
826
827/* nouveau_backlight.c */
828#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
829extern int nouveau_backlight_init(struct drm_device *);
830extern void nouveau_backlight_exit(struct drm_device *);
831#else
832static inline int nouveau_backlight_init(struct drm_device *dev)
833{
834 return 0;
835}
836
837static inline void nouveau_backlight_exit(struct drm_device *dev) { }
838#endif
839
840/* nouveau_bios.c */
841extern int nouveau_bios_init(struct drm_device *);
842extern void nouveau_bios_takedown(struct drm_device *dev);
843extern int nouveau_run_vbios_init(struct drm_device *);
844extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
845 struct dcb_entry *);
846extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
847 enum dcb_gpio_tag);
848extern struct dcb_connector_table_entry *
849nouveau_bios_connector_entry(struct drm_device *, int index);
850extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
851 struct pll_lims *);
852extern int nouveau_bios_run_display_table(struct drm_device *,
853 struct dcb_entry *,
854 uint32_t script, int pxclk);
855extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
856 int *length);
857extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
858extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
859extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
860 bool *dl, bool *if_is_24bit);
861extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
862 int head, int pxclk);
863extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
864 enum LVDS_script, int pxclk);
865
866/* nouveau_ttm.c */
867int nouveau_ttm_global_init(struct drm_nouveau_private *);
868void nouveau_ttm_global_release(struct drm_nouveau_private *);
869int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
870
871/* nouveau_dp.c */
872int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
873 uint8_t *data, int data_nr);
874bool nouveau_dp_detect(struct drm_encoder *);
875bool nouveau_dp_link_train(struct drm_encoder *);
876
877/* nv04_fb.c */
878extern int nv04_fb_init(struct drm_device *);
879extern void nv04_fb_takedown(struct drm_device *);
880
881/* nv10_fb.c */
882extern int nv10_fb_init(struct drm_device *);
883extern void nv10_fb_takedown(struct drm_device *);
884
885/* nv40_fb.c */
886extern int nv40_fb_init(struct drm_device *);
887extern void nv40_fb_takedown(struct drm_device *);
888
889/* nv04_fifo.c */
890extern int nv04_fifo_init(struct drm_device *);
891extern void nv04_fifo_disable(struct drm_device *);
892extern void nv04_fifo_enable(struct drm_device *);
893extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12
FJ		 894extern bool nv04_fifo_cache_flush(struct drm_device *);
895extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 896extern int nv04_fifo_channel_id(struct drm_device *);
897extern int nv04_fifo_create_context(struct nouveau_channel *);
898extern void nv04_fifo_destroy_context(struct nouveau_channel *);
899extern int nv04_fifo_load_context(struct nouveau_channel *);
900extern int nv04_fifo_unload_context(struct drm_device *);
901
902/* nv10_fifo.c */
903extern int nv10_fifo_init(struct drm_device *);
904extern int nv10_fifo_channel_id(struct drm_device *);
905extern int nv10_fifo_create_context(struct nouveau_channel *);
906extern void nv10_fifo_destroy_context(struct nouveau_channel *);
907extern int nv10_fifo_load_context(struct nouveau_channel *);
908extern int nv10_fifo_unload_context(struct drm_device *);
909
910/* nv40_fifo.c */
911extern int nv40_fifo_init(struct drm_device *);
912extern int nv40_fifo_create_context(struct nouveau_channel *);
913extern void nv40_fifo_destroy_context(struct nouveau_channel *);
914extern int nv40_fifo_load_context(struct nouveau_channel *);
915extern int nv40_fifo_unload_context(struct drm_device *);
916
917/* nv50_fifo.c */
918extern int nv50_fifo_init(struct drm_device *);
919extern void nv50_fifo_takedown(struct drm_device *);
920extern int nv50_fifo_channel_id(struct drm_device *);
921extern int nv50_fifo_create_context(struct nouveau_channel *);
922extern void nv50_fifo_destroy_context(struct nouveau_channel *);
923extern int nv50_fifo_load_context(struct nouveau_channel *);
924extern int nv50_fifo_unload_context(struct drm_device *);
925
926/* nv04_graph.c */
927extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
928extern int nv04_graph_init(struct drm_device *);
929extern void nv04_graph_takedown(struct drm_device *);
930extern void nv04_graph_fifo_access(struct drm_device *, bool);
931extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
932extern int nv04_graph_create_context(struct nouveau_channel *);
933extern void nv04_graph_destroy_context(struct nouveau_channel *);
934extern int nv04_graph_load_context(struct nouveau_channel *);
935extern int nv04_graph_unload_context(struct drm_device *);
936extern void nv04_graph_context_switch(struct drm_device *);
937
938/* nv10_graph.c */
939extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
940extern int nv10_graph_init(struct drm_device *);
941extern void nv10_graph_takedown(struct drm_device *);
942extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
943extern int nv10_graph_create_context(struct nouveau_channel *);
944extern void nv10_graph_destroy_context(struct nouveau_channel *);
945extern int nv10_graph_load_context(struct nouveau_channel *);
946extern int nv10_graph_unload_context(struct drm_device *);
947extern void nv10_graph_context_switch(struct drm_device *);
948
949/* nv20_graph.c */
950extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
951extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
952extern int nv20_graph_create_context(struct nouveau_channel *);
953extern void nv20_graph_destroy_context(struct nouveau_channel *);
954extern int nv20_graph_load_context(struct nouveau_channel *);
955extern int nv20_graph_unload_context(struct drm_device *);
956extern int nv20_graph_init(struct drm_device *);
957extern void nv20_graph_takedown(struct drm_device *);
958extern int nv30_graph_init(struct drm_device *);
959
960/* nv40_graph.c */
961extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
962extern int nv40_graph_init(struct drm_device *);
963extern void nv40_graph_takedown(struct drm_device *);
964extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
965extern int nv40_graph_create_context(struct nouveau_channel *);
966extern void nv40_graph_destroy_context(struct nouveau_channel *);
967extern int nv40_graph_load_context(struct nouveau_channel *);
968extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 969extern void nv40_grctx_init(struct nouveau_grctx *);
6ee73861
BS		 970
971/* nv50_graph.c */
972extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
973extern int nv50_graph_init(struct drm_device *);
974extern void nv50_graph_takedown(struct drm_device *);
975extern void nv50_graph_fifo_access(struct drm_device *, bool);
976extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
977extern int nv50_graph_create_context(struct nouveau_channel *);
978extern void nv50_graph_destroy_context(struct nouveau_channel *);
979extern int nv50_graph_load_context(struct nouveau_channel *);
980extern int nv50_graph_unload_context(struct drm_device *);
981extern void nv50_graph_context_switch(struct drm_device *);
982
054b93e4
BS		 983/* nouveau_grctx.c */
984extern int nouveau_grctx_prog_load(struct drm_device *);
985extern void nouveau_grctx_vals_load(struct drm_device *,
986 struct nouveau_gpuobj *);
987extern void nouveau_grctx_fini(struct drm_device *);
988
6ee73861
BS		 989/* nv04_instmem.c */
990extern int nv04_instmem_init(struct drm_device *);
991extern void nv04_instmem_takedown(struct drm_device *);
992extern int nv04_instmem_suspend(struct drm_device *);
993extern void nv04_instmem_resume(struct drm_device *);
994extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
995 uint32_t *size);
996extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
997extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
998extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
999extern void nv04_instmem_prepare_access(struct drm_device *, bool write);
1000extern void nv04_instmem_finish_access(struct drm_device *);
1001
1002/* nv50_instmem.c */
1003extern int nv50_instmem_init(struct drm_device *);
1004extern void nv50_instmem_takedown(struct drm_device *);
1005extern int nv50_instmem_suspend(struct drm_device *);
1006extern void nv50_instmem_resume(struct drm_device *);
1007extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1008 uint32_t *size);
1009extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1010extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1011extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1012extern void nv50_instmem_prepare_access(struct drm_device *, bool write);
1013extern void nv50_instmem_finish_access(struct drm_device *);
1014
1015/* nv04_mc.c */
1016extern int nv04_mc_init(struct drm_device *);
1017extern void nv04_mc_takedown(struct drm_device *);
1018
1019/* nv40_mc.c */
1020extern int nv40_mc_init(struct drm_device *);
1021extern void nv40_mc_takedown(struct drm_device *);
1022
1023/* nv50_mc.c */
1024extern int nv50_mc_init(struct drm_device *);
1025extern void nv50_mc_takedown(struct drm_device *);
1026
1027/* nv04_timer.c */
1028extern int nv04_timer_init(struct drm_device *);
1029extern uint64_t nv04_timer_read(struct drm_device *);
1030extern void nv04_timer_takedown(struct drm_device *);
1031
1032extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1033 unsigned long arg);
1034
1035/* nv04_dac.c */
1036extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry);
1037extern enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
1038 struct drm_connector *connector);
1039extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1040extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1041
1042/* nv04_dfp.c */
1043extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry);
1044extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1045extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1046 int head, bool dl);
1047extern void nv04_dfp_disable(struct drm_device *dev, int head);
1048extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1049
1050/* nv04_tv.c */
1051extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1052extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1053
1054/* nv17_tv.c */
1055extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1056extern enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder,
1057 struct drm_connector *connector,
1058 uint32_t pin_mask);
1059
1060/* nv04_display.c */
1061extern int nv04_display_create(struct drm_device *);
1062extern void nv04_display_destroy(struct drm_device *);
1063extern void nv04_display_restore(struct drm_device *);
1064
1065/* nv04_crtc.c */
1066extern int nv04_crtc_create(struct drm_device *, int index);
1067
1068/* nouveau_bo.c */
1069extern struct ttm_bo_driver nouveau_bo_driver;
1070extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1071 int size, int align, uint32_t flags,
1072 uint32_t tile_mode, uint32_t tile_flags,
1073 bool no_vm, bool mappable, struct nouveau_bo **);
1074extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1075extern int nouveau_bo_unpin(struct nouveau_bo *);
1076extern int nouveau_bo_map(struct nouveau_bo *);
1077extern void nouveau_bo_unmap(struct nouveau_bo *);
1078extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t memtype);
1079extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1080extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1081extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1082extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1083
1084/* nouveau_fence.c */
1085struct nouveau_fence;
1086extern int nouveau_fence_init(struct nouveau_channel *);
1087extern void nouveau_fence_fini(struct nouveau_channel *);
1088extern void nouveau_fence_update(struct nouveau_channel *);
1089extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1090 bool emit);
1091extern int nouveau_fence_emit(struct nouveau_fence *);
1092struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1093extern bool nouveau_fence_signalled(void *obj, void *arg);
1094extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1095extern int nouveau_fence_flush(void *obj, void *arg);
1096extern void nouveau_fence_unref(void **obj);
1097extern void *nouveau_fence_ref(void *obj);
1098extern void nouveau_fence_handler(struct drm_device *dev, int channel);
1099
1100/* nouveau_gem.c */
1101extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1102 int size, int align, uint32_t flags,
1103 uint32_t tile_mode, uint32_t tile_flags,
1104 bool no_vm, bool mappable, struct nouveau_bo **);
1105extern int nouveau_gem_object_new(struct drm_gem_object *);
1106extern void nouveau_gem_object_del(struct drm_gem_object *);
1107extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1108 struct drm_file *);
1109extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1110 struct drm_file *);
1111extern int nouveau_gem_ioctl_pushbuf_call(struct drm_device *, void *,
1112 struct drm_file *);
1113extern int nouveau_gem_ioctl_pushbuf_call2(struct drm_device *, void *,
1114 struct drm_file *);
1115extern int nouveau_gem_ioctl_pin(struct drm_device *, void *,
1116 struct drm_file *);
1117extern int nouveau_gem_ioctl_unpin(struct drm_device *, void *,
1118 struct drm_file *);
1119extern int nouveau_gem_ioctl_tile(struct drm_device *, void *,
1120 struct drm_file *);
1121extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1122 struct drm_file *);
1123extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1124 struct drm_file *);
1125extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1126 struct drm_file *);
1127
1128/* nv17_gpio.c */
1129int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1130int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1131
1132#ifndef ioread32_native
1133#ifdef __BIG_ENDIAN
1134#define ioread16_native ioread16be
1135#define iowrite16_native iowrite16be
1136#define ioread32_native ioread32be
1137#define iowrite32_native iowrite32be
1138#else /* def __BIG_ENDIAN */
1139#define ioread16_native ioread16
1140#define iowrite16_native iowrite16
1141#define ioread32_native ioread32
1142#define iowrite32_native iowrite32
1143#endif /* def __BIG_ENDIAN else */
1144#endif /* !ioread32_native */
1145
1146/* channel control reg access */
1147static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1148{
1149 return ioread32_native(chan->user + reg);
1150}
1151
1152static inline void nvchan_wr32(struct nouveau_channel *chan,
1153 unsigned reg, u32 val)
1154{
1155 iowrite32_native(val, chan->user + reg);
1156}
1157
1158/* register access */
1159static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1160{
1161 struct drm_nouveau_private *dev_priv = dev->dev_private;
1162 return ioread32_native(dev_priv->mmio + reg);
1163}
1164
1165static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1166{
1167 struct drm_nouveau_private *dev_priv = dev->dev_private;
1168 iowrite32_native(val, dev_priv->mmio + reg);
1169}
1170
1171static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1172{
1173 struct drm_nouveau_private *dev_priv = dev->dev_private;
1174 return ioread8(dev_priv->mmio + reg);
1175}
1176
1177static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1178{
1179 struct drm_nouveau_private *dev_priv = dev->dev_private;
1180 iowrite8(val, dev_priv->mmio + reg);
1181}
1182
1183#define nv_wait(reg, mask, val) \
1184 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1185
1186/* PRAMIN access */
1187static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1188{
1189 struct drm_nouveau_private *dev_priv = dev->dev_private;
1190 return ioread32_native(dev_priv->ramin + offset);
1191}
1192
1193static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1194{
1195 struct drm_nouveau_private *dev_priv = dev->dev_private;
1196 iowrite32_native(val, dev_priv->ramin + offset);
1197}
1198
1199/* object access */
1200static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1201 unsigned index)
1202{
1203 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1204}
1205
1206static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1207 unsigned index, u32 val)
1208{
1209 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1210}
1211
1212/*
1213 * Logging
1214 * Argument d is (struct drm_device *).
1215 */
1216#define NV_PRINTK(level, d, fmt, arg...) \
1217 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1218 pci_name(d->pdev), ##arg)
1219#ifndef NV_DEBUG_NOTRACE
1220#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1221 if (drm_debug & DRM_UT_DRIVER) { \
1222 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1223 __LINE__, ##arg); \
1224 } \
1225} while (0)
1226#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1227 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1228 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1229 __LINE__, ##arg); \
1230 } \
1231} while (0)
1232#else
1233#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1234 if (drm_debug & DRM_UT_DRIVER) \
1235 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1236} while (0)
1237#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1238 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1239 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1240} while (0)
1241#endif
1242#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1243#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1244#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1245#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1246#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1247
1248/* nouveau_reg_debug bitmask */
1249enum {
1250 NOUVEAU_REG_DEBUG_MC = 0x1,
1251 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1252 NOUVEAU_REG_DEBUG_FB = 0x4,
1253 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1254 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1255 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1256 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1257 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1258 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1259 NOUVEAU_REG_DEBUG_EVO = 0x200,
1260};
1261
1262#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1263 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1264 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1265} while (0)
1266
1267static inline bool
1268nv_two_heads(struct drm_device *dev)
1269{
1270 struct drm_nouveau_private *dev_priv = dev->dev_private;
1271 const int impl = dev->pci_device & 0x0ff0;
1272
1273 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1274 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1275 return true;
1276
1277 return false;
1278}
1279
1280static inline bool
1281nv_gf4_disp_arch(struct drm_device *dev)
1282{
1283 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1284}
1285
1286static inline bool
1287nv_two_reg_pll(struct drm_device *dev)
1288{
1289 struct drm_nouveau_private *dev_priv = dev->dev_private;
1290 const int impl = dev->pci_device & 0x0ff0;
1291
1292 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1293 return true;
1294 return false;
1295}
1296
1297#define NV50_NVSW 0x0000506e
1298#define NV50_NVSW_DMA_SEMAPHORE 0x00000060
1299#define NV50_NVSW_SEMAPHORE_OFFSET 0x00000064
1300#define NV50_NVSW_SEMAPHORE_ACQUIRE 0x00000068
1301#define NV50_NVSW_SEMAPHORE_RELEASE 0x0000006c
1302#define NV50_NVSW_DMA_VBLSEM 0x0000018c
1303#define NV50_NVSW_VBLSEM_OFFSET 0x00000400
1304#define NV50_NVSW_VBLSEM_RELEASE_VALUE 0x00000404
1305#define NV50_NVSW_VBLSEM_RELEASE 0x00000408
1306
1307#endif /* __NOUVEAU_DRV_H__ */
Linux kernel - Deliverables
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