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1 | /* |
2 | * Copyright 2006 Dave Airlie | |
3 | * Copyright 2007 Maarten Maathuis | |
4 | * Copyright 2007-2009 Stuart Bennett | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
20 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF | |
21 | * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
22 | * SOFTWARE. | |
23 | */ | |
24 | ||
760285e7 | 25 | #include <drm/drmP.h> |
77145f1c | 26 | #include "nouveau_drm.h" |
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27 | #include "nouveau_hw.h" |
28 | ||
70790f4f | 29 | #include <subdev/bios/pll.h> |
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30 | #include <subdev/clock.h> |
31 | #include <subdev/timer.h> | |
70790f4f | 32 | |
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33 | #define CHIPSET_NFORCE 0x01a0 |
34 | #define CHIPSET_NFORCE2 0x01f0 | |
35 | ||
36 | /* | |
37 | * misc hw access wrappers/control functions | |
38 | */ | |
39 | ||
40 | void | |
41 | NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value) | |
42 | { | |
43 | NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); | |
44 | NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value); | |
45 | } | |
46 | ||
47 | uint8_t | |
48 | NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index) | |
49 | { | |
50 | NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); | |
51 | return NVReadPRMVIO(dev, head, NV_PRMVIO_SR); | |
52 | } | |
53 | ||
54 | void | |
55 | NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value) | |
56 | { | |
57 | NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); | |
58 | NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value); | |
59 | } | |
60 | ||
61 | uint8_t | |
62 | NVReadVgaGr(struct drm_device *dev, int head, uint8_t index) | |
63 | { | |
64 | NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); | |
65 | return NVReadPRMVIO(dev, head, NV_PRMVIO_GX); | |
66 | } | |
67 | ||
68 | /* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied) | |
69 | * it affects only the 8 bit vga io regs, which we access using mmio at | |
70 | * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d* | |
71 | * in general, the set value of cr44 does not matter: reg access works as | |
72 | * expected and values can be set for the appropriate head by using a 0x2000 | |
73 | * offset as required | |
74 | * however: | |
75 | * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and | |
76 | * cr44 must be set to 0 or 3 for accessing values on the correct head | |
77 | * through the common 0xc03c* addresses | |
78 | * b) in tied mode (4) head B is programmed to the values set on head A, and | |
79 | * access using the head B addresses can have strange results, ergo we leave | |
80 | * tied mode in init once we know to what cr44 should be restored on exit | |
81 | * | |
82 | * the owner parameter is slightly abused: | |
83 | * 0 and 1 are treated as head values and so the set value is (owner * 3) | |
84 | * other values are treated as literal values to set | |
85 | */ | |
86 | void | |
87 | NVSetOwner(struct drm_device *dev, int owner) | |
88 | { | |
77145f1c | 89 | struct nouveau_drm *drm = nouveau_drm(dev); |
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90 | |
91 | if (owner == 1) | |
92 | owner *= 3; | |
93 | ||
77145f1c | 94 | if (nv_device(drm->device)->chipset == 0x11) { |
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95 | /* This might seem stupid, but the blob does it and |
96 | * omitting it often locks the system up. | |
97 | */ | |
98 | NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX); | |
99 | NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX); | |
100 | } | |
101 | ||
102 | /* CR44 is always changed on CRTC0 */ | |
103 | NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner); | |
104 | ||
77145f1c | 105 | if (nv_device(drm->device)->chipset == 0x11) { /* set me harder */ |
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106 | NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); |
107 | NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); | |
108 | } | |
109 | } | |
110 | ||
111 | void | |
112 | NVBlankScreen(struct drm_device *dev, int head, bool blank) | |
113 | { | |
114 | unsigned char seq1; | |
115 | ||
116 | if (nv_two_heads(dev)) | |
117 | NVSetOwner(dev, head); | |
118 | ||
119 | seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); | |
120 | ||
121 | NVVgaSeqReset(dev, head, true); | |
122 | if (blank) | |
123 | NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); | |
124 | else | |
125 | NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); | |
126 | NVVgaSeqReset(dev, head, false); | |
127 | } | |
128 | ||
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129 | /* |
130 | * PLL getting | |
131 | */ | |
132 | ||
133 | static void | |
134 | nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, | |
135 | uint32_t pll2, struct nouveau_pll_vals *pllvals) | |
136 | { | |
77145f1c | 137 | struct nouveau_drm *drm = nouveau_drm(dev); |
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138 | |
139 | /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ | |
140 | ||
141 | /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */ | |
142 | pllvals->log2P = (pll1 >> 16) & 0x7; | |
143 | pllvals->N2 = pllvals->M2 = 1; | |
144 | ||
145 | if (reg1 <= 0x405c) { | |
146 | pllvals->NM1 = pll2 & 0xffff; | |
147 | /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */ | |
148 | if (!(pll1 & 0x1100)) | |
149 | pllvals->NM2 = pll2 >> 16; | |
150 | } else { | |
151 | pllvals->NM1 = pll1 & 0xffff; | |
152 | if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) | |
153 | pllvals->NM2 = pll2 & 0xffff; | |
77145f1c | 154 | else if (nv_device(drm->device)->chipset == 0x30 || nv_device(drm->device)->chipset == 0x35) { |
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155 | pllvals->M1 &= 0xf; /* only 4 bits */ |
156 | if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { | |
157 | pllvals->M2 = (pll1 >> 4) & 0x7; | |
158 | pllvals->N2 = ((pll1 >> 21) & 0x18) | | |
159 | ((pll1 >> 19) & 0x7); | |
160 | } | |
161 | } | |
162 | } | |
163 | } | |
164 | ||
165 | int | |
70790f4f | 166 | nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype, |
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167 | struct nouveau_pll_vals *pllvals) |
168 | { | |
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169 | struct nouveau_drm *drm = nouveau_drm(dev); |
170 | struct nouveau_device *device = nv_device(drm->device); | |
171 | struct nouveau_bios *bios = nouveau_bios(device); | |
172 | uint32_t reg1, pll1, pll2 = 0; | |
70790f4f | 173 | struct nvbios_pll pll_lim; |
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174 | int ret; |
175 | ||
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176 | ret = nvbios_pll_parse(bios, plltype, &pll_lim); |
177 | if (ret || !(reg1 = pll_lim.reg)) | |
442b626e | 178 | return -ENOENT; |
6ee73861 | 179 | |
77145f1c | 180 | pll1 = nv_rd32(device, reg1); |
6ee73861 | 181 | if (reg1 <= 0x405c) |
77145f1c | 182 | pll2 = nv_rd32(device, reg1 + 4); |
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183 | else if (nv_two_reg_pll(dev)) { |
184 | uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); | |
185 | ||
77145f1c | 186 | pll2 = nv_rd32(device, reg2); |
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187 | } |
188 | ||
77145f1c | 189 | if (nv_device(drm->device)->card_type == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) { |
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190 | uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580); |
191 | ||
192 | /* check whether vpll has been forced into single stage mode */ | |
193 | if (reg1 == NV_PRAMDAC_VPLL_COEFF) { | |
194 | if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE) | |
195 | pll2 = 0; | |
196 | } else | |
197 | if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE) | |
198 | pll2 = 0; | |
199 | } | |
200 | ||
201 | nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals); | |
6ee73861 | 202 | pllvals->refclk = pll_lim.refclk; |
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203 | return 0; |
204 | } | |
205 | ||
206 | int | |
207 | nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pv) | |
208 | { | |
209 | /* Avoid divide by zero if called at an inappropriate time */ | |
210 | if (!pv->M1 || !pv->M2) | |
211 | return 0; | |
212 | ||
213 | return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; | |
214 | } | |
215 | ||
216 | int | |
70790f4f | 217 | nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype) |
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218 | { |
219 | struct nouveau_pll_vals pllvals; | |
442b626e | 220 | int ret; |
6ee73861 | 221 | |
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222 | if (plltype == PLL_MEMORY && |
223 | (dev->pci_device & 0x0ff0) == CHIPSET_NFORCE) { | |
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224 | uint32_t mpllP; |
225 | ||
226 | pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP); | |
227 | if (!mpllP) | |
228 | mpllP = 4; | |
229 | ||
230 | return 400000 / mpllP; | |
231 | } else | |
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232 | if (plltype == PLL_MEMORY && |
233 | (dev->pci_device & 0xff0) == CHIPSET_NFORCE2) { | |
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234 | uint32_t clock; |
235 | ||
236 | pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock); | |
237 | return clock; | |
238 | } | |
239 | ||
442b626e BS |
240 | ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals); |
241 | if (ret) | |
242 | return ret; | |
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243 | |
244 | return nouveau_hw_pllvals_to_clk(&pllvals); | |
245 | } | |
246 | ||
247 | static void | |
248 | nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head) | |
249 | { | |
250 | /* the vpll on an unused head can come up with a random value, way | |
251 | * beyond the pll limits. for some reason this causes the chip to | |
252 | * lock up when reading the dac palette regs, so set a valid pll here | |
253 | * when such a condition detected. only seen on nv11 to date | |
254 | */ | |
255 | ||
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256 | struct nouveau_drm *drm = nouveau_drm(dev); |
257 | struct nouveau_device *device = nv_device(drm->device); | |
258 | struct nouveau_clock *clk = nouveau_clock(device); | |
259 | struct nouveau_bios *bios = nouveau_bios(device); | |
70790f4f | 260 | struct nvbios_pll pll_lim; |
6ee73861 | 261 | struct nouveau_pll_vals pv; |
70790f4f | 262 | enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0; |
6ee73861 | 263 | |
77145f1c | 264 | if (nvbios_pll_parse(bios, pll, &pll_lim)) |
6ee73861 | 265 | return; |
5eb94fbb | 266 | nouveau_hw_get_pllvals(dev, pll, &pv); |
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267 | |
268 | if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m && | |
269 | pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n && | |
70790f4f | 270 | pv.log2P <= pll_lim.max_p) |
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271 | return; |
272 | ||
77145f1c | 273 | NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1); |
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274 | |
275 | /* set lowest clock within static limits */ | |
276 | pv.M1 = pll_lim.vco1.max_m; | |
277 | pv.N1 = pll_lim.vco1.min_n; | |
70790f4f | 278 | pv.log2P = pll_lim.max_p_usable; |
77145f1c | 279 | clk->pll_prog(clk, pll_lim.reg, &pv); |
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280 | } |
281 | ||
282 | /* | |
283 | * vga font save/restore | |
284 | */ | |
285 | ||
286 | static void nouveau_vga_font_io(struct drm_device *dev, | |
287 | void __iomem *iovram, | |
288 | bool save, unsigned plane) | |
289 | { | |
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290 | unsigned i; |
291 | ||
292 | NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane); | |
293 | NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane); | |
294 | for (i = 0; i < 16384; i++) { | |
295 | if (save) { | |
017e6e29 | 296 | nv04_display(dev)->saved_vga_font[plane][i] = |
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297 | ioread32_native(iovram + i * 4); |
298 | } else { | |
017e6e29 | 299 | iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i], |
6ee73861 BS |
300 | iovram + i * 4); |
301 | } | |
302 | } | |
303 | } | |
304 | ||
305 | void | |
306 | nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save) | |
307 | { | |
77145f1c | 308 | struct nouveau_drm *drm = nouveau_drm(dev); |
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309 | uint8_t misc, gr4, gr5, gr6, seq2, seq4; |
310 | bool graphicsmode; | |
311 | unsigned plane; | |
312 | void __iomem *iovram; | |
313 | ||
314 | if (nv_two_heads(dev)) | |
315 | NVSetOwner(dev, 0); | |
316 | ||
317 | NVSetEnablePalette(dev, 0, true); | |
318 | graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1; | |
319 | NVSetEnablePalette(dev, 0, false); | |
320 | ||
321 | if (graphicsmode) /* graphics mode => framebuffer => no need to save */ | |
322 | return; | |
323 | ||
77145f1c | 324 | NV_INFO(drm, "%sing VGA fonts\n", save ? "Sav" : "Restor"); |
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325 | |
326 | /* map first 64KiB of VRAM, holds VGA fonts etc */ | |
327 | iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536); | |
328 | if (!iovram) { | |
77145f1c | 329 | NV_ERROR(drm, "Failed to map VRAM, " |
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330 | "cannot save/restore VGA fonts.\n"); |
331 | return; | |
332 | } | |
333 | ||
334 | if (nv_two_heads(dev)) | |
335 | NVBlankScreen(dev, 1, true); | |
336 | NVBlankScreen(dev, 0, true); | |
337 | ||
338 | /* save control regs */ | |
339 | misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ); | |
340 | seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX); | |
341 | seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX); | |
342 | gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX); | |
343 | gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX); | |
344 | gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX); | |
345 | ||
346 | NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67); | |
347 | NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6); | |
348 | NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0); | |
349 | NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5); | |
350 | ||
351 | /* store font in planes 0..3 */ | |
352 | for (plane = 0; plane < 4; plane++) | |
353 | nouveau_vga_font_io(dev, iovram, save, plane); | |
354 | ||
355 | /* restore control regs */ | |
356 | NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc); | |
357 | NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4); | |
358 | NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5); | |
359 | NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6); | |
360 | NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2); | |
361 | NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4); | |
362 | ||
363 | if (nv_two_heads(dev)) | |
364 | NVBlankScreen(dev, 1, false); | |
365 | NVBlankScreen(dev, 0, false); | |
366 | ||
367 | iounmap(iovram); | |
368 | } | |
369 | ||
370 | /* | |
371 | * mode state save/load | |
372 | */ | |
373 | ||
374 | static void | |
375 | rd_cio_state(struct drm_device *dev, int head, | |
376 | struct nv04_crtc_reg *crtcstate, int index) | |
377 | { | |
378 | crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index); | |
379 | } | |
380 | ||
381 | static void | |
382 | wr_cio_state(struct drm_device *dev, int head, | |
383 | struct nv04_crtc_reg *crtcstate, int index) | |
384 | { | |
385 | NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); | |
386 | } | |
387 | ||
388 | static void | |
389 | nv_save_state_ramdac(struct drm_device *dev, int head, | |
390 | struct nv04_mode_state *state) | |
391 | { | |
77145f1c | 392 | struct nouveau_drm *drm = nouveau_drm(dev); |
6ee73861 BS |
393 | struct nv04_crtc_reg *regp = &state->crtc_reg[head]; |
394 | int i; | |
395 | ||
77145f1c | 396 | if (nv_device(drm->device)->card_type >= NV_10) |
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397 | regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); |
398 | ||
855a95e4 | 399 | nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals); |
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400 | state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT); |
401 | if (nv_two_heads(dev)) | |
402 | state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); | |
77145f1c | 403 | if (nv_device(drm->device)->chipset == 0x11) |
6ee73861 BS |
404 | regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); |
405 | ||
406 | regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); | |
407 | ||
408 | if (nv_gf4_disp_arch(dev)) | |
409 | regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); | |
77145f1c | 410 | if (nv_device(drm->device)->chipset >= 0x30) |
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411 | regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); |
412 | ||
413 | regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); | |
414 | regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL); | |
415 | regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW); | |
416 | regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY); | |
417 | regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL); | |
418 | regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW); | |
419 | regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY); | |
420 | regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2); | |
421 | ||
422 | for (i = 0; i < 7; i++) { | |
423 | uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); | |
424 | regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); | |
425 | regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20); | |
426 | } | |
427 | ||
428 | if (nv_gf4_disp_arch(dev)) { | |
429 | regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER); | |
430 | for (i = 0; i < 3; i++) { | |
431 | regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4); | |
432 | regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4); | |
433 | } | |
434 | } | |
435 | ||
436 | regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); | |
437 | regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0); | |
438 | if (!nv_gf4_disp_arch(dev) && head == 0) { | |
439 | /* early chips don't allow access to PRAMDAC_TMDS_* without | |
440 | * the head A FPCLK on (nv11 even locks up) */ | |
441 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 & | |
442 | ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK); | |
443 | } | |
444 | regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1); | |
445 | regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2); | |
446 | ||
447 | regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR); | |
448 | ||
449 | if (nv_gf4_disp_arch(dev)) | |
450 | regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); | |
451 | ||
77145f1c | 452 | if (nv_device(drm->device)->card_type == NV_40) { |
6ee73861 BS |
453 | regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); |
454 | regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); | |
455 | regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); | |
456 | ||
457 | for (i = 0; i < 38; i++) | |
458 | regp->ctv_regs[i] = NVReadRAMDAC(dev, head, | |
459 | NV_PRAMDAC_CTV + 4*i); | |
460 | } | |
461 | } | |
462 | ||
463 | static void | |
464 | nv_load_state_ramdac(struct drm_device *dev, int head, | |
465 | struct nv04_mode_state *state) | |
466 | { | |
77145f1c BS |
467 | struct nouveau_drm *drm = nouveau_drm(dev); |
468 | struct nouveau_clock *clk = nouveau_clock(drm->device); | |
6ee73861 BS |
469 | struct nv04_crtc_reg *regp = &state->crtc_reg[head]; |
470 | uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; | |
471 | int i; | |
472 | ||
77145f1c | 473 | if (nv_device(drm->device)->card_type >= NV_10) |
6ee73861 BS |
474 | NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); |
475 | ||
77145f1c | 476 | clk->pll_prog(clk, pllreg, ®p->pllvals); |
6ee73861 BS |
477 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel); |
478 | if (nv_two_heads(dev)) | |
479 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk); | |
77145f1c | 480 | if (nv_device(drm->device)->chipset == 0x11) |
6ee73861 BS |
481 | NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); |
482 | ||
483 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); | |
484 | ||
485 | if (nv_gf4_disp_arch(dev)) | |
486 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); | |
77145f1c | 487 | if (nv_device(drm->device)->chipset >= 0x30) |
6ee73861 BS |
488 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); |
489 | ||
490 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); | |
491 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal); | |
492 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew); | |
493 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay); | |
494 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal); | |
495 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew); | |
496 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay); | |
497 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2); | |
498 | ||
499 | for (i = 0; i < 7; i++) { | |
500 | uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); | |
501 | ||
502 | NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); | |
503 | NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]); | |
504 | } | |
505 | ||
506 | if (nv_gf4_disp_arch(dev)) { | |
507 | NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither); | |
508 | for (i = 0; i < 3; i++) { | |
509 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]); | |
510 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]); | |
511 | } | |
512 | } | |
513 | ||
514 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control); | |
515 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0); | |
516 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1); | |
517 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2); | |
518 | ||
519 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color); | |
520 | ||
521 | if (nv_gf4_disp_arch(dev)) | |
522 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); | |
523 | ||
77145f1c | 524 | if (nv_device(drm->device)->card_type == NV_40) { |
6ee73861 BS |
525 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); |
526 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); | |
527 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); | |
528 | ||
529 | for (i = 0; i < 38; i++) | |
530 | NVWriteRAMDAC(dev, head, | |
531 | NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]); | |
532 | } | |
533 | } | |
534 | ||
535 | static void | |
536 | nv_save_state_vga(struct drm_device *dev, int head, | |
537 | struct nv04_mode_state *state) | |
538 | { | |
539 | struct nv04_crtc_reg *regp = &state->crtc_reg[head]; | |
540 | int i; | |
541 | ||
542 | regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ); | |
543 | ||
544 | for (i = 0; i < 25; i++) | |
545 | rd_cio_state(dev, head, regp, i); | |
546 | ||
547 | NVSetEnablePalette(dev, head, true); | |
548 | for (i = 0; i < 21; i++) | |
549 | regp->Attribute[i] = NVReadVgaAttr(dev, head, i); | |
550 | NVSetEnablePalette(dev, head, false); | |
551 | ||
552 | for (i = 0; i < 9; i++) | |
553 | regp->Graphics[i] = NVReadVgaGr(dev, head, i); | |
554 | ||
555 | for (i = 0; i < 5; i++) | |
556 | regp->Sequencer[i] = NVReadVgaSeq(dev, head, i); | |
557 | } | |
558 | ||
559 | static void | |
560 | nv_load_state_vga(struct drm_device *dev, int head, | |
561 | struct nv04_mode_state *state) | |
562 | { | |
563 | struct nv04_crtc_reg *regp = &state->crtc_reg[head]; | |
564 | int i; | |
565 | ||
566 | NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg); | |
567 | ||
568 | for (i = 0; i < 5; i++) | |
569 | NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]); | |
570 | ||
571 | nv_lock_vga_crtc_base(dev, head, false); | |
572 | for (i = 0; i < 25; i++) | |
573 | wr_cio_state(dev, head, regp, i); | |
574 | nv_lock_vga_crtc_base(dev, head, true); | |
575 | ||
576 | for (i = 0; i < 9; i++) | |
577 | NVWriteVgaGr(dev, head, i, regp->Graphics[i]); | |
578 | ||
579 | NVSetEnablePalette(dev, head, true); | |
580 | for (i = 0; i < 21; i++) | |
581 | NVWriteVgaAttr(dev, head, i, regp->Attribute[i]); | |
582 | NVSetEnablePalette(dev, head, false); | |
583 | } | |
584 | ||
585 | static void | |
586 | nv_save_state_ext(struct drm_device *dev, int head, | |
587 | struct nv04_mode_state *state) | |
588 | { | |
77145f1c | 589 | struct nouveau_drm *drm = nouveau_drm(dev); |
6ee73861 BS |
590 | struct nv04_crtc_reg *regp = &state->crtc_reg[head]; |
591 | int i; | |
592 | ||
593 | rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); | |
594 | rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); | |
595 | rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); | |
596 | rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); | |
597 | rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); | |
598 | rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); | |
599 | rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); | |
600 | ||
601 | rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); | |
602 | rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); | |
603 | rd_cio_state(dev, head, regp, NV_CIO_CRE_21); | |
4a9f822f | 604 | |
77145f1c | 605 | if (nv_device(drm->device)->card_type >= NV_20) |
6ee73861 | 606 | rd_cio_state(dev, head, regp, NV_CIO_CRE_47); |
4295f188 | 607 | |
77145f1c | 608 | if (nv_device(drm->device)->card_type >= NV_30) |
4a9f822f | 609 | rd_cio_state(dev, head, regp, 0x9f); |
4a9f822f | 610 | |
6ee73861 BS |
611 | rd_cio_state(dev, head, regp, NV_CIO_CRE_49); |
612 | rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); | |
613 | rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); | |
614 | rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); | |
615 | rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); | |
616 | ||
77145f1c | 617 | if (nv_device(drm->device)->card_type >= NV_10) { |
6ee73861 BS |
618 | regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); |
619 | regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); | |
620 | ||
77145f1c | 621 | if (nv_device(drm->device)->card_type >= NV_30) |
6ee73861 BS |
622 | regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); |
623 | ||
77145f1c | 624 | if (nv_device(drm->device)->card_type == NV_40) |
6ee73861 BS |
625 | regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); |
626 | ||
627 | if (nv_two_heads(dev)) | |
628 | regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL); | |
629 | regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG); | |
630 | } | |
631 | ||
632 | regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG); | |
633 | ||
634 | rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); | |
635 | rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); | |
77145f1c | 636 | if (nv_device(drm->device)->card_type >= NV_10) { |
6ee73861 BS |
637 | rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); |
638 | rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB); | |
639 | rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); | |
640 | rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); | |
641 | } | |
642 | /* NV11 and NV20 don't have this, they stop at 0x52. */ | |
643 | if (nv_gf4_disp_arch(dev)) { | |
c1003d9c | 644 | rd_cio_state(dev, head, regp, NV_CIO_CRE_42); |
6ee73861 BS |
645 | rd_cio_state(dev, head, regp, NV_CIO_CRE_53); |
646 | rd_cio_state(dev, head, regp, NV_CIO_CRE_54); | |
647 | ||
648 | for (i = 0; i < 0x10; i++) | |
649 | regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i); | |
650 | rd_cio_state(dev, head, regp, NV_CIO_CRE_59); | |
651 | rd_cio_state(dev, head, regp, NV_CIO_CRE_5B); | |
652 | ||
653 | rd_cio_state(dev, head, regp, NV_CIO_CRE_85); | |
654 | rd_cio_state(dev, head, regp, NV_CIO_CRE_86); | |
655 | } | |
656 | ||
657 | regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START); | |
658 | } | |
659 | ||
660 | static void | |
661 | nv_load_state_ext(struct drm_device *dev, int head, | |
662 | struct nv04_mode_state *state) | |
663 | { | |
77145f1c BS |
664 | struct nouveau_drm *drm = nouveau_drm(dev); |
665 | struct nouveau_device *device = nv_device(drm->device); | |
666 | struct nouveau_timer *ptimer = nouveau_timer(device); | |
6ee73861 BS |
667 | struct nv04_crtc_reg *regp = &state->crtc_reg[head]; |
668 | uint32_t reg900; | |
669 | int i; | |
670 | ||
77145f1c | 671 | if (nv_device(drm->device)->card_type >= NV_10) { |
6ee73861 BS |
672 | if (nv_two_heads(dev)) |
673 | /* setting ENGINE_CTRL (EC) *must* come before | |
674 | * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in | |
675 | * EC that should not be overwritten by writing stale EC | |
676 | */ | |
677 | NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl); | |
678 | ||
77145f1c BS |
679 | nv_wr32(device, NV_PVIDEO_STOP, 1); |
680 | nv_wr32(device, NV_PVIDEO_INTR_EN, 0); | |
681 | nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0); | |
682 | nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0); | |
683 | nv_wr32(device, NV_PVIDEO_LIMIT(0), 0); //drm->fb_available_size - 1); | |
684 | nv_wr32(device, NV_PVIDEO_LIMIT(1), 0); //drm->fb_available_size - 1); | |
685 | nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), 0); //drm->fb_available_size - 1); | |
686 | nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), 0); //drm->fb_available_size - 1); | |
687 | nv_wr32(device, NV_PBUS_POWERCTRL_2, 0); | |
6ee73861 BS |
688 | |
689 | NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); | |
690 | NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); | |
691 | NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); | |
692 | ||
77145f1c | 693 | if (nv_device(drm->device)->card_type >= NV_30) |
6ee73861 BS |
694 | NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); |
695 | ||
77145f1c | 696 | if (nv_device(drm->device)->card_type == NV_40) { |
6ee73861 BS |
697 | NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); |
698 | ||
699 | reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900); | |
63f7fcfe | 700 | if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC) |
6ee73861 BS |
701 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000); |
702 | else | |
703 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000); | |
704 | } | |
705 | } | |
706 | ||
707 | NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg); | |
708 | ||
709 | wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); | |
710 | wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); | |
711 | wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); | |
712 | wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); | |
713 | wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); | |
714 | wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); | |
715 | wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); | |
716 | wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); | |
717 | wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); | |
4a9f822f | 718 | |
77145f1c | 719 | if (nv_device(drm->device)->card_type >= NV_20) |
6ee73861 | 720 | wr_cio_state(dev, head, regp, NV_CIO_CRE_47); |
4295f188 | 721 | |
77145f1c | 722 | if (nv_device(drm->device)->card_type >= NV_30) |
4a9f822f | 723 | wr_cio_state(dev, head, regp, 0x9f); |
6ee73861 BS |
724 | |
725 | wr_cio_state(dev, head, regp, NV_CIO_CRE_49); | |
726 | wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); | |
727 | wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); | |
728 | wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); | |
77145f1c | 729 | if (nv_device(drm->device)->card_type == NV_40) |
6ee73861 BS |
730 | nv_fix_nv40_hw_cursor(dev, head); |
731 | wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); | |
732 | ||
733 | wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); | |
734 | wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); | |
77145f1c | 735 | if (nv_device(drm->device)->card_type >= NV_10) { |
6ee73861 BS |
736 | wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); |
737 | wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB); | |
738 | wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); | |
739 | wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); | |
740 | } | |
741 | /* NV11 and NV20 stop at 0x52. */ | |
742 | if (nv_gf4_disp_arch(dev)) { | |
77145f1c | 743 | if (nv_device(drm->device)->card_type == NV_10) { |
6ee73861 BS |
744 | /* Not waiting for vertical retrace before modifying |
745 | CRE_53/CRE_54 causes lockups. */ | |
77145f1c BS |
746 | nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8); |
747 | nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0); | |
6ee73861 BS |
748 | } |
749 | ||
c1003d9c | 750 | wr_cio_state(dev, head, regp, NV_CIO_CRE_42); |
6ee73861 BS |
751 | wr_cio_state(dev, head, regp, NV_CIO_CRE_53); |
752 | wr_cio_state(dev, head, regp, NV_CIO_CRE_54); | |
753 | ||
754 | for (i = 0; i < 0x10; i++) | |
755 | NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); | |
756 | wr_cio_state(dev, head, regp, NV_CIO_CRE_59); | |
757 | wr_cio_state(dev, head, regp, NV_CIO_CRE_5B); | |
758 | ||
759 | wr_cio_state(dev, head, regp, NV_CIO_CRE_85); | |
760 | wr_cio_state(dev, head, regp, NV_CIO_CRE_86); | |
761 | } | |
762 | ||
763 | NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start); | |
6ee73861 BS |
764 | } |
765 | ||
766 | static void | |
767 | nv_save_state_palette(struct drm_device *dev, int head, | |
768 | struct nv04_mode_state *state) | |
769 | { | |
77145f1c | 770 | struct nouveau_device *device = nouveau_dev(dev); |
6ee73861 BS |
771 | int head_offset = head * NV_PRMDIO_SIZE, i; |
772 | ||
77145f1c | 773 | nv_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, |
6ee73861 | 774 | NV_PRMDIO_PIXEL_MASK_MASK); |
77145f1c | 775 | nv_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0); |
6ee73861 BS |
776 | |
777 | for (i = 0; i < 768; i++) { | |
77145f1c | 778 | state->crtc_reg[head].DAC[i] = nv_rd08(device, |
6ee73861 BS |
779 | NV_PRMDIO_PALETTE_DATA + head_offset); |
780 | } | |
781 | ||
782 | NVSetEnablePalette(dev, head, false); | |
783 | } | |
784 | ||
785 | void | |
786 | nouveau_hw_load_state_palette(struct drm_device *dev, int head, | |
787 | struct nv04_mode_state *state) | |
788 | { | |
77145f1c | 789 | struct nouveau_device *device = nouveau_dev(dev); |
6ee73861 BS |
790 | int head_offset = head * NV_PRMDIO_SIZE, i; |
791 | ||
77145f1c | 792 | nv_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, |
6ee73861 | 793 | NV_PRMDIO_PIXEL_MASK_MASK); |
77145f1c | 794 | nv_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0); |
6ee73861 BS |
795 | |
796 | for (i = 0; i < 768; i++) { | |
77145f1c | 797 | nv_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset, |
6ee73861 BS |
798 | state->crtc_reg[head].DAC[i]); |
799 | } | |
800 | ||
801 | NVSetEnablePalette(dev, head, false); | |
802 | } | |
803 | ||
804 | void nouveau_hw_save_state(struct drm_device *dev, int head, | |
805 | struct nv04_mode_state *state) | |
806 | { | |
77145f1c | 807 | struct nouveau_drm *drm = nouveau_drm(dev); |
6ee73861 | 808 | |
77145f1c | 809 | if (nv_device(drm->device)->chipset == 0x11) |
6ee73861 BS |
810 | /* NB: no attempt is made to restore the bad pll later on */ |
811 | nouveau_hw_fix_bad_vpll(dev, head); | |
812 | nv_save_state_ramdac(dev, head, state); | |
813 | nv_save_state_vga(dev, head, state); | |
814 | nv_save_state_palette(dev, head, state); | |
815 | nv_save_state_ext(dev, head, state); | |
816 | } | |
817 | ||
818 | void nouveau_hw_load_state(struct drm_device *dev, int head, | |
819 | struct nv04_mode_state *state) | |
820 | { | |
821 | NVVgaProtect(dev, head, true); | |
822 | nv_load_state_ramdac(dev, head, state); | |
823 | nv_load_state_ext(dev, head, state); | |
824 | nouveau_hw_load_state_palette(dev, head, state); | |
825 | nv_load_state_vga(dev, head, state); | |
826 | NVVgaProtect(dev, head, false); | |
827 | } |