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6ee73861 BS |
1 | /* |
2 | * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. | |
3 | * Copyright 2005 Stephane Marchesin | |
4 | * | |
5 | * The Weather Channel (TM) funded Tungsten Graphics to develop the | |
6 | * initial release of the Radeon 8500 driver under the XFree86 license. | |
7 | * This notice must be preserved. | |
8 | * | |
9 | * Permission is hereby granted, free of charge, to any person obtaining a | |
10 | * copy of this software and associated documentation files (the "Software"), | |
11 | * to deal in the Software without restriction, including without limitation | |
12 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
13 | * and/or sell copies of the Software, and to permit persons to whom the | |
14 | * Software is furnished to do so, subject to the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the next | |
17 | * paragraph) shall be included in all copies or substantial portions of the | |
18 | * Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
23 | * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
24 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
25 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
26 | * DEALINGS IN THE SOFTWARE. | |
27 | * | |
28 | * Authors: | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | */ | |
31 | ||
32 | ||
33 | #include "drmP.h" | |
34 | #include "drm.h" | |
35 | #include "drm_sarea.h" | |
6ee73861 | 36 | |
cbab95db FJ |
37 | #include "nouveau_drv.h" |
38 | #include "nouveau_pm.h" | |
573a2a37 | 39 | #include "nouveau_mm.h" |
a11c3198 | 40 | #include "nouveau_vm.h" |
a845fff8 | 41 | |
a0af9add FJ |
42 | /* |
43 | * NV10-NV40 tiling helpers | |
44 | */ | |
45 | ||
46 | static void | |
a5cf68b0 FJ |
47 | nv10_mem_update_tile_region(struct drm_device *dev, |
48 | struct nouveau_tile_reg *tile, uint32_t addr, | |
49 | uint32_t size, uint32_t pitch, uint32_t flags) | |
a0af9add FJ |
50 | { |
51 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
52 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; | |
53 | struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; | |
54 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; | |
a5cf68b0 FJ |
55 | int i = tile - dev_priv->tile.reg; |
56 | unsigned long save; | |
a0af9add | 57 | |
382d62e5 | 58 | nouveau_fence_unref(&tile->fence); |
a0af9add | 59 | |
a5cf68b0 FJ |
60 | if (tile->pitch) |
61 | pfb->free_tile_region(dev, i); | |
62 | ||
63 | if (pitch) | |
64 | pfb->init_tile_region(dev, i, addr, size, pitch, flags); | |
65 | ||
66 | spin_lock_irqsave(&dev_priv->context_switch_lock, save); | |
a0af9add | 67 | pfifo->reassign(dev, false); |
a0af9add FJ |
68 | pfifo->cache_pull(dev, false); |
69 | ||
70 | nouveau_wait_for_idle(dev); | |
71 | ||
a5cf68b0 FJ |
72 | pfb->set_tile_region(dev, i); |
73 | pgraph->set_tile_region(dev, i); | |
a0af9add FJ |
74 | |
75 | pfifo->cache_pull(dev, true); | |
76 | pfifo->reassign(dev, true); | |
a5cf68b0 | 77 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, save); |
a0af9add FJ |
78 | } |
79 | ||
a5cf68b0 FJ |
80 | static struct nouveau_tile_reg * |
81 | nv10_mem_get_tile_region(struct drm_device *dev, int i) | |
a0af9add FJ |
82 | { |
83 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
a5cf68b0 | 84 | struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; |
a0af9add | 85 | |
a5cf68b0 | 86 | spin_lock(&dev_priv->tile.lock); |
a0af9add | 87 | |
a5cf68b0 FJ |
88 | if (!tile->used && |
89 | (!tile->fence || nouveau_fence_signalled(tile->fence))) | |
90 | tile->used = true; | |
91 | else | |
92 | tile = NULL; | |
a0af9add | 93 | |
a5cf68b0 FJ |
94 | spin_unlock(&dev_priv->tile.lock); |
95 | return tile; | |
96 | } | |
a0af9add | 97 | |
a5cf68b0 FJ |
98 | void |
99 | nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_tile_reg *tile, | |
100 | struct nouveau_fence *fence) | |
101 | { | |
102 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
a0af9add | 103 | |
a5cf68b0 FJ |
104 | if (tile) { |
105 | spin_lock(&dev_priv->tile.lock); | |
106 | if (fence) { | |
107 | /* Mark it as pending. */ | |
108 | tile->fence = fence; | |
109 | nouveau_fence_ref(fence); | |
a0af9add | 110 | } |
a0af9add | 111 | |
a5cf68b0 FJ |
112 | tile->used = false; |
113 | spin_unlock(&dev_priv->tile.lock); | |
114 | } | |
a0af9add FJ |
115 | } |
116 | ||
a5cf68b0 FJ |
117 | struct nouveau_tile_reg * |
118 | nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size, | |
119 | uint32_t pitch, uint32_t flags) | |
a0af9add | 120 | { |
a5cf68b0 FJ |
121 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
122 | struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; | |
123 | struct nouveau_tile_reg *tile, *found = NULL; | |
124 | int i; | |
125 | ||
126 | for (i = 0; i < pfb->num_tiles; i++) { | |
127 | tile = nv10_mem_get_tile_region(dev, i); | |
128 | ||
129 | if (pitch && !found) { | |
130 | found = tile; | |
131 | continue; | |
132 | ||
133 | } else if (tile && tile->pitch) { | |
134 | /* Kill an unused tile region. */ | |
135 | nv10_mem_update_tile_region(dev, tile, 0, 0, 0, 0); | |
136 | } | |
137 | ||
138 | nv10_mem_put_tile_region(dev, tile, NULL); | |
a0af9add FJ |
139 | } |
140 | ||
a5cf68b0 FJ |
141 | if (found) |
142 | nv10_mem_update_tile_region(dev, found, addr, size, | |
143 | pitch, flags); | |
144 | return found; | |
a0af9add FJ |
145 | } |
146 | ||
6ee73861 BS |
147 | /* |
148 | * Cleanup everything | |
149 | */ | |
b833ac26 | 150 | void |
fbd2895e | 151 | nouveau_mem_vram_fini(struct drm_device *dev) |
6ee73861 BS |
152 | { |
153 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
154 | ||
ac8fb975 BS |
155 | nouveau_bo_unpin(dev_priv->vga_ram); |
156 | nouveau_bo_ref(NULL, &dev_priv->vga_ram); | |
157 | ||
6ee73861 BS |
158 | ttm_bo_device_release(&dev_priv->ttm.bdev); |
159 | ||
160 | nouveau_ttm_global_release(dev_priv); | |
161 | ||
fbd2895e BS |
162 | if (dev_priv->fb_mtrr >= 0) { |
163 | drm_mtrr_del(dev_priv->fb_mtrr, | |
164 | pci_resource_start(dev->pdev, 1), | |
165 | pci_resource_len(dev->pdev, 1), DRM_MTRR_WC); | |
166 | dev_priv->fb_mtrr = -1; | |
167 | } | |
168 | } | |
169 | ||
170 | void | |
171 | nouveau_mem_gart_fini(struct drm_device *dev) | |
172 | { | |
173 | nouveau_sgdma_takedown(dev); | |
174 | ||
cd0b072f | 175 | if (drm_core_has_AGP(dev) && dev->agp) { |
6ee73861 BS |
176 | struct drm_agp_mem *entry, *tempe; |
177 | ||
178 | /* Remove AGP resources, but leave dev->agp | |
179 | intact until drv_cleanup is called. */ | |
180 | list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) { | |
181 | if (entry->bound) | |
182 | drm_unbind_agp(entry->memory); | |
183 | drm_free_agp(entry->memory, entry->pages); | |
184 | kfree(entry); | |
185 | } | |
186 | INIT_LIST_HEAD(&dev->agp->memory); | |
187 | ||
188 | if (dev->agp->acquired) | |
189 | drm_agp_release(dev); | |
190 | ||
191 | dev->agp->acquired = 0; | |
192 | dev->agp->enabled = 0; | |
193 | } | |
6ee73861 BS |
194 | } |
195 | ||
6ee73861 | 196 | static uint32_t |
a76fb4e8 BS |
197 | nouveau_mem_detect_nv04(struct drm_device *dev) |
198 | { | |
3c7066bc | 199 | uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0); |
a76fb4e8 BS |
200 | |
201 | if (boot0 & 0x00000100) | |
202 | return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024; | |
203 | ||
3c7066bc FJ |
204 | switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) { |
205 | case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB: | |
a76fb4e8 | 206 | return 32 * 1024 * 1024; |
3c7066bc | 207 | case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB: |
a76fb4e8 | 208 | return 16 * 1024 * 1024; |
3c7066bc | 209 | case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB: |
a76fb4e8 | 210 | return 8 * 1024 * 1024; |
3c7066bc | 211 | case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB: |
a76fb4e8 BS |
212 | return 4 * 1024 * 1024; |
213 | } | |
214 | ||
215 | return 0; | |
216 | } | |
217 | ||
218 | static uint32_t | |
219 | nouveau_mem_detect_nforce(struct drm_device *dev) | |
6ee73861 BS |
220 | { |
221 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
222 | struct pci_dev *bridge; | |
223 | uint32_t mem; | |
224 | ||
225 | bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1)); | |
226 | if (!bridge) { | |
227 | NV_ERROR(dev, "no bridge device\n"); | |
228 | return 0; | |
229 | } | |
230 | ||
a76fb4e8 | 231 | if (dev_priv->flags & NV_NFORCE) { |
6ee73861 BS |
232 | pci_read_config_dword(bridge, 0x7C, &mem); |
233 | return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024; | |
234 | } else | |
a76fb4e8 | 235 | if (dev_priv->flags & NV_NFORCE2) { |
6ee73861 BS |
236 | pci_read_config_dword(bridge, 0x84, &mem); |
237 | return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024; | |
238 | } | |
239 | ||
240 | NV_ERROR(dev, "impossible!\n"); | |
241 | return 0; | |
242 | } | |
243 | ||
fbd2895e | 244 | static int |
a76fb4e8 | 245 | nouveau_mem_detect(struct drm_device *dev) |
6ee73861 BS |
246 | { |
247 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
a76fb4e8 BS |
248 | |
249 | if (dev_priv->card_type == NV_04) { | |
250 | dev_priv->vram_size = nouveau_mem_detect_nv04(dev); | |
251 | } else | |
252 | if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) { | |
253 | dev_priv->vram_size = nouveau_mem_detect_nforce(dev); | |
7a2e4e03 BS |
254 | } else |
255 | if (dev_priv->card_type < NV_50) { | |
3c7066bc FJ |
256 | dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA); |
257 | dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK; | |
c556d989 BS |
258 | } else |
259 | if (dev_priv->card_type < NV_C0) { | |
573a2a37 BS |
260 | if (nv50_vram_init(dev)) |
261 | return -ENOMEM; | |
c556d989 BS |
262 | } else { |
263 | dev_priv->vram_size = nv_rd32(dev, 0x10f20c) << 20; | |
264 | dev_priv->vram_size *= nv_rd32(dev, 0x121c74); | |
6ee73861 BS |
265 | } |
266 | ||
a76fb4e8 BS |
267 | NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20)); |
268 | if (dev_priv->vram_sys_base) { | |
269 | NV_INFO(dev, "Stolen system memory at: 0x%010llx\n", | |
270 | dev_priv->vram_sys_base); | |
271 | } | |
272 | ||
273 | if (dev_priv->vram_size) | |
274 | return 0; | |
275 | return -ENOMEM; | |
6ee73861 BS |
276 | } |
277 | ||
71d06186 FJ |
278 | #if __OS_HAS_AGP |
279 | static unsigned long | |
280 | get_agp_mode(struct drm_device *dev, unsigned long mode) | |
281 | { | |
282 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
283 | ||
284 | /* | |
285 | * FW seems to be broken on nv18, it makes the card lock up | |
286 | * randomly. | |
287 | */ | |
288 | if (dev_priv->chipset == 0x18) | |
289 | mode &= ~PCI_AGP_COMMAND_FW; | |
290 | ||
de5899bd FJ |
291 | /* |
292 | * AGP mode set in the command line. | |
293 | */ | |
294 | if (nouveau_agpmode > 0) { | |
295 | bool agpv3 = mode & 0x8; | |
296 | int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode; | |
297 | ||
298 | mode = (mode & ~0x7) | (rate & 0x7); | |
299 | } | |
300 | ||
71d06186 FJ |
301 | return mode; |
302 | } | |
303 | #endif | |
304 | ||
e04d8e82 FJ |
305 | int |
306 | nouveau_mem_reset_agp(struct drm_device *dev) | |
6ee73861 | 307 | { |
e04d8e82 FJ |
308 | #if __OS_HAS_AGP |
309 | uint32_t saved_pci_nv_1, pmc_enable; | |
310 | int ret; | |
311 | ||
312 | /* First of all, disable fast writes, otherwise if it's | |
313 | * already enabled in the AGP bridge and we disable the card's | |
314 | * AGP controller we might be locking ourselves out of it. */ | |
316f60a1 FJ |
315 | if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) | |
316 | dev->agp->mode) & PCI_AGP_COMMAND_FW) { | |
e04d8e82 FJ |
317 | struct drm_agp_info info; |
318 | struct drm_agp_mode mode; | |
319 | ||
320 | ret = drm_agp_info(dev, &info); | |
321 | if (ret) | |
322 | return ret; | |
323 | ||
71d06186 | 324 | mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW; |
e04d8e82 FJ |
325 | ret = drm_agp_enable(dev, mode); |
326 | if (ret) | |
327 | return ret; | |
328 | } | |
6ee73861 BS |
329 | |
330 | saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1); | |
6ee73861 BS |
331 | |
332 | /* clear busmaster bit */ | |
333 | nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4); | |
e04d8e82 FJ |
334 | /* disable AGP */ |
335 | nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0); | |
6ee73861 BS |
336 | |
337 | /* power cycle pgraph, if enabled */ | |
338 | pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE); | |
339 | if (pmc_enable & NV_PMC_ENABLE_PGRAPH) { | |
340 | nv_wr32(dev, NV03_PMC_ENABLE, | |
341 | pmc_enable & ~NV_PMC_ENABLE_PGRAPH); | |
342 | nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | | |
343 | NV_PMC_ENABLE_PGRAPH); | |
344 | } | |
345 | ||
346 | /* and restore (gives effect of resetting AGP) */ | |
6ee73861 | 347 | nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1); |
b694dfb2 | 348 | #endif |
6ee73861 | 349 | |
e04d8e82 FJ |
350 | return 0; |
351 | } | |
352 | ||
6ee73861 BS |
353 | int |
354 | nouveau_mem_init_agp(struct drm_device *dev) | |
355 | { | |
b694dfb2 | 356 | #if __OS_HAS_AGP |
6ee73861 BS |
357 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
358 | struct drm_agp_info info; | |
359 | struct drm_agp_mode mode; | |
360 | int ret; | |
361 | ||
6ee73861 BS |
362 | if (!dev->agp->acquired) { |
363 | ret = drm_agp_acquire(dev); | |
364 | if (ret) { | |
365 | NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret); | |
366 | return ret; | |
367 | } | |
368 | } | |
369 | ||
2b495268 FJ |
370 | nouveau_mem_reset_agp(dev); |
371 | ||
6ee73861 BS |
372 | ret = drm_agp_info(dev, &info); |
373 | if (ret) { | |
374 | NV_ERROR(dev, "Unable to get AGP info: %d\n", ret); | |
375 | return ret; | |
376 | } | |
377 | ||
378 | /* see agp.h for the AGPSTAT_* modes available */ | |
71d06186 | 379 | mode.mode = get_agp_mode(dev, info.mode); |
6ee73861 BS |
380 | ret = drm_agp_enable(dev, mode); |
381 | if (ret) { | |
382 | NV_ERROR(dev, "Unable to enable AGP: %d\n", ret); | |
383 | return ret; | |
384 | } | |
385 | ||
386 | dev_priv->gart_info.type = NOUVEAU_GART_AGP; | |
387 | dev_priv->gart_info.aper_base = info.aperture_base; | |
388 | dev_priv->gart_info.aper_size = info.aperture_size; | |
b694dfb2 | 389 | #endif |
6ee73861 BS |
390 | return 0; |
391 | } | |
392 | ||
393 | int | |
fbd2895e | 394 | nouveau_mem_vram_init(struct drm_device *dev) |
6ee73861 BS |
395 | { |
396 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
397 | struct ttm_bo_device *bdev = &dev_priv->ttm.bdev; | |
fbd2895e | 398 | int ret, dma_bits; |
6ee73861 BS |
399 | |
400 | if (dev_priv->card_type >= NV_50 && | |
401 | pci_dma_supported(dev->pdev, DMA_BIT_MASK(40))) | |
402 | dma_bits = 40; | |
fbd2895e BS |
403 | else |
404 | dma_bits = 32; | |
6ee73861 BS |
405 | |
406 | ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits)); | |
fbd2895e | 407 | if (ret) |
6ee73861 | 408 | return ret; |
fbd2895e | 409 | |
fbd2895e | 410 | dev_priv->fb_phys = pci_resource_start(dev->pdev, 1); |
6ee73861 BS |
411 | |
412 | ret = nouveau_ttm_global_init(dev_priv); | |
413 | if (ret) | |
414 | return ret; | |
415 | ||
416 | ret = ttm_bo_device_init(&dev_priv->ttm.bdev, | |
417 | dev_priv->ttm.bo_global_ref.ref.object, | |
418 | &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET, | |
419 | dma_bits <= 32 ? true : false); | |
420 | if (ret) { | |
421 | NV_ERROR(dev, "Error initialising bo driver: %d\n", ret); | |
422 | return ret; | |
423 | } | |
424 | ||
fbd2895e BS |
425 | /* reserve space at end of VRAM for PRAMIN */ |
426 | if (dev_priv->chipset == 0x40 || dev_priv->chipset == 0x47 || | |
427 | dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b) | |
428 | dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024); | |
429 | else | |
430 | if (dev_priv->card_type >= NV_40) | |
431 | dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024); | |
432 | else | |
433 | dev_priv->ramin_rsvd_vram = (512 * 1024); | |
434 | ||
573a2a37 BS |
435 | /* initialise gpu-specific vram backend */ |
436 | ret = nouveau_mem_detect(dev); | |
437 | if (ret) | |
438 | return ret; | |
439 | ||
440 | dev_priv->fb_available_size = dev_priv->vram_size; | |
441 | dev_priv->fb_mappable_pages = dev_priv->fb_available_size; | |
442 | if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1)) | |
443 | dev_priv->fb_mappable_pages = pci_resource_len(dev->pdev, 1); | |
444 | dev_priv->fb_mappable_pages >>= PAGE_SHIFT; | |
445 | ||
6ee73861 BS |
446 | dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram; |
447 | dev_priv->fb_aper_free = dev_priv->fb_available_size; | |
448 | ||
449 | /* mappable vram */ | |
450 | ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM, | |
451 | dev_priv->fb_available_size >> PAGE_SHIFT); | |
452 | if (ret) { | |
453 | NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret); | |
454 | return ret; | |
455 | } | |
456 | ||
ac8fb975 BS |
457 | ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM, |
458 | 0, 0, true, true, &dev_priv->vga_ram); | |
459 | if (ret == 0) | |
460 | ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM); | |
461 | if (ret) { | |
462 | NV_WARN(dev, "failed to reserve VGA memory\n"); | |
463 | nouveau_bo_ref(NULL, &dev_priv->vga_ram); | |
464 | } | |
465 | ||
fbd2895e BS |
466 | dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1), |
467 | pci_resource_len(dev->pdev, 1), | |
468 | DRM_MTRR_WC); | |
469 | return 0; | |
470 | } | |
471 | ||
472 | int | |
473 | nouveau_mem_gart_init(struct drm_device *dev) | |
474 | { | |
475 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
476 | struct ttm_bo_device *bdev = &dev_priv->ttm.bdev; | |
477 | int ret; | |
478 | ||
479 | dev_priv->gart_info.type = NOUVEAU_GART_NONE; | |
480 | ||
6ee73861 | 481 | #if !defined(__powerpc__) && !defined(__ia64__) |
de5899bd | 482 | if (drm_device_is_agp(dev) && dev->agp && nouveau_agpmode) { |
6ee73861 BS |
483 | ret = nouveau_mem_init_agp(dev); |
484 | if (ret) | |
485 | NV_ERROR(dev, "Error initialising AGP: %d\n", ret); | |
486 | } | |
487 | #endif | |
488 | ||
489 | if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) { | |
490 | ret = nouveau_sgdma_init(dev); | |
491 | if (ret) { | |
492 | NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret); | |
493 | return ret; | |
494 | } | |
495 | } | |
496 | ||
497 | NV_INFO(dev, "%d MiB GART (aperture)\n", | |
498 | (int)(dev_priv->gart_info.aper_size >> 20)); | |
499 | dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size; | |
500 | ||
501 | ret = ttm_bo_init_mm(bdev, TTM_PL_TT, | |
502 | dev_priv->gart_info.aper_size >> PAGE_SHIFT); | |
503 | if (ret) { | |
504 | NV_ERROR(dev, "Failed TT mm init: %d\n", ret); | |
505 | return ret; | |
506 | } | |
507 | ||
6ee73861 BS |
508 | return 0; |
509 | } | |
510 | ||
7760fcb0 RS |
511 | void |
512 | nouveau_mem_timing_init(struct drm_device *dev) | |
513 | { | |
cac8f05b | 514 | /* cards < NVC0 only */ |
7760fcb0 RS |
515 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
516 | struct nouveau_pm_engine *pm = &dev_priv->engine.pm; | |
517 | struct nouveau_pm_memtimings *memtimings = &pm->memtimings; | |
518 | struct nvbios *bios = &dev_priv->vbios; | |
519 | struct bit_entry P; | |
520 | u8 tUNK_0, tUNK_1, tUNK_2; | |
521 | u8 tRP; /* Byte 3 */ | |
522 | u8 tRAS; /* Byte 5 */ | |
523 | u8 tRFC; /* Byte 7 */ | |
524 | u8 tRC; /* Byte 9 */ | |
525 | u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14; | |
526 | u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; | |
527 | u8 *mem = NULL, *entry; | |
528 | int i, recordlen, entries; | |
529 | ||
530 | if (bios->type == NVBIOS_BIT) { | |
531 | if (bit_table(dev, 'P', &P)) | |
532 | return; | |
533 | ||
534 | if (P.version == 1) | |
535 | mem = ROMPTR(bios, P.data[4]); | |
536 | else | |
537 | if (P.version == 2) | |
538 | mem = ROMPTR(bios, P.data[8]); | |
539 | else { | |
540 | NV_WARN(dev, "unknown mem for BIT P %d\n", P.version); | |
541 | } | |
542 | } else { | |
543 | NV_DEBUG(dev, "BMP version too old for memory\n"); | |
544 | return; | |
545 | } | |
546 | ||
547 | if (!mem) { | |
548 | NV_DEBUG(dev, "memory timing table pointer invalid\n"); | |
549 | return; | |
550 | } | |
551 | ||
552 | if (mem[0] != 0x10) { | |
553 | NV_WARN(dev, "memory timing table 0x%02x unknown\n", mem[0]); | |
554 | return; | |
555 | } | |
556 | ||
557 | /* validate record length */ | |
558 | entries = mem[2]; | |
559 | recordlen = mem[3]; | |
560 | if (recordlen < 15) { | |
561 | NV_ERROR(dev, "mem timing table length unknown: %d\n", mem[3]); | |
562 | return; | |
563 | } | |
564 | ||
565 | /* parse vbios entries into common format */ | |
566 | memtimings->timing = | |
567 | kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL); | |
568 | if (!memtimings->timing) | |
569 | return; | |
570 | ||
571 | entry = mem + mem[1]; | |
572 | for (i = 0; i < entries; i++, entry += recordlen) { | |
573 | struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i]; | |
574 | if (entry[0] == 0) | |
575 | continue; | |
576 | ||
577 | tUNK_18 = 1; | |
578 | tUNK_19 = 1; | |
579 | tUNK_20 = 0; | |
580 | tUNK_21 = 0; | |
cac8f05b RS |
581 | switch (min(recordlen, 22)) { |
582 | case 22: | |
7760fcb0 | 583 | tUNK_21 = entry[21]; |
cac8f05b | 584 | case 21: |
7760fcb0 | 585 | tUNK_20 = entry[20]; |
cac8f05b | 586 | case 20: |
7760fcb0 | 587 | tUNK_19 = entry[19]; |
cac8f05b | 588 | case 19: |
7760fcb0 RS |
589 | tUNK_18 = entry[18]; |
590 | default: | |
591 | tUNK_0 = entry[0]; | |
592 | tUNK_1 = entry[1]; | |
593 | tUNK_2 = entry[2]; | |
594 | tRP = entry[3]; | |
595 | tRAS = entry[5]; | |
596 | tRFC = entry[7]; | |
597 | tRC = entry[9]; | |
598 | tUNK_10 = entry[10]; | |
599 | tUNK_11 = entry[11]; | |
600 | tUNK_12 = entry[12]; | |
601 | tUNK_13 = entry[13]; | |
602 | tUNK_14 = entry[14]; | |
603 | break; | |
604 | } | |
605 | ||
606 | timing->reg_100220 = (tRC << 24 | tRFC << 16 | tRAS << 8 | tRP); | |
607 | ||
608 | /* XXX: I don't trust the -1's and +1's... they must come | |
609 | * from somewhere! */ | |
610 | timing->reg_100224 = ((tUNK_0 + tUNK_19 + 1) << 24 | | |
611 | tUNK_18 << 16 | | |
612 | (tUNK_1 + tUNK_19 + 1) << 8 | | |
613 | (tUNK_2 - 1)); | |
614 | ||
615 | timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10); | |
616 | if(recordlen > 19) { | |
617 | timing->reg_100228 += (tUNK_19 - 1) << 24; | |
cac8f05b RS |
618 | }/* I cannot back-up this else-statement right now |
619 | else { | |
7760fcb0 | 620 | timing->reg_100228 += tUNK_12 << 24; |
cac8f05b | 621 | }*/ |
7760fcb0 RS |
622 | |
623 | /* XXX: reg_10022c */ | |
cac8f05b | 624 | timing->reg_10022c = tUNK_2 - 1; |
7760fcb0 RS |
625 | |
626 | timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 | | |
627 | tUNK_13 << 8 | tUNK_13); | |
628 | ||
629 | /* XXX: +6? */ | |
630 | timing->reg_100234 = (tRAS << 24 | (tUNK_19 + 6) << 8 | tRC); | |
cac8f05b RS |
631 | timing->reg_100234 += max(tUNK_10,tUNK_11) << 16; |
632 | ||
633 | /* XXX; reg_100238, reg_10023c | |
634 | * reg: 0x00?????? | |
635 | * reg_10023c: | |
636 | * 0 for pre-NV50 cards | |
637 | * 0x????0202 for NV50+ cards (empirical evidence) */ | |
638 | if(dev_priv->card_type >= NV_50) { | |
639 | timing->reg_10023c = 0x202; | |
7760fcb0 RS |
640 | } |
641 | ||
7760fcb0 RS |
642 | NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i, |
643 | timing->reg_100220, timing->reg_100224, | |
644 | timing->reg_100228, timing->reg_10022c); | |
645 | NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n", | |
646 | timing->reg_100230, timing->reg_100234, | |
647 | timing->reg_100238, timing->reg_10023c); | |
648 | } | |
649 | ||
650 | memtimings->nr_timing = entries; | |
651 | memtimings->supported = true; | |
652 | } | |
653 | ||
654 | void | |
655 | nouveau_mem_timing_fini(struct drm_device *dev) | |
656 | { | |
657 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
658 | struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings; | |
659 | ||
660 | kfree(mem->timing); | |
661 | } | |
573a2a37 BS |
662 | |
663 | static int | |
664 | nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long p_size) | |
665 | { | |
666 | struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev); | |
667 | struct nouveau_mm *mm; | |
668 | u32 b_size; | |
669 | int ret; | |
670 | ||
671 | p_size = (p_size << PAGE_SHIFT) >> 12; | |
672 | b_size = dev_priv->vram_rblock_size >> 12; | |
673 | ||
674 | ret = nouveau_mm_init(&mm, 0, p_size, b_size); | |
675 | if (ret) | |
676 | return ret; | |
677 | ||
678 | man->priv = mm; | |
679 | return 0; | |
680 | } | |
681 | ||
682 | static int | |
683 | nouveau_vram_manager_fini(struct ttm_mem_type_manager *man) | |
684 | { | |
685 | struct nouveau_mm *mm = man->priv; | |
686 | int ret; | |
687 | ||
688 | ret = nouveau_mm_fini(&mm); | |
689 | if (ret) | |
690 | return ret; | |
691 | ||
692 | man->priv = NULL; | |
693 | return 0; | |
694 | } | |
695 | ||
696 | static void | |
697 | nouveau_vram_manager_del(struct ttm_mem_type_manager *man, | |
698 | struct ttm_mem_reg *mem) | |
699 | { | |
700 | struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev); | |
701 | struct drm_device *dev = dev_priv->dev; | |
702 | ||
703 | nv50_vram_del(dev, (struct nouveau_vram **)&mem->mm_node); | |
704 | } | |
705 | ||
706 | static int | |
707 | nouveau_vram_manager_new(struct ttm_mem_type_manager *man, | |
708 | struct ttm_buffer_object *bo, | |
709 | struct ttm_placement *placement, | |
710 | struct ttm_mem_reg *mem) | |
711 | { | |
712 | struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev); | |
713 | struct drm_device *dev = dev_priv->dev; | |
714 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
715 | struct nouveau_vram *vram; | |
716 | int ret; | |
717 | ||
718 | ret = nv50_vram_new(dev, mem->num_pages << PAGE_SHIFT, 65536, 0, | |
719 | (nvbo->tile_flags >> 8) & 0x7f, &vram); | |
720 | if (ret) | |
721 | return ret; | |
722 | ||
723 | mem->mm_node = vram; | |
724 | mem->start = vram->offset >> PAGE_SHIFT; | |
725 | return 0; | |
726 | } | |
727 | ||
728 | void | |
729 | nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) | |
730 | { | |
731 | struct ttm_bo_global *glob = man->bdev->glob; | |
732 | struct nouveau_mm *mm = man->priv; | |
733 | struct nouveau_mm_node *r; | |
734 | u64 total = 0, ttotal[3] = {}, tused[3] = {}, tfree[3] = {}; | |
735 | int i; | |
736 | ||
737 | mutex_lock(&mm->mutex); | |
738 | list_for_each_entry(r, &mm->nodes, nl_entry) { | |
739 | printk(KERN_DEBUG "%s %s-%d: 0x%010llx 0x%010llx\n", | |
740 | prefix, r->free ? "free" : "used", r->type, | |
741 | ((u64)r->offset << 12), | |
742 | (((u64)r->offset + r->length) << 12)); | |
743 | total += r->length; | |
744 | ttotal[r->type] += r->length; | |
745 | if (r->free) | |
746 | tfree[r->type] += r->length; | |
747 | else | |
748 | tused[r->type] += r->length; | |
749 | } | |
750 | mutex_unlock(&mm->mutex); | |
751 | ||
752 | printk(KERN_DEBUG "%s total: 0x%010llx\n", prefix, total << 12); | |
753 | for (i = 0; i < 3; i++) { | |
754 | printk(KERN_DEBUG "%s type %d: 0x%010llx, " | |
755 | "used 0x%010llx, free 0x%010llx\n", prefix, | |
756 | i, ttotal[i] << 12, tused[i] << 12, tfree[i] << 12); | |
757 | } | |
758 | } | |
759 | ||
760 | const struct ttm_mem_type_manager_func nouveau_vram_manager = { | |
761 | nouveau_vram_manager_init, | |
762 | nouveau_vram_manager_fini, | |
763 | nouveau_vram_manager_new, | |
764 | nouveau_vram_manager_del, | |
765 | nouveau_vram_manager_debug | |
766 | }; |