Commit | Line | Data |
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6ee73861 BS |
1 | /* |
2 | * Copyright 2005 Stephane Marchesin | |
3 | * Copyright 2008 Stuart Bennett | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
21 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
22 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | */ | |
25 | ||
26 | #include <linux/swab.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
6ee73861 BS |
28 | #include "drmP.h" |
29 | #include "drm.h" | |
30 | #include "drm_sarea.h" | |
31 | #include "drm_crtc_helper.h" | |
32 | #include <linux/vgaarb.h> | |
6a9ee8af | 33 | #include <linux/vga_switcheroo.h> |
6ee73861 BS |
34 | |
35 | #include "nouveau_drv.h" | |
94580299 | 36 | #include <nouveau_drm.h> |
38651674 | 37 | #include "nouveau_fbcon.h" |
330c5988 | 38 | #include "nouveau_pm.h" |
017e6e29 | 39 | #include "nv04_display.h" |
6ee73861 BS |
40 | #include "nv50_display.h" |
41 | ||
6ee73861 | 42 | static void nouveau_stub_takedown(struct drm_device *dev) {} |
ee2e0131 | 43 | static int nouveau_stub_init(struct drm_device *dev) { return 0; } |
6ee73861 BS |
44 | |
45 | static int nouveau_init_engine_ptrs(struct drm_device *dev) | |
46 | { | |
47 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
48 | struct nouveau_engine *engine = &dev_priv->engine; | |
49 | ||
50 | switch (dev_priv->chipset & 0xf0) { | |
51 | case 0x00: | |
c88c2e06 FJ |
52 | engine->display.early_init = nv04_display_early_init; |
53 | engine->display.late_takedown = nv04_display_late_takedown; | |
54 | engine->display.create = nv04_display_create; | |
c88c2e06 | 55 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
56 | engine->display.init = nv04_display_init; |
57 | engine->display.fini = nv04_display_fini; | |
36f1317e BS |
58 | engine->pm.clocks_get = nv04_pm_clocks_get; |
59 | engine->pm.clocks_pre = nv04_pm_clocks_pre; | |
60 | engine->pm.clocks_set = nv04_pm_clocks_set; | |
6ee73861 BS |
61 | break; |
62 | case 0x10: | |
c88c2e06 FJ |
63 | engine->display.early_init = nv04_display_early_init; |
64 | engine->display.late_takedown = nv04_display_late_takedown; | |
65 | engine->display.create = nv04_display_create; | |
c88c2e06 | 66 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
67 | engine->display.init = nv04_display_init; |
68 | engine->display.fini = nv04_display_fini; | |
36f1317e BS |
69 | engine->pm.clocks_get = nv04_pm_clocks_get; |
70 | engine->pm.clocks_pre = nv04_pm_clocks_pre; | |
71 | engine->pm.clocks_set = nv04_pm_clocks_set; | |
6ee73861 BS |
72 | break; |
73 | case 0x20: | |
c88c2e06 FJ |
74 | engine->display.early_init = nv04_display_early_init; |
75 | engine->display.late_takedown = nv04_display_late_takedown; | |
76 | engine->display.create = nv04_display_create; | |
c88c2e06 | 77 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
78 | engine->display.init = nv04_display_init; |
79 | engine->display.fini = nv04_display_fini; | |
36f1317e BS |
80 | engine->pm.clocks_get = nv04_pm_clocks_get; |
81 | engine->pm.clocks_pre = nv04_pm_clocks_pre; | |
82 | engine->pm.clocks_set = nv04_pm_clocks_set; | |
6ee73861 BS |
83 | break; |
84 | case 0x30: | |
c88c2e06 FJ |
85 | engine->display.early_init = nv04_display_early_init; |
86 | engine->display.late_takedown = nv04_display_late_takedown; | |
87 | engine->display.create = nv04_display_create; | |
c88c2e06 | 88 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
89 | engine->display.init = nv04_display_init; |
90 | engine->display.fini = nv04_display_fini; | |
36f1317e BS |
91 | engine->pm.clocks_get = nv04_pm_clocks_get; |
92 | engine->pm.clocks_pre = nv04_pm_clocks_pre; | |
93 | engine->pm.clocks_set = nv04_pm_clocks_set; | |
442b626e BS |
94 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
95 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
6ee73861 BS |
96 | break; |
97 | case 0x40: | |
98 | case 0x60: | |
c88c2e06 FJ |
99 | engine->display.early_init = nv04_display_early_init; |
100 | engine->display.late_takedown = nv04_display_late_takedown; | |
101 | engine->display.create = nv04_display_create; | |
c88c2e06 | 102 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
103 | engine->display.init = nv04_display_init; |
104 | engine->display.fini = nv04_display_fini; | |
1262a206 BS |
105 | engine->pm.clocks_get = nv40_pm_clocks_get; |
106 | engine->pm.clocks_pre = nv40_pm_clocks_pre; | |
107 | engine->pm.clocks_set = nv40_pm_clocks_set; | |
442b626e BS |
108 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
109 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
8155cac4 | 110 | engine->pm.temp_get = nv40_temp_get; |
69346180 BS |
111 | engine->pm.pwm_get = nv40_pm_pwm_get; |
112 | engine->pm.pwm_set = nv40_pm_pwm_set; | |
6ee73861 BS |
113 | break; |
114 | case 0x50: | |
115 | case 0x80: /* gotta love NVIDIA's consistency.. */ | |
116 | case 0x90: | |
d9f61c2d | 117 | case 0xa0: |
c88c2e06 FJ |
118 | engine->display.early_init = nv50_display_early_init; |
119 | engine->display.late_takedown = nv50_display_late_takedown; | |
120 | engine->display.create = nv50_display_create; | |
c88c2e06 | 121 | engine->display.destroy = nv50_display_destroy; |
2a44e499 BS |
122 | engine->display.init = nv50_display_init; |
123 | engine->display.fini = nv50_display_fini; | |
fade7ad5 | 124 | switch (dev_priv->chipset) { |
bd2e597d BS |
125 | case 0x84: |
126 | case 0x86: | |
127 | case 0x92: | |
128 | case 0x94: | |
129 | case 0x96: | |
130 | case 0x98: | |
131 | case 0xa0: | |
5f80198e BS |
132 | case 0xaa: |
133 | case 0xac: | |
bd2e597d | 134 | case 0x50: |
f3fbaf34 BS |
135 | engine->pm.clocks_get = nv50_pm_clocks_get; |
136 | engine->pm.clocks_pre = nv50_pm_clocks_pre; | |
137 | engine->pm.clocks_set = nv50_pm_clocks_set; | |
fade7ad5 | 138 | break; |
bd2e597d | 139 | default: |
ca94a71f BS |
140 | engine->pm.clocks_get = nva3_pm_clocks_get; |
141 | engine->pm.clocks_pre = nva3_pm_clocks_pre; | |
142 | engine->pm.clocks_set = nva3_pm_clocks_set; | |
bd2e597d | 143 | break; |
fade7ad5 | 144 | } |
02c30ca0 BS |
145 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
146 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
8155cac4 FJ |
147 | if (dev_priv->chipset >= 0x84) |
148 | engine->pm.temp_get = nv84_temp_get; | |
149 | else | |
150 | engine->pm.temp_get = nv40_temp_get; | |
5a4267ab BS |
151 | engine->pm.pwm_get = nv50_pm_pwm_get; |
152 | engine->pm.pwm_set = nv50_pm_pwm_set; | |
6ee73861 | 153 | break; |
d9f61c2d | 154 | case 0xc0: |
4b223eef BS |
155 | engine->display.early_init = nv50_display_early_init; |
156 | engine->display.late_takedown = nv50_display_late_takedown; | |
157 | engine->display.create = nv50_display_create; | |
4b223eef | 158 | engine->display.destroy = nv50_display_destroy; |
2a44e499 BS |
159 | engine->display.init = nv50_display_init; |
160 | engine->display.fini = nv50_display_fini; | |
74cfad18 | 161 | engine->pm.temp_get = nv84_temp_get; |
354d0781 | 162 | engine->pm.clocks_get = nvc0_pm_clocks_get; |
045da4e5 BS |
163 | engine->pm.clocks_pre = nvc0_pm_clocks_pre; |
164 | engine->pm.clocks_set = nvc0_pm_clocks_set; | |
3c71c233 | 165 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
da1dc4cf | 166 | engine->pm.voltage_set = nouveau_voltage_gpio_set; |
5a4267ab BS |
167 | engine->pm.pwm_get = nv50_pm_pwm_get; |
168 | engine->pm.pwm_set = nv50_pm_pwm_set; | |
4b223eef | 169 | break; |
d9f61c2d | 170 | case 0xd0: |
d9f61c2d BS |
171 | engine->display.early_init = nouveau_stub_init; |
172 | engine->display.late_takedown = nouveau_stub_takedown; | |
26f6d88b | 173 | engine->display.create = nvd0_display_create; |
26f6d88b | 174 | engine->display.destroy = nvd0_display_destroy; |
2a44e499 BS |
175 | engine->display.init = nvd0_display_init; |
176 | engine->display.fini = nvd0_display_fini; | |
61091837 | 177 | engine->pm.temp_get = nv84_temp_get; |
4784e4aa | 178 | engine->pm.clocks_get = nvc0_pm_clocks_get; |
045da4e5 BS |
179 | engine->pm.clocks_pre = nvc0_pm_clocks_pre; |
180 | engine->pm.clocks_set = nvc0_pm_clocks_set; | |
4784e4aa BS |
181 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
182 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
d9f61c2d | 183 | break; |
68455a43 | 184 | case 0xe0: |
68455a43 BS |
185 | engine->display.early_init = nouveau_stub_init; |
186 | engine->display.late_takedown = nouveau_stub_takedown; | |
187 | engine->display.create = nvd0_display_create; | |
188 | engine->display.destroy = nvd0_display_destroy; | |
189 | engine->display.init = nvd0_display_init; | |
190 | engine->display.fini = nvd0_display_fini; | |
68455a43 | 191 | break; |
6ee73861 BS |
192 | default: |
193 | NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset); | |
194 | return 1; | |
195 | } | |
196 | ||
03bc9675 BS |
197 | /* headless mode */ |
198 | if (nouveau_modeset == 2) { | |
199 | engine->display.early_init = nouveau_stub_init; | |
200 | engine->display.late_takedown = nouveau_stub_takedown; | |
201 | engine->display.create = nouveau_stub_init; | |
202 | engine->display.init = nouveau_stub_init; | |
203 | engine->display.destroy = nouveau_stub_takedown; | |
204 | } | |
205 | ||
6ee73861 BS |
206 | return 0; |
207 | } | |
208 | ||
209 | static unsigned int | |
210 | nouveau_vga_set_decode(void *priv, bool state) | |
211 | { | |
9967b948 MK |
212 | struct drm_device *dev = priv; |
213 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
214 | ||
215 | if (dev_priv->chipset >= 0x40) | |
216 | nv_wr32(dev, 0x88054, state); | |
217 | else | |
218 | nv_wr32(dev, 0x1854, state); | |
219 | ||
6ee73861 BS |
220 | if (state) |
221 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
222 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
223 | else | |
224 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
225 | } | |
226 | ||
6a9ee8af DA |
227 | static void nouveau_switcheroo_set_state(struct pci_dev *pdev, |
228 | enum vga_switcheroo_state state) | |
229 | { | |
fbf81762 | 230 | struct drm_device *dev = pci_get_drvdata(pdev); |
6a9ee8af DA |
231 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; |
232 | if (state == VGA_SWITCHEROO_ON) { | |
233 | printk(KERN_ERR "VGA switcheroo: switched nouveau on\n"); | |
5bcf719b | 234 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af | 235 | nouveau_pci_resume(pdev); |
fbf81762 | 236 | drm_kms_helper_poll_enable(dev); |
5bcf719b | 237 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af DA |
238 | } else { |
239 | printk(KERN_ERR "VGA switcheroo: switched nouveau off\n"); | |
5bcf719b | 240 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
fbf81762 | 241 | drm_kms_helper_poll_disable(dev); |
d099230c | 242 | nouveau_switcheroo_optimus_dsm(); |
6a9ee8af | 243 | nouveau_pci_suspend(pdev, pmm); |
5bcf719b | 244 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
245 | } |
246 | } | |
247 | ||
8d608aa6 DA |
248 | static void nouveau_switcheroo_reprobe(struct pci_dev *pdev) |
249 | { | |
250 | struct drm_device *dev = pci_get_drvdata(pdev); | |
251 | nouveau_fbcon_output_poll_changed(dev); | |
252 | } | |
253 | ||
6a9ee8af DA |
254 | static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev) |
255 | { | |
256 | struct drm_device *dev = pci_get_drvdata(pdev); | |
257 | bool can_switch; | |
258 | ||
259 | spin_lock(&dev->count_lock); | |
260 | can_switch = (dev->open_count == 0); | |
261 | spin_unlock(&dev->count_lock); | |
262 | return can_switch; | |
263 | } | |
264 | ||
26ec685f TI |
265 | static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops = { |
266 | .set_gpu_state = nouveau_switcheroo_set_state, | |
267 | .reprobe = nouveau_switcheroo_reprobe, | |
268 | .can_switch = nouveau_switcheroo_can_switch, | |
269 | }; | |
270 | ||
6ee73861 BS |
271 | int |
272 | nouveau_card_init(struct drm_device *dev) | |
273 | { | |
274 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
275 | struct nouveau_engine *engine; | |
ebb945a9 | 276 | int ret; |
6ee73861 | 277 | |
6ee73861 | 278 | vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode); |
26ec685f | 279 | vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops); |
6ee73861 BS |
280 | |
281 | /* Initialise internal driver API hooks */ | |
282 | ret = nouveau_init_engine_ptrs(dev); | |
283 | if (ret) | |
c5804be0 | 284 | goto out; |
6ee73861 | 285 | engine = &dev_priv->engine; |
ff9e5279 | 286 | spin_lock_init(&dev_priv->context_switch_lock); |
6ee73861 | 287 | |
c88c2e06 FJ |
288 | /* Make the CRTCs and I2C buses accessible */ |
289 | ret = engine->display.early_init(dev); | |
290 | if (ret) | |
291 | goto out; | |
292 | ||
6ee73861 | 293 | /* Parse BIOS tables / Run init tables if card not POSTed */ |
cd0b072f BS |
294 | ret = nouveau_bios_init(dev); |
295 | if (ret) | |
c88c2e06 | 296 | goto out_display_early; |
6ee73861 | 297 | |
4c5df493 BS |
298 | /* workaround an odd issue on nvc1 by disabling the device's |
299 | * nosnoop capability. hopefully won't cause issues until a | |
300 | * better fix is found - assuming there is one... | |
301 | */ | |
302 | if (dev_priv->chipset == 0xc1) { | |
303 | nv_mask(dev, 0x00088080, 0x00000800, 0x00000000); | |
304 | } | |
305 | ||
1575b364 BS |
306 | ret = nouveau_irq_init(dev); |
307 | if (ret) | |
ebb945a9 | 308 | goto out_bios; |
1575b364 | 309 | |
27d5030a | 310 | ret = nouveau_display_create(dev); |
e88efe05 | 311 | if (ret) |
1575b364 | 312 | goto out_irq; |
6ee73861 | 313 | |
10b461e4 | 314 | nouveau_backlight_init(dev); |
7d3a766b | 315 | nouveau_pm_init(dev); |
10b461e4 | 316 | |
1575b364 | 317 | if (dev->mode_config.num_crtc) { |
f62b27db | 318 | ret = nouveau_display_init(dev); |
1575b364 | 319 | if (ret) |
ebb945a9 | 320 | goto out_pm; |
6ee73861 BS |
321 | } |
322 | ||
6ee73861 | 323 | return 0; |
c5804be0 | 324 | |
7d3a766b BS |
325 | out_pm: |
326 | nouveau_pm_fini(dev); | |
10b461e4 | 327 | nouveau_backlight_exit(dev); |
27d5030a | 328 | nouveau_display_destroy(dev); |
c5804be0 | 329 | out_irq: |
35fa2f2a | 330 | nouveau_irq_fini(dev); |
c5804be0 MK |
331 | out_bios: |
332 | nouveau_bios_takedown(dev); | |
c88c2e06 FJ |
333 | out_display_early: |
334 | engine->display.late_takedown(dev); | |
c5804be0 | 335 | out: |
5c5ed6e2 | 336 | vga_switcheroo_unregister_client(dev->pdev); |
c5804be0 MK |
337 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
338 | return ret; | |
6ee73861 BS |
339 | } |
340 | ||
341 | static void nouveau_card_takedown(struct drm_device *dev) | |
342 | { | |
343 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
344 | struct nouveau_engine *engine = &dev_priv->engine; | |
345 | ||
ebb945a9 | 346 | if (dev->mode_config.num_crtc) |
f62b27db | 347 | nouveau_display_fini(dev); |
06b75e35 | 348 | |
7d3a766b | 349 | nouveau_pm_fini(dev); |
10b461e4 | 350 | nouveau_backlight_exit(dev); |
27d5030a | 351 | nouveau_display_destroy(dev); |
06b75e35 | 352 | |
97666109 JR |
353 | if (dev_priv->vga_ram) { |
354 | nouveau_bo_unpin(dev_priv->vga_ram); | |
355 | nouveau_bo_ref(NULL, &dev_priv->vga_ram); | |
356 | } | |
357 | ||
b6d3d871 | 358 | nouveau_bios_takedown(dev); |
668b6c09 BS |
359 | engine->display.late_takedown(dev); |
360 | ||
361 | nouveau_irq_fini(dev); | |
6ee73861 | 362 | |
5c5ed6e2 | 363 | vga_switcheroo_unregister_client(dev->pdev); |
b6d3d871 | 364 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
6ee73861 BS |
365 | } |
366 | ||
6ee73861 BS |
367 | /* first module load, setup the mmio/fb mapping */ |
368 | /* KMS: we need mmio at load time, not when the first drm client opens. */ | |
369 | int nouveau_firstopen(struct drm_device *dev) | |
370 | { | |
371 | return 0; | |
372 | } | |
373 | ||
374 | /* if we have an OF card, copy vbios to RAMIN */ | |
375 | static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev) | |
376 | { | |
377 | #if defined(__powerpc__) | |
378 | int size, i; | |
379 | const uint32_t *bios; | |
380 | struct device_node *dn = pci_device_to_OF_node(dev->pdev); | |
381 | if (!dn) { | |
382 | NV_INFO(dev, "Unable to get the OF node\n"); | |
383 | return; | |
384 | } | |
385 | ||
386 | bios = of_get_property(dn, "NVDA,BMP", &size); | |
387 | if (bios) { | |
388 | for (i = 0; i < size; i += 4) | |
389 | nv_wi32(dev, i, bios[i/4]); | |
390 | NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size); | |
391 | } else { | |
392 | NV_INFO(dev, "Unable to get the OF bios\n"); | |
393 | } | |
394 | #endif | |
395 | } | |
396 | ||
397 | int nouveau_load(struct drm_device *dev, unsigned long flags) | |
398 | { | |
399 | struct drm_nouveau_private *dev_priv; | |
2f5394c3 | 400 | uint32_t reg0 = ~0, strap; |
cd0b072f | 401 | int ret; |
6ee73861 BS |
402 | |
403 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
a0d069ea DC |
404 | if (!dev_priv) { |
405 | ret = -ENOMEM; | |
406 | goto err_out; | |
407 | } | |
94580299 | 408 | dev_priv->newpriv = dev->dev_private; |
6ee73861 BS |
409 | dev->dev_private = dev_priv; |
410 | dev_priv->dev = dev; | |
411 | ||
412 | dev_priv->flags = flags & NOUVEAU_FLAGS; | |
6ee73861 BS |
413 | |
414 | NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n", | |
415 | dev->pci_vendor, dev->pci_device, dev->pdev->class); | |
416 | ||
586c55f6 BS |
417 | /* determine chipset and derive architecture from it */ |
418 | reg0 = nv_rd32(dev, NV03_PMC_BOOT_0); | |
419 | if ((reg0 & 0x0f000000) > 0) { | |
420 | dev_priv->chipset = (reg0 & 0xff00000) >> 20; | |
421 | switch (dev_priv->chipset & 0xf0) { | |
422 | case 0x10: | |
423 | case 0x20: | |
424 | case 0x30: | |
425 | dev_priv->card_type = dev_priv->chipset & 0xf0; | |
426 | break; | |
427 | case 0x40: | |
428 | case 0x60: | |
429 | dev_priv->card_type = NV_40; | |
430 | break; | |
431 | case 0x50: | |
432 | case 0x80: | |
433 | case 0x90: | |
434 | case 0xa0: | |
435 | dev_priv->card_type = NV_50; | |
436 | break; | |
437 | case 0xc0: | |
438 | dev_priv->card_type = NV_C0; | |
439 | break; | |
440 | case 0xd0: | |
441 | dev_priv->card_type = NV_D0; | |
442 | break; | |
443 | case 0xe0: | |
444 | dev_priv->card_type = NV_E0; | |
445 | break; | |
446 | default: | |
447 | break; | |
2f5394c3 | 448 | } |
586c55f6 BS |
449 | } else |
450 | if ((reg0 & 0xff00fff0) == 0x20004000) { | |
451 | if (reg0 & 0x00f00000) | |
452 | dev_priv->chipset = 0x05; | |
453 | else | |
454 | dev_priv->chipset = 0x04; | |
455 | dev_priv->card_type = NV_04; | |
2f5394c3 BS |
456 | } |
457 | ||
458 | if (!dev_priv->card_type) { | |
459 | NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0); | |
460 | ret = -EINVAL; | |
461 | goto err_priv; | |
462 | } | |
463 | ||
42eddbd7 | 464 | NV_INFO(dev, "Detected an NV%02x generation card (0x%08x)\n", |
2f5394c3 | 465 | dev_priv->card_type, reg0); |
6ee73861 | 466 | |
f2cbe46f BS |
467 | /* determine frequency of timing crystal */ |
468 | strap = nv_rd32(dev, 0x101000); | |
469 | if ( dev_priv->chipset < 0x17 || | |
470 | (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25)) | |
471 | strap &= 0x00000040; | |
472 | else | |
473 | strap &= 0x00400040; | |
474 | ||
475 | switch (strap) { | |
476 | case 0x00000000: dev_priv->crystal = 13500; break; | |
477 | case 0x00000040: dev_priv->crystal = 14318; break; | |
478 | case 0x00400000: dev_priv->crystal = 27000; break; | |
479 | case 0x00400040: dev_priv->crystal = 25000; break; | |
480 | } | |
481 | ||
482 | NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal); | |
483 | ||
6ee73861 BS |
484 | nouveau_OF_copy_vbios_to_ramin(dev); |
485 | ||
486 | /* Special flags */ | |
487 | if (dev->pci_device == 0x01a0) | |
488 | dev_priv->flags |= NV_NFORCE; | |
489 | else if (dev->pci_device == 0x01f0) | |
490 | dev_priv->flags |= NV_NFORCE2; | |
491 | ||
492 | /* For kernel modesetting, init card now and bring up fbcon */ | |
cd0b072f BS |
493 | ret = nouveau_card_init(dev); |
494 | if (ret) | |
3863c9bc | 495 | goto err_priv; |
6ee73861 BS |
496 | |
497 | return 0; | |
a0d069ea | 498 | |
a0d069ea | 499 | err_priv: |
94580299 | 500 | dev->dev_private = dev_priv->newpriv; |
a0d069ea | 501 | kfree(dev_priv); |
a0d069ea DC |
502 | err_out: |
503 | return ret; | |
6ee73861 BS |
504 | } |
505 | ||
6ee73861 BS |
506 | void nouveau_lastclose(struct drm_device *dev) |
507 | { | |
5ccb377f | 508 | vga_switcheroo_process_delayed_switch(); |
6ee73861 BS |
509 | } |
510 | ||
511 | int nouveau_unload(struct drm_device *dev) | |
512 | { | |
513 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
514 | ||
cd0b072f | 515 | nouveau_card_takedown(dev); |
6ee73861 | 516 | |
94580299 | 517 | dev->dev_private = dev_priv->newpriv; |
6ee73861 | 518 | kfree(dev_priv); |
6ee73861 BS |
519 | return 0; |
520 | } | |
521 | ||
6ee73861 BS |
522 | /* Waits for PGRAPH to go completely idle */ |
523 | bool nouveau_wait_for_idle(struct drm_device *dev) | |
524 | { | |
0541324a FJ |
525 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
526 | uint32_t mask = ~0; | |
527 | ||
528 | if (dev_priv->card_type == NV_40) | |
529 | mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL; | |
530 | ||
531 | if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) { | |
6ee73861 BS |
532 | NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n", |
533 | nv_rd32(dev, NV04_PGRAPH_STATUS)); | |
534 | return false; | |
535 | } | |
536 | ||
537 | return true; | |
538 | } | |
539 |