[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_ttm.c

/*
 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA,
 * All Rights Reserved.
 * Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA,
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sub license,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#include "nouveau_drm.h"
#include "nouveau_ttm.h"
#include "nouveau_gem.h"

#include "drm_legacy.h"
static int
nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{
	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
	struct nvkm_fb *fb = nvxx_fb(&drm->device);
	man->priv = fb;
	return 0;
}

static int
nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
{
	man->priv = NULL;
	return 0;
}

static inline void
nvkm_mem_node_cleanup(struct nvkm_mem *node)
{
	if (node->vma[0].node) {
		nvkm_vm_unmap(&node->vma[0]);
		nvkm_vm_put(&node->vma[0]);
	}

	if (node->vma[1].node) {
		nvkm_vm_unmap(&node->vma[1]);
		nvkm_vm_put(&node->vma[1]);
	}
}

static void
nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
			 struct ttm_mem_reg *mem)
{
	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
	struct nvkm_ram *ram = nvxx_fb(&drm->device)->ram;
	nvkm_mem_node_cleanup(mem->mm_node);
	ram->func->put(ram, (struct nvkm_mem **)&mem->mm_node);
}

static int
nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
			 struct ttm_buffer_object *bo,
			 const struct ttm_place *place,
			 struct ttm_mem_reg *mem)
{
	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
	struct nvkm_ram *ram = nvxx_fb(&drm->device)->ram;
	struct nouveau_bo *nvbo = nouveau_bo(bo);
	struct nvkm_mem *node;
	u32 size_nc = 0;
	int ret;

	if (drm->device.info.ram_size == 0)
		return -ENOMEM;

	if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
		size_nc = 1 << nvbo->page_shift;

	ret = ram->func->get(ram, mem->num_pages << PAGE_SHIFT,
			     mem->page_alignment << PAGE_SHIFT, size_nc,
			     (nvbo->tile_flags >> 8) & 0x3ff, &node);
	if (ret) {
		mem->mm_node = NULL;
		return (ret == -ENOSPC) ? 0 : ret;
	}

	node->page_shift = nvbo->page_shift;

	mem->mm_node = node;
	mem->start   = node->offset >> PAGE_SHIFT;
	return 0;
}

const struct ttm_mem_type_manager_func nouveau_vram_manager = {
	nouveau_vram_manager_init,
	nouveau_vram_manager_fini,
	nouveau_vram_manager_new,
	nouveau_vram_manager_del,
};

static int
nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{
	return 0;
}

static int
nouveau_gart_manager_fini(struct ttm_mem_type_manager *man)
{
	return 0;
}

static void
nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
			 struct ttm_mem_reg *mem)
{
	nvkm_mem_node_cleanup(mem->mm_node);
	kfree(mem->mm_node);
	mem->mm_node = NULL;
}

static int
nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
			 struct ttm_buffer_object *bo,
			 const struct ttm_place *place,
			 struct ttm_mem_reg *mem)
{
	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
	struct nouveau_bo *nvbo = nouveau_bo(bo);
	struct nvkm_mem *node;

	node = kzalloc(sizeof(*node), GFP_KERNEL);
	if (!node)
		return -ENOMEM;

	node->page_shift = 12;

	switch (drm->device.info.family) {
	case NV_DEVICE_INFO_V0_TNT:
	case NV_DEVICE_INFO_V0_CELSIUS:
	case NV_DEVICE_INFO_V0_KELVIN:
	case NV_DEVICE_INFO_V0_RANKINE:
	case NV_DEVICE_INFO_V0_CURIE:
		break;
	case NV_DEVICE_INFO_V0_TESLA:
		if (drm->device.info.chipset != 0x50)
			node->memtype = (nvbo->tile_flags & 0x7f00) >> 8;
		break;
	case NV_DEVICE_INFO_V0_FERMI:
	case NV_DEVICE_INFO_V0_KEPLER:
	case NV_DEVICE_INFO_V0_MAXWELL:
		node->memtype = (nvbo->tile_flags & 0xff00) >> 8;
		break;
	default:
		NV_WARN(drm, "%s: unhandled family type %x\n", __func__,
			drm->device.info.family);
		break;
	}

	mem->mm_node = node;
	mem->start   = 0;
	return 0;
}

static void
nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
{
}

const struct ttm_mem_type_manager_func nouveau_gart_manager = {
	nouveau_gart_manager_init,
	nouveau_gart_manager_fini,
	nouveau_gart_manager_new,
	nouveau_gart_manager_del,
	nouveau_gart_manager_debug
};

/*XXX*/
#include <subdev/mmu/nv04.h>
static int
nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
{
	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
	struct nvkm_mmu *mmu = nvxx_mmu(&drm->device);
	struct nv04_mmu *priv = (void *)mmu;
	struct nvkm_vm *vm = NULL;
	nvkm_vm_ref(priv->vm, &vm, NULL);
	man->priv = vm;
	return 0;
}

static int
nv04_gart_manager_fini(struct ttm_mem_type_manager *man)
{
	struct nvkm_vm *vm = man->priv;
	nvkm_vm_ref(NULL, &vm, NULL);
	man->priv = NULL;
	return 0;
}

static void
nv04_gart_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem)
{
	struct nvkm_mem *node = mem->mm_node;
	if (node->vma[0].node)
		nvkm_vm_put(&node->vma[0]);
	kfree(mem->mm_node);
	mem->mm_node = NULL;
}

static int
nv04_gart_manager_new(struct ttm_mem_type_manager *man,
		      struct ttm_buffer_object *bo,
		      const struct ttm_place *place,
		      struct ttm_mem_reg *mem)
{
	struct nvkm_mem *node;
	int ret;

	node = kzalloc(sizeof(*node), GFP_KERNEL);
	if (!node)
		return -ENOMEM;

	node->page_shift = 12;

	ret = nvkm_vm_get(man->priv, mem->num_pages << 12, node->page_shift,
			  NV_MEM_ACCESS_RW, &node->vma[0]);
	if (ret) {
		kfree(node);
		return ret;
	}

	mem->mm_node = node;
	mem->start   = node->vma[0].offset >> PAGE_SHIFT;
	return 0;
}

static void
nv04_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
{
}

const struct ttm_mem_type_manager_func nv04_gart_manager = {
	nv04_gart_manager_init,
	nv04_gart_manager_fini,
	nv04_gart_manager_new,
	nv04_gart_manager_del,
	nv04_gart_manager_debug
};

int
nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma)
{
	struct drm_file *file_priv = filp->private_data;
	struct nouveau_drm *drm = nouveau_drm(file_priv->minor->dev);

	if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
		return drm_legacy_mmap(filp, vma);

	return ttm_bo_mmap(filp, vma, &drm->ttm.bdev);
}

static int
nouveau_ttm_mem_global_init(struct drm_global_reference *ref)
{
	return ttm_mem_global_init(ref->object);
}

static void
nouveau_ttm_mem_global_release(struct drm_global_reference *ref)
{
	ttm_mem_global_release(ref->object);
}

int
nouveau_ttm_global_init(struct nouveau_drm *drm)
{
	struct drm_global_reference *global_ref;
	int ret;

	global_ref = &drm->ttm.mem_global_ref;
	global_ref->global_type = DRM_GLOBAL_TTM_MEM;
	global_ref->size = sizeof(struct ttm_mem_global);
	global_ref->init = &nouveau_ttm_mem_global_init;
	global_ref->release = &nouveau_ttm_mem_global_release;

	ret = drm_global_item_ref(global_ref);
	if (unlikely(ret != 0)) {
		DRM_ERROR("Failed setting up TTM memory accounting\n");
		drm->ttm.mem_global_ref.release = NULL;
		return ret;
	}

	drm->ttm.bo_global_ref.mem_glob = global_ref->object;
	global_ref = &drm->ttm.bo_global_ref.ref;
	global_ref->global_type = DRM_GLOBAL_TTM_BO;
	global_ref->size = sizeof(struct ttm_bo_global);
	global_ref->init = &ttm_bo_global_init;
	global_ref->release = &ttm_bo_global_release;

	ret = drm_global_item_ref(global_ref);
	if (unlikely(ret != 0)) {
		DRM_ERROR("Failed setting up TTM BO subsystem\n");
		drm_global_item_unref(&drm->ttm.mem_global_ref);
		drm->ttm.mem_global_ref.release = NULL;
		return ret;
	}

	return 0;
}

void
nouveau_ttm_global_release(struct nouveau_drm *drm)
{
	if (drm->ttm.mem_global_ref.release == NULL)
		return;

	drm_global_item_unref(&drm->ttm.bo_global_ref.ref);
	drm_global_item_unref(&drm->ttm.mem_global_ref);
	drm->ttm.mem_global_ref.release = NULL;
}

int
nouveau_ttm_init(struct nouveau_drm *drm)
{
	struct drm_device *dev = drm->dev;
	u32 bits;
	int ret;

	bits = nvxx_mmu(&drm->device)->dma_bits;
	if (nv_device_is_pci(nvxx_device(&drm->device))) {
		if (drm->agp.stat == ENABLED ||
		     !pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits)))
			bits = 32;

		ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(bits));
		if (ret)
			return ret;

		ret = pci_set_consistent_dma_mask(dev->pdev,
						  DMA_BIT_MASK(bits));
		if (ret)
			pci_set_consistent_dma_mask(dev->pdev,
						    DMA_BIT_MASK(32));
	}

	ret = nouveau_ttm_global_init(drm);
	if (ret)
		return ret;

	ret = ttm_bo_device_init(&drm->ttm.bdev,
				  drm->ttm.bo_global_ref.ref.object,
				  &nouveau_bo_driver,
				  dev->anon_inode->i_mapping,
				  DRM_FILE_PAGE_OFFSET,
				  bits <= 32 ? true : false);
	if (ret) {
		NV_ERROR(drm, "error initialising bo driver, %d\n", ret);
		return ret;
	}

	/* VRAM init */
	drm->gem.vram_available = drm->device.info.ram_user;

	ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_VRAM,
			      drm->gem.vram_available >> PAGE_SHIFT);
	if (ret) {
		NV_ERROR(drm, "VRAM mm init failed, %d\n", ret);
		return ret;
	}

	drm->ttm.mtrr = arch_phys_wc_add(nv_device_resource_start(nvxx_device(&drm->device), 1),
					 nv_device_resource_len(nvxx_device(&drm->device), 1));

	/* GART init */
	if (drm->agp.stat != ENABLED) {
		drm->gem.gart_available = nvxx_mmu(&drm->device)->limit;
	} else {
		drm->gem.gart_available = drm->agp.size;
	}

	ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_TT,
			      drm->gem.gart_available >> PAGE_SHIFT);
	if (ret) {
		NV_ERROR(drm, "GART mm init failed, %d\n", ret);
		return ret;
	}

	NV_INFO(drm, "VRAM: %d MiB\n", (u32)(drm->gem.vram_available >> 20));
	NV_INFO(drm, "GART: %d MiB\n", (u32)(drm->gem.gart_available >> 20));
	return 0;
}

void
nouveau_ttm_fini(struct nouveau_drm *drm)
{
	ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_VRAM);
	ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_TT);

	ttm_bo_device_release(&drm->ttm.bdev);

	nouveau_ttm_global_release(drm);

	arch_phys_wc_del(drm->ttm.mtrr);
	drm->ttm.mtrr = 0;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA,
	3	* All Rights Reserved.
	4	* Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA,
	5	* All Rights Reserved.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a
	8	* copy of this software and associated documentation files (the "Software"),
	9	* to deal in the Software without restriction, including without limitation
	10	* the rights to use, copy, modify, merge, publish, distribute, sub license,
	11	* and/or sell copies of the Software, and to permit persons to whom the
	12	* Software is furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice (including the
	15	* next paragraph) shall be included in all copies or substantial portions
	16	* of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	21	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	22	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	23	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	24	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	25	*/
	26
ebb945a9 BS	27	#include "nouveau_drm.h"
	28	#include "nouveau_ttm.h"
	29	#include "nouveau_gem.h"
6ee73861	30
2036eaa7	31	#include "drm_legacy.h"
bc9e7b9a BS	32	static int
	33	nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
	34	{
897a6e27	35	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
b1e4553c BS	36	struct nvkm_fb *fb = nvxx_fb(&drm->device);
b1e4553c BS	37	man->priv = fb;
bc9e7b9a BS	38	return 0;
	39	}
	40
	41	static int
	42	nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
	43	{
897a6e27	44	man->priv = NULL;
bc9e7b9a BS	45	return 0;
	46	}
	47
	48	static inline void
be83cd4e	49	nvkm_mem_node_cleanup(struct nvkm_mem *node)
bc9e7b9a BS	50	{
bc9e7b9a BS	51	if (node->vma[0].node) {
be83cd4e BS	52	nvkm_vm_unmap(&node->vma[0]);
be83cd4e BS	53	nvkm_vm_put(&node->vma[0]);
bc9e7b9a BS	54	}
	55
	56	if (node->vma[1].node) {
be83cd4e BS	57	nvkm_vm_unmap(&node->vma[1]);
be83cd4e BS	58	nvkm_vm_put(&node->vma[1]);
bc9e7b9a BS	59	}
	60	}
	61
	62	static void
	63	nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
	64	struct ttm_mem_reg *mem)
	65	{
ebb945a9	66	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
d36a99d2	67	struct nvkm_ram *ram = nvxx_fb(&drm->device)->ram;
be83cd4e	68	nvkm_mem_node_cleanup(mem->mm_node);
d36a99d2	69	ram->func->put(ram, (struct nvkm_mem **)&mem->mm_node);
bc9e7b9a BS	70	}
	71
	72	static int
	73	nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
	74	struct ttm_buffer_object *bo,
f1217ed0	75	const struct ttm_place *place,
bc9e7b9a BS	76	struct ttm_mem_reg *mem)
bc9e7b9a BS	77	{
ebb945a9	78	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
d36a99d2	79	struct nvkm_ram *ram = nvxx_fb(&drm->device)->ram;
bc9e7b9a	80	struct nouveau_bo *nvbo = nouveau_bo(bo);
be83cd4e	81	struct nvkm_mem *node;
bc9e7b9a BS	82	u32 size_nc = 0;
	83	int ret;
	84
eaecf032 AC	85	if (drm->device.info.ram_size == 0)
	86	return -ENOMEM;
	87
bc9e7b9a BS	88	if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
	89	size_nc = 1 << nvbo->page_shift;
	90
d36a99d2 BS	91	ret = ram->func->get(ram, mem->num_pages << PAGE_SHIFT,
	92	mem->page_alignment << PAGE_SHIFT, size_nc,
	93	(nvbo->tile_flags >> 8) & 0x3ff, &node);
bc9e7b9a BS	94	if (ret) {
	95	mem->mm_node = NULL;
	96	return (ret == -ENOSPC) ? 0 : ret;
	97	}
	98
	99	node->page_shift = nvbo->page_shift;
	100
	101	mem->mm_node = node;
	102	mem->start = node->offset >> PAGE_SHIFT;
	103	return 0;
	104	}
	105
bc9e7b9a BS	106	const struct ttm_mem_type_manager_func nouveau_vram_manager = {
	107	nouveau_vram_manager_init,
	108	nouveau_vram_manager_fini,
	109	nouveau_vram_manager_new,
	110	nouveau_vram_manager_del,
bc9e7b9a BS	111	};
	112
	113	static int
	114	nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
	115	{
	116	return 0;
	117	}
	118
	119	static int
	120	nouveau_gart_manager_fini(struct ttm_mem_type_manager *man)
	121	{
	122	return 0;
	123	}
	124
	125	static void
	126	nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
	127	struct ttm_mem_reg *mem)
	128	{
be83cd4e	129	nvkm_mem_node_cleanup(mem->mm_node);
bc9e7b9a BS	130	kfree(mem->mm_node);
	131	mem->mm_node = NULL;
	132	}
	133
	134	static int
	135	nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
	136	struct ttm_buffer_object *bo,
f1217ed0	137	const struct ttm_place *place,
bc9e7b9a BS	138	struct ttm_mem_reg *mem)
bc9e7b9a BS	139	{
de7b7d59 BS	140	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
de7b7d59 BS	141	struct nouveau_bo *nvbo = nouveau_bo(bo);
be83cd4e	142	struct nvkm_mem *node;
bc9e7b9a	143
bc9e7b9a BS	144	node = kzalloc(sizeof(*node), GFP_KERNEL);
	145	if (!node)
	146	return -ENOMEM;
2e2cfbe6	147
bc9e7b9a BS	148	node->page_shift = 12;
bc9e7b9a BS	149
967e7bde	150	switch (drm->device.info.family) {
eb48b12e AC	151	case NV_DEVICE_INFO_V0_TNT:
	152	case NV_DEVICE_INFO_V0_CELSIUS:
	153	case NV_DEVICE_INFO_V0_KELVIN:
	154	case NV_DEVICE_INFO_V0_RANKINE:
	155	case NV_DEVICE_INFO_V0_CURIE:
	156	break;
967e7bde BS	157	case NV_DEVICE_INFO_V0_TESLA:
967e7bde BS	158	if (drm->device.info.chipset != 0x50)
de7b7d59 BS	159	node->memtype = (nvbo->tile_flags & 0x7f00) >> 8;
de7b7d59 BS	160	break;
967e7bde BS	161	case NV_DEVICE_INFO_V0_FERMI:
967e7bde BS	162	case NV_DEVICE_INFO_V0_KEPLER:
eb48b12e	163	case NV_DEVICE_INFO_V0_MAXWELL:
de7b7d59 BS	164	node->memtype = (nvbo->tile_flags & 0xff00) >> 8;
	165	break;
	166	default:
eb48b12e AC	167	NV_WARN(drm, "%s: unhandled family type %x\n", __func__,
eb48b12e AC	168	drm->device.info.family);
de7b7d59 BS	169	break;
	170	}
	171
bc9e7b9a BS	172	mem->mm_node = node;
	173	mem->start = 0;
	174	return 0;
	175	}
	176
5b8a43ae	177	static void
bc9e7b9a BS	178	nouveau_gart_manager_debug(struct ttm_mem_type_manager man, const char prefix)
	179	{
	180	}
	181
	182	const struct ttm_mem_type_manager_func nouveau_gart_manager = {
	183	nouveau_gart_manager_init,
	184	nouveau_gart_manager_fini,
	185	nouveau_gart_manager_new,
	186	nouveau_gart_manager_del,
	187	nouveau_gart_manager_debug
	188	};
	189
fdb751ef	190	/XXX/
5ce3bf3c	191	#include <subdev/mmu/nv04.h>
bc9e7b9a BS	192	static int
	193	nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
	194	{
ebb945a9	195	struct nouveau_drm *drm = nouveau_bdev(man->bdev);
be83cd4e	196	struct nvkm_mmu *mmu = nvxx_mmu(&drm->device);
1f5bffca	197	struct nv04_mmu priv = (void )mmu;
be83cd4e BS	198	struct nvkm_vm *vm = NULL;
be83cd4e BS	199	nvkm_vm_ref(priv->vm, &vm, NULL);
ebb945a9 BS	200	man->priv = vm;
ebb945a9 BS	201	return 0;
bc9e7b9a BS	202	}
	203
	204	static int
	205	nv04_gart_manager_fini(struct ttm_mem_type_manager *man)
	206	{
be83cd4e BS	207	struct nvkm_vm *vm = man->priv;
be83cd4e BS	208	nvkm_vm_ref(NULL, &vm, NULL);
bc9e7b9a BS	209	man->priv = NULL;
	210	return 0;
	211	}
	212
	213	static void
	214	nv04_gart_manager_del(struct ttm_mem_type_manager man, struct ttm_mem_reg mem)
	215	{
be83cd4e	216	struct nvkm_mem *node = mem->mm_node;
bc9e7b9a	217	if (node->vma[0].node)
be83cd4e	218	nvkm_vm_put(&node->vma[0]);
bc9e7b9a BS	219	kfree(mem->mm_node);
	220	mem->mm_node = NULL;
	221	}
	222
	223	static int
	224	nv04_gart_manager_new(struct ttm_mem_type_manager *man,
	225	struct ttm_buffer_object *bo,
f1217ed0	226	const struct ttm_place *place,
bc9e7b9a BS	227	struct ttm_mem_reg *mem)
bc9e7b9a BS	228	{
be83cd4e	229	struct nvkm_mem *node;
bc9e7b9a BS	230	int ret;
	231
	232	node = kzalloc(sizeof(*node), GFP_KERNEL);
	233	if (!node)
	234	return -ENOMEM;
	235
	236	node->page_shift = 12;
	237
be83cd4e BS	238	ret = nvkm_vm_get(man->priv, mem->num_pages << 12, node->page_shift,
be83cd4e BS	239	NV_MEM_ACCESS_RW, &node->vma[0]);
bc9e7b9a BS	240	if (ret) {
	241	kfree(node);
	242	return ret;
	243	}
	244
	245	mem->mm_node = node;
	246	mem->start = node->vma[0].offset >> PAGE_SHIFT;
	247	return 0;
	248	}
	249
5b8a43ae	250	static void
bc9e7b9a BS	251	nv04_gart_manager_debug(struct ttm_mem_type_manager man, const char prefix)
	252	{
	253	}
	254
	255	const struct ttm_mem_type_manager_func nv04_gart_manager = {
	256	nv04_gart_manager_init,
	257	nv04_gart_manager_fini,
	258	nv04_gart_manager_new,
	259	nv04_gart_manager_del,
	260	nv04_gart_manager_debug
	261	};
	262
6ee73861 BS	263	int
	264	nouveau_ttm_mmap(struct file filp, struct vm_area_struct vma)
	265	{
	266	struct drm_file *file_priv = filp->private_data;
77145f1c	267	struct nouveau_drm *drm = nouveau_drm(file_priv->minor->dev);
6ee73861 BS	268
6ee73861 BS	269	if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
2036eaa7	270	return drm_legacy_mmap(filp, vma);
6ee73861	271
ebb945a9	272	return ttm_bo_mmap(filp, vma, &drm->ttm.bdev);
6ee73861 BS	273	}
	274
	275	static int
ba4420c2	276	nouveau_ttm_mem_global_init(struct drm_global_reference *ref)
6ee73861 BS	277	{
	278	return ttm_mem_global_init(ref->object);
	279	}
	280
	281	static void
ba4420c2	282	nouveau_ttm_mem_global_release(struct drm_global_reference *ref)
6ee73861 BS	283	{
	284	ttm_mem_global_release(ref->object);
	285	}
	286
	287	int
ebb945a9	288	nouveau_ttm_global_init(struct nouveau_drm *drm)
6ee73861	289	{
ba4420c2	290	struct drm_global_reference *global_ref;
6ee73861 BS	291	int ret;
6ee73861 BS	292
ebb945a9	293	global_ref = &drm->ttm.mem_global_ref;
ba4420c2	294	global_ref->global_type = DRM_GLOBAL_TTM_MEM;
6ee73861 BS	295	global_ref->size = sizeof(struct ttm_mem_global);
	296	global_ref->init = &nouveau_ttm_mem_global_init;
	297	global_ref->release = &nouveau_ttm_mem_global_release;
	298
ba4420c2	299	ret = drm_global_item_ref(global_ref);
6ee73861 BS	300	if (unlikely(ret != 0)) {
6ee73861 BS	301	DRM_ERROR("Failed setting up TTM memory accounting\n");
ebb945a9	302	drm->ttm.mem_global_ref.release = NULL;
6ee73861 BS	303	return ret;
	304	}
	305
ebb945a9 BS	306	drm->ttm.bo_global_ref.mem_glob = global_ref->object;
ebb945a9 BS	307	global_ref = &drm->ttm.bo_global_ref.ref;
ba4420c2	308	global_ref->global_type = DRM_GLOBAL_TTM_BO;
6ee73861 BS	309	global_ref->size = sizeof(struct ttm_bo_global);
	310	global_ref->init = &ttm_bo_global_init;
	311	global_ref->release = &ttm_bo_global_release;
	312
ba4420c2	313	ret = drm_global_item_ref(global_ref);
6ee73861 BS	314	if (unlikely(ret != 0)) {
6ee73861 BS	315	DRM_ERROR("Failed setting up TTM BO subsystem\n");
ebb945a9 BS	316	drm_global_item_unref(&drm->ttm.mem_global_ref);
ebb945a9 BS	317	drm->ttm.mem_global_ref.release = NULL;
6ee73861 BS	318	return ret;
	319	}
	320
	321	return 0;
	322	}
	323
	324	void
ebb945a9	325	nouveau_ttm_global_release(struct nouveau_drm *drm)
6ee73861	326	{
ebb945a9	327	if (drm->ttm.mem_global_ref.release == NULL)
6ee73861 BS	328	return;
6ee73861 BS	329
ebb945a9 BS	330	drm_global_item_unref(&drm->ttm.bo_global_ref.ref);
	331	drm_global_item_unref(&drm->ttm.mem_global_ref);
	332	drm->ttm.mem_global_ref.release = NULL;
	333	}
	334
	335	int
	336	nouveau_ttm_init(struct nouveau_drm *drm)
	337	{
	338	struct drm_device *dev = drm->dev;
	339	u32 bits;
	340	int ret;
	341
989aa5b7 BS	342	bits = nvxx_mmu(&drm->device)->dma_bits;
989aa5b7 BS	343	if (nv_device_is_pci(nvxx_device(&drm->device))) {
420b9469 AC	344	if (drm->agp.stat == ENABLED \|\|
	345	!pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits)))
	346	bits = 32;
	347
	348	ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(bits));
	349	if (ret)
	350	return ret;
	351
	352	ret = pci_set_consistent_dma_mask(dev->pdev,
	353	DMA_BIT_MASK(bits));
	354	if (ret)
	355	pci_set_consistent_dma_mask(dev->pdev,
	356	DMA_BIT_MASK(32));
	357	}
ebb945a9 BS	358
	359	ret = nouveau_ttm_global_init(drm);
	360	if (ret)
	361	return ret;
	362
	363	ret = ttm_bo_device_init(&drm->ttm.bdev,
	364	drm->ttm.bo_global_ref.ref.object,
44d847b7 DH	365	&nouveau_bo_driver,
	366	dev->anon_inode->i_mapping,
	367	DRM_FILE_PAGE_OFFSET,
ebb945a9 BS	368	bits <= 32 ? true : false);
	369	if (ret) {
	370	NV_ERROR(drm, "error initialising bo driver, %d\n", ret);
	371	return ret;
	372	}
	373
	374	/* VRAM init */
f392ec4b	375	drm->gem.vram_available = drm->device.info.ram_user;
ebb945a9 BS	376
	377	ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_VRAM,
	378	drm->gem.vram_available >> PAGE_SHIFT);
	379	if (ret) {
	380	NV_ERROR(drm, "VRAM mm init failed, %d\n", ret);
	381	return ret;
	382	}
	383
989aa5b7 BS	384	drm->ttm.mtrr = arch_phys_wc_add(nv_device_resource_start(nvxx_device(&drm->device), 1),
989aa5b7 BS	385	nv_device_resource_len(nvxx_device(&drm->device), 1));
ebb945a9 BS	386
	387	/* GART init */
	388	if (drm->agp.stat != ENABLED) {
989aa5b7	389	drm->gem.gart_available = nvxx_mmu(&drm->device)->limit;
ebb945a9 BS	390	} else {
	391	drm->gem.gart_available = drm->agp.size;
	392	}
	393
	394	ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_TT,
	395	drm->gem.gart_available >> PAGE_SHIFT);
	396	if (ret) {
	397	NV_ERROR(drm, "GART mm init failed, %d\n", ret);
	398	return ret;
	399	}
	400
	401	NV_INFO(drm, "VRAM: %d MiB\n", (u32)(drm->gem.vram_available >> 20));
	402	NV_INFO(drm, "GART: %d MiB\n", (u32)(drm->gem.gart_available >> 20));
	403	return 0;
	404	}
	405
	406	void
	407	nouveau_ttm_fini(struct nouveau_drm *drm)
	408	{
ebb945a9 BS	409	ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_VRAM);
ebb945a9 BS	410	ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_TT);
ebb945a9 BS	411
	412	ttm_bo_device_release(&drm->ttm.bdev);
	413
	414	nouveau_ttm_global_release(drm);
	415
247d36d7 AL	416	arch_phys_wc_del(drm->ttm.mtrr);
247d36d7 AL	417	drm->ttm.mtrr = 0;
6ee73861	418	}