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6ee73861 BS |
1 | /* |
2 | * Copyright 2009 Ben Skeggs | |
3 | * Copyright 2008 Stuart Bennett | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | ||
ebb945a9 | 25 | #include "nouveau_drm.h" |
6ee73861 BS |
26 | #include "nouveau_dma.h" |
27 | #include "nouveau_fbcon.h" | |
28 | ||
ceed5f30 | 29 | int |
6ee73861 BS |
30 | nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) |
31 | { | |
8be48d92 | 32 | struct nouveau_fbdev *nfbdev = info->par; |
77145f1c | 33 | struct nouveau_drm *drm = nouveau_drm(nfbdev->dev); |
ebb945a9 | 34 | struct nouveau_channel *chan = drm->channel; |
ceed5f30 | 35 | int ret; |
6ee73861 | 36 | |
ceed5f30 BS |
37 | ret = RING_SPACE(chan, 4); |
38 | if (ret) | |
39 | return ret; | |
6ee73861 | 40 | |
6d597027 | 41 | BEGIN_NV04(chan, NvSubImageBlit, 0x0300, 3); |
6ee73861 BS |
42 | OUT_RING(chan, (region->sy << 16) | region->sx); |
43 | OUT_RING(chan, (region->dy << 16) | region->dx); | |
44 | OUT_RING(chan, (region->height << 16) | region->width); | |
45 | FIRE_RING(chan); | |
ceed5f30 | 46 | return 0; |
6ee73861 BS |
47 | } |
48 | ||
ceed5f30 | 49 | int |
6ee73861 BS |
50 | nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) |
51 | { | |
8be48d92 | 52 | struct nouveau_fbdev *nfbdev = info->par; |
77145f1c | 53 | struct nouveau_drm *drm = nouveau_drm(nfbdev->dev); |
ebb945a9 | 54 | struct nouveau_channel *chan = drm->channel; |
ceed5f30 | 55 | int ret; |
6ee73861 | 56 | |
ceed5f30 BS |
57 | ret = RING_SPACE(chan, 7); |
58 | if (ret) | |
59 | return ret; | |
6ee73861 | 60 | |
6d597027 | 61 | BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1); |
6ee73861 | 62 | OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3); |
6d597027 | 63 | BEGIN_NV04(chan, NvSubGdiRect, 0x03fc, 1); |
bf5302b9 BS |
64 | if (info->fix.visual == FB_VISUAL_TRUECOLOR || |
65 | info->fix.visual == FB_VISUAL_DIRECTCOLOR) | |
66 | OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); | |
67 | else | |
68 | OUT_RING(chan, rect->color); | |
6d597027 | 69 | BEGIN_NV04(chan, NvSubGdiRect, 0x0400, 2); |
6ee73861 BS |
70 | OUT_RING(chan, (rect->dx << 16) | rect->dy); |
71 | OUT_RING(chan, (rect->width << 16) | rect->height); | |
72 | FIRE_RING(chan); | |
ceed5f30 | 73 | return 0; |
6ee73861 BS |
74 | } |
75 | ||
ceed5f30 | 76 | int |
6ee73861 BS |
77 | nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) |
78 | { | |
8be48d92 | 79 | struct nouveau_fbdev *nfbdev = info->par; |
77145f1c | 80 | struct nouveau_drm *drm = nouveau_drm(nfbdev->dev); |
ebb945a9 | 81 | struct nouveau_channel *chan = drm->channel; |
6ee73861 BS |
82 | uint32_t fg; |
83 | uint32_t bg; | |
84 | uint32_t dsize; | |
85 | uint32_t width; | |
86 | uint32_t *data = (uint32_t *)image->data; | |
ceed5f30 | 87 | int ret; |
6ee73861 | 88 | |
ceed5f30 BS |
89 | if (image->depth != 1) |
90 | return -ENODEV; | |
6ee73861 | 91 | |
ceed5f30 BS |
92 | ret = RING_SPACE(chan, 8); |
93 | if (ret) | |
94 | return ret; | |
6ee73861 | 95 | |
c82b88d5 MK |
96 | width = ALIGN(image->width, 8); |
97 | dsize = ALIGN(width * image->height, 32) >> 5; | |
6ee73861 BS |
98 | |
99 | if (info->fix.visual == FB_VISUAL_TRUECOLOR || | |
100 | info->fix.visual == FB_VISUAL_DIRECTCOLOR) { | |
101 | fg = ((uint32_t *) info->pseudo_palette)[image->fg_color]; | |
102 | bg = ((uint32_t *) info->pseudo_palette)[image->bg_color]; | |
103 | } else { | |
104 | fg = image->fg_color; | |
105 | bg = image->bg_color; | |
106 | } | |
107 | ||
6d597027 | 108 | BEGIN_NV04(chan, NvSubGdiRect, 0x0be4, 7); |
6ee73861 BS |
109 | OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff)); |
110 | OUT_RING(chan, ((image->dy + image->height) << 16) | | |
111 | ((image->dx + image->width) & 0xffff)); | |
112 | OUT_RING(chan, bg); | |
113 | OUT_RING(chan, fg); | |
6ee73861 | 114 | OUT_RING(chan, (image->height << 16) | width); |
c82b88d5 | 115 | OUT_RING(chan, (image->height << 16) | image->width); |
6ee73861 BS |
116 | OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff)); |
117 | ||
118 | while (dsize) { | |
119 | int iter_len = dsize > 128 ? 128 : dsize; | |
120 | ||
ceed5f30 BS |
121 | ret = RING_SPACE(chan, iter_len + 1); |
122 | if (ret) | |
123 | return ret; | |
6ee73861 | 124 | |
6d597027 | 125 | BEGIN_NV04(chan, NvSubGdiRect, 0x0c00, iter_len); |
6ee73861 BS |
126 | OUT_RINGp(chan, data, iter_len); |
127 | data += iter_len; | |
128 | dsize -= iter_len; | |
129 | } | |
130 | ||
131 | FIRE_RING(chan); | |
ceed5f30 | 132 | return 0; |
6ee73861 BS |
133 | } |
134 | ||
6ee73861 BS |
135 | int |
136 | nv04_fbcon_accel_init(struct fb_info *info) | |
137 | { | |
8be48d92 DA |
138 | struct nouveau_fbdev *nfbdev = info->par; |
139 | struct drm_device *dev = nfbdev->dev; | |
77145f1c | 140 | struct nouveau_drm *drm = nouveau_drm(dev); |
ebb945a9 | 141 | struct nouveau_channel *chan = drm->channel; |
967e7bde | 142 | struct nvif_device *device = &drm->device; |
6ee73861 BS |
143 | int surface_fmt, pattern_fmt, rect_fmt; |
144 | int ret; | |
145 | ||
146 | switch (info->var.bits_per_pixel) { | |
147 | case 8: | |
148 | surface_fmt = 1; | |
149 | pattern_fmt = 3; | |
150 | rect_fmt = 3; | |
151 | break; | |
152 | case 16: | |
153 | surface_fmt = 4; | |
154 | pattern_fmt = 1; | |
155 | rect_fmt = 1; | |
156 | break; | |
157 | case 32: | |
158 | switch (info->var.transp.length) { | |
159 | case 0: /* depth 24 */ | |
160 | case 8: /* depth 32 */ | |
161 | break; | |
162 | default: | |
163 | return -EINVAL; | |
164 | } | |
165 | ||
166 | surface_fmt = 6; | |
167 | pattern_fmt = 3; | |
168 | rect_fmt = 3; | |
169 | break; | |
170 | default: | |
171 | return -EINVAL; | |
172 | } | |
173 | ||
a01ca78c | 174 | ret = nvif_object_init(&chan->user, 0x0062, |
0ad72863 BS |
175 | device->info.family >= NV_DEVICE_INFO_V0_CELSIUS ? |
176 | 0x0062 : 0x0042, NULL, 0, &nfbdev->surf2d); | |
6ee73861 BS |
177 | if (ret) |
178 | return ret; | |
179 | ||
a01ca78c | 180 | ret = nvif_object_init(&chan->user, 0x0019, 0x0019, NULL, 0, |
0ad72863 | 181 | &nfbdev->clip); |
6ee73861 BS |
182 | if (ret) |
183 | return ret; | |
184 | ||
a01ca78c | 185 | ret = nvif_object_init(&chan->user, 0x0043, 0x0043, NULL, 0, |
0ad72863 | 186 | &nfbdev->rop); |
6ee73861 BS |
187 | if (ret) |
188 | return ret; | |
189 | ||
a01ca78c | 190 | ret = nvif_object_init(&chan->user, 0x0044, 0x0044, NULL, 0, |
0ad72863 | 191 | &nfbdev->patt); |
6ee73861 BS |
192 | if (ret) |
193 | return ret; | |
194 | ||
a01ca78c | 195 | ret = nvif_object_init(&chan->user, 0x004a, 0x004a, NULL, 0, |
0ad72863 | 196 | &nfbdev->gdi); |
6ee73861 BS |
197 | if (ret) |
198 | return ret; | |
199 | ||
a01ca78c | 200 | ret = nvif_object_init(&chan->user, 0x005f, |
0ad72863 BS |
201 | device->info.chipset >= 0x11 ? 0x009f : 0x005f, |
202 | NULL, 0, &nfbdev->blit); | |
6ee73861 BS |
203 | if (ret) |
204 | return ret; | |
205 | ||
d108142c | 206 | if (RING_SPACE(chan, 49 + (device->info.chipset >= 0x11 ? 4 : 0))) { |
846975a9 | 207 | nouveau_fbcon_gpu_lockup(info); |
6ee73861 BS |
208 | return 0; |
209 | } | |
210 | ||
ebb945a9 | 211 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); |
f45f55c4 | 212 | OUT_RING(chan, nfbdev->surf2d.handle); |
ebb945a9 | 213 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2); |
f45f55c4 BS |
214 | OUT_RING(chan, chan->vram.handle); |
215 | OUT_RING(chan, chan->vram.handle); | |
ebb945a9 | 216 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4); |
6ee73861 BS |
217 | OUT_RING(chan, surface_fmt); |
218 | OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16)); | |
219 | OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); | |
220 | OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); | |
221 | ||
ebb945a9 | 222 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); |
f45f55c4 | 223 | OUT_RING(chan, nfbdev->rop.handle); |
ebb945a9 | 224 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1); |
6ee73861 BS |
225 | OUT_RING(chan, 0x55); |
226 | ||
ebb945a9 | 227 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); |
f45f55c4 | 228 | OUT_RING(chan, nfbdev->patt.handle); |
ebb945a9 | 229 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8); |
6ee73861 BS |
230 | OUT_RING(chan, pattern_fmt); |
231 | #ifdef __BIG_ENDIAN | |
232 | OUT_RING(chan, 2); | |
233 | #else | |
234 | OUT_RING(chan, 1); | |
235 | #endif | |
236 | OUT_RING(chan, 0); | |
237 | OUT_RING(chan, 1); | |
238 | OUT_RING(chan, ~0); | |
239 | OUT_RING(chan, ~0); | |
240 | OUT_RING(chan, ~0); | |
241 | OUT_RING(chan, ~0); | |
242 | ||
ebb945a9 | 243 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); |
f45f55c4 | 244 | OUT_RING(chan, nfbdev->clip.handle); |
ebb945a9 | 245 | BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2); |
6ee73861 BS |
246 | OUT_RING(chan, 0); |
247 | OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual); | |
248 | ||
6d597027 | 249 | BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1); |
f45f55c4 | 250 | OUT_RING(chan, nfbdev->blit.handle); |
6d597027 | 251 | BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1); |
f45f55c4 | 252 | OUT_RING(chan, nfbdev->surf2d.handle); |
6d597027 | 253 | BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1); |
6ee73861 | 254 | OUT_RING(chan, 3); |
967e7bde | 255 | if (device->info.chipset >= 0x11 /*XXX: oclass == 0x009f*/) { |
b9d9dcda BS |
256 | BEGIN_NV04(chan, NvSubImageBlit, 0x0120, 3); |
257 | OUT_RING(chan, 0); | |
258 | OUT_RING(chan, 1); | |
259 | OUT_RING(chan, 2); | |
260 | } | |
6ee73861 | 261 | |
6d597027 | 262 | BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1); |
f45f55c4 | 263 | OUT_RING(chan, nfbdev->gdi.handle); |
6d597027 | 264 | BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1); |
f45f55c4 | 265 | OUT_RING(chan, nfbdev->surf2d.handle); |
6d597027 | 266 | BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2); |
f45f55c4 BS |
267 | OUT_RING(chan, nfbdev->patt.handle); |
268 | OUT_RING(chan, nfbdev->rop.handle); | |
6d597027 | 269 | BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1); |
6ee73861 | 270 | OUT_RING(chan, 1); |
6d597027 | 271 | BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1); |
6ee73861 | 272 | OUT_RING(chan, rect_fmt); |
6d597027 | 273 | BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1); |
6ee73861 BS |
274 | OUT_RING(chan, 3); |
275 | ||
276 | FIRE_RING(chan); | |
277 | ||
6ee73861 BS |
278 | return 0; |
279 | } | |
280 |