[deliverable/linux.git] / drivers / gpu / drm / nouveau / nv04_fbcon.c

/*
 * Copyright 2009 Ben Skeggs
 * Copyright 2008 Stuart Bennett
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_dma.h"
#include "nouveau_ramht.h"
#include "nouveau_fbcon.h"

int
nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
{
	struct nouveau_fbdev *nfbdev = info->par;
	struct drm_device *dev = nfbdev->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_channel *chan = dev_priv->channel;
	int ret;

	ret = RING_SPACE(chan, 4);
	if (ret)
		return ret;

	BEGIN_RING(chan, NvSubImageBlit, 0x0300, 3);
	OUT_RING(chan, (region->sy << 16) | region->sx);
	OUT_RING(chan, (region->dy << 16) | region->dx);
	OUT_RING(chan, (region->height << 16) | region->width);
	FIRE_RING(chan);
	return 0;
}

int
nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
	struct nouveau_fbdev *nfbdev = info->par;
	struct drm_device *dev = nfbdev->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_channel *chan = dev_priv->channel;
	int ret;

	ret = RING_SPACE(chan, 7);
	if (ret)
		return ret;

	BEGIN_RING(chan, NvSubGdiRect, 0x02fc, 1);
	OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3);
	BEGIN_RING(chan, NvSubGdiRect, 0x03fc, 1);
	if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
	    info->fix.visual == FB_VISUAL_DIRECTCOLOR)
		OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
	else
		OUT_RING(chan, rect->color);
	BEGIN_RING(chan, NvSubGdiRect, 0x0400, 2);
	OUT_RING(chan, (rect->dx << 16) | rect->dy);
	OUT_RING(chan, (rect->width << 16) | rect->height);
	FIRE_RING(chan);
	return 0;
}

int
nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
{
	struct nouveau_fbdev *nfbdev = info->par;
	struct drm_device *dev = nfbdev->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_channel *chan = dev_priv->channel;
	uint32_t fg;
	uint32_t bg;
	uint32_t dsize;
	uint32_t width;
	uint32_t *data = (uint32_t *)image->data;
	int ret;

	if (image->depth != 1)
		return -ENODEV;

	ret = RING_SPACE(chan, 8);
	if (ret)
		return ret;

	width = ALIGN(image->width, 8);
	dsize = ALIGN(width * image->height, 32) >> 5;

	if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
	    info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
		fg = ((uint32_t *) info->pseudo_palette)[image->fg_color];
		bg = ((uint32_t *) info->pseudo_palette)[image->bg_color];
	} else {
		fg = image->fg_color;
		bg = image->bg_color;
	}

	BEGIN_RING(chan, NvSubGdiRect, 0x0be4, 7);
	OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
	OUT_RING(chan, ((image->dy + image->height) << 16) |
			 ((image->dx + image->width) & 0xffff));
	OUT_RING(chan, bg);
	OUT_RING(chan, fg);
	OUT_RING(chan, (image->height << 16) | width);
	OUT_RING(chan, (image->height << 16) | image->width);
	OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));

	while (dsize) {
		int iter_len = dsize > 128 ? 128 : dsize;

		ret = RING_SPACE(chan, iter_len + 1);
		if (ret)
			return ret;

		BEGIN_RING(chan, NvSubGdiRect, 0x0c00, iter_len);
		OUT_RINGp(chan, data, iter_len);
		data += iter_len;
		dsize -= iter_len;
	}

	FIRE_RING(chan);
	return 0;
}

int
nv04_fbcon_accel_init(struct fb_info *info)
{
	struct nouveau_fbdev *nfbdev = info->par;
	struct drm_device *dev = nfbdev->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_channel *chan = dev_priv->channel;
	const int sub = NvSubCtxSurf2D;
	int surface_fmt, pattern_fmt, rect_fmt;
	int ret;

	switch (info->var.bits_per_pixel) {
	case 8:
		surface_fmt = 1;
		pattern_fmt = 3;
		rect_fmt = 3;
		break;
	case 16:
		surface_fmt = 4;
		pattern_fmt = 1;
		rect_fmt = 1;
		break;
	case 32:
		switch (info->var.transp.length) {
		case 0: /* depth 24 */
		case 8: /* depth 32 */
			break;
		default:
			return -EINVAL;
		}

		surface_fmt = 6;
		pattern_fmt = 3;
		rect_fmt = 3;
		break;
	default:
		return -EINVAL;
	}

	ret = nouveau_gpuobj_gr_new(chan, NvCtxSurf2D,
				    dev_priv->card_type >= NV_10 ?
				    0x0062 : 0x0042);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_gr_new(chan, NvClipRect, 0x0019);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_gr_new(chan, NvRop, 0x0043);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_gr_new(chan, NvImagePatt, 0x0044);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_gr_new(chan, NvGdiRect, 0x004a);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_gr_new(chan, NvImageBlit,
				    dev_priv->chipset >= 0x11 ?
				    0x009f : 0x005f);
	if (ret)
		return ret;

	if (RING_SPACE(chan, 49)) {
		nouveau_fbcon_gpu_lockup(info);
		return 0;
	}

	BEGIN_RING(chan, sub, 0x0000, 1);
	OUT_RING(chan, NvCtxSurf2D);
	BEGIN_RING(chan, sub, 0x0184, 2);
	OUT_RING(chan, NvDmaFB);
	OUT_RING(chan, NvDmaFB);
	BEGIN_RING(chan, sub, 0x0300, 4);
	OUT_RING(chan, surface_fmt);
	OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16));
	OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
	OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);

	BEGIN_RING(chan, sub, 0x0000, 1);
	OUT_RING(chan, NvRop);
	BEGIN_RING(chan, sub, 0x0300, 1);
	OUT_RING(chan, 0x55);

	BEGIN_RING(chan, sub, 0x0000, 1);
	OUT_RING(chan, NvImagePatt);
	BEGIN_RING(chan, sub, 0x0300, 8);
	OUT_RING(chan, pattern_fmt);
#ifdef __BIG_ENDIAN
	OUT_RING(chan, 2);
#else
	OUT_RING(chan, 1);
#endif
	OUT_RING(chan, 0);
	OUT_RING(chan, 1);
	OUT_RING(chan, ~0);
	OUT_RING(chan, ~0);
	OUT_RING(chan, ~0);
	OUT_RING(chan, ~0);

	BEGIN_RING(chan, sub, 0x0000, 1);
	OUT_RING(chan, NvClipRect);
	BEGIN_RING(chan, sub, 0x0300, 2);
	OUT_RING(chan, 0);
	OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual);

	BEGIN_RING(chan, NvSubImageBlit, 0x0000, 1);
	OUT_RING(chan, NvImageBlit);
	BEGIN_RING(chan, NvSubImageBlit, 0x019c, 1);
	OUT_RING(chan, NvCtxSurf2D);
	BEGIN_RING(chan, NvSubImageBlit, 0x02fc, 1);
	OUT_RING(chan, 3);

	BEGIN_RING(chan, NvSubGdiRect, 0x0000, 1);
	OUT_RING(chan, NvGdiRect);
	BEGIN_RING(chan, NvSubGdiRect, 0x0198, 1);
	OUT_RING(chan, NvCtxSurf2D);
	BEGIN_RING(chan, NvSubGdiRect, 0x0188, 2);
	OUT_RING(chan, NvImagePatt);
	OUT_RING(chan, NvRop);
	BEGIN_RING(chan, NvSubGdiRect, 0x0304, 1);
	OUT_RING(chan, 1);
	BEGIN_RING(chan, NvSubGdiRect, 0x0300, 1);
	OUT_RING(chan, rect_fmt);
	BEGIN_RING(chan, NvSubGdiRect, 0x02fc, 1);
	OUT_RING(chan, 3);

	FIRE_RING(chan);

	return 0;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2009 Ben Skeggs
	3	* Copyright 2008 Stuart Bennett
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*/
	24
	25	#include "drmP.h"
	26	#include "nouveau_drv.h"
	27	#include "nouveau_dma.h"
a8eaebc6	28	#include "nouveau_ramht.h"
6ee73861 BS	29	#include "nouveau_fbcon.h"
6ee73861 BS	30
ceed5f30	31	int
6ee73861 BS	32	nv04_fbcon_copyarea(struct fb_info info, const struct fb_copyarea region)
6ee73861 BS	33	{
8be48d92 DA	34	struct nouveau_fbdev *nfbdev = info->par;
8be48d92 DA	35	struct drm_device *dev = nfbdev->dev;
6ee73861 BS	36	struct drm_nouveau_private *dev_priv = dev->dev_private;
6ee73861 BS	37	struct nouveau_channel *chan = dev_priv->channel;
ceed5f30	38	int ret;
6ee73861	39
ceed5f30 BS	40	ret = RING_SPACE(chan, 4);
	41	if (ret)
	42	return ret;
6ee73861 BS	43
	44	BEGIN_RING(chan, NvSubImageBlit, 0x0300, 3);
	45	OUT_RING(chan, (region->sy << 16) \| region->sx);
	46	OUT_RING(chan, (region->dy << 16) \| region->dx);
	47	OUT_RING(chan, (region->height << 16) \| region->width);
	48	FIRE_RING(chan);
ceed5f30	49	return 0;
6ee73861 BS	50	}
6ee73861 BS	51
ceed5f30	52	int
6ee73861 BS	53	nv04_fbcon_fillrect(struct fb_info info, const struct fb_fillrect rect)
6ee73861 BS	54	{
8be48d92 DA	55	struct nouveau_fbdev *nfbdev = info->par;
8be48d92 DA	56	struct drm_device *dev = nfbdev->dev;
6ee73861 BS	57	struct drm_nouveau_private *dev_priv = dev->dev_private;
6ee73861 BS	58	struct nouveau_channel *chan = dev_priv->channel;
ceed5f30	59	int ret;
6ee73861	60
ceed5f30 BS	61	ret = RING_SPACE(chan, 7);
	62	if (ret)
	63	return ret;
6ee73861 BS	64
	65	BEGIN_RING(chan, NvSubGdiRect, 0x02fc, 1);
	66	OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3);
	67	BEGIN_RING(chan, NvSubGdiRect, 0x03fc, 1);
bf5302b9 BS	68	if (info->fix.visual == FB_VISUAL_TRUECOLOR \|\|
	69	info->fix.visual == FB_VISUAL_DIRECTCOLOR)
	70	OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
	71	else
	72	OUT_RING(chan, rect->color);
6ee73861 BS	73	BEGIN_RING(chan, NvSubGdiRect, 0x0400, 2);
	74	OUT_RING(chan, (rect->dx << 16) \| rect->dy);
	75	OUT_RING(chan, (rect->width << 16) \| rect->height);
	76	FIRE_RING(chan);
ceed5f30	77	return 0;
6ee73861 BS	78	}
6ee73861 BS	79
ceed5f30	80	int
6ee73861 BS	81	nv04_fbcon_imageblit(struct fb_info info, const struct fb_image image)
6ee73861 BS	82	{
8be48d92 DA	83	struct nouveau_fbdev *nfbdev = info->par;
8be48d92 DA	84	struct drm_device *dev = nfbdev->dev;
6ee73861 BS	85	struct drm_nouveau_private *dev_priv = dev->dev_private;
	86	struct nouveau_channel *chan = dev_priv->channel;
	87	uint32_t fg;
	88	uint32_t bg;
	89	uint32_t dsize;
	90	uint32_t width;
	91	uint32_t data = (uint32_t )image->data;
ceed5f30	92	int ret;
6ee73861	93
ceed5f30 BS	94	if (image->depth != 1)
ceed5f30 BS	95	return -ENODEV;
6ee73861	96
ceed5f30 BS	97	ret = RING_SPACE(chan, 8);
	98	if (ret)
	99	return ret;
6ee73861	100
c82b88d5 MK	101	width = ALIGN(image->width, 8);
c82b88d5 MK	102	dsize = ALIGN(width * image->height, 32) >> 5;
6ee73861 BS	103
	104	if (info->fix.visual == FB_VISUAL_TRUECOLOR \|\|
	105	info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
	106	fg = ((uint32_t *) info->pseudo_palette)[image->fg_color];
	107	bg = ((uint32_t *) info->pseudo_palette)[image->bg_color];
	108	} else {
	109	fg = image->fg_color;
	110	bg = image->bg_color;
	111	}
	112
	113	BEGIN_RING(chan, NvSubGdiRect, 0x0be4, 7);
	114	OUT_RING(chan, (image->dy << 16) \| (image->dx & 0xffff));
	115	OUT_RING(chan, ((image->dy + image->height) << 16) \|
	116	((image->dx + image->width) & 0xffff));
	117	OUT_RING(chan, bg);
	118	OUT_RING(chan, fg);
6ee73861	119	OUT_RING(chan, (image->height << 16) \| width);
c82b88d5	120	OUT_RING(chan, (image->height << 16) \| image->width);
6ee73861 BS	121	OUT_RING(chan, (image->dy << 16) \| (image->dx & 0xffff));
	122
	123	while (dsize) {
	124	int iter_len = dsize > 128 ? 128 : dsize;
	125
ceed5f30 BS	126	ret = RING_SPACE(chan, iter_len + 1);
	127	if (ret)
	128	return ret;
6ee73861 BS	129
	130	BEGIN_RING(chan, NvSubGdiRect, 0x0c00, iter_len);
	131	OUT_RINGp(chan, data, iter_len);
	132	data += iter_len;
	133	dsize -= iter_len;
	134	}
	135
	136	FIRE_RING(chan);
ceed5f30	137	return 0;
6ee73861 BS	138	}
6ee73861 BS	139
6ee73861 BS	140	int
	141	nv04_fbcon_accel_init(struct fb_info *info)
	142	{
8be48d92 DA	143	struct nouveau_fbdev *nfbdev = info->par;
8be48d92 DA	144	struct drm_device *dev = nfbdev->dev;
6ee73861 BS	145	struct drm_nouveau_private *dev_priv = dev->dev_private;
6ee73861 BS	146	struct nouveau_channel *chan = dev_priv->channel;
f03a314b	147	const int sub = NvSubCtxSurf2D;
6ee73861 BS	148	int surface_fmt, pattern_fmt, rect_fmt;
	149	int ret;
	150
	151	switch (info->var.bits_per_pixel) {
	152	case 8:
	153	surface_fmt = 1;
	154	pattern_fmt = 3;
	155	rect_fmt = 3;
	156	break;
	157	case 16:
	158	surface_fmt = 4;
	159	pattern_fmt = 1;
	160	rect_fmt = 1;
	161	break;
	162	case 32:
	163	switch (info->var.transp.length) {
	164	case 0: /* depth 24 */
	165	case 8: /* depth 32 */
	166	break;
	167	default:
	168	return -EINVAL;
	169	}
	170
	171	surface_fmt = 6;
	172	pattern_fmt = 3;
	173	rect_fmt = 3;
	174	break;
	175	default:
	176	return -EINVAL;
	177	}
	178
ceac3099 BS	179	ret = nouveau_gpuobj_gr_new(chan, NvCtxSurf2D,
	180	dev_priv->card_type >= NV_10 ?
	181	0x0062 : 0x0042);
6ee73861 BS	182	if (ret)
	183	return ret;
	184
ceac3099	185	ret = nouveau_gpuobj_gr_new(chan, NvClipRect, 0x0019);
6ee73861 BS	186	if (ret)
	187	return ret;
	188
ceac3099	189	ret = nouveau_gpuobj_gr_new(chan, NvRop, 0x0043);
6ee73861 BS	190	if (ret)
	191	return ret;
	192
ceac3099	193	ret = nouveau_gpuobj_gr_new(chan, NvImagePatt, 0x0044);
6ee73861 BS	194	if (ret)
	195	return ret;
	196
ceac3099	197	ret = nouveau_gpuobj_gr_new(chan, NvGdiRect, 0x004a);
6ee73861 BS	198	if (ret)
	199	return ret;
	200
ceac3099 BS	201	ret = nouveau_gpuobj_gr_new(chan, NvImageBlit,
	202	dev_priv->chipset >= 0x11 ?
	203	0x009f : 0x005f);
6ee73861 BS	204	if (ret)
	205	return ret;
	206
	207	if (RING_SPACE(chan, 49)) {
846975a9	208	nouveau_fbcon_gpu_lockup(info);
6ee73861 BS	209	return 0;
	210	}
	211
f03a314b	212	BEGIN_RING(chan, sub, 0x0000, 1);
6ee73861	213	OUT_RING(chan, NvCtxSurf2D);
f03a314b	214	BEGIN_RING(chan, sub, 0x0184, 2);
6ee73861 BS	215	OUT_RING(chan, NvDmaFB);
6ee73861 BS	216	OUT_RING(chan, NvDmaFB);
f03a314b	217	BEGIN_RING(chan, sub, 0x0300, 4);
6ee73861 BS	218	OUT_RING(chan, surface_fmt);
	219	OUT_RING(chan, info->fix.line_length \| (info->fix.line_length << 16));
	220	OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
	221	OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
	222
f03a314b	223	BEGIN_RING(chan, sub, 0x0000, 1);
6ee73861	224	OUT_RING(chan, NvRop);
f03a314b	225	BEGIN_RING(chan, sub, 0x0300, 1);
6ee73861 BS	226	OUT_RING(chan, 0x55);
6ee73861 BS	227
f03a314b	228	BEGIN_RING(chan, sub, 0x0000, 1);
6ee73861	229	OUT_RING(chan, NvImagePatt);
f03a314b	230	BEGIN_RING(chan, sub, 0x0300, 8);
6ee73861 BS	231	OUT_RING(chan, pattern_fmt);
	232	#ifdef __BIG_ENDIAN
	233	OUT_RING(chan, 2);
	234	#else
	235	OUT_RING(chan, 1);
	236	#endif
	237	OUT_RING(chan, 0);
	238	OUT_RING(chan, 1);
	239	OUT_RING(chan, ~0);
	240	OUT_RING(chan, ~0);
	241	OUT_RING(chan, ~0);
	242	OUT_RING(chan, ~0);
	243
f03a314b	244	BEGIN_RING(chan, sub, 0x0000, 1);
6ee73861	245	OUT_RING(chan, NvClipRect);
f03a314b	246	BEGIN_RING(chan, sub, 0x0300, 2);
6ee73861 BS	247	OUT_RING(chan, 0);
	248	OUT_RING(chan, (info->var.yres_virtual << 16) \| info->var.xres_virtual);
	249
	250	BEGIN_RING(chan, NvSubImageBlit, 0x0000, 1);
	251	OUT_RING(chan, NvImageBlit);
	252	BEGIN_RING(chan, NvSubImageBlit, 0x019c, 1);
	253	OUT_RING(chan, NvCtxSurf2D);
	254	BEGIN_RING(chan, NvSubImageBlit, 0x02fc, 1);
	255	OUT_RING(chan, 3);
	256
	257	BEGIN_RING(chan, NvSubGdiRect, 0x0000, 1);
	258	OUT_RING(chan, NvGdiRect);
	259	BEGIN_RING(chan, NvSubGdiRect, 0x0198, 1);
	260	OUT_RING(chan, NvCtxSurf2D);
	261	BEGIN_RING(chan, NvSubGdiRect, 0x0188, 2);
	262	OUT_RING(chan, NvImagePatt);
	263	OUT_RING(chan, NvRop);
	264	BEGIN_RING(chan, NvSubGdiRect, 0x0304, 1);
	265	OUT_RING(chan, 1);
	266	BEGIN_RING(chan, NvSubGdiRect, 0x0300, 1);
	267	OUT_RING(chan, rect_fmt);
	268	BEGIN_RING(chan, NvSubGdiRect, 0x02fc, 1);
	269	OUT_RING(chan, 3);
	270
	271	FIRE_RING(chan);
	272
6ee73861 BS	273	return 0;
	274	}
	275