[deliverable/linux.git] / drivers / gpu / drm / nouveau / nv10_fifo.c

/*
 * Copyright (C) 2007 Ben Skeggs.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_ramht.h"

#define NV10_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV10_RAMFC__SIZE))
#define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32)

int
nv10_fifo_create_context(struct nouveau_channel *chan)
{
	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
	struct drm_device *dev = chan->dev;
	uint32_t fc = NV10_RAMFC(chan->id);
	int ret;

	ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id), ~0,
				      NV10_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC |
				      NVOBJ_FLAG_ZERO_FREE, &chan->ramfc);
	if (ret)
		return ret;

	chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
			     NV03_USER(chan->id), PAGE_SIZE);
	if (!chan->user)
		return -ENOMEM;

	/* Fill entries that are seen filled in dumps of nvidia driver just
	 * after channel's is put into DMA mode
	 */
	nv_wi32(dev, fc +  0, chan->pushbuf_base);
	nv_wi32(dev, fc +  4, chan->pushbuf_base);
	nv_wi32(dev, fc + 12, chan->pushbuf->pinst >> 4);
	nv_wi32(dev, fc + 20, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
			      NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
			      NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
#ifdef __BIG_ENDIAN
			      NV_PFIFO_CACHE1_BIG_ENDIAN |
#endif
			      0);

	/* enable the fifo dma operation */
	nv_wr32(dev, NV04_PFIFO_MODE,
		nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id));
	return 0;
}

static void
nv10_fifo_do_load_context(struct drm_device *dev, int chid)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t fc = NV10_RAMFC(chid), tmp;

	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
	nv_wr32(dev, NV10_PFIFO_CACHE1_REF_CNT, nv_ri32(dev, fc + 8));

	tmp = nv_ri32(dev, fc + 12);
	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);

	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 16));
	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, nv_ri32(dev, fc + 20));
	nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 24));
	nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 28));

	if (dev_priv->chipset < 0x17)
		goto out;

	nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE, nv_ri32(dev, fc + 32));
	tmp = nv_ri32(dev, fc + 36);
	nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, tmp);
	nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT, nv_ri32(dev, fc + 40));
	nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, nv_ri32(dev, fc + 44));
	nv_wr32(dev, NV10_PFIFO_CACHE1_DMA_SUBROUTINE, nv_ri32(dev, fc + 48));

out:
	nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
	nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
}

int
nv10_fifo_load_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	uint32_t tmp;

	nv10_fifo_do_load_context(dev, chan->id);

	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
		     NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);

	/* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
	tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);

	return 0;
}

int
nv10_fifo_unload_context(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	uint32_t fc, tmp;
	int chid;

	chid = nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & 0x1f;
	if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
		return 0;
	fc = NV10_RAMFC(chid);

	nv_wi32(dev, fc +  0, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
	nv_wi32(dev, fc +  4, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
	nv_wi32(dev, fc +  8, nv_rd32(dev, NV10_PFIFO_CACHE1_REF_CNT));
	tmp  = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE) & 0xFFFF;
	tmp |= (nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16);
	nv_wi32(dev, fc + 12, tmp);
	nv_wi32(dev, fc + 16, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
	nv_wi32(dev, fc + 20, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH));
	nv_wi32(dev, fc + 24, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
	nv_wi32(dev, fc + 28, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));

	if (dev_priv->chipset < 0x17)
		goto out;

	nv_wi32(dev, fc + 32, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
	tmp = nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP);
	nv_wi32(dev, fc + 36, tmp);
	nv_wi32(dev, fc + 40, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
	nv_wi32(dev, fc + 44, nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE));
	nv_wi32(dev, fc + 48, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));

out:
	nv10_fifo_do_load_context(dev, pfifo->channels - 1);
	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
	return 0;
}

static void
nv10_fifo_init_reset(struct drm_device *dev)
{
	nv_wr32(dev, NV03_PMC_ENABLE,
		nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
	nv_wr32(dev, NV03_PMC_ENABLE,
		nv_rd32(dev, NV03_PMC_ENABLE) |  NV_PMC_ENABLE_PFIFO);

	nv_wr32(dev, 0x003224, 0x000f0078);
	nv_wr32(dev, 0x002044, 0x0101ffff);
	nv_wr32(dev, 0x002040, 0x000000ff);
	nv_wr32(dev, 0x002500, 0x00000000);
	nv_wr32(dev, 0x003000, 0x00000000);
	nv_wr32(dev, 0x003050, 0x00000000);

	nv_wr32(dev, 0x003258, 0x00000000);
	nv_wr32(dev, 0x003210, 0x00000000);
	nv_wr32(dev, 0x003270, 0x00000000);
}

static void
nv10_fifo_init_ramxx(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
				       ((dev_priv->ramht->bits - 9) << 16) |
				       (dev_priv->ramht->gpuobj->pinst >> 8));
	nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8);

	if (dev_priv->chipset < 0x17) {
		nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc->pinst >> 8);
	} else {
		nv_wr32(dev, NV03_PFIFO_RAMFC, (dev_priv->ramfc->pinst >> 8) |
					       (1 << 16) /* 64 Bytes entry*/);
		/* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */
	}
}

static void
nv10_fifo_init_intr(struct drm_device *dev)
{
	nouveau_irq_register(dev, 8, nv04_fifo_isr);
	nv_wr32(dev, 0x002100, 0xffffffff);
	nv_wr32(dev, 0x002140, 0xffffffff);
}

int
nv10_fifo_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	int i;

	nv10_fifo_init_reset(dev);
	nv10_fifo_init_ramxx(dev);

	nv10_fifo_do_load_context(dev, pfifo->channels - 1);
	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);

	nv10_fifo_init_intr(dev);
	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
	nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
	nv_wr32(dev, NV03_PFIFO_CACHES, 1);

	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
		if (dev_priv->channels.ptr[i]) {
			uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
			nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i));
		}
	}

	return 0;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) 2007 Ben Skeggs.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining
	6	* a copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sublicense, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial
	15	* portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	18	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	20	* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	21	* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	22	* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	23	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*
	25	*/
	26
	27	#include "drmP.h"
	28	#include "drm.h"
	29	#include "nouveau_drv.h"
e05c5a31	30	#include "nouveau_ramht.h"
6ee73861	31
e05c5a31	32	#define NV10_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV10_RAMFC__SIZE))
6ee73861 BS	33	#define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32)
6ee73861 BS	34
6ee73861 BS	35	int
	36	nv10_fifo_create_context(struct nouveau_channel *chan)
	37	{
	38	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
	39	struct drm_device *dev = chan->dev;
	40	uint32_t fc = NV10_RAMFC(chan->id);
	41	int ret;
	42
	43	ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id), ~0,
	44	NV10_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC \|
a8eaebc6	45	NVOBJ_FLAG_ZERO_FREE, &chan->ramfc);
6ee73861 BS	46	if (ret)
	47	return ret;
	48
d908175c BS	49	chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
	50	NV03_USER(chan->id), PAGE_SIZE);
	51	if (!chan->user)
	52	return -ENOMEM;
	53
6ee73861 BS	54	/* Fill entries that are seen filled in dumps of nvidia driver just
	55	* after channel's is put into DMA mode
	56	*/
6ee73861 BS	57	nv_wi32(dev, fc + 0, chan->pushbuf_base);
6ee73861 BS	58	nv_wi32(dev, fc + 4, chan->pushbuf_base);
a8eaebc6	59	nv_wi32(dev, fc + 12, chan->pushbuf->pinst >> 4);
6ee73861 BS	60	nv_wi32(dev, fc + 20, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES \|
	61	NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES \|
	62	NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 \|
	63	#ifdef __BIG_ENDIAN
	64	NV_PFIFO_CACHE1_BIG_ENDIAN \|
	65	#endif
	66	0);
6ee73861 BS	67
	68	/* enable the fifo dma operation */
	69	nv_wr32(dev, NV04_PFIFO_MODE,
	70	nv_rd32(dev, NV04_PFIFO_MODE) \| (1 << chan->id));
	71	return 0;
	72	}
	73
6ee73861 BS	74	static void
	75	nv10_fifo_do_load_context(struct drm_device *dev, int chid)
	76	{
	77	struct drm_nouveau_private *dev_priv = dev->dev_private;
	78	uint32_t fc = NV10_RAMFC(chid), tmp;
	79
6ee73861 BS	80	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
	81	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
	82	nv_wr32(dev, NV10_PFIFO_CACHE1_REF_CNT, nv_ri32(dev, fc + 8));
	83
	84	tmp = nv_ri32(dev, fc + 12);
	85	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
	86	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
	87
	88	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 16));
	89	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, nv_ri32(dev, fc + 20));
	90	nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 24));
	91	nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 28));
	92
	93	if (dev_priv->chipset < 0x17)
	94	goto out;
	95
	96	nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE, nv_ri32(dev, fc + 32));
	97	tmp = nv_ri32(dev, fc + 36);
	98	nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, tmp);
	99	nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT, nv_ri32(dev, fc + 40));
	100	nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, nv_ri32(dev, fc + 44));
	101	nv_wr32(dev, NV10_PFIFO_CACHE1_DMA_SUBROUTINE, nv_ri32(dev, fc + 48));
	102
	103	out:
6ee73861 BS	104	nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
	105	nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
	106	}
	107
	108	int
	109	nv10_fifo_load_context(struct nouveau_channel *chan)
	110	{
	111	struct drm_device *dev = chan->dev;
	112	uint32_t tmp;
	113
	114	nv10_fifo_do_load_context(dev, chan->id);
	115
	116	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
	117	NV03_PFIFO_CACHE1_PUSH1_DMA \| chan->id);
	118	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);
	119
	120	/* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
	121	tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
	122	nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
	123
	124	return 0;
	125	}
	126
	127	int
	128	nv10_fifo_unload_context(struct drm_device *dev)
	129	{
	130	struct drm_nouveau_private *dev_priv = dev->dev_private;
	131	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	132	uint32_t fc, tmp;
	133	int chid;
	134
67b342ef	135	chid = nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & 0x1f;
6ee73861 BS	136	if (chid < 0 \|\| chid >= dev_priv->engine.fifo.channels)
	137	return 0;
	138	fc = NV10_RAMFC(chid);
	139
6ee73861 BS	140	nv_wi32(dev, fc + 0, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
	141	nv_wi32(dev, fc + 4, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
	142	nv_wi32(dev, fc + 8, nv_rd32(dev, NV10_PFIFO_CACHE1_REF_CNT));
	143	tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE) & 0xFFFF;
	144	tmp \|= (nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16);
	145	nv_wi32(dev, fc + 12, tmp);
	146	nv_wi32(dev, fc + 16, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
	147	nv_wi32(dev, fc + 20, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH));
	148	nv_wi32(dev, fc + 24, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
	149	nv_wi32(dev, fc + 28, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
	150
	151	if (dev_priv->chipset < 0x17)
	152	goto out;
	153
	154	nv_wi32(dev, fc + 32, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
	155	tmp = nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP);
	156	nv_wi32(dev, fc + 36, tmp);
	157	nv_wi32(dev, fc + 40, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
	158	nv_wi32(dev, fc + 44, nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE));
	159	nv_wi32(dev, fc + 48, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
	160
	161	out:
6ee73861 BS	162	nv10_fifo_do_load_context(dev, pfifo->channels - 1);
	163	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
	164	return 0;
	165	}
	166
	167	static void
	168	nv10_fifo_init_reset(struct drm_device *dev)
	169	{
	170	nv_wr32(dev, NV03_PMC_ENABLE,
	171	nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
	172	nv_wr32(dev, NV03_PMC_ENABLE,
	173	nv_rd32(dev, NV03_PMC_ENABLE) \| NV_PMC_ENABLE_PFIFO);
	174
	175	nv_wr32(dev, 0x003224, 0x000f0078);
	176	nv_wr32(dev, 0x002044, 0x0101ffff);
	177	nv_wr32(dev, 0x002040, 0x000000ff);
	178	nv_wr32(dev, 0x002500, 0x00000000);
	179	nv_wr32(dev, 0x003000, 0x00000000);
	180	nv_wr32(dev, 0x003050, 0x00000000);
	181
	182	nv_wr32(dev, 0x003258, 0x00000000);
	183	nv_wr32(dev, 0x003210, 0x00000000);
	184	nv_wr32(dev, 0x003270, 0x00000000);
	185	}
	186
	187	static void
	188	nv10_fifo_init_ramxx(struct drm_device *dev)
	189	{
	190	struct drm_nouveau_private *dev_priv = dev->dev_private;
	191
	192	nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ \|
e05c5a31 BS	193	((dev_priv->ramht->bits - 9) << 16) \|
	194	(dev_priv->ramht->gpuobj->pinst >> 8));
	195	nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8);
6ee73861 BS	196
6ee73861 BS	197	if (dev_priv->chipset < 0x17) {
e05c5a31	198	nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc->pinst >> 8);
6ee73861	199	} else {
e05c5a31	200	nv_wr32(dev, NV03_PFIFO_RAMFC, (dev_priv->ramfc->pinst >> 8) \|
6ee73861 BS	201	(1 << 16) /* 64 Bytes entry*/);
	202	/* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */
	203	}
	204	}
	205
	206	static void
	207	nv10_fifo_init_intr(struct drm_device *dev)
	208	{
5178d40d	209	nouveau_irq_register(dev, 8, nv04_fifo_isr);
6ee73861 BS	210	nv_wr32(dev, 0x002100, 0xffffffff);
	211	nv_wr32(dev, 0x002140, 0xffffffff);
	212	}
	213
	214	int
	215	nv10_fifo_init(struct drm_device *dev)
	216	{
	217	struct drm_nouveau_private *dev_priv = dev->dev_private;
	218	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	219	int i;
	220
	221	nv10_fifo_init_reset(dev);
	222	nv10_fifo_init_ramxx(dev);
	223
	224	nv10_fifo_do_load_context(dev, pfifo->channels - 1);
	225	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
	226
	227	nv10_fifo_init_intr(dev);
67b342ef BS	228	nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
	229	nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
	230	nv_wr32(dev, NV03_PFIFO_CACHES, 1);
6ee73861 BS	231
6ee73861 BS	232	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
cff5c133	233	if (dev_priv->channels.ptr[i]) {
6ee73861 BS	234	uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
	235	nv_wr32(dev, NV04_PFIFO_MODE, mode \| (1 << i));
	236	}
	237	}
	238
	239	return 0;
	240	}