[deliverable/linux.git] / drivers / gpu / drm / nouveau / nv40_graph.c

/*
 * Copyright (C) 2007 Ben Skeggs.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_grctx.h"
#include "nouveau_ramht.h"

struct nv40_graph_engine {
	struct nouveau_exec_engine base;
	u32 grctx_size;
};

static struct nouveau_channel *
nv40_graph_channel(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *grctx;
	uint32_t inst;
	int i;

	inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
	if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
		return NULL;
	inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;

	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
		if (!dev_priv->channels.ptr[i])
			continue;

		grctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_GR];
		if (grctx && grctx->pinst == inst)
			return dev_priv->channels.ptr[i];
	}

	return NULL;
}

static int
nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
{
	uint32_t old_cp, tv = 1000, tmp;
	int i;

	old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER);
	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);

	tmp  = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310);
	tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
		      NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp);

	tmp  = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304);
	tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp);

	nouveau_wait_for_idle(dev);

	for (i = 0; i < tv; i++) {
		if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0)
			break;
	}

	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);

	if (i == tv) {
		uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT);
		NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save);
		NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n",
			 ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
			 ucstat  & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
		NV_ERROR(dev, "0x40030C = 0x%08x\n",
			 nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C));
		return -EBUSY;
	}

	return 0;
}

static int
nv40_graph_unload_context(struct drm_device *dev)
{
	uint32_t inst;
	int ret;

	inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
	if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
		return 0;
	inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE;

	ret = nv40_graph_transfer_context(dev, inst, 1);

	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst);
	return ret;
}

static int
nv40_graph_context_new(struct nouveau_channel *chan, int engine)
{
	struct nv40_graph_engine *pgraph = nv_engine(chan->dev, engine);
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *grctx = NULL;
	struct nouveau_grctx ctx = {};
	unsigned long flags;
	int ret;

	ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 16,
				 NVOBJ_FLAG_ZERO_ALLOC, &grctx);
	if (ret)
		return ret;

	/* Initialise default context values */
	ctx.dev = chan->dev;
	ctx.mode = NOUVEAU_GRCTX_VALS;
	ctx.data = grctx;
	nv40_grctx_init(&ctx);

	nv_wo32(grctx, 0, grctx->vinst);

	/* init grctx pointer in ramfc, and on PFIFO if channel is
	 * already active there
	 */
	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	nv_wo32(chan->ramfc, 0x38, grctx->vinst >> 4);
	nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
	if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
		nv_wr32(dev, 0x0032e0, grctx->vinst >> 4);
	nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);

	chan->engctx[engine] = grctx;
	return 0;
}

static void
nv40_graph_context_del(struct nouveau_channel *chan, int engine)
{
	struct nouveau_gpuobj *grctx = chan->engctx[engine];
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	unsigned long flags;

	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	nv04_graph_fifo_access(dev, false);

	/* Unload the context if it's the currently active one */
	if (nv40_graph_channel(dev) == chan)
		nv40_graph_unload_context(dev);

	nv04_graph_fifo_access(dev, true);
	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);

	/* Free the context resources */
	nouveau_gpuobj_ref(NULL, &grctx);
	chan->engctx[engine] = NULL;
}

int
nv40_graph_object_new(struct nouveau_channel *chan, int engine,
		      u32 handle, u16 class)
{
	struct drm_device *dev = chan->dev;
	struct nouveau_gpuobj *obj = NULL;
	int ret;

	ret = nouveau_gpuobj_new(dev, chan, 20, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
	if (ret)
		return ret;
	obj->engine = 1;
	obj->class  = class;

	nv_wo32(obj, 0x00, class);
	nv_wo32(obj, 0x04, 0x00000000);
#ifndef __BIG_ENDIAN
	nv_wo32(obj, 0x08, 0x00000000);
#else
	nv_wo32(obj, 0x08, 0x01000000);
#endif
	nv_wo32(obj, 0x0c, 0x00000000);
	nv_wo32(obj, 0x10, 0x00000000);

	ret = nouveau_ramht_insert(chan, handle, obj);
	nouveau_gpuobj_ref(NULL, &obj);
	return ret;
}

static void
nv40_graph_set_tile_region(struct drm_device *dev, int i)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];

	switch (dev_priv->chipset) {
	case 0x40:
	case 0x41: /* guess */
	case 0x42:
	case 0x43:
	case 0x45: /* guess */
	case 0x4e:
		nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
		nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
		nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
		nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
		nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
		nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
		break;
	case 0x44:
	case 0x4a:
		nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
		nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
		nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
		break;
	case 0x46:
	case 0x47:
	case 0x49:
	case 0x4b:
	case 0x4c:
	case 0x67:
	default:
		nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch);
		nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit);
		nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr);
		nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
		nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
		nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
		break;
	}
}

/*
 * G70		0x47
 * G71		0x49
 * NV45		0x48
 * G72[M]	0x46
 * G73		0x4b
 * C51_G7X	0x4c
 * C51		0x4e
 */
int
nv40_graph_init(struct drm_device *dev, int engine)
{
	struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	struct nouveau_grctx ctx = {};
	uint32_t vramsz, *cp;
	int i, j;

	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
			~NV_PMC_ENABLE_PGRAPH);
	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
			 NV_PMC_ENABLE_PGRAPH);

	cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
	if (!cp)
		return -ENOMEM;

	ctx.dev = dev;
	ctx.mode = NOUVEAU_GRCTX_PROG;
	ctx.data = cp;
	ctx.ctxprog_max = 256;
	nv40_grctx_init(&ctx);
	pgraph->grctx_size = ctx.ctxvals_pos * 4;

	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
	for (i = 0; i < ctx.ctxprog_len; i++)
		nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);

	kfree(cp);

	/* No context present currently */
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);

	nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
	nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);

	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
	nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
	nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
	nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
	nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);

	nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
	nv_wr32(dev, NV10_PGRAPH_STATE      , 0xFFFFFFFF);

	j = nv_rd32(dev, 0x1540) & 0xff;
	if (j) {
		for (i = 0; !(j & 1); j >>= 1, i++)
			;
		nv_wr32(dev, 0x405000, i);
	}

	if (dev_priv->chipset == 0x40) {
		nv_wr32(dev, 0x4009b0, 0x83280fff);
		nv_wr32(dev, 0x4009b4, 0x000000a0);
	} else {
		nv_wr32(dev, 0x400820, 0x83280eff);
		nv_wr32(dev, 0x400824, 0x000000a0);
	}

	switch (dev_priv->chipset) {
	case 0x40:
	case 0x45:
		nv_wr32(dev, 0x4009b8, 0x0078e366);
		nv_wr32(dev, 0x4009bc, 0x0000014c);
		break;
	case 0x41:
	case 0x42: /* pciid also 0x00Cx */
	/* case 0x0120: XXX (pciid) */
		nv_wr32(dev, 0x400828, 0x007596ff);
		nv_wr32(dev, 0x40082c, 0x00000108);
		break;
	case 0x43:
		nv_wr32(dev, 0x400828, 0x0072cb77);
		nv_wr32(dev, 0x40082c, 0x00000108);
		break;
	case 0x44:
	case 0x46: /* G72 */
	case 0x4a:
	case 0x4c: /* G7x-based C51 */
	case 0x4e:
		nv_wr32(dev, 0x400860, 0);
		nv_wr32(dev, 0x400864, 0);
		break;
	case 0x47: /* G70 */
	case 0x49: /* G71 */
	case 0x4b: /* G73 */
		nv_wr32(dev, 0x400828, 0x07830610);
		nv_wr32(dev, 0x40082c, 0x0000016A);
		break;
	default:
		break;
	}

	nv_wr32(dev, 0x400b38, 0x2ffff800);
	nv_wr32(dev, 0x400b3c, 0x00006000);

	/* Tiling related stuff. */
	switch (dev_priv->chipset) {
	case 0x44:
	case 0x4a:
		nv_wr32(dev, 0x400bc4, 0x1003d888);
		nv_wr32(dev, 0x400bbc, 0xb7a7b500);
		break;
	case 0x46:
		nv_wr32(dev, 0x400bc4, 0x0000e024);
		nv_wr32(dev, 0x400bbc, 0xb7a7b520);
		break;
	case 0x4c:
	case 0x4e:
	case 0x67:
		nv_wr32(dev, 0x400bc4, 0x1003d888);
		nv_wr32(dev, 0x400bbc, 0xb7a7b540);
		break;
	default:
		break;
	}

	/* Turn all the tiling regions off. */
	for (i = 0; i < pfb->num_tiles; i++)
		nv40_graph_set_tile_region(dev, i);

	/* begin RAM config */
	vramsz = pci_resource_len(dev->pdev, 0) - 1;
	switch (dev_priv->chipset) {
	case 0x40:
		nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
		nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
		nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
		nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
		nv_wr32(dev, 0x400820, 0);
		nv_wr32(dev, 0x400824, 0);
		nv_wr32(dev, 0x400864, vramsz);
		nv_wr32(dev, 0x400868, vramsz);
		break;
	default:
		switch (dev_priv->chipset) {
		case 0x41:
		case 0x42:
		case 0x43:
		case 0x45:
		case 0x4e:
		case 0x44:
		case 0x4a:
			nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
			nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
			break;
		default:
			nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
			nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
			break;
		}
		nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
		nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
		nv_wr32(dev, 0x400840, 0);
		nv_wr32(dev, 0x400844, 0);
		nv_wr32(dev, 0x4008A0, vramsz);
		nv_wr32(dev, 0x4008A4, vramsz);
		break;
	}

	return 0;
}

static int
nv40_graph_fini(struct drm_device *dev, int engine)
{
	nv40_graph_unload_context(dev);
	return 0;
}

static int
nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *grctx;
	unsigned long flags;
	int i;

	spin_lock_irqsave(&dev_priv->channels.lock, flags);
	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
		if (!dev_priv->channels.ptr[i])
			continue;
		grctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_GR];

		if (grctx && grctx->pinst == inst)
			break;
	}
	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
	return i;
}

static void
nv40_graph_isr(struct drm_device *dev)
{
	u32 stat;

	while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
		u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
		u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
		u32 inst = (nv_rd32(dev, 0x40032c) & 0x000fffff) << 4;
		u32 chid = nv40_graph_isr_chid(dev, inst);
		u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
		u32 subc = (addr & 0x00070000) >> 16;
		u32 mthd = (addr & 0x00001ffc);
		u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
		u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xffff;
		u32 show = stat;

		if (stat & NV_PGRAPH_INTR_ERROR) {
			if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
				if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
					show &= ~NV_PGRAPH_INTR_ERROR;
			} else
			if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
				nv_mask(dev, 0x402000, 0, 0);
			}
		}

		nv_wr32(dev, NV03_PGRAPH_INTR, stat);
		nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);

		if (show && nouveau_ratelimit()) {
			NV_INFO(dev, "PGRAPH -");
			nouveau_bitfield_print(nv10_graph_intr, show);
			printk(" nsource:");
			nouveau_bitfield_print(nv04_graph_nsource, nsource);
			printk(" nstatus:");
			nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
			printk("\n");
			NV_INFO(dev, "PGRAPH - ch %d (0x%08x) subc %d "
				     "class 0x%04x mthd 0x%04x data 0x%08x\n",
				chid, inst, subc, class, mthd, data);
		}
	}
}

static void
nv40_graph_destroy(struct drm_device *dev, int engine)
{
	struct nv40_graph_engine *pgraph = nv_engine(dev, engine);

	nouveau_irq_unregister(dev, 12);

	NVOBJ_ENGINE_DEL(dev, GR);
	kfree(pgraph);
}

int
nv40_graph_create(struct drm_device *dev)
{
	struct nv40_graph_engine *pgraph;

	pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
	if (!pgraph)
		return -ENOMEM;

	pgraph->base.destroy = nv40_graph_destroy;
	pgraph->base.init = nv40_graph_init;
	pgraph->base.fini = nv40_graph_fini;
	pgraph->base.context_new = nv40_graph_context_new;
	pgraph->base.context_del = nv40_graph_context_del;
	pgraph->base.object_new = nv40_graph_object_new;
	pgraph->base.set_tile_region = nv40_graph_set_tile_region;

	NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
	nouveau_irq_register(dev, 12, nv40_graph_isr);

	NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
	NVOBJ_CLASS(dev, 0x0030, GR); /* null */
	NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
	NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
	NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
	NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
	NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
	NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
	NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
	NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
	NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
	NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
	NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
	NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
	NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
	NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */

	/* curie */
	if (nv44_graph_class(dev))
		NVOBJ_CLASS(dev, 0x4497, GR);
	else
		NVOBJ_CLASS(dev, 0x4097, GR);

	/* nvsw */
	NVOBJ_CLASS(dev, 0x506e, SW);
	NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
	return 0;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) 2007 Ben Skeggs.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining
	6	* a copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sublicense, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial
	15	* portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	18	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	20	* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	21	* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	22	* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	23	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*
	25	*/
	26
6ee73861 BS	27	#include "drmP.h"
	28	#include "drm.h"
	29	#include "nouveau_drv.h"
054b93e4	30	#include "nouveau_grctx.h"
4ea52f89	31	#include "nouveau_ramht.h"
6ee73861	32
39c8d368 BS	33	struct nv40_graph_engine {
	34	struct nouveau_exec_engine base;
	35	u32 grctx_size;
	36	};
b8c157d3	37
39c8d368	38	static struct nouveau_channel *
6ee73861 BS	39	nv40_graph_channel(struct drm_device *dev)
	40	{
	41	struct drm_nouveau_private *dev_priv = dev->dev_private;
39c8d368	42	struct nouveau_gpuobj *grctx;
6ee73861 BS	43	uint32_t inst;
	44	int i;
	45
	46	inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
	47	if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
	48	return NULL;
	49	inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;
	50
	51	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
39c8d368 BS	52	if (!dev_priv->channels.ptr[i])
39c8d368 BS	53	continue;
6ee73861	54
39c8d368 BS	55	grctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_GR];
	56	if (grctx && grctx->pinst == inst)
	57	return dev_priv->channels.ptr[i];
6ee73861 BS	58	}
	59
	60	return NULL;
	61	}
	62
6ee73861 BS	63	static int
	64	nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
	65	{
	66	uint32_t old_cp, tv = 1000, tmp;
	67	int i;
	68
	69	old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER);
	70	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
	71
	72	tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310);
	73	tmp \|= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
	74	NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
	75	nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp);
	76
	77	tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304);
	78	tmp \|= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
	79	nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp);
	80
	81	nouveau_wait_for_idle(dev);
	82
	83	for (i = 0; i < tv; i++) {
	84	if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0)
	85	break;
	86	}
	87
	88	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
	89
	90	if (i == tv) {
	91	uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT);
	92	NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save);
	93	NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n",
	94	ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
	95	ucstat & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
	96	NV_ERROR(dev, "0x40030C = 0x%08x\n",
	97	nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C));
	98	return -EBUSY;
	99	}
	100
	101	return 0;
	102	}
	103
39c8d368 BS	104	static int
39c8d368 BS	105	nv40_graph_unload_context(struct drm_device *dev)
6ee73861	106	{
6ee73861 BS	107	uint32_t inst;
	108	int ret;
	109
39c8d368 BS	110	inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
	111	if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
	112	return 0;
	113	inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE;
	114
	115	ret = nv40_graph_transfer_context(dev, inst, 1);
	116
	117	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst);
	118	return ret;
	119	}
6ee73861	120
39c8d368 BS	121	static int
	122	nv40_graph_context_new(struct nouveau_channel *chan, int engine)
	123	{
	124	struct nv40_graph_engine *pgraph = nv_engine(chan->dev, engine);
	125	struct drm_device *dev = chan->dev;
	126	struct drm_nouveau_private *dev_priv = dev->dev_private;
	127	struct nouveau_gpuobj *grctx = NULL;
	128	struct nouveau_grctx ctx = {};
	129	unsigned long flags;
	130	int ret;
	131
	132	ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 16,
	133	NVOBJ_FLAG_ZERO_ALLOC, &grctx);
6ee73861 BS	134	if (ret)
	135	return ret;
	136
39c8d368 BS	137	/* Initialise default context values */
	138	ctx.dev = chan->dev;
	139	ctx.mode = NOUVEAU_GRCTX_VALS;
	140	ctx.data = grctx;
	141	nv40_grctx_init(&ctx);
	142
	143	nv_wo32(grctx, 0, grctx->vinst);
	144
	145	/* init grctx pointer in ramfc, and on PFIFO if channel is
	146	* already active there
6ee73861	147	*/
39c8d368 BS	148	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	149	nv_wo32(chan->ramfc, 0x38, grctx->vinst >> 4);
	150	nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
	151	if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
	152	nv_wr32(dev, 0x0032e0, grctx->vinst >> 4);
	153	nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
	154	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
	155
	156	chan->engctx[engine] = grctx;
6ee73861 BS	157	return 0;
	158	}
	159
39c8d368 BS	160	static void
39c8d368 BS	161	nv40_graph_context_del(struct nouveau_channel *chan, int engine)
6ee73861	162	{
39c8d368 BS	163	struct nouveau_gpuobj *grctx = chan->engctx[engine];
	164	struct drm_device *dev = chan->dev;
	165	struct drm_nouveau_private *dev_priv = dev->dev_private;
	166	unsigned long flags;
6ee73861	167
39c8d368 BS	168	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
39c8d368 BS	169	nv04_graph_fifo_access(dev, false);
6ee73861	170
39c8d368 BS	171	/* Unload the context if it's the currently active one */
	172	if (nv40_graph_channel(dev) == chan)
	173	nv40_graph_unload_context(dev);
6ee73861	174
39c8d368 BS	175	nv04_graph_fifo_access(dev, true);
	176	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
	177
	178	/* Free the context resources */
	179	nouveau_gpuobj_ref(NULL, &grctx);
	180	chan->engctx[engine] = NULL;
6ee73861 BS	181	}
6ee73861 BS	182
4ea52f89	183	int
39c8d368 BS	184	nv40_graph_object_new(struct nouveau_channel *chan, int engine,
39c8d368 BS	185	u32 handle, u16 class)
4ea52f89 BS	186	{
	187	struct drm_device *dev = chan->dev;
	188	struct nouveau_gpuobj *obj = NULL;
	189	int ret;
	190
	191	ret = nouveau_gpuobj_new(dev, chan, 20, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
	192	if (ret)
	193	return ret;
	194	obj->engine = 1;
	195	obj->class = class;
	196
	197	nv_wo32(obj, 0x00, class);
	198	nv_wo32(obj, 0x04, 0x00000000);
3acf67f6 BS	199	#ifndef __BIG_ENDIAN
	200	nv_wo32(obj, 0x08, 0x00000000);
	201	#else
4ea52f89 BS	202	nv_wo32(obj, 0x08, 0x01000000);
	203	#endif
	204	nv_wo32(obj, 0x0c, 0x00000000);
	205	nv_wo32(obj, 0x10, 0x00000000);
	206
	207	ret = nouveau_ramht_insert(chan, handle, obj);
	208	nouveau_gpuobj_ref(NULL, &obj);
	209	return ret;
	210	}
	211
96c50082	212	static void
a5cf68b0	213	nv40_graph_set_tile_region(struct drm_device *dev, int i)
0d87c100 FJ	214	{
0d87c100 FJ	215	struct drm_nouveau_private *dev_priv = dev->dev_private;
a5cf68b0	216	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
0d87c100 FJ	217
0d87c100 FJ	218	switch (dev_priv->chipset) {
1dc32671 BS	219	case 0x40:
	220	case 0x41: /* guess */
	221	case 0x42:
	222	case 0x43:
	223	case 0x45: /* guess */
	224	case 0x4e:
	225	nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
	226	nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
	227	nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
	228	nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
	229	nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
	230	nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
	231	break;
0d87c100 FJ	232	case 0x44:
0d87c100 FJ	233	case 0x4a:
a5cf68b0 FJ	234	nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
	235	nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
	236	nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
0d87c100	237	break;
0d87c100 FJ	238	case 0x46:
	239	case 0x47:
	240	case 0x49:
	241	case 0x4b:
1dc32671 BS	242	case 0x4c:
	243	case 0x67:
	244	default:
a5cf68b0 FJ	245	nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch);
	246	nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit);
	247	nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr);
	248	nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
	249	nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
	250	nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
0d87c100	251	break;
0d87c100 FJ	252	}
	253	}
	254
6ee73861 BS	255	/*
	256	* G70 0x47
	257	* G71 0x49
	258	* NV45 0x48
	259	* G72[M] 0x46
	260	* G73 0x4b
	261	* C51_G7X 0x4c
	262	* C51 0x4e
	263	*/
	264	int
39c8d368	265	nv40_graph_init(struct drm_device *dev, int engine)
6ee73861	266	{
39c8d368 BS	267	struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
39c8d368 BS	268	struct drm_nouveau_private *dev_priv = dev->dev_private;
0d87c100	269	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
ec91db26 BS	270	struct nouveau_grctx ctx = {};
ec91db26 BS	271	uint32_t vramsz, *cp;
39c8d368	272	int i, j;
6ee73861 BS	273
	274	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
	275	~NV_PMC_ENABLE_PGRAPH);
	276	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) \|
	277	NV_PMC_ENABLE_PGRAPH);
	278
ec91db26 BS	279	cp = kmalloc(sizeof(cp) 256, GFP_KERNEL);
	280	if (!cp)
	281	return -ENOMEM;
054b93e4	282
ec91db26 BS	283	ctx.dev = dev;
	284	ctx.mode = NOUVEAU_GRCTX_PROG;
	285	ctx.data = cp;
	286	ctx.ctxprog_max = 256;
	287	nv40_grctx_init(&ctx);
39c8d368	288	pgraph->grctx_size = ctx.ctxvals_pos * 4;
054b93e4	289
ec91db26 BS	290	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
	291	for (i = 0; i < ctx.ctxprog_len; i++)
	292	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
f49d273d	293
ec91db26	294	kfree(cp);
6ee73861 BS	295
	296	/* No context present currently */
	297	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
	298
	299	nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
	300	nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
	301
	302	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	303	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
	304	nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
	305	nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
	306	nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
	307	nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
	308
	309	nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
	310	nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
	311
	312	j = nv_rd32(dev, 0x1540) & 0xff;
	313	if (j) {
	314	for (i = 0; !(j & 1); j >>= 1, i++)
	315	;
	316	nv_wr32(dev, 0x405000, i);
	317	}
	318
	319	if (dev_priv->chipset == 0x40) {
	320	nv_wr32(dev, 0x4009b0, 0x83280fff);
	321	nv_wr32(dev, 0x4009b4, 0x000000a0);
	322	} else {
	323	nv_wr32(dev, 0x400820, 0x83280eff);
	324	nv_wr32(dev, 0x400824, 0x000000a0);
	325	}
	326
	327	switch (dev_priv->chipset) {
	328	case 0x40:
	329	case 0x45:
	330	nv_wr32(dev, 0x4009b8, 0x0078e366);
	331	nv_wr32(dev, 0x4009bc, 0x0000014c);
	332	break;
	333	case 0x41:
	334	case 0x42: /* pciid also 0x00Cx */
	335	/* case 0x0120: XXX (pciid) */
	336	nv_wr32(dev, 0x400828, 0x007596ff);
	337	nv_wr32(dev, 0x40082c, 0x00000108);
	338	break;
	339	case 0x43:
	340	nv_wr32(dev, 0x400828, 0x0072cb77);
	341	nv_wr32(dev, 0x40082c, 0x00000108);
	342	break;
	343	case 0x44:
	344	case 0x46: /* G72 */
	345	case 0x4a:
	346	case 0x4c: /* G7x-based C51 */
	347	case 0x4e:
	348	nv_wr32(dev, 0x400860, 0);
	349	nv_wr32(dev, 0x400864, 0);
	350	break;
	351	case 0x47: /* G70 */
	352	case 0x49: /* G71 */
	353	case 0x4b: /* G73 */
	354	nv_wr32(dev, 0x400828, 0x07830610);
	355	nv_wr32(dev, 0x40082c, 0x0000016A);
	356	break;
	357	default:
	358	break;
359	}
360
361	nv_wr32(dev, 0x400b38, 0x2ffff800);
362	nv_wr32(dev, 0x400b3c, 0x00006000);
363
2295e17a FJ	364	/* Tiling related stuff. */
	365	switch (dev_priv->chipset) {
	366	case 0x44:
	367	case 0x4a:
	368	nv_wr32(dev, 0x400bc4, 0x1003d888);
	369	nv_wr32(dev, 0x400bbc, 0xb7a7b500);
	370	break;
	371	case 0x46:
	372	nv_wr32(dev, 0x400bc4, 0x0000e024);
	373	nv_wr32(dev, 0x400bbc, 0xb7a7b520);
	374	break;
	375	case 0x4c:
	376	case 0x4e:
	377	case 0x67:
	378	nv_wr32(dev, 0x400bc4, 0x1003d888);
	379	nv_wr32(dev, 0x400bbc, 0xb7a7b540);
	380	break;
	381	default:
	382	break;
	383	}
	384
0d87c100 FJ	385	/* Turn all the tiling regions off. */
0d87c100 FJ	386	for (i = 0; i < pfb->num_tiles; i++)
a5cf68b0	387	nv40_graph_set_tile_region(dev, i);
6ee73861 BS	388
6ee73861 BS	389	/* begin RAM config */
01d73a69	390	vramsz = pci_resource_len(dev->pdev, 0) - 1;
6ee73861 BS	391	switch (dev_priv->chipset) {
	392	case 0x40:
	393	nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
	394	nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
	395	nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
	396	nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
	397	nv_wr32(dev, 0x400820, 0);
	398	nv_wr32(dev, 0x400824, 0);
	399	nv_wr32(dev, 0x400864, vramsz);
	400	nv_wr32(dev, 0x400868, vramsz);
	401	break;
	402	default:
	403	switch (dev_priv->chipset) {
1dc32671 BS	404	case 0x41:
	405	case 0x42:
	406	case 0x43:
	407	case 0x45:
	408	case 0x4e:
	409	case 0x44:
	410	case 0x4a:
6ee73861 BS	411	nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
	412	nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
	413	break;
1dc32671 BS	414	default:
	415	nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
	416	nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
	417	break;
6ee73861 BS	418	}
	419	nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
	420	nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
	421	nv_wr32(dev, 0x400840, 0);
	422	nv_wr32(dev, 0x400844, 0);
	423	nv_wr32(dev, 0x4008A0, vramsz);
	424	nv_wr32(dev, 0x4008A4, vramsz);
	425	break;
	426	}
	427
	428	return 0;
	429	}
	430
b8c157d3	431	static int
39c8d368	432	nv40_graph_fini(struct drm_device *dev, int engine)
b8c157d3	433	{
39c8d368	434	nv40_graph_unload_context(dev);
b8c157d3 BS	435	return 0;
b8c157d3 BS	436	}
274fec93 BS	437
	438	static int
	439	nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
	440	{
	441	struct drm_nouveau_private *dev_priv = dev->dev_private;
39c8d368	442	struct nouveau_gpuobj *grctx;
274fec93 BS	443	unsigned long flags;
	444	int i;
	445
	446	spin_lock_irqsave(&dev_priv->channels.lock, flags);
	447	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
39c8d368	448	if (!dev_priv->channels.ptr[i])
274fec93	449	continue;
39c8d368	450	grctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_GR];
274fec93	451
39c8d368	452	if (grctx && grctx->pinst == inst)
274fec93 BS	453	break;
	454	}
	455	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
	456	return i;
	457	}
	458
	459	static void
	460	nv40_graph_isr(struct drm_device *dev)
	461	{
	462	u32 stat;
	463
	464	while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
	465	u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
	466	u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
	467	u32 inst = (nv_rd32(dev, 0x40032c) & 0x000fffff) << 4;
	468	u32 chid = nv40_graph_isr_chid(dev, inst);
	469	u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
	470	u32 subc = (addr & 0x00070000) >> 16;
	471	u32 mthd = (addr & 0x00001ffc);
	472	u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
	473	u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xffff;
	474	u32 show = stat;
	475
	476	if (stat & NV_PGRAPH_INTR_ERROR) {
	477	if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
	478	if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
	479	show &= ~NV_PGRAPH_INTR_ERROR;
	480	} else
	481	if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
	482	nv_mask(dev, 0x402000, 0, 0);
	483	}
	484	}
	485
	486	nv_wr32(dev, NV03_PGRAPH_INTR, stat);
	487	nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
	488
	489	if (show && nouveau_ratelimit()) {
	490	NV_INFO(dev, "PGRAPH -");
	491	nouveau_bitfield_print(nv10_graph_intr, show);
	492	printk(" nsource:");
	493	nouveau_bitfield_print(nv04_graph_nsource, nsource);
	494	printk(" nstatus:");
	495	nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
	496	printk("\n");
	497	NV_INFO(dev, "PGRAPH - ch %d (0x%08x) subc %d "
	498	"class 0x%04x mthd 0x%04x data 0x%08x\n",
	499	chid, inst, subc, class, mthd, data);
	500	}
	501	}
	502	}
39c8d368 BS	503
	504	static void
	505	nv40_graph_destroy(struct drm_device *dev, int engine)
	506	{
	507	struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
	508
	509	nouveau_irq_unregister(dev, 12);
	510
	511	NVOBJ_ENGINE_DEL(dev, GR);
	512	kfree(pgraph);
	513	}
	514
	515	int
	516	nv40_graph_create(struct drm_device *dev)
	517	{
	518	struct nv40_graph_engine *pgraph;
	519
	520	pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
	521	if (!pgraph)
	522	return -ENOMEM;
	523
	524	pgraph->base.destroy = nv40_graph_destroy;
	525	pgraph->base.init = nv40_graph_init;
	526	pgraph->base.fini = nv40_graph_fini;
	527	pgraph->base.context_new = nv40_graph_context_new;
	528	pgraph->base.context_del = nv40_graph_context_del;
	529	pgraph->base.object_new = nv40_graph_object_new;
96c50082	530	pgraph->base.set_tile_region = nv40_graph_set_tile_region;
39c8d368 BS	531
	532	NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
	533	nouveau_irq_register(dev, 12, nv40_graph_isr);
	534
	535	NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
	536	NVOBJ_CLASS(dev, 0x0030, GR); /* null */
	537	NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
	538	NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
	539	NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
	540	NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
	541	NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
	542	NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
	543	NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
	544	NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
	545	NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
	546	NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
	547	NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
	548	NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
	549	NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
	550	NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */
	551
	552	/* curie */
	553	if (nv44_graph_class(dev))
	554	NVOBJ_CLASS(dev, 0x4497, GR);
	555	else
	556	NVOBJ_CLASS(dev, 0x4097, GR);
	557
	558	/* nvsw */
	559	NVOBJ_CLASS(dev, 0x506e, SW);
	560	NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
	561	return 0;
	562	}