[deliverable/linux.git] / drivers / gpu / drm / nouveau / nv40_graph.c

/*
 * Copyright (C) 2007 Ben Skeggs.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_grctx.h"

static int nv40_graph_register(struct drm_device *);

struct nouveau_channel *
nv40_graph_channel(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t inst;
	int i;

	inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
	if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
		return NULL;
	inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;

	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
		struct nouveau_channel *chan = dev_priv->channels.ptr[i];

		if (chan && chan->ramin_grctx &&
		    chan->ramin_grctx->pinst == inst)
			return chan;
	}

	return NULL;
}

int
nv40_graph_create_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	struct nouveau_grctx ctx = {};
	int ret;

	ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,
				 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx);
	if (ret)
		return ret;

	/* Initialise default context values */
	ctx.dev = chan->dev;
	ctx.mode = NOUVEAU_GRCTX_VALS;
	ctx.data = chan->ramin_grctx;
	nv40_grctx_init(&ctx);

	nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->pinst);
	return 0;
}

void
nv40_graph_destroy_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	unsigned long flags;

	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	pgraph->fifo_access(dev, false);

	/* Unload the context if it's the currently active one */
	if (pgraph->channel(dev) == chan)
		pgraph->unload_context(dev);

	pgraph->fifo_access(dev, true);
	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);

	/* Free the context resources */
	nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
}

static int
nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
{
	uint32_t old_cp, tv = 1000, tmp;
	int i;

	old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER);
	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);

	tmp  = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310);
	tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
		      NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp);

	tmp  = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304);
	tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp);

	nouveau_wait_for_idle(dev);

	for (i = 0; i < tv; i++) {
		if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0)
			break;
	}

	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);

	if (i == tv) {
		uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT);
		NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save);
		NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n",
			 ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
			 ucstat  & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
		NV_ERROR(dev, "0x40030C = 0x%08x\n",
			 nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C));
		return -EBUSY;
	}

	return 0;
}

/* Restore the context for a specific channel into PGRAPH */
int
nv40_graph_load_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	uint32_t inst;
	int ret;

	if (!chan->ramin_grctx)
		return -EINVAL;
	inst = chan->ramin_grctx->pinst >> 4;

	ret = nv40_graph_transfer_context(dev, inst, 0);
	if (ret)
		return ret;

	/* 0x40032C, no idea of it's exact function.  Could simply be a
	 * record of the currently active PGRAPH context.  It's currently
	 * unknown as to what bit 24 does.  The nv ddx has it set, so we will
	 * set it here too.
	 */
	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR,
		 (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) |
		  NV40_PGRAPH_CTXCTL_CUR_LOADED);
	/* 0x32E0 records the instance address of the active FIFO's PGRAPH
	 * context.  If at any time this doesn't match 0x40032C, you will
	 * recieve PGRAPH_INTR_CONTEXT_SWITCH
	 */
	nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst);
	return 0;
}

int
nv40_graph_unload_context(struct drm_device *dev)
{
	uint32_t inst;
	int ret;

	inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
	if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
		return 0;
	inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE;

	ret = nv40_graph_transfer_context(dev, inst, 1);

	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst);
	return ret;
}

void
nv40_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
			     uint32_t size, uint32_t pitch)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t limit = max(1u, addr + size) - 1;

	if (pitch)
		addr |= 1;

	switch (dev_priv->chipset) {
	case 0x44:
	case 0x4a:
	case 0x4e:
		nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
		nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
		nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
		break;

	case 0x46:
	case 0x47:
	case 0x49:
	case 0x4b:
		nv_wr32(dev, NV47_PGRAPH_TSIZE(i), pitch);
		nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), limit);
		nv_wr32(dev, NV47_PGRAPH_TILE(i), addr);
		nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
		nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
		nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
		break;

	default:
		nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
		nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
		nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
		nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
		nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
		nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
		break;
	}
}

/*
 * G70		0x47
 * G71		0x49
 * NV45		0x48
 * G72[M]	0x46
 * G73		0x4b
 * C51_G7X	0x4c
 * C51		0x4e
 */
int
nv40_graph_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv =
		(struct drm_nouveau_private *)dev->dev_private;
	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	struct nouveau_grctx ctx = {};
	uint32_t vramsz, *cp;
	int ret, i, j;

	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
			~NV_PMC_ENABLE_PGRAPH);
	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
			 NV_PMC_ENABLE_PGRAPH);

	cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
	if (!cp)
		return -ENOMEM;

	ctx.dev = dev;
	ctx.mode = NOUVEAU_GRCTX_PROG;
	ctx.data = cp;
	ctx.ctxprog_max = 256;
	nv40_grctx_init(&ctx);
	dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;

	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
	for (i = 0; i < ctx.ctxprog_len; i++)
		nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);

	kfree(cp);

	ret = nv40_graph_register(dev);
	if (ret)
		return ret;

	/* No context present currently */
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);

	nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
	nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);

	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
	nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
	nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
	nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
	nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);

	nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
	nv_wr32(dev, NV10_PGRAPH_STATE      , 0xFFFFFFFF);

	j = nv_rd32(dev, 0x1540) & 0xff;
	if (j) {
		for (i = 0; !(j & 1); j >>= 1, i++)
			;
		nv_wr32(dev, 0x405000, i);
	}

	if (dev_priv->chipset == 0x40) {
		nv_wr32(dev, 0x4009b0, 0x83280fff);
		nv_wr32(dev, 0x4009b4, 0x000000a0);
	} else {
		nv_wr32(dev, 0x400820, 0x83280eff);
		nv_wr32(dev, 0x400824, 0x000000a0);
	}

	switch (dev_priv->chipset) {
	case 0x40:
	case 0x45:
		nv_wr32(dev, 0x4009b8, 0x0078e366);
		nv_wr32(dev, 0x4009bc, 0x0000014c);
		break;
	case 0x41:
	case 0x42: /* pciid also 0x00Cx */
	/* case 0x0120: XXX (pciid) */
		nv_wr32(dev, 0x400828, 0x007596ff);
		nv_wr32(dev, 0x40082c, 0x00000108);
		break;
	case 0x43:
		nv_wr32(dev, 0x400828, 0x0072cb77);
		nv_wr32(dev, 0x40082c, 0x00000108);
		break;
	case 0x44:
	case 0x46: /* G72 */
	case 0x4a:
	case 0x4c: /* G7x-based C51 */
	case 0x4e:
		nv_wr32(dev, 0x400860, 0);
		nv_wr32(dev, 0x400864, 0);
		break;
	case 0x47: /* G70 */
	case 0x49: /* G71 */
	case 0x4b: /* G73 */
		nv_wr32(dev, 0x400828, 0x07830610);
		nv_wr32(dev, 0x40082c, 0x0000016A);
		break;
	default:
		break;
	}

	nv_wr32(dev, 0x400b38, 0x2ffff800);
	nv_wr32(dev, 0x400b3c, 0x00006000);

	/* Tiling related stuff. */
	switch (dev_priv->chipset) {
	case 0x44:
	case 0x4a:
		nv_wr32(dev, 0x400bc4, 0x1003d888);
		nv_wr32(dev, 0x400bbc, 0xb7a7b500);
		break;
	case 0x46:
		nv_wr32(dev, 0x400bc4, 0x0000e024);
		nv_wr32(dev, 0x400bbc, 0xb7a7b520);
		break;
	case 0x4c:
	case 0x4e:
	case 0x67:
		nv_wr32(dev, 0x400bc4, 0x1003d888);
		nv_wr32(dev, 0x400bbc, 0xb7a7b540);
		break;
	default:
		break;
	}

	/* Turn all the tiling regions off. */
	for (i = 0; i < pfb->num_tiles; i++)
		nv40_graph_set_region_tiling(dev, i, 0, 0, 0);

	/* begin RAM config */
	vramsz = pci_resource_len(dev->pdev, 0) - 1;
	switch (dev_priv->chipset) {
	case 0x40:
		nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
		nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
		nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
		nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
		nv_wr32(dev, 0x400820, 0);
		nv_wr32(dev, 0x400824, 0);
		nv_wr32(dev, 0x400864, vramsz);
		nv_wr32(dev, 0x400868, vramsz);
		break;
	default:
		switch (dev_priv->chipset) {
		case 0x46:
		case 0x47:
		case 0x49:
		case 0x4b:
			nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
			nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
			break;
		default:
			nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
			nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
			break;
		}
		nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
		nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
		nv_wr32(dev, 0x400840, 0);
		nv_wr32(dev, 0x400844, 0);
		nv_wr32(dev, 0x4008A0, vramsz);
		nv_wr32(dev, 0x4008A4, vramsz);
		break;
	}

	return 0;
}

void nv40_graph_takedown(struct drm_device *dev)
{
}

static int
nv40_graph_register(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	if (dev_priv->engine.graph.registered)
		return 0;

	NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
	NVOBJ_CLASS(dev, 0x0030, GR); /* null */
	NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
	NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
	NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
	NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
	NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
	NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
	NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
	NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
	NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
	NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
	NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
	NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
	NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
	NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */

	/* curie */
	if (dev_priv->chipset >= 0x60 ||
	    0x00005450 & (1 << (dev_priv->chipset & 0x0f)))
		NVOBJ_CLASS(dev, 0x4497, GR);
	else
		NVOBJ_CLASS(dev, 0x4097, GR);

	/* nvsw */
	NVOBJ_CLASS(dev, 0x506e, SW);
	NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);

	dev_priv->engine.graph.registered = true;
	return 0;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) 2007 Ben Skeggs.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining
	6	* a copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sublicense, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial
	15	* portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	18	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	20	* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	21	* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	22	* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	23	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*
	25	*/
	26
6ee73861 BS	27	#include "drmP.h"
	28	#include "drm.h"
	29	#include "nouveau_drv.h"
054b93e4	30	#include "nouveau_grctx.h"
6ee73861	31
b8c157d3 BS	32	static int nv40_graph_register(struct drm_device *);
b8c157d3 BS	33
6ee73861 BS	34	struct nouveau_channel *
	35	nv40_graph_channel(struct drm_device *dev)
	36	{
	37	struct drm_nouveau_private *dev_priv = dev->dev_private;
	38	uint32_t inst;
	39	int i;
	40
	41	inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
	42	if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
	43	return NULL;
	44	inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;
	45
	46	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
cff5c133	47	struct nouveau_channel *chan = dev_priv->channels.ptr[i];
6ee73861 BS	48
6ee73861 BS	49	if (chan && chan->ramin_grctx &&
a8eaebc6	50	chan->ramin_grctx->pinst == inst)
6ee73861 BS	51	return chan;
	52	}
	53
	54	return NULL;
	55	}
	56
	57	int
	58	nv40_graph_create_context(struct nouveau_channel *chan)
	59	{
	60	struct drm_device *dev = chan->dev;
	61	struct drm_nouveau_private *dev_priv = dev->dev_private;
054b93e4	62	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
ec91db26	63	struct nouveau_grctx ctx = {};
6ee73861 BS	64	int ret;
6ee73861 BS	65
a8eaebc6 BS	66	ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,
a8eaebc6 BS	67	NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx);
6ee73861 BS	68	if (ret)
6ee73861 BS	69	return ret;
6ee73861 BS	70
6ee73861 BS	71	/* Initialise default context values */
ec91db26 BS	72	ctx.dev = chan->dev;
ec91db26 BS	73	ctx.mode = NOUVEAU_GRCTX_VALS;
a8eaebc6	74	ctx.data = chan->ramin_grctx;
ec91db26	75	nv40_grctx_init(&ctx);
6ee73861	76
5125bfd8	77	nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->pinst);
6ee73861 BS	78	return 0;
	79	}
	80
	81	void
	82	nv40_graph_destroy_context(struct nouveau_channel *chan)
	83	{
3945e475 FJ	84	struct drm_device *dev = chan->dev;
	85	struct drm_nouveau_private *dev_priv = dev->dev_private;
	86	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	87	unsigned long flags;
	88
	89	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	90	pgraph->fifo_access(dev, false);
	91
	92	/* Unload the context if it's the currently active one */
	93	if (pgraph->channel(dev) == chan)
	94	pgraph->unload_context(dev);
	95
	96	pgraph->fifo_access(dev, true);
	97	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
	98
	99	/* Free the context resources */
a8eaebc6	100	nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
6ee73861 BS	101	}
	102
	103	static int
	104	nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
	105	{
	106	uint32_t old_cp, tv = 1000, tmp;
	107	int i;
	108
	109	old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER);
	110	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
	111
	112	tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310);
	113	tmp \|= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
	114	NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
	115	nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp);
	116
	117	tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304);
	118	tmp \|= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
	119	nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp);
	120
	121	nouveau_wait_for_idle(dev);
	122
	123	for (i = 0; i < tv; i++) {
	124	if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0)
	125	break;
	126	}
	127
	128	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
	129
	130	if (i == tv) {
	131	uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT);
	132	NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save);
	133	NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n",
	134	ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
	135	ucstat & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
	136	NV_ERROR(dev, "0x40030C = 0x%08x\n",
	137	nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C));
	138	return -EBUSY;
	139	}
	140
	141	return 0;
	142	}
	143
	144	/* Restore the context for a specific channel into PGRAPH */
	145	int
	146	nv40_graph_load_context(struct nouveau_channel *chan)
	147	{
	148	struct drm_device *dev = chan->dev;
	149	uint32_t inst;
	150	int ret;
	151
	152	if (!chan->ramin_grctx)
	153	return -EINVAL;
a8eaebc6	154	inst = chan->ramin_grctx->pinst >> 4;
6ee73861 BS	155
	156	ret = nv40_graph_transfer_context(dev, inst, 0);
	157	if (ret)
	158	return ret;
	159
	160	/* 0x40032C, no idea of it's exact function. Could simply be a
	161	* record of the currently active PGRAPH context. It's currently
	162	* unknown as to what bit 24 does. The nv ddx has it set, so we will
	163	* set it here too.
	164	*/
	165	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
	166	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR,
	167	(inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) \|
	168	NV40_PGRAPH_CTXCTL_CUR_LOADED);
	169	/* 0x32E0 records the instance address of the active FIFO's PGRAPH
	170	* context. If at any time this doesn't match 0x40032C, you will
	171	* recieve PGRAPH_INTR_CONTEXT_SWITCH
	172	*/
	173	nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst);
	174	return 0;
	175	}
	176
	177	int
	178	nv40_graph_unload_context(struct drm_device *dev)
	179	{
	180	uint32_t inst;
	181	int ret;
	182
	183	inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
	184	if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
	185	return 0;
	186	inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE;
	187
	188	ret = nv40_graph_transfer_context(dev, inst, 1);
	189
	190	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst);
	191	return ret;
	192	}
	193
0d87c100 FJ	194	void
	195	nv40_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
	196	uint32_t size, uint32_t pitch)
	197	{
	198	struct drm_nouveau_private *dev_priv = dev->dev_private;
	199	uint32_t limit = max(1u, addr + size) - 1;
	200
	201	if (pitch)
	202	addr \|= 1;
	203
	204	switch (dev_priv->chipset) {
	205	case 0x44:
	206	case 0x4a:
	207	case 0x4e:
	208	nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
	209	nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
	210	nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
	211	break;
	212
	213	case 0x46:
	214	case 0x47:
	215	case 0x49:
	216	case 0x4b:
	217	nv_wr32(dev, NV47_PGRAPH_TSIZE(i), pitch);
	218	nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), limit);
	219	nv_wr32(dev, NV47_PGRAPH_TILE(i), addr);
	220	nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
	221	nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
	222	nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
	223	break;
	224
	225	default:
	226	nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
	227	nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
	228	nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
	229	nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
	230	nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
	231	nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
	232	break;
	233	}
	234	}
	235
6ee73861 BS	236	/*
	237	* G70 0x47
	238	* G71 0x49
	239	* NV45 0x48
	240	* G72[M] 0x46
	241	* G73 0x4b
	242	* C51_G7X 0x4c
	243	* C51 0x4e
	244	*/
	245	int
	246	nv40_graph_init(struct drm_device *dev)
	247	{
	248	struct drm_nouveau_private *dev_priv =
	249	(struct drm_nouveau_private *)dev->dev_private;
0d87c100	250	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
ec91db26 BS	251	struct nouveau_grctx ctx = {};
ec91db26 BS	252	uint32_t vramsz, *cp;
b8c157d3	253	int ret, i, j;
6ee73861 BS	254
	255	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
	256	~NV_PMC_ENABLE_PGRAPH);
	257	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) \|
	258	NV_PMC_ENABLE_PGRAPH);
	259
ec91db26 BS	260	cp = kmalloc(sizeof(cp) 256, GFP_KERNEL);
	261	if (!cp)
	262	return -ENOMEM;
054b93e4	263
ec91db26 BS	264	ctx.dev = dev;
	265	ctx.mode = NOUVEAU_GRCTX_PROG;
	266	ctx.data = cp;
	267	ctx.ctxprog_max = 256;
	268	nv40_grctx_init(&ctx);
	269	dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
054b93e4	270
ec91db26 BS	271	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
	272	for (i = 0; i < ctx.ctxprog_len; i++)
	273	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
f49d273d	274
ec91db26	275	kfree(cp);
6ee73861	276
b8c157d3 BS	277	ret = nv40_graph_register(dev);
	278	if (ret)
	279	return ret;
	280
6ee73861 BS	281	/* No context present currently */
	282	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
	283
	284	nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
	285	nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
	286
	287	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	288	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
	289	nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
	290	nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
	291	nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
	292	nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
	293
	294	nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
	295	nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
	296
	297	j = nv_rd32(dev, 0x1540) & 0xff;
	298	if (j) {
	299	for (i = 0; !(j & 1); j >>= 1, i++)
	300	;
	301	nv_wr32(dev, 0x405000, i);
	302	}
	303
	304	if (dev_priv->chipset == 0x40) {
	305	nv_wr32(dev, 0x4009b0, 0x83280fff);
	306	nv_wr32(dev, 0x4009b4, 0x000000a0);
	307	} else {
	308	nv_wr32(dev, 0x400820, 0x83280eff);
	309	nv_wr32(dev, 0x400824, 0x000000a0);
	310	}
	311
	312	switch (dev_priv->chipset) {
	313	case 0x40:
	314	case 0x45:
	315	nv_wr32(dev, 0x4009b8, 0x0078e366);
	316	nv_wr32(dev, 0x4009bc, 0x0000014c);
	317	break;
	318	case 0x41:
	319	case 0x42: /* pciid also 0x00Cx */
	320	/* case 0x0120: XXX (pciid) */
	321	nv_wr32(dev, 0x400828, 0x007596ff);
	322	nv_wr32(dev, 0x40082c, 0x00000108);
	323	break;
	324	case 0x43:
	325	nv_wr32(dev, 0x400828, 0x0072cb77);
	326	nv_wr32(dev, 0x40082c, 0x00000108);
	327	break;
	328	case 0x44:
	329	case 0x46: /* G72 */
	330	case 0x4a:
	331	case 0x4c: /* G7x-based C51 */
	332	case 0x4e:
	333	nv_wr32(dev, 0x400860, 0);
	334	nv_wr32(dev, 0x400864, 0);
	335	break;
	336	case 0x47: /* G70 */
	337	case 0x49: /* G71 */
	338	case 0x4b: /* G73 */
	339	nv_wr32(dev, 0x400828, 0x07830610);
	340	nv_wr32(dev, 0x40082c, 0x0000016A);
	341	break;
	342	default:
	343	break;
	344	}
345
346	nv_wr32(dev, 0x400b38, 0x2ffff800);
347	nv_wr32(dev, 0x400b3c, 0x00006000);
348
2295e17a FJ	349	/* Tiling related stuff. */
	350	switch (dev_priv->chipset) {
	351	case 0x44:
	352	case 0x4a:
	353	nv_wr32(dev, 0x400bc4, 0x1003d888);
	354	nv_wr32(dev, 0x400bbc, 0xb7a7b500);
	355	break;
	356	case 0x46:
	357	nv_wr32(dev, 0x400bc4, 0x0000e024);
	358	nv_wr32(dev, 0x400bbc, 0xb7a7b520);
	359	break;
	360	case 0x4c:
	361	case 0x4e:
	362	case 0x67:
	363	nv_wr32(dev, 0x400bc4, 0x1003d888);
	364	nv_wr32(dev, 0x400bbc, 0xb7a7b540);
	365	break;
	366	default:
	367	break;
	368	}
	369
0d87c100 FJ	370	/* Turn all the tiling regions off. */
	371	for (i = 0; i < pfb->num_tiles; i++)
	372	nv40_graph_set_region_tiling(dev, i, 0, 0, 0);
6ee73861 BS	373
6ee73861 BS	374	/* begin RAM config */
01d73a69	375	vramsz = pci_resource_len(dev->pdev, 0) - 1;
6ee73861 BS	376	switch (dev_priv->chipset) {
	377	case 0x40:
	378	nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
	379	nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
	380	nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
	381	nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
	382	nv_wr32(dev, 0x400820, 0);
	383	nv_wr32(dev, 0x400824, 0);
	384	nv_wr32(dev, 0x400864, vramsz);
	385	nv_wr32(dev, 0x400868, vramsz);
	386	break;
	387	default:
	388	switch (dev_priv->chipset) {
	389	case 0x46:
	390	case 0x47:
	391	case 0x49:
	392	case 0x4b:
	393	nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
	394	nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
	395	break;
	396	default:
	397	nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
	398	nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
	399	break;
	400	}
	401	nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
	402	nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
	403	nv_wr32(dev, 0x400840, 0);
	404	nv_wr32(dev, 0x400844, 0);
	405	nv_wr32(dev, 0x4008A0, vramsz);
	406	nv_wr32(dev, 0x4008A4, vramsz);
	407	break;
	408	}
	409
	410	return 0;
	411	}
	412
	413	void nv40_graph_takedown(struct drm_device *dev)
	414	{
	415	}
	416
b8c157d3 BS	417	static int
	418	nv40_graph_register(struct drm_device *dev)
	419	{
	420	struct drm_nouveau_private *dev_priv = dev->dev_private;
	421
	422	if (dev_priv->engine.graph.registered)
	423	return 0;
6ee73861	424
b8c157d3 BS	425	NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
	426	NVOBJ_CLASS(dev, 0x0030, GR); /* null */
	427	NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
	428	NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
	429	NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
	430	NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
	431	NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
	432	NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
	433	NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
	434	NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
	435	NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
	436	NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
	437	NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
	438	NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
	439	NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
	440	NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */
	441
	442	/* curie */
	443	if (dev_priv->chipset >= 0x60 \|\|
	444	0x00005450 & (1 << (dev_priv->chipset & 0x0f)))
	445	NVOBJ_CLASS(dev, 0x4497, GR);
	446	else
	447	NVOBJ_CLASS(dev, 0x4097, GR);
	448
332b242f FJ	449	/* nvsw */
	450	NVOBJ_CLASS(dev, 0x506e, SW);
	451	NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
	452
b8c157d3 BS	453	dev_priv->engine.graph.registered = true;
	454	return 0;
	455	}